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24 * Robert Bragg <robert@sixbynine.org>
29 * DOC: i915 Perf Overview
31 * Gen graphics supports a large number of performance counters that can help
32 * driver and application developers understand and optimize their use of the
35 * This i915 perf interface enables userspace to configure and open a file
36 * descriptor representing a stream of GPU metrics which can then be read() as
37 * a stream of sample records.
39 * The interface is particularly suited to exposing buffered metrics that are
40 * captured by DMA from the GPU, unsynchronized with and unrelated to the CPU.
42 * Streams representing a single context are accessible to applications with a
43 * corresponding drm file descriptor, such that OpenGL can use the interface
44 * without special privileges. Access to system-wide metrics requires root
45 * privileges by default, unless changed via the dev.i915.perf_event_paranoid
51 * DOC: i915 Perf History and Comparison with Core Perf
53 * The interface was initially inspired by the core Perf infrastructure but
54 * some notable differences are:
56 * i915 perf file descriptors represent a "stream" instead of an "event"; where
57 * a perf event primarily corresponds to a single 64bit value, while a stream
58 * might sample sets of tightly-coupled counters, depending on the
59 * configuration. For example the Gen OA unit isn't designed to support
60 * orthogonal configurations of individual counters; it's configured for a set
61 * of related counters. Samples for an i915 perf stream capturing OA metrics
62 * will include a set of counter values packed in a compact HW specific format.
63 * The OA unit supports a number of different packing formats which can be
64 * selected by the user opening the stream. Perf has support for grouping
65 * events, but each event in the group is configured, validated and
66 * authenticated individually with separate system calls.
68 * i915 perf stream configurations are provided as an array of u64 (key,value)
69 * pairs, instead of a fixed struct with multiple miscellaneous config members,
70 * interleaved with event-type specific members.
72 * i915 perf doesn't support exposing metrics via an mmap'd circular buffer.
73 * The supported metrics are being written to memory by the GPU unsynchronized
74 * with the CPU, using HW specific packing formats for counter sets. Sometimes
75 * the constraints on HW configuration require reports to be filtered before it
76 * would be acceptable to expose them to unprivileged applications - to hide
77 * the metrics of other processes/contexts. For these use cases a read() based
78 * interface is a good fit, and provides an opportunity to filter data as it
79 * gets copied from the GPU mapped buffers to userspace buffers.
82 * Issues hit with first prototype based on Core Perf
83 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
85 * The first prototype of this driver was based on the core perf
86 * infrastructure, and while we did make that mostly work, with some changes to
87 * perf, we found we were breaking or working around too many assumptions baked
88 * into perf's currently cpu centric design.
90 * In the end we didn't see a clear benefit to making perf's implementation and
91 * interface more complex by changing design assumptions while we knew we still
92 * wouldn't be able to use any existing perf based userspace tools.
94 * Also considering the Gen specific nature of the Observability hardware and
95 * how userspace will sometimes need to combine i915 perf OA metrics with
96 * side-band OA data captured via MI_REPORT_PERF_COUNT commands; we're
97 * expecting the interface to be used by a platform specific userspace such as
98 * OpenGL or tools. This is to say; we aren't inherently missing out on having
99 * a standard vendor/architecture agnostic interface by not using perf.
102 * For posterity, in case we might re-visit trying to adapt core perf to be
103 * better suited to exposing i915 metrics these were the main pain points we
106 * - The perf based OA PMU driver broke some significant design assumptions:
108 * Existing perf pmus are used for profiling work on a cpu and we were
109 * introducing the idea of _IS_DEVICE pmus with different security
110 * implications, the need to fake cpu-related data (such as user/kernel
111 * registers) to fit with perf's current design, and adding _DEVICE records
112 * as a way to forward device-specific status records.
114 * The OA unit writes reports of counters into a circular buffer, without
115 * involvement from the CPU, making our PMU driver the first of a kind.
117 * Given the way we were periodically forward data from the GPU-mapped, OA
118 * buffer to perf's buffer, those bursts of sample writes looked to perf like
119 * we were sampling too fast and so we had to subvert its throttling checks.
121 * Perf supports groups of counters and allows those to be read via
122 * transactions internally but transactions currently seem designed to be
123 * explicitly initiated from the cpu (say in response to a userspace read())
124 * and while we could pull a report out of the OA buffer we can't
125 * trigger a report from the cpu on demand.
127 * Related to being report based; the OA counters are configured in HW as a
128 * set while perf generally expects counter configurations to be orthogonal.
129 * Although counters can be associated with a group leader as they are
130 * opened, there's no clear precedent for being able to provide group-wide
131 * configuration attributes (for example we want to let userspace choose the
132 * OA unit report format used to capture all counters in a set, or specify a
133 * GPU context to filter metrics on). We avoided using perf's grouping
134 * feature and forwarded OA reports to userspace via perf's 'raw' sample
135 * field. This suited our userspace well considering how coupled the counters
136 * are when dealing with normalizing. It would be inconvenient to split
137 * counters up into separate events, only to require userspace to recombine
138 * them. For Mesa it's also convenient to be forwarded raw, periodic reports
139 * for combining with the side-band raw reports it captures using
140 * MI_REPORT_PERF_COUNT commands.
142 * - As a side note on perf's grouping feature; there was also some concern
143 * that using PERF_FORMAT_GROUP as a way to pack together counter values
144 * would quite drastically inflate our sample sizes, which would likely
145 * lower the effective sampling resolutions we could use when the available
146 * memory bandwidth is limited.
148 * With the OA unit's report formats, counters are packed together as 32
149 * or 40bit values, with the largest report size being 256 bytes.
151 * PERF_FORMAT_GROUP values are 64bit, but there doesn't appear to be a
152 * documented ordering to the values, implying PERF_FORMAT_ID must also be
153 * used to add a 64bit ID before each value; giving 16 bytes per counter.
155 * Related to counter orthogonality; we can't time share the OA unit, while
156 * event scheduling is a central design idea within perf for allowing
157 * userspace to open + enable more events than can be configured in HW at any
158 * one time. The OA unit is not designed to allow re-configuration while in
159 * use. We can't reconfigure the OA unit without losing internal OA unit
160 * state which we can't access explicitly to save and restore. Reconfiguring
161 * the OA unit is also relatively slow, involving ~100 register writes. From
162 * userspace Mesa also depends on a stable OA configuration when emitting
163 * MI_REPORT_PERF_COUNT commands and importantly the OA unit can't be
164 * disabled while there are outstanding MI_RPC commands lest we hang the
167 * The contents of sample records aren't extensible by device drivers (i.e.
168 * the sample_type bits). As an example; Sourab Gupta had been looking to
169 * attach GPU timestamps to our OA samples. We were shoehorning OA reports
170 * into sample records by using the 'raw' field, but it's tricky to pack more
171 * than one thing into this field because events/core.c currently only lets a
172 * pmu give a single raw data pointer plus len which will be copied into the
173 * ring buffer. To include more than the OA report we'd have to copy the
174 * report into an intermediate larger buffer. I'd been considering allowing a
175 * vector of data+len values to be specified for copying the raw data, but
176 * it felt like a kludge to being using the raw field for this purpose.
178 * - It felt like our perf based PMU was making some technical compromises
179 * just for the sake of using perf:
181 * perf_event_open() requires events to either relate to a pid or a specific
182 * cpu core, while our device pmu related to neither. Events opened with a
183 * pid will be automatically enabled/disabled according to the scheduling of
184 * that process - so not appropriate for us. When an event is related to a
185 * cpu id, perf ensures pmu methods will be invoked via an inter process
186 * interrupt on that core. To avoid invasive changes our userspace opened OA
187 * perf events for a specific cpu. This was workable but it meant the
188 * majority of the OA driver ran in atomic context, including all OA report
189 * forwarding, which wasn't really necessary in our case and seems to make
190 * our locking requirements somewhat complex as we handled the interaction
191 * with the rest of the i915 driver.
194 #include <linux/anon_inodes.h>
195 #include <linux/nospec.h>
196 #include <linux/sizes.h>
197 #include <linux/uuid.h>
199 #include "gem/i915_gem_context.h"
200 #include "gem/i915_gem_internal.h"
201 #include "gt/intel_engine_pm.h"
202 #include "gt/intel_engine_regs.h"
203 #include "gt/intel_engine_user.h"
204 #include "gt/intel_execlists_submission.h"
205 #include "gt/intel_gpu_commands.h"
206 #include "gt/intel_gt.h"
207 #include "gt/intel_gt_clock_utils.h"
208 #include "gt/intel_gt_mcr.h"
209 #include "gt/intel_gt_regs.h"
210 #include "gt/intel_lrc.h"
211 #include "gt/intel_lrc_reg.h"
212 #include "gt/intel_ring.h"
213 #include "gt/uc/intel_guc_slpc.h"
215 #include "i915_drv.h"
216 #include "i915_file_private.h"
217 #include "i915_perf.h"
218 #include "i915_perf_oa_regs.h"
219 #include "i915_reg.h"
221 /* HW requires this to be a power of two, between 128k and 16M, though driver
222 * is currently generally designed assuming the largest 16M size is used such
223 * that the overflow cases are unlikely in normal operation.
225 #define OA_BUFFER_SIZE SZ_16M
227 #define OA_TAKEN(tail, head) ((tail - head) & (OA_BUFFER_SIZE - 1))
230 * DOC: OA Tail Pointer Race
232 * There's a HW race condition between OA unit tail pointer register updates and
233 * writes to memory whereby the tail pointer can sometimes get ahead of what's
234 * been written out to the OA buffer so far (in terms of what's visible to the
237 * Although this can be observed explicitly while copying reports to userspace
238 * by checking for a zeroed report-id field in tail reports, we want to account
239 * for this earlier, as part of the oa_buffer_check_unlocked to avoid lots of
240 * redundant read() attempts.
242 * We workaround this issue in oa_buffer_check_unlocked() by reading the reports
243 * in the OA buffer, starting from the tail reported by the HW until we find a
244 * report with its first 2 dwords not 0 meaning its previous report is
245 * completely in memory and ready to be read. Those dwords are also set to 0
246 * once read and the whole buffer is cleared upon OA buffer initialization. The
247 * first dword is the reason for this report while the second is the timestamp,
248 * making the chances of having those 2 fields at 0 fairly unlikely. A more
249 * detailed explanation is available in oa_buffer_check_unlocked().
251 * Most of the implementation details for this workaround are in
252 * oa_buffer_check_unlocked() and _append_oa_reports()
254 * Note for posterity: previously the driver used to define an effective tail
255 * pointer that lagged the real pointer by a 'tail margin' measured in bytes
256 * derived from %OA_TAIL_MARGIN_NSEC and the configured sampling frequency.
257 * This was flawed considering that the OA unit may also automatically generate
258 * non-periodic reports (such as on context switch) or the OA unit may be
259 * enabled without any periodic sampling.
261 #define OA_TAIL_MARGIN_NSEC 100000ULL
262 #define INVALID_TAIL_PTR 0xffffffff
264 /* The default frequency for checking whether the OA unit has written new
265 * reports to the circular OA buffer...
267 #define DEFAULT_POLL_FREQUENCY_HZ 200
268 #define DEFAULT_POLL_PERIOD_NS (NSEC_PER_SEC / DEFAULT_POLL_FREQUENCY_HZ)
270 /* for sysctl proc_dointvec_minmax of dev.i915.perf_stream_paranoid */
271 static u32 i915_perf_stream_paranoid = true;
273 /* The maximum exponent the hardware accepts is 63 (essentially it selects one
274 * of the 64bit timestamp bits to trigger reports from) but there's currently
275 * no known use case for sampling as infrequently as once per 47 thousand years.
277 * Since the timestamps included in OA reports are only 32bits it seems
278 * reasonable to limit the OA exponent where it's still possible to account for
279 * overflow in OA report timestamps.
281 #define OA_EXPONENT_MAX 31
283 #define INVALID_CTX_ID 0xffffffff
285 /* On Gen8+ automatically triggered OA reports include a 'reason' field... */
286 #define OAREPORT_REASON_MASK 0x3f
287 #define OAREPORT_REASON_MASK_EXTENDED 0x7f
288 #define OAREPORT_REASON_SHIFT 19
289 #define OAREPORT_REASON_TIMER (1<<0)
290 #define OAREPORT_REASON_CTX_SWITCH (1<<3)
291 #define OAREPORT_REASON_CLK_RATIO (1<<5)
293 #define HAS_MI_SET_PREDICATE(i915) (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
295 /* For sysctl proc_dointvec_minmax of i915_oa_max_sample_rate
297 * The highest sampling frequency we can theoretically program the OA unit
298 * with is always half the timestamp frequency: E.g. 6.25Mhz for Haswell.
300 * Initialized just before we register the sysctl parameter.
302 static int oa_sample_rate_hard_limit;
304 /* Theoretically we can program the OA unit to sample every 160ns but don't
305 * allow that by default unless root...
307 * The default threshold of 100000Hz is based on perf's similar
308 * kernel.perf_event_max_sample_rate sysctl parameter.
310 static u32 i915_oa_max_sample_rate = 100000;
312 /* XXX: beware if future OA HW adds new report formats that the current
313 * code assumes all reports have a power-of-two size and ~(size - 1) can
314 * be used as a mask to align the OA tail pointer.
316 static const struct i915_oa_format oa_formats[I915_OA_FORMAT_MAX] = {
317 [I915_OA_FORMAT_A13] = { 0, 64 },
318 [I915_OA_FORMAT_A29] = { 1, 128 },
319 [I915_OA_FORMAT_A13_B8_C8] = { 2, 128 },
320 /* A29_B8_C8 Disallowed as 192 bytes doesn't factor into buffer size */
321 [I915_OA_FORMAT_B4_C8] = { 4, 64 },
322 [I915_OA_FORMAT_A45_B8_C8] = { 5, 256 },
323 [I915_OA_FORMAT_B4_C8_A16] = { 6, 128 },
324 [I915_OA_FORMAT_C4_B8] = { 7, 64 },
325 [I915_OA_FORMAT_A12] = { 0, 64 },
326 [I915_OA_FORMAT_A12_B8_C8] = { 2, 128 },
327 [I915_OA_FORMAT_A32u40_A4u32_B8_C8] = { 5, 256 },
328 [I915_OAR_FORMAT_A32u40_A4u32_B8_C8] = { 5, 256 },
329 [I915_OA_FORMAT_A24u40_A14u32_B8_C8] = { 5, 256 },
330 [I915_OAM_FORMAT_MPEC8u64_B8_C8] = { 1, 192, TYPE_OAM, HDR_64_BIT },
331 [I915_OAM_FORMAT_MPEC8u32_B8_C8] = { 2, 128, TYPE_OAM, HDR_64_BIT },
334 static const u32 mtl_oa_base[] = {
335 [PERF_GROUP_OAM_SAMEDIA_0] = 0x393000,
338 #define SAMPLE_OA_REPORT (1<<0)
341 * struct perf_open_properties - for validated properties given to open a stream
342 * @sample_flags: `DRM_I915_PERF_PROP_SAMPLE_*` properties are tracked as flags
343 * @single_context: Whether a single or all gpu contexts should be monitored
344 * @hold_preemption: Whether the preemption is disabled for the filtered
346 * @ctx_handle: A gem ctx handle for use with @single_context
347 * @metrics_set: An ID for an OA unit metric set advertised via sysfs
348 * @oa_format: An OA unit HW report format
349 * @oa_periodic: Whether to enable periodic OA unit sampling
350 * @oa_period_exponent: The OA unit sampling period is derived from this
351 * @engine: The engine (typically rcs0) being monitored by the OA unit
352 * @has_sseu: Whether @sseu was specified by userspace
353 * @sseu: internal SSEU configuration computed either from the userspace
354 * specified configuration in the opening parameters or a default value
355 * (see get_default_sseu_config())
356 * @poll_oa_period: The period in nanoseconds at which the CPU will check for OA
359 * As read_properties_unlocked() enumerates and validates the properties given
360 * to open a stream of metrics the configuration is built up in the structure
361 * which starts out zero initialized.
363 struct perf_open_properties {
366 u64 single_context:1;
367 u64 hold_preemption:1;
370 /* OA sampling state */
374 int oa_period_exponent;
376 struct intel_engine_cs *engine;
379 struct intel_sseu sseu;
384 struct i915_oa_config_bo {
385 struct llist_node node;
387 struct i915_oa_config *oa_config;
388 struct i915_vma *vma;
391 static struct ctl_table_header *sysctl_header;
393 static enum hrtimer_restart oa_poll_check_timer_cb(struct hrtimer *hrtimer);
395 void i915_oa_config_release(struct kref *ref)
397 struct i915_oa_config *oa_config =
398 container_of(ref, typeof(*oa_config), ref);
400 kfree(oa_config->flex_regs);
401 kfree(oa_config->b_counter_regs);
402 kfree(oa_config->mux_regs);
404 kfree_rcu(oa_config, rcu);
407 struct i915_oa_config *
408 i915_perf_get_oa_config(struct i915_perf *perf, int metrics_set)
410 struct i915_oa_config *oa_config;
413 oa_config = idr_find(&perf->metrics_idr, metrics_set);
415 oa_config = i915_oa_config_get(oa_config);
421 static void free_oa_config_bo(struct i915_oa_config_bo *oa_bo)
423 i915_oa_config_put(oa_bo->oa_config);
424 i915_vma_put(oa_bo->vma);
429 struct i915_perf_regs *__oa_regs(struct i915_perf_stream *stream)
431 return &stream->engine->oa_group->regs;
434 static u32 gen12_oa_hw_tail_read(struct i915_perf_stream *stream)
436 struct intel_uncore *uncore = stream->uncore;
438 return intel_uncore_read(uncore, __oa_regs(stream)->oa_tail_ptr) &
439 GEN12_OAG_OATAILPTR_MASK;
442 static u32 gen8_oa_hw_tail_read(struct i915_perf_stream *stream)
444 struct intel_uncore *uncore = stream->uncore;
446 return intel_uncore_read(uncore, GEN8_OATAILPTR) & GEN8_OATAILPTR_MASK;
449 static u32 gen7_oa_hw_tail_read(struct i915_perf_stream *stream)
451 struct intel_uncore *uncore = stream->uncore;
452 u32 oastatus1 = intel_uncore_read(uncore, GEN7_OASTATUS1);
454 return oastatus1 & GEN7_OASTATUS1_TAIL_MASK;
457 #define oa_report_header_64bit(__s) \
458 ((__s)->oa_buffer.format->header == HDR_64_BIT)
460 static u64 oa_report_id(struct i915_perf_stream *stream, void *report)
462 return oa_report_header_64bit(stream) ? *(u64 *)report : *(u32 *)report;
465 static u64 oa_report_reason(struct i915_perf_stream *stream, void *report)
467 return (oa_report_id(stream, report) >> OAREPORT_REASON_SHIFT) &
468 (GRAPHICS_VER(stream->perf->i915) == 12 ?
469 OAREPORT_REASON_MASK_EXTENDED :
470 OAREPORT_REASON_MASK);
473 static void oa_report_id_clear(struct i915_perf_stream *stream, u32 *report)
475 if (oa_report_header_64bit(stream))
481 static bool oa_report_ctx_invalid(struct i915_perf_stream *stream, void *report)
483 return !(oa_report_id(stream, report) &
484 stream->perf->gen8_valid_ctx_bit) &&
485 GRAPHICS_VER(stream->perf->i915) <= 11;
488 static u64 oa_timestamp(struct i915_perf_stream *stream, void *report)
490 return oa_report_header_64bit(stream) ?
491 *((u64 *)report + 1) :
492 *((u32 *)report + 1);
495 static void oa_timestamp_clear(struct i915_perf_stream *stream, u32 *report)
497 if (oa_report_header_64bit(stream))
498 *(u64 *)&report[2] = 0;
503 static u32 oa_context_id(struct i915_perf_stream *stream, u32 *report)
505 u32 ctx_id = oa_report_header_64bit(stream) ? report[4] : report[2];
507 return ctx_id & stream->specific_ctx_id_mask;
510 static void oa_context_id_squash(struct i915_perf_stream *stream, u32 *report)
512 if (oa_report_header_64bit(stream))
513 report[4] = INVALID_CTX_ID;
515 report[2] = INVALID_CTX_ID;
519 * oa_buffer_check_unlocked - check for data and update tail ptr state
520 * @stream: i915 stream instance
522 * This is either called via fops (for blocking reads in user ctx) or the poll
523 * check hrtimer (atomic ctx) to check the OA buffer tail pointer and check
524 * if there is data available for userspace to read.
526 * This function is central to providing a workaround for the OA unit tail
527 * pointer having a race with respect to what data is visible to the CPU.
528 * It is responsible for reading tail pointers from the hardware and giving
529 * the pointers time to 'age' before they are made available for reading.
530 * (See description of OA_TAIL_MARGIN_NSEC above for further details.)
532 * Besides returning true when there is data available to read() this function
533 * also updates the tail, aging_tail and aging_timestamp in the oa_buffer
536 * Note: It's safe to read OA config state here unlocked, assuming that this is
537 * only called while the stream is enabled, while the global OA configuration
540 * Returns: %true if the OA buffer contains data, else %false
542 static bool oa_buffer_check_unlocked(struct i915_perf_stream *stream)
544 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
545 int report_size = stream->oa_buffer.format->size;
550 u32 partial_report_size;
552 /* We have to consider the (unlikely) possibility that read() errors
553 * could result in an OA buffer reset which might reset the head and
556 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
558 hw_tail = stream->perf->ops.oa_hw_tail_read(stream);
560 /* The tail pointer increases in 64 byte increments, not in report_size
561 * steps. Also the report size may not be a power of 2. Compute
562 * potentially partially landed report in the OA buffer
564 partial_report_size = OA_TAKEN(hw_tail, stream->oa_buffer.tail);
565 partial_report_size %= report_size;
567 /* Subtract partial amount off the tail */
568 hw_tail = gtt_offset + OA_TAKEN(hw_tail, partial_report_size);
570 now = ktime_get_mono_fast_ns();
572 if (hw_tail == stream->oa_buffer.aging_tail &&
573 (now - stream->oa_buffer.aging_timestamp) > OA_TAIL_MARGIN_NSEC) {
574 /* If the HW tail hasn't move since the last check and the HW
575 * tail has been aging for long enough, declare it the new
578 stream->oa_buffer.tail = stream->oa_buffer.aging_tail;
580 u32 head, tail, aged_tail;
582 /* NB: The head we observe here might effectively be a little
583 * out of date. If a read() is in progress, the head could be
584 * anywhere between this head and stream->oa_buffer.tail.
586 head = stream->oa_buffer.head - gtt_offset;
587 aged_tail = stream->oa_buffer.tail - gtt_offset;
589 hw_tail -= gtt_offset;
592 /* Walk the stream backward until we find a report with report
593 * id and timestmap not at 0. Since the circular buffer pointers
594 * progress by increments of 64 bytes and that reports can be up
595 * to 256 bytes long, we can't tell whether a report has fully
596 * landed in memory before the report id and timestamp of the
597 * following report have effectively landed.
599 * This is assuming that the writes of the OA unit land in
600 * memory in the order they were written to.
601 * If not : (╯°□°)╯︵ ┻━┻
603 while (OA_TAKEN(tail, aged_tail) >= report_size) {
604 void *report = stream->oa_buffer.vaddr + tail;
606 if (oa_report_id(stream, report) ||
607 oa_timestamp(stream, report))
610 tail = (tail - report_size) & (OA_BUFFER_SIZE - 1);
613 if (OA_TAKEN(hw_tail, tail) > report_size &&
614 __ratelimit(&stream->perf->tail_pointer_race))
615 drm_notice(&stream->uncore->i915->drm,
616 "unlanded report(s) head=0x%x tail=0x%x hw_tail=0x%x\n",
617 head, tail, hw_tail);
619 stream->oa_buffer.tail = gtt_offset + tail;
620 stream->oa_buffer.aging_tail = gtt_offset + hw_tail;
621 stream->oa_buffer.aging_timestamp = now;
624 pollin = OA_TAKEN(stream->oa_buffer.tail - gtt_offset,
625 stream->oa_buffer.head - gtt_offset) >= report_size;
627 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
633 * append_oa_status - Appends a status record to a userspace read() buffer.
634 * @stream: An i915-perf stream opened for OA metrics
635 * @buf: destination buffer given by userspace
636 * @count: the number of bytes userspace wants to read
637 * @offset: (inout): the current position for writing into @buf
638 * @type: The kind of status to report to userspace
640 * Writes a status record (such as `DRM_I915_PERF_RECORD_OA_REPORT_LOST`)
641 * into the userspace read() buffer.
643 * The @buf @offset will only be updated on success.
645 * Returns: 0 on success, negative error code on failure.
647 static int append_oa_status(struct i915_perf_stream *stream,
651 enum drm_i915_perf_record_type type)
653 struct drm_i915_perf_record_header header = { type, 0, sizeof(header) };
655 if ((count - *offset) < header.size)
658 if (copy_to_user(buf + *offset, &header, sizeof(header)))
661 (*offset) += header.size;
667 * append_oa_sample - Copies single OA report into userspace read() buffer.
668 * @stream: An i915-perf stream opened for OA metrics
669 * @buf: destination buffer given by userspace
670 * @count: the number of bytes userspace wants to read
671 * @offset: (inout): the current position for writing into @buf
672 * @report: A single OA report to (optionally) include as part of the sample
674 * The contents of a sample are configured through `DRM_I915_PERF_PROP_SAMPLE_*`
675 * properties when opening a stream, tracked as `stream->sample_flags`. This
676 * function copies the requested components of a single sample to the given
679 * The @buf @offset will only be updated on success.
681 * Returns: 0 on success, negative error code on failure.
683 static int append_oa_sample(struct i915_perf_stream *stream,
689 int report_size = stream->oa_buffer.format->size;
690 struct drm_i915_perf_record_header header;
691 int report_size_partial;
694 header.type = DRM_I915_PERF_RECORD_SAMPLE;
696 header.size = stream->sample_size;
698 if ((count - *offset) < header.size)
702 if (copy_to_user(buf, &header, sizeof(header)))
704 buf += sizeof(header);
706 oa_buf_end = stream->oa_buffer.vaddr + OA_BUFFER_SIZE;
707 report_size_partial = oa_buf_end - report;
709 if (report_size_partial < report_size) {
710 if (copy_to_user(buf, report, report_size_partial))
712 buf += report_size_partial;
714 if (copy_to_user(buf, stream->oa_buffer.vaddr,
715 report_size - report_size_partial))
717 } else if (copy_to_user(buf, report, report_size)) {
721 (*offset) += header.size;
727 * gen8_append_oa_reports - Copies all buffered OA reports into
728 * userspace read() buffer.
729 * @stream: An i915-perf stream opened for OA metrics
730 * @buf: destination buffer given by userspace
731 * @count: the number of bytes userspace wants to read
732 * @offset: (inout): the current position for writing into @buf
734 * Notably any error condition resulting in a short read (-%ENOSPC or
735 * -%EFAULT) will be returned even though one or more records may
736 * have been successfully copied. In this case it's up to the caller
737 * to decide if the error should be squashed before returning to
740 * Note: reports are consumed from the head, and appended to the
741 * tail, so the tail chases the head?... If you think that's mad
742 * and back-to-front you're not alone, but this follows the
743 * Gen PRM naming convention.
745 * Returns: 0 on success, negative error code on failure.
747 static int gen8_append_oa_reports(struct i915_perf_stream *stream,
752 struct intel_uncore *uncore = stream->uncore;
753 int report_size = stream->oa_buffer.format->size;
754 u8 *oa_buf_base = stream->oa_buffer.vaddr;
755 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
756 u32 mask = (OA_BUFFER_SIZE - 1);
757 size_t start_offset = *offset;
762 if (drm_WARN_ON(&uncore->i915->drm, !stream->enabled))
765 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
767 head = stream->oa_buffer.head;
768 tail = stream->oa_buffer.tail;
770 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
773 * NB: oa_buffer.head/tail include the gtt_offset which we don't want
774 * while indexing relative to oa_buf_base.
780 * An out of bounds or misaligned head or tail pointer implies a driver
781 * bug since we validate + align the tail pointers we read from the
782 * hardware and we are in full control of the head pointer which should
783 * only be incremented by multiples of the report size.
785 if (drm_WARN_ONCE(&uncore->i915->drm,
786 head > OA_BUFFER_SIZE ||
787 tail > OA_BUFFER_SIZE,
788 "Inconsistent OA buffer pointers: head = %u, tail = %u\n",
794 OA_TAKEN(tail, head);
795 head = (head + report_size) & mask) {
796 u8 *report = oa_buf_base + head;
797 u32 *report32 = (void *)report;
802 * The reason field includes flags identifying what
803 * triggered this specific report (mostly timer
804 * triggered or e.g. due to a context switch).
806 * In MMIO triggered reports, some platforms do not set the
807 * reason bit in this field and it is valid to have a reason
810 reason = oa_report_reason(stream, report);
811 ctx_id = oa_context_id(stream, report32);
814 * Squash whatever is in the CTX_ID field if it's marked as
815 * invalid to be sure we avoid false-positive, single-context
818 * Note: that we don't clear the valid_ctx_bit so userspace can
819 * understand that the ID has been squashed by the kernel.
821 if (oa_report_ctx_invalid(stream, report)) {
822 ctx_id = INVALID_CTX_ID;
823 oa_context_id_squash(stream, report32);
827 * NB: For Gen 8 the OA unit no longer supports clock gating
828 * off for a specific context and the kernel can't securely
829 * stop the counters from updating as system-wide / global
832 * Automatic reports now include a context ID so reports can be
833 * filtered on the cpu but it's not worth trying to
834 * automatically subtract/hide counter progress for other
835 * contexts while filtering since we can't stop userspace
836 * issuing MI_REPORT_PERF_COUNT commands which would still
837 * provide a side-band view of the real values.
839 * To allow userspace (such as Mesa/GL_INTEL_performance_query)
840 * to normalize counters for a single filtered context then it
841 * needs be forwarded bookend context-switch reports so that it
842 * can track switches in between MI_REPORT_PERF_COUNT commands
843 * and can itself subtract/ignore the progress of counters
844 * associated with other contexts. Note that the hardware
845 * automatically triggers reports when switching to a new
846 * context which are tagged with the ID of the newly active
847 * context. To avoid the complexity (and likely fragility) of
848 * reading ahead while parsing reports to try and minimize
849 * forwarding redundant context switch reports (i.e. between
850 * other, unrelated contexts) we simply elect to forward them
853 * We don't rely solely on the reason field to identify context
854 * switches since it's not-uncommon for periodic samples to
855 * identify a switch before any 'context switch' report.
858 stream->specific_ctx_id == ctx_id ||
859 stream->oa_buffer.last_ctx_id == stream->specific_ctx_id ||
860 reason & OAREPORT_REASON_CTX_SWITCH) {
863 * While filtering for a single context we avoid
864 * leaking the IDs of other contexts.
867 stream->specific_ctx_id != ctx_id) {
868 oa_context_id_squash(stream, report32);
871 ret = append_oa_sample(stream, buf, count, offset,
876 stream->oa_buffer.last_ctx_id = ctx_id;
880 * Clear out the report id and timestamp as a means to detect unlanded
883 oa_report_id_clear(stream, report32);
884 oa_timestamp_clear(stream, report32);
887 if (start_offset != *offset) {
888 i915_reg_t oaheadptr;
890 oaheadptr = GRAPHICS_VER(stream->perf->i915) == 12 ?
891 __oa_regs(stream)->oa_head_ptr :
894 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
897 * We removed the gtt_offset for the copy loop above, indexing
898 * relative to oa_buf_base so put back here...
901 intel_uncore_write(uncore, oaheadptr,
902 head & GEN12_OAG_OAHEADPTR_MASK);
903 stream->oa_buffer.head = head;
905 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
912 * gen8_oa_read - copy status records then buffered OA reports
913 * @stream: An i915-perf stream opened for OA metrics
914 * @buf: destination buffer given by userspace
915 * @count: the number of bytes userspace wants to read
916 * @offset: (inout): the current position for writing into @buf
918 * Checks OA unit status registers and if necessary appends corresponding
919 * status records for userspace (such as for a buffer full condition) and then
920 * initiate appending any buffered OA reports.
922 * Updates @offset according to the number of bytes successfully copied into
923 * the userspace buffer.
925 * NB: some data may be successfully copied to the userspace buffer
926 * even if an error is returned, and this is reflected in the
929 * Returns: zero on success or a negative error code
931 static int gen8_oa_read(struct i915_perf_stream *stream,
936 struct intel_uncore *uncore = stream->uncore;
938 i915_reg_t oastatus_reg;
941 if (drm_WARN_ON(&uncore->i915->drm, !stream->oa_buffer.vaddr))
944 oastatus_reg = GRAPHICS_VER(stream->perf->i915) == 12 ?
945 __oa_regs(stream)->oa_status :
948 oastatus = intel_uncore_read(uncore, oastatus_reg);
951 * We treat OABUFFER_OVERFLOW as a significant error:
953 * Although theoretically we could handle this more gracefully
954 * sometimes, some Gens don't correctly suppress certain
955 * automatically triggered reports in this condition and so we
956 * have to assume that old reports are now being trampled
959 * Considering how we don't currently give userspace control
960 * over the OA buffer size and always configure a large 16MB
961 * buffer, then a buffer overflow does anyway likely indicate
962 * that something has gone quite badly wrong.
964 if (oastatus & GEN8_OASTATUS_OABUFFER_OVERFLOW) {
965 ret = append_oa_status(stream, buf, count, offset,
966 DRM_I915_PERF_RECORD_OA_BUFFER_LOST);
970 drm_dbg(&stream->perf->i915->drm,
971 "OA buffer overflow (exponent = %d): force restart\n",
972 stream->period_exponent);
974 stream->perf->ops.oa_disable(stream);
975 stream->perf->ops.oa_enable(stream);
978 * Note: .oa_enable() is expected to re-init the oabuffer and
979 * reset GEN8_OASTATUS for us
981 oastatus = intel_uncore_read(uncore, oastatus_reg);
984 if (oastatus & GEN8_OASTATUS_REPORT_LOST) {
985 ret = append_oa_status(stream, buf, count, offset,
986 DRM_I915_PERF_RECORD_OA_REPORT_LOST);
990 intel_uncore_rmw(uncore, oastatus_reg,
991 GEN8_OASTATUS_COUNTER_OVERFLOW |
992 GEN8_OASTATUS_REPORT_LOST,
993 IS_GRAPHICS_VER(uncore->i915, 8, 11) ?
994 (GEN8_OASTATUS_HEAD_POINTER_WRAP |
995 GEN8_OASTATUS_TAIL_POINTER_WRAP) : 0);
998 return gen8_append_oa_reports(stream, buf, count, offset);
1002 * gen7_append_oa_reports - Copies all buffered OA reports into
1003 * userspace read() buffer.
1004 * @stream: An i915-perf stream opened for OA metrics
1005 * @buf: destination buffer given by userspace
1006 * @count: the number of bytes userspace wants to read
1007 * @offset: (inout): the current position for writing into @buf
1009 * Notably any error condition resulting in a short read (-%ENOSPC or
1010 * -%EFAULT) will be returned even though one or more records may
1011 * have been successfully copied. In this case it's up to the caller
1012 * to decide if the error should be squashed before returning to
1015 * Note: reports are consumed from the head, and appended to the
1016 * tail, so the tail chases the head?... If you think that's mad
1017 * and back-to-front you're not alone, but this follows the
1018 * Gen PRM naming convention.
1020 * Returns: 0 on success, negative error code on failure.
1022 static int gen7_append_oa_reports(struct i915_perf_stream *stream,
1027 struct intel_uncore *uncore = stream->uncore;
1028 int report_size = stream->oa_buffer.format->size;
1029 u8 *oa_buf_base = stream->oa_buffer.vaddr;
1030 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
1031 u32 mask = (OA_BUFFER_SIZE - 1);
1032 size_t start_offset = *offset;
1033 unsigned long flags;
1037 if (drm_WARN_ON(&uncore->i915->drm, !stream->enabled))
1040 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
1042 head = stream->oa_buffer.head;
1043 tail = stream->oa_buffer.tail;
1045 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
1047 /* NB: oa_buffer.head/tail include the gtt_offset which we don't want
1048 * while indexing relative to oa_buf_base.
1053 /* An out of bounds or misaligned head or tail pointer implies a driver
1054 * bug since we validate + align the tail pointers we read from the
1055 * hardware and we are in full control of the head pointer which should
1056 * only be incremented by multiples of the report size (notably also
1057 * all a power of two).
1059 if (drm_WARN_ONCE(&uncore->i915->drm,
1060 head > OA_BUFFER_SIZE || head % report_size ||
1061 tail > OA_BUFFER_SIZE || tail % report_size,
1062 "Inconsistent OA buffer pointers: head = %u, tail = %u\n",
1068 OA_TAKEN(tail, head);
1069 head = (head + report_size) & mask) {
1070 u8 *report = oa_buf_base + head;
1071 u32 *report32 = (void *)report;
1073 /* All the report sizes factor neatly into the buffer
1074 * size so we never expect to see a report split
1075 * between the beginning and end of the buffer.
1077 * Given the initial alignment check a misalignment
1078 * here would imply a driver bug that would result
1081 if (drm_WARN_ON(&uncore->i915->drm,
1082 (OA_BUFFER_SIZE - head) < report_size)) {
1083 drm_err(&uncore->i915->drm,
1084 "Spurious OA head ptr: non-integral report offset\n");
1088 /* The report-ID field for periodic samples includes
1089 * some undocumented flags related to what triggered
1090 * the report and is never expected to be zero so we
1091 * can check that the report isn't invalid before
1092 * copying it to userspace...
1094 if (report32[0] == 0) {
1095 if (__ratelimit(&stream->perf->spurious_report_rs))
1096 drm_notice(&uncore->i915->drm,
1097 "Skipping spurious, invalid OA report\n");
1101 ret = append_oa_sample(stream, buf, count, offset, report);
1105 /* Clear out the first 2 dwords as a mean to detect unlanded
1112 if (start_offset != *offset) {
1113 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
1115 /* We removed the gtt_offset for the copy loop above, indexing
1116 * relative to oa_buf_base so put back here...
1120 intel_uncore_write(uncore, GEN7_OASTATUS2,
1121 (head & GEN7_OASTATUS2_HEAD_MASK) |
1122 GEN7_OASTATUS2_MEM_SELECT_GGTT);
1123 stream->oa_buffer.head = head;
1125 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
1132 * gen7_oa_read - copy status records then buffered OA reports
1133 * @stream: An i915-perf stream opened for OA metrics
1134 * @buf: destination buffer given by userspace
1135 * @count: the number of bytes userspace wants to read
1136 * @offset: (inout): the current position for writing into @buf
1138 * Checks Gen 7 specific OA unit status registers and if necessary appends
1139 * corresponding status records for userspace (such as for a buffer full
1140 * condition) and then initiate appending any buffered OA reports.
1142 * Updates @offset according to the number of bytes successfully copied into
1143 * the userspace buffer.
1145 * Returns: zero on success or a negative error code
1147 static int gen7_oa_read(struct i915_perf_stream *stream,
1152 struct intel_uncore *uncore = stream->uncore;
1156 if (drm_WARN_ON(&uncore->i915->drm, !stream->oa_buffer.vaddr))
1159 oastatus1 = intel_uncore_read(uncore, GEN7_OASTATUS1);
1161 /* XXX: On Haswell we don't have a safe way to clear oastatus1
1162 * bits while the OA unit is enabled (while the tail pointer
1163 * may be updated asynchronously) so we ignore status bits
1164 * that have already been reported to userspace.
1166 oastatus1 &= ~stream->perf->gen7_latched_oastatus1;
1168 /* We treat OABUFFER_OVERFLOW as a significant error:
1170 * - The status can be interpreted to mean that the buffer is
1171 * currently full (with a higher precedence than OA_TAKEN()
1172 * which will start to report a near-empty buffer after an
1173 * overflow) but it's awkward that we can't clear the status
1174 * on Haswell, so without a reset we won't be able to catch
1177 * - Since it also implies the HW has started overwriting old
1178 * reports it may also affect our sanity checks for invalid
1179 * reports when copying to userspace that assume new reports
1180 * are being written to cleared memory.
1182 * - In the future we may want to introduce a flight recorder
1183 * mode where the driver will automatically maintain a safe
1184 * guard band between head/tail, avoiding this overflow
1185 * condition, but we avoid the added driver complexity for
1188 if (unlikely(oastatus1 & GEN7_OASTATUS1_OABUFFER_OVERFLOW)) {
1189 ret = append_oa_status(stream, buf, count, offset,
1190 DRM_I915_PERF_RECORD_OA_BUFFER_LOST);
1194 drm_dbg(&stream->perf->i915->drm,
1195 "OA buffer overflow (exponent = %d): force restart\n",
1196 stream->period_exponent);
1198 stream->perf->ops.oa_disable(stream);
1199 stream->perf->ops.oa_enable(stream);
1201 oastatus1 = intel_uncore_read(uncore, GEN7_OASTATUS1);
1204 if (unlikely(oastatus1 & GEN7_OASTATUS1_REPORT_LOST)) {
1205 ret = append_oa_status(stream, buf, count, offset,
1206 DRM_I915_PERF_RECORD_OA_REPORT_LOST);
1209 stream->perf->gen7_latched_oastatus1 |=
1210 GEN7_OASTATUS1_REPORT_LOST;
1213 return gen7_append_oa_reports(stream, buf, count, offset);
1217 * i915_oa_wait_unlocked - handles blocking IO until OA data available
1218 * @stream: An i915-perf stream opened for OA metrics
1220 * Called when userspace tries to read() from a blocking stream FD opened
1221 * for OA metrics. It waits until the hrtimer callback finds a non-empty
1222 * OA buffer and wakes us.
1224 * Note: it's acceptable to have this return with some false positives
1225 * since any subsequent read handling will return -EAGAIN if there isn't
1226 * really data ready for userspace yet.
1228 * Returns: zero on success or a negative error code
1230 static int i915_oa_wait_unlocked(struct i915_perf_stream *stream)
1232 /* We would wait indefinitely if periodic sampling is not enabled */
1233 if (!stream->periodic)
1236 return wait_event_interruptible(stream->poll_wq,
1237 oa_buffer_check_unlocked(stream));
1241 * i915_oa_poll_wait - call poll_wait() for an OA stream poll()
1242 * @stream: An i915-perf stream opened for OA metrics
1243 * @file: An i915 perf stream file
1244 * @wait: poll() state table
1246 * For handling userspace polling on an i915 perf stream opened for OA metrics,
1247 * this starts a poll_wait with the wait queue that our hrtimer callback wakes
1248 * when it sees data ready to read in the circular OA buffer.
1250 static void i915_oa_poll_wait(struct i915_perf_stream *stream,
1254 poll_wait(file, &stream->poll_wq, wait);
1258 * i915_oa_read - just calls through to &i915_oa_ops->read
1259 * @stream: An i915-perf stream opened for OA metrics
1260 * @buf: destination buffer given by userspace
1261 * @count: the number of bytes userspace wants to read
1262 * @offset: (inout): the current position for writing into @buf
1264 * Updates @offset according to the number of bytes successfully copied into
1265 * the userspace buffer.
1267 * Returns: zero on success or a negative error code
1269 static int i915_oa_read(struct i915_perf_stream *stream,
1274 return stream->perf->ops.read(stream, buf, count, offset);
1277 static struct intel_context *oa_pin_context(struct i915_perf_stream *stream)
1279 struct i915_gem_engines_iter it;
1280 struct i915_gem_context *ctx = stream->ctx;
1281 struct intel_context *ce;
1282 struct i915_gem_ww_ctx ww;
1285 for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
1286 if (ce->engine != stream->engine) /* first match! */
1292 i915_gem_context_unlock_engines(ctx);
1295 return ERR_PTR(err);
1297 i915_gem_ww_ctx_init(&ww, true);
1300 * As the ID is the gtt offset of the context's vma we
1301 * pin the vma to ensure the ID remains fixed.
1303 err = intel_context_pin_ww(ce, &ww);
1304 if (err == -EDEADLK) {
1305 err = i915_gem_ww_ctx_backoff(&ww);
1309 i915_gem_ww_ctx_fini(&ww);
1312 return ERR_PTR(err);
1314 stream->pinned_ctx = ce;
1315 return stream->pinned_ctx;
1319 __store_reg_to_mem(struct i915_request *rq, i915_reg_t reg, u32 ggtt_offset)
1323 cmd = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
1324 if (GRAPHICS_VER(rq->engine->i915) >= 8)
1327 cs = intel_ring_begin(rq, 4);
1332 *cs++ = i915_mmio_reg_offset(reg);
1333 *cs++ = ggtt_offset;
1336 intel_ring_advance(rq, cs);
1342 __read_reg(struct intel_context *ce, i915_reg_t reg, u32 ggtt_offset)
1344 struct i915_request *rq;
1347 rq = i915_request_create(ce);
1351 i915_request_get(rq);
1353 err = __store_reg_to_mem(rq, reg, ggtt_offset);
1355 i915_request_add(rq);
1356 if (!err && i915_request_wait(rq, 0, HZ / 2) < 0)
1359 i915_request_put(rq);
1365 gen12_guc_sw_ctx_id(struct intel_context *ce, u32 *ctx_id)
1367 struct i915_vma *scratch;
1371 scratch = __vm_create_scratch_for_read_pinned(&ce->engine->gt->ggtt->vm, 4);
1372 if (IS_ERR(scratch))
1373 return PTR_ERR(scratch);
1375 err = i915_vma_sync(scratch);
1379 err = __read_reg(ce, RING_EXECLIST_STATUS_HI(ce->engine->mmio_base),
1380 i915_ggtt_offset(scratch));
1384 val = i915_gem_object_pin_map_unlocked(scratch->obj, I915_MAP_WB);
1391 i915_gem_object_unpin_map(scratch->obj);
1394 i915_vma_unpin_and_release(&scratch, 0);
1399 * For execlist mode of submission, pick an unused context id
1400 * 0 - (NUM_CONTEXT_TAG -1) are used by other contexts
1401 * XXX_MAX_CONTEXT_HW_ID is used by idle context
1403 * For GuC mode of submission read context id from the upper dword of the
1404 * EXECLIST_STATUS register. Note that we read this value only once and expect
1405 * that the value stays fixed for the entire OA use case. There are cases where
1406 * GuC KMD implementation may deregister a context to reuse it's context id, but
1407 * we prevent that from happening to the OA context by pinning it.
1409 static int gen12_get_render_context_id(struct i915_perf_stream *stream)
1414 if (intel_engine_uses_guc(stream->engine)) {
1415 ret = gen12_guc_sw_ctx_id(stream->pinned_ctx, &ctx_id);
1419 mask = ((1U << GEN12_GUC_SW_CTX_ID_WIDTH) - 1) <<
1420 (GEN12_GUC_SW_CTX_ID_SHIFT - 32);
1421 } else if (GRAPHICS_VER_FULL(stream->engine->i915) >= IP_VER(12, 50)) {
1422 ctx_id = (XEHP_MAX_CONTEXT_HW_ID - 1) <<
1423 (XEHP_SW_CTX_ID_SHIFT - 32);
1425 mask = ((1U << XEHP_SW_CTX_ID_WIDTH) - 1) <<
1426 (XEHP_SW_CTX_ID_SHIFT - 32);
1428 ctx_id = (GEN12_MAX_CONTEXT_HW_ID - 1) <<
1429 (GEN11_SW_CTX_ID_SHIFT - 32);
1431 mask = ((1U << GEN11_SW_CTX_ID_WIDTH) - 1) <<
1432 (GEN11_SW_CTX_ID_SHIFT - 32);
1434 stream->specific_ctx_id = ctx_id & mask;
1435 stream->specific_ctx_id_mask = mask;
1440 static bool oa_find_reg_in_lri(u32 *state, u32 reg, u32 *offset, u32 end)
1443 u32 len = min(MI_LRI_LEN(state[idx]) + idx, end);
1447 for (; idx < len; idx += 2) {
1448 if (state[idx] == reg) {
1458 static u32 oa_context_image_offset(struct intel_context *ce, u32 reg)
1460 u32 offset, len = (ce->engine->context_size - PAGE_SIZE) / 4;
1461 u32 *state = ce->lrc_reg_state;
1463 if (drm_WARN_ON(&ce->engine->i915->drm, !state))
1466 for (offset = 0; offset < len; ) {
1467 if (IS_MI_LRI_CMD(state[offset])) {
1469 * We expect reg-value pairs in MI_LRI command, so
1470 * MI_LRI_LEN() should be even, if not, issue a warning.
1472 drm_WARN_ON(&ce->engine->i915->drm,
1473 MI_LRI_LEN(state[offset]) & 0x1);
1475 if (oa_find_reg_in_lri(state, reg, &offset, len))
1482 return offset < len ? offset : U32_MAX;
1485 static int set_oa_ctx_ctrl_offset(struct intel_context *ce)
1487 i915_reg_t reg = GEN12_OACTXCONTROL(ce->engine->mmio_base);
1488 struct i915_perf *perf = &ce->engine->i915->perf;
1489 u32 offset = perf->ctx_oactxctrl_offset;
1491 /* Do this only once. Failure is stored as offset of U32_MAX */
1495 offset = oa_context_image_offset(ce, i915_mmio_reg_offset(reg));
1496 perf->ctx_oactxctrl_offset = offset;
1498 drm_dbg(&ce->engine->i915->drm,
1499 "%s oa ctx control at 0x%08x dword offset\n",
1500 ce->engine->name, offset);
1503 return offset && offset != U32_MAX ? 0 : -ENODEV;
1506 static bool engine_supports_mi_query(struct intel_engine_cs *engine)
1508 return engine->class == RENDER_CLASS;
1512 * oa_get_render_ctx_id - determine and hold ctx hw id
1513 * @stream: An i915-perf stream opened for OA metrics
1515 * Determine the render context hw id, and ensure it remains fixed for the
1516 * lifetime of the stream. This ensures that we don't have to worry about
1517 * updating the context ID in OACONTROL on the fly.
1519 * Returns: zero on success or a negative error code
1521 static int oa_get_render_ctx_id(struct i915_perf_stream *stream)
1523 struct intel_context *ce;
1526 ce = oa_pin_context(stream);
1530 if (engine_supports_mi_query(stream->engine) &&
1531 HAS_LOGICAL_RING_CONTEXTS(stream->perf->i915)) {
1533 * We are enabling perf query here. If we don't find the context
1534 * offset here, just return an error.
1536 ret = set_oa_ctx_ctrl_offset(ce);
1538 intel_context_unpin(ce);
1539 drm_err(&stream->perf->i915->drm,
1540 "Enabling perf query failed for %s\n",
1541 stream->engine->name);
1546 switch (GRAPHICS_VER(ce->engine->i915)) {
1549 * On Haswell we don't do any post processing of the reports
1550 * and don't need to use the mask.
1552 stream->specific_ctx_id = i915_ggtt_offset(ce->state);
1553 stream->specific_ctx_id_mask = 0;
1559 if (intel_engine_uses_guc(ce->engine)) {
1561 * When using GuC, the context descriptor we write in
1562 * i915 is read by GuC and rewritten before it's
1563 * actually written into the hardware. The LRCA is
1564 * what is put into the context id field of the
1565 * context descriptor by GuC. Because it's aligned to
1566 * a page, the lower 12bits are always at 0 and
1567 * dropped by GuC. They won't be part of the context
1568 * ID in the OA reports, so squash those lower bits.
1570 stream->specific_ctx_id = ce->lrc.lrca >> 12;
1573 * GuC uses the top bit to signal proxy submission, so
1576 stream->specific_ctx_id_mask =
1577 (1U << (GEN8_CTX_ID_WIDTH - 1)) - 1;
1579 stream->specific_ctx_id_mask =
1580 (1U << GEN8_CTX_ID_WIDTH) - 1;
1581 stream->specific_ctx_id = stream->specific_ctx_id_mask;
1587 ret = gen12_get_render_context_id(stream);
1591 MISSING_CASE(GRAPHICS_VER(ce->engine->i915));
1594 ce->tag = stream->specific_ctx_id;
1596 drm_dbg(&stream->perf->i915->drm,
1597 "filtering on ctx_id=0x%x ctx_id_mask=0x%x\n",
1598 stream->specific_ctx_id,
1599 stream->specific_ctx_id_mask);
1605 * oa_put_render_ctx_id - counterpart to oa_get_render_ctx_id releases hold
1606 * @stream: An i915-perf stream opened for OA metrics
1608 * In case anything needed doing to ensure the context HW ID would remain valid
1609 * for the lifetime of the stream, then that can be undone here.
1611 static void oa_put_render_ctx_id(struct i915_perf_stream *stream)
1613 struct intel_context *ce;
1615 ce = fetch_and_zero(&stream->pinned_ctx);
1617 ce->tag = 0; /* recomputed on next submission after parking */
1618 intel_context_unpin(ce);
1621 stream->specific_ctx_id = INVALID_CTX_ID;
1622 stream->specific_ctx_id_mask = 0;
1626 free_oa_buffer(struct i915_perf_stream *stream)
1628 i915_vma_unpin_and_release(&stream->oa_buffer.vma,
1629 I915_VMA_RELEASE_MAP);
1631 stream->oa_buffer.vaddr = NULL;
1635 free_oa_configs(struct i915_perf_stream *stream)
1637 struct i915_oa_config_bo *oa_bo, *tmp;
1639 i915_oa_config_put(stream->oa_config);
1640 llist_for_each_entry_safe(oa_bo, tmp, stream->oa_config_bos.first, node)
1641 free_oa_config_bo(oa_bo);
1645 free_noa_wait(struct i915_perf_stream *stream)
1647 i915_vma_unpin_and_release(&stream->noa_wait, 0);
1650 static bool engine_supports_oa(const struct intel_engine_cs *engine)
1652 return engine->oa_group;
1655 static bool engine_supports_oa_format(struct intel_engine_cs *engine, int type)
1657 return engine->oa_group && engine->oa_group->type == type;
1660 static void i915_oa_stream_destroy(struct i915_perf_stream *stream)
1662 struct i915_perf *perf = stream->perf;
1663 struct intel_gt *gt = stream->engine->gt;
1664 struct i915_perf_group *g = stream->engine->oa_group;
1666 if (WARN_ON(stream != g->exclusive_stream))
1670 * Unset exclusive_stream first, it will be checked while disabling
1671 * the metric set on gen8+.
1673 * See i915_oa_init_reg_state() and lrc_configure_all_contexts()
1675 WRITE_ONCE(g->exclusive_stream, NULL);
1676 perf->ops.disable_metric_set(stream);
1678 free_oa_buffer(stream);
1681 * Wa_16011777198:dg2: Unset the override of GUCRC mode to enable rc6.
1683 if (stream->override_gucrc)
1684 drm_WARN_ON(>->i915->drm,
1685 intel_guc_slpc_unset_gucrc_mode(>->uc.guc.slpc));
1687 intel_uncore_forcewake_put(stream->uncore, FORCEWAKE_ALL);
1688 intel_engine_pm_put(stream->engine);
1691 oa_put_render_ctx_id(stream);
1693 free_oa_configs(stream);
1694 free_noa_wait(stream);
1696 if (perf->spurious_report_rs.missed) {
1697 drm_notice(>->i915->drm,
1698 "%d spurious OA report notices suppressed due to ratelimiting\n",
1699 perf->spurious_report_rs.missed);
1703 static void gen7_init_oa_buffer(struct i915_perf_stream *stream)
1705 struct intel_uncore *uncore = stream->uncore;
1706 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
1707 unsigned long flags;
1709 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
1711 /* Pre-DevBDW: OABUFFER must be set with counters off,
1712 * before OASTATUS1, but after OASTATUS2
1714 intel_uncore_write(uncore, GEN7_OASTATUS2, /* head */
1715 gtt_offset | GEN7_OASTATUS2_MEM_SELECT_GGTT);
1716 stream->oa_buffer.head = gtt_offset;
1718 intel_uncore_write(uncore, GEN7_OABUFFER, gtt_offset);
1720 intel_uncore_write(uncore, GEN7_OASTATUS1, /* tail */
1721 gtt_offset | OABUFFER_SIZE_16M);
1723 /* Mark that we need updated tail pointers to read from... */
1724 stream->oa_buffer.aging_tail = INVALID_TAIL_PTR;
1725 stream->oa_buffer.tail = gtt_offset;
1727 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
1729 /* On Haswell we have to track which OASTATUS1 flags we've
1730 * already seen since they can't be cleared while periodic
1731 * sampling is enabled.
1733 stream->perf->gen7_latched_oastatus1 = 0;
1735 /* NB: although the OA buffer will initially be allocated
1736 * zeroed via shmfs (and so this memset is redundant when
1737 * first allocating), we may re-init the OA buffer, either
1738 * when re-enabling a stream or in error/reset paths.
1740 * The reason we clear the buffer for each re-init is for the
1741 * sanity check in gen7_append_oa_reports() that looks at the
1742 * report-id field to make sure it's non-zero which relies on
1743 * the assumption that new reports are being written to zeroed
1746 memset(stream->oa_buffer.vaddr, 0, OA_BUFFER_SIZE);
1749 static void gen8_init_oa_buffer(struct i915_perf_stream *stream)
1751 struct intel_uncore *uncore = stream->uncore;
1752 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
1753 unsigned long flags;
1755 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
1757 intel_uncore_write(uncore, GEN8_OASTATUS, 0);
1758 intel_uncore_write(uncore, GEN8_OAHEADPTR, gtt_offset);
1759 stream->oa_buffer.head = gtt_offset;
1761 intel_uncore_write(uncore, GEN8_OABUFFER_UDW, 0);
1766 * "This MMIO must be set before the OATAILPTR
1767 * register and after the OAHEADPTR register. This is
1768 * to enable proper functionality of the overflow
1771 intel_uncore_write(uncore, GEN8_OABUFFER, gtt_offset |
1772 OABUFFER_SIZE_16M | GEN8_OABUFFER_MEM_SELECT_GGTT);
1773 intel_uncore_write(uncore, GEN8_OATAILPTR, gtt_offset & GEN8_OATAILPTR_MASK);
1775 /* Mark that we need updated tail pointers to read from... */
1776 stream->oa_buffer.aging_tail = INVALID_TAIL_PTR;
1777 stream->oa_buffer.tail = gtt_offset;
1780 * Reset state used to recognise context switches, affecting which
1781 * reports we will forward to userspace while filtering for a single
1784 stream->oa_buffer.last_ctx_id = INVALID_CTX_ID;
1786 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
1789 * NB: although the OA buffer will initially be allocated
1790 * zeroed via shmfs (and so this memset is redundant when
1791 * first allocating), we may re-init the OA buffer, either
1792 * when re-enabling a stream or in error/reset paths.
1794 * The reason we clear the buffer for each re-init is for the
1795 * sanity check in gen8_append_oa_reports() that looks at the
1796 * reason field to make sure it's non-zero which relies on
1797 * the assumption that new reports are being written to zeroed
1800 memset(stream->oa_buffer.vaddr, 0, OA_BUFFER_SIZE);
1803 static void gen12_init_oa_buffer(struct i915_perf_stream *stream)
1805 struct intel_uncore *uncore = stream->uncore;
1806 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
1807 unsigned long flags;
1809 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
1811 intel_uncore_write(uncore, __oa_regs(stream)->oa_status, 0);
1812 intel_uncore_write(uncore, __oa_regs(stream)->oa_head_ptr,
1813 gtt_offset & GEN12_OAG_OAHEADPTR_MASK);
1814 stream->oa_buffer.head = gtt_offset;
1819 * "This MMIO must be set before the OATAILPTR
1820 * register and after the OAHEADPTR register. This is
1821 * to enable proper functionality of the overflow
1824 intel_uncore_write(uncore, __oa_regs(stream)->oa_buffer, gtt_offset |
1825 OABUFFER_SIZE_16M | GEN8_OABUFFER_MEM_SELECT_GGTT);
1826 intel_uncore_write(uncore, __oa_regs(stream)->oa_tail_ptr,
1827 gtt_offset & GEN12_OAG_OATAILPTR_MASK);
1829 /* Mark that we need updated tail pointers to read from... */
1830 stream->oa_buffer.aging_tail = INVALID_TAIL_PTR;
1831 stream->oa_buffer.tail = gtt_offset;
1834 * Reset state used to recognise context switches, affecting which
1835 * reports we will forward to userspace while filtering for a single
1838 stream->oa_buffer.last_ctx_id = INVALID_CTX_ID;
1840 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
1843 * NB: although the OA buffer will initially be allocated
1844 * zeroed via shmfs (and so this memset is redundant when
1845 * first allocating), we may re-init the OA buffer, either
1846 * when re-enabling a stream or in error/reset paths.
1848 * The reason we clear the buffer for each re-init is for the
1849 * sanity check in gen8_append_oa_reports() that looks at the
1850 * reason field to make sure it's non-zero which relies on
1851 * the assumption that new reports are being written to zeroed
1854 memset(stream->oa_buffer.vaddr, 0,
1855 stream->oa_buffer.vma->size);
1858 static int alloc_oa_buffer(struct i915_perf_stream *stream)
1860 struct drm_i915_private *i915 = stream->perf->i915;
1861 struct intel_gt *gt = stream->engine->gt;
1862 struct drm_i915_gem_object *bo;
1863 struct i915_vma *vma;
1866 if (drm_WARN_ON(&i915->drm, stream->oa_buffer.vma))
1869 BUILD_BUG_ON_NOT_POWER_OF_2(OA_BUFFER_SIZE);
1870 BUILD_BUG_ON(OA_BUFFER_SIZE < SZ_128K || OA_BUFFER_SIZE > SZ_16M);
1872 bo = i915_gem_object_create_shmem(stream->perf->i915, OA_BUFFER_SIZE);
1874 drm_err(&i915->drm, "Failed to allocate OA buffer\n");
1878 i915_gem_object_set_cache_coherency(bo, I915_CACHE_LLC);
1880 /* PreHSW required 512K alignment, HSW requires 16M */
1881 vma = i915_vma_instance(bo, >->ggtt->vm, NULL);
1888 * PreHSW required 512K alignment.
1889 * HSW and onwards, align to requested size of OA buffer.
1891 ret = i915_vma_pin(vma, 0, SZ_16M, PIN_GLOBAL | PIN_HIGH);
1893 drm_err(>->i915->drm, "Failed to pin OA buffer %d\n", ret);
1897 stream->oa_buffer.vma = vma;
1899 stream->oa_buffer.vaddr =
1900 i915_gem_object_pin_map_unlocked(bo, I915_MAP_WB);
1901 if (IS_ERR(stream->oa_buffer.vaddr)) {
1902 ret = PTR_ERR(stream->oa_buffer.vaddr);
1909 __i915_vma_unpin(vma);
1912 i915_gem_object_put(bo);
1914 stream->oa_buffer.vaddr = NULL;
1915 stream->oa_buffer.vma = NULL;
1920 static u32 *save_restore_register(struct i915_perf_stream *stream, u32 *cs,
1921 bool save, i915_reg_t reg, u32 offset,
1927 cmd = save ? MI_STORE_REGISTER_MEM : MI_LOAD_REGISTER_MEM;
1928 cmd |= MI_SRM_LRM_GLOBAL_GTT;
1929 if (GRAPHICS_VER(stream->perf->i915) >= 8)
1932 for (d = 0; d < dword_count; d++) {
1934 *cs++ = i915_mmio_reg_offset(reg) + 4 * d;
1935 *cs++ = i915_ggtt_offset(stream->noa_wait) + offset + 4 * d;
1942 static int alloc_noa_wait(struct i915_perf_stream *stream)
1944 struct drm_i915_private *i915 = stream->perf->i915;
1945 struct intel_gt *gt = stream->engine->gt;
1946 struct drm_i915_gem_object *bo;
1947 struct i915_vma *vma;
1948 const u64 delay_ticks = 0xffffffffffffffff -
1949 intel_gt_ns_to_clock_interval(to_gt(stream->perf->i915),
1950 atomic64_read(&stream->perf->noa_programming_delay));
1951 const u32 base = stream->engine->mmio_base;
1952 #define CS_GPR(x) GEN8_RING_CS_GPR(base, x)
1953 u32 *batch, *ts0, *cs, *jump;
1954 struct i915_gem_ww_ctx ww;
1964 i915_reg_t mi_predicate_result = HAS_MI_SET_PREDICATE(i915) ?
1965 MI_PREDICATE_RESULT_2_ENGINE(base) :
1966 MI_PREDICATE_RESULT_1(RENDER_RING_BASE);
1969 * gt->scratch was being used to save/restore the GPR registers, but on
1970 * MTL the scratch uses stolen lmem. An MI_SRM to this memory region
1971 * causes an engine hang. Instead allocate an additional page here to
1972 * save/restore GPR registers
1974 bo = i915_gem_object_create_internal(i915, 8192);
1977 "Failed to allocate NOA wait batchbuffer\n");
1981 i915_gem_ww_ctx_init(&ww, true);
1983 ret = i915_gem_object_lock(bo, &ww);
1988 * We pin in GGTT because we jump into this buffer now because
1989 * multiple OA config BOs will have a jump to this address and it
1990 * needs to be fixed during the lifetime of the i915/perf stream.
1992 vma = i915_vma_instance(bo, >->ggtt->vm, NULL);
1998 ret = i915_vma_pin_ww(vma, &ww, 0, 0, PIN_GLOBAL | PIN_HIGH);
2002 batch = cs = i915_gem_object_pin_map(bo, I915_MAP_WB);
2003 if (IS_ERR(batch)) {
2004 ret = PTR_ERR(batch);
2008 stream->noa_wait = vma;
2010 #define GPR_SAVE_OFFSET 4096
2011 #define PREDICATE_SAVE_OFFSET 4160
2013 /* Save registers. */
2014 for (i = 0; i < N_CS_GPR; i++)
2015 cs = save_restore_register(
2016 stream, cs, true /* save */, CS_GPR(i),
2017 GPR_SAVE_OFFSET + 8 * i, 2);
2018 cs = save_restore_register(
2019 stream, cs, true /* save */, mi_predicate_result,
2020 PREDICATE_SAVE_OFFSET, 1);
2022 /* First timestamp snapshot location. */
2026 * Initial snapshot of the timestamp register to implement the wait.
2027 * We work with 32b values, so clear out the top 32b bits of the
2028 * register because the ALU works 64bits.
2030 *cs++ = MI_LOAD_REGISTER_IMM(1);
2031 *cs++ = i915_mmio_reg_offset(CS_GPR(START_TS)) + 4;
2033 *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
2034 *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(base));
2035 *cs++ = i915_mmio_reg_offset(CS_GPR(START_TS));
2038 * This is the location we're going to jump back into until the
2039 * required amount of time has passed.
2044 * Take another snapshot of the timestamp register. Take care to clear
2045 * up the top 32bits of CS_GPR(1) as we're using it for other
2048 *cs++ = MI_LOAD_REGISTER_IMM(1);
2049 *cs++ = i915_mmio_reg_offset(CS_GPR(NOW_TS)) + 4;
2051 *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
2052 *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(base));
2053 *cs++ = i915_mmio_reg_offset(CS_GPR(NOW_TS));
2056 * Do a diff between the 2 timestamps and store the result back into
2060 *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(NOW_TS));
2061 *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(START_TS));
2062 *cs++ = MI_MATH_SUB;
2063 *cs++ = MI_MATH_STORE(MI_MATH_REG(DELTA_TS), MI_MATH_REG_ACCU);
2064 *cs++ = MI_MATH_STORE(MI_MATH_REG(JUMP_PREDICATE), MI_MATH_REG_CF);
2067 * Transfer the carry flag (set to 1 if ts1 < ts0, meaning the
2068 * timestamp have rolled over the 32bits) into the predicate register
2069 * to be used for the predicated jump.
2071 *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
2072 *cs++ = i915_mmio_reg_offset(CS_GPR(JUMP_PREDICATE));
2073 *cs++ = i915_mmio_reg_offset(mi_predicate_result);
2075 if (HAS_MI_SET_PREDICATE(i915))
2076 *cs++ = MI_SET_PREDICATE | 1;
2078 /* Restart from the beginning if we had timestamps roll over. */
2079 *cs++ = (GRAPHICS_VER(i915) < 8 ?
2080 MI_BATCH_BUFFER_START :
2081 MI_BATCH_BUFFER_START_GEN8) |
2083 *cs++ = i915_ggtt_offset(vma) + (ts0 - batch) * 4;
2086 if (HAS_MI_SET_PREDICATE(i915))
2087 *cs++ = MI_SET_PREDICATE;
2090 * Now add the diff between to previous timestamps and add it to :
2091 * (((1 * << 64) - 1) - delay_ns)
2093 * When the Carry Flag contains 1 this means the elapsed time is
2094 * longer than the expected delay, and we can exit the wait loop.
2096 *cs++ = MI_LOAD_REGISTER_IMM(2);
2097 *cs++ = i915_mmio_reg_offset(CS_GPR(DELTA_TARGET));
2098 *cs++ = lower_32_bits(delay_ticks);
2099 *cs++ = i915_mmio_reg_offset(CS_GPR(DELTA_TARGET)) + 4;
2100 *cs++ = upper_32_bits(delay_ticks);
2103 *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(DELTA_TS));
2104 *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(DELTA_TARGET));
2105 *cs++ = MI_MATH_ADD;
2106 *cs++ = MI_MATH_STOREINV(MI_MATH_REG(JUMP_PREDICATE), MI_MATH_REG_CF);
2108 *cs++ = MI_ARB_CHECK;
2111 * Transfer the result into the predicate register to be used for the
2114 *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
2115 *cs++ = i915_mmio_reg_offset(CS_GPR(JUMP_PREDICATE));
2116 *cs++ = i915_mmio_reg_offset(mi_predicate_result);
2118 if (HAS_MI_SET_PREDICATE(i915))
2119 *cs++ = MI_SET_PREDICATE | 1;
2121 /* Predicate the jump. */
2122 *cs++ = (GRAPHICS_VER(i915) < 8 ?
2123 MI_BATCH_BUFFER_START :
2124 MI_BATCH_BUFFER_START_GEN8) |
2126 *cs++ = i915_ggtt_offset(vma) + (jump - batch) * 4;
2129 if (HAS_MI_SET_PREDICATE(i915))
2130 *cs++ = MI_SET_PREDICATE;
2132 /* Restore registers. */
2133 for (i = 0; i < N_CS_GPR; i++)
2134 cs = save_restore_register(
2135 stream, cs, false /* restore */, CS_GPR(i),
2136 GPR_SAVE_OFFSET + 8 * i, 2);
2137 cs = save_restore_register(
2138 stream, cs, false /* restore */, mi_predicate_result,
2139 PREDICATE_SAVE_OFFSET, 1);
2141 /* And return to the ring. */
2142 *cs++ = MI_BATCH_BUFFER_END;
2144 GEM_BUG_ON(cs - batch > PAGE_SIZE / sizeof(*batch));
2146 i915_gem_object_flush_map(bo);
2147 __i915_gem_object_release_map(bo);
2152 i915_vma_unpin_and_release(&vma, 0);
2154 if (ret == -EDEADLK) {
2155 ret = i915_gem_ww_ctx_backoff(&ww);
2159 i915_gem_ww_ctx_fini(&ww);
2161 i915_gem_object_put(bo);
2165 static u32 *write_cs_mi_lri(u32 *cs,
2166 const struct i915_oa_reg *reg_data,
2171 for (i = 0; i < n_regs; i++) {
2172 if ((i % MI_LOAD_REGISTER_IMM_MAX_REGS) == 0) {
2173 u32 n_lri = min_t(u32,
2175 MI_LOAD_REGISTER_IMM_MAX_REGS);
2177 *cs++ = MI_LOAD_REGISTER_IMM(n_lri);
2179 *cs++ = i915_mmio_reg_offset(reg_data[i].addr);
2180 *cs++ = reg_data[i].value;
2186 static int num_lri_dwords(int num_regs)
2191 count += DIV_ROUND_UP(num_regs, MI_LOAD_REGISTER_IMM_MAX_REGS);
2192 count += num_regs * 2;
2198 static struct i915_oa_config_bo *
2199 alloc_oa_config_buffer(struct i915_perf_stream *stream,
2200 struct i915_oa_config *oa_config)
2202 struct drm_i915_gem_object *obj;
2203 struct i915_oa_config_bo *oa_bo;
2204 struct i915_gem_ww_ctx ww;
2205 size_t config_length = 0;
2209 oa_bo = kzalloc(sizeof(*oa_bo), GFP_KERNEL);
2211 return ERR_PTR(-ENOMEM);
2213 config_length += num_lri_dwords(oa_config->mux_regs_len);
2214 config_length += num_lri_dwords(oa_config->b_counter_regs_len);
2215 config_length += num_lri_dwords(oa_config->flex_regs_len);
2216 config_length += 3; /* MI_BATCH_BUFFER_START */
2217 config_length = ALIGN(sizeof(u32) * config_length, I915_GTT_PAGE_SIZE);
2219 obj = i915_gem_object_create_shmem(stream->perf->i915, config_length);
2225 i915_gem_ww_ctx_init(&ww, true);
2227 err = i915_gem_object_lock(obj, &ww);
2231 cs = i915_gem_object_pin_map(obj, I915_MAP_WB);
2237 cs = write_cs_mi_lri(cs,
2238 oa_config->mux_regs,
2239 oa_config->mux_regs_len);
2240 cs = write_cs_mi_lri(cs,
2241 oa_config->b_counter_regs,
2242 oa_config->b_counter_regs_len);
2243 cs = write_cs_mi_lri(cs,
2244 oa_config->flex_regs,
2245 oa_config->flex_regs_len);
2247 /* Jump into the active wait. */
2248 *cs++ = (GRAPHICS_VER(stream->perf->i915) < 8 ?
2249 MI_BATCH_BUFFER_START :
2250 MI_BATCH_BUFFER_START_GEN8);
2251 *cs++ = i915_ggtt_offset(stream->noa_wait);
2254 i915_gem_object_flush_map(obj);
2255 __i915_gem_object_release_map(obj);
2257 oa_bo->vma = i915_vma_instance(obj,
2258 &stream->engine->gt->ggtt->vm,
2260 if (IS_ERR(oa_bo->vma)) {
2261 err = PTR_ERR(oa_bo->vma);
2265 oa_bo->oa_config = i915_oa_config_get(oa_config);
2266 llist_add(&oa_bo->node, &stream->oa_config_bos);
2269 if (err == -EDEADLK) {
2270 err = i915_gem_ww_ctx_backoff(&ww);
2274 i915_gem_ww_ctx_fini(&ww);
2277 i915_gem_object_put(obj);
2281 return ERR_PTR(err);
2286 static struct i915_vma *
2287 get_oa_vma(struct i915_perf_stream *stream, struct i915_oa_config *oa_config)
2289 struct i915_oa_config_bo *oa_bo;
2292 * Look for the buffer in the already allocated BOs attached
2295 llist_for_each_entry(oa_bo, stream->oa_config_bos.first, node) {
2296 if (oa_bo->oa_config == oa_config &&
2297 memcmp(oa_bo->oa_config->uuid,
2299 sizeof(oa_config->uuid)) == 0)
2303 oa_bo = alloc_oa_config_buffer(stream, oa_config);
2305 return ERR_CAST(oa_bo);
2308 return i915_vma_get(oa_bo->vma);
2312 emit_oa_config(struct i915_perf_stream *stream,
2313 struct i915_oa_config *oa_config,
2314 struct intel_context *ce,
2315 struct i915_active *active)
2317 struct i915_request *rq;
2318 struct i915_vma *vma;
2319 struct i915_gem_ww_ctx ww;
2322 vma = get_oa_vma(stream, oa_config);
2324 return PTR_ERR(vma);
2326 i915_gem_ww_ctx_init(&ww, true);
2328 err = i915_gem_object_lock(vma->obj, &ww);
2332 err = i915_vma_pin_ww(vma, &ww, 0, 0, PIN_GLOBAL | PIN_HIGH);
2336 intel_engine_pm_get(ce->engine);
2337 rq = i915_request_create(ce);
2338 intel_engine_pm_put(ce->engine);
2344 if (!IS_ERR_OR_NULL(active)) {
2345 /* After all individual context modifications */
2346 err = i915_request_await_active(rq, active,
2347 I915_ACTIVE_AWAIT_ACTIVE);
2349 goto err_add_request;
2351 err = i915_active_add_request(active, rq);
2353 goto err_add_request;
2356 err = i915_vma_move_to_active(vma, rq, 0);
2358 goto err_add_request;
2360 err = rq->engine->emit_bb_start(rq,
2361 i915_vma_offset(vma), 0,
2362 I915_DISPATCH_SECURE);
2364 goto err_add_request;
2367 i915_request_add(rq);
2369 i915_vma_unpin(vma);
2371 if (err == -EDEADLK) {
2372 err = i915_gem_ww_ctx_backoff(&ww);
2377 i915_gem_ww_ctx_fini(&ww);
2382 static struct intel_context *oa_context(struct i915_perf_stream *stream)
2384 return stream->pinned_ctx ?: stream->engine->kernel_context;
2388 hsw_enable_metric_set(struct i915_perf_stream *stream,
2389 struct i915_active *active)
2391 struct intel_uncore *uncore = stream->uncore;
2396 * OA unit is using “crclk” for its functionality. When trunk
2397 * level clock gating takes place, OA clock would be gated,
2398 * unable to count the events from non-render clock domain.
2399 * Render clock gating must be disabled when OA is enabled to
2400 * count the events from non-render domain. Unit level clock
2401 * gating for RCS should also be disabled.
2403 intel_uncore_rmw(uncore, GEN7_MISCCPCTL,
2404 GEN7_DOP_CLOCK_GATE_ENABLE, 0);
2405 intel_uncore_rmw(uncore, GEN6_UCGCTL1,
2406 0, GEN6_CSUNIT_CLOCK_GATE_DISABLE);
2408 return emit_oa_config(stream,
2409 stream->oa_config, oa_context(stream),
2413 static void hsw_disable_metric_set(struct i915_perf_stream *stream)
2415 struct intel_uncore *uncore = stream->uncore;
2417 intel_uncore_rmw(uncore, GEN6_UCGCTL1,
2418 GEN6_CSUNIT_CLOCK_GATE_DISABLE, 0);
2419 intel_uncore_rmw(uncore, GEN7_MISCCPCTL,
2420 0, GEN7_DOP_CLOCK_GATE_ENABLE);
2422 intel_uncore_rmw(uncore, GDT_CHICKEN_BITS, GT_NOA_ENABLE, 0);
2425 static u32 oa_config_flex_reg(const struct i915_oa_config *oa_config,
2428 u32 mmio = i915_mmio_reg_offset(reg);
2432 * This arbitrary default will select the 'EU FPU0 Pipeline
2433 * Active' event. In the future it's anticipated that there
2434 * will be an explicit 'No Event' we can select, but not yet...
2439 for (i = 0; i < oa_config->flex_regs_len; i++) {
2440 if (i915_mmio_reg_offset(oa_config->flex_regs[i].addr) == mmio)
2441 return oa_config->flex_regs[i].value;
2447 * NB: It must always remain pointer safe to run this even if the OA unit
2448 * has been disabled.
2450 * It's fine to put out-of-date values into these per-context registers
2451 * in the case that the OA unit has been disabled.
2454 gen8_update_reg_state_unlocked(const struct intel_context *ce,
2455 const struct i915_perf_stream *stream)
2457 u32 ctx_oactxctrl = stream->perf->ctx_oactxctrl_offset;
2458 u32 ctx_flexeu0 = stream->perf->ctx_flexeu0_offset;
2459 /* The MMIO offsets for Flex EU registers aren't contiguous */
2460 static const i915_reg_t flex_regs[] = {
2469 u32 *reg_state = ce->lrc_reg_state;
2472 reg_state[ctx_oactxctrl + 1] =
2473 (stream->period_exponent << GEN8_OA_TIMER_PERIOD_SHIFT) |
2474 (stream->periodic ? GEN8_OA_TIMER_ENABLE : 0) |
2475 GEN8_OA_COUNTER_RESUME;
2477 for (i = 0; i < ARRAY_SIZE(flex_regs); i++)
2478 reg_state[ctx_flexeu0 + i * 2 + 1] =
2479 oa_config_flex_reg(stream->oa_config, flex_regs[i]);
2489 gen8_store_flex(struct i915_request *rq,
2490 struct intel_context *ce,
2491 const struct flex *flex, unsigned int count)
2496 cs = intel_ring_begin(rq, 4 * count);
2500 offset = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET;
2502 *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
2503 *cs++ = offset + flex->offset * sizeof(u32);
2505 *cs++ = flex->value;
2506 } while (flex++, --count);
2508 intel_ring_advance(rq, cs);
2514 gen8_load_flex(struct i915_request *rq,
2515 struct intel_context *ce,
2516 const struct flex *flex, unsigned int count)
2520 GEM_BUG_ON(!count || count > 63);
2522 cs = intel_ring_begin(rq, 2 * count + 2);
2526 *cs++ = MI_LOAD_REGISTER_IMM(count);
2528 *cs++ = i915_mmio_reg_offset(flex->reg);
2529 *cs++ = flex->value;
2530 } while (flex++, --count);
2533 intel_ring_advance(rq, cs);
2538 static int gen8_modify_context(struct intel_context *ce,
2539 const struct flex *flex, unsigned int count)
2541 struct i915_request *rq;
2544 rq = intel_engine_create_kernel_request(ce->engine);
2548 /* Serialise with the remote context */
2549 err = intel_context_prepare_remote_request(ce, rq);
2551 err = gen8_store_flex(rq, ce, flex, count);
2553 i915_request_add(rq);
2558 gen8_modify_self(struct intel_context *ce,
2559 const struct flex *flex, unsigned int count,
2560 struct i915_active *active)
2562 struct i915_request *rq;
2565 intel_engine_pm_get(ce->engine);
2566 rq = i915_request_create(ce);
2567 intel_engine_pm_put(ce->engine);
2571 if (!IS_ERR_OR_NULL(active)) {
2572 err = i915_active_add_request(active, rq);
2574 goto err_add_request;
2577 err = gen8_load_flex(rq, ce, flex, count);
2579 goto err_add_request;
2582 i915_request_add(rq);
2586 static int gen8_configure_context(struct i915_perf_stream *stream,
2587 struct i915_gem_context *ctx,
2588 struct flex *flex, unsigned int count)
2590 struct i915_gem_engines_iter it;
2591 struct intel_context *ce;
2594 for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
2595 GEM_BUG_ON(ce == ce->engine->kernel_context);
2597 if (ce->engine->class != RENDER_CLASS)
2600 /* Otherwise OA settings will be set upon first use */
2601 if (!intel_context_pin_if_active(ce))
2604 flex->value = intel_sseu_make_rpcs(ce->engine->gt, &ce->sseu);
2605 err = gen8_modify_context(ce, flex, count);
2607 intel_context_unpin(ce);
2611 i915_gem_context_unlock_engines(ctx);
2616 static int gen12_configure_oar_context(struct i915_perf_stream *stream,
2617 struct i915_active *active)
2620 struct intel_context *ce = stream->pinned_ctx;
2621 u32 format = stream->oa_buffer.format->format;
2622 u32 offset = stream->perf->ctx_oactxctrl_offset;
2623 struct flex regs_context[] = {
2627 active ? GEN8_OA_COUNTER_RESUME : 0,
2630 /* Offsets in regs_lri are not used since this configuration is only
2631 * applied using LRI. Initialize the correct offsets for posterity.
2633 #define GEN12_OAR_OACONTROL_OFFSET 0x5B0
2634 struct flex regs_lri[] = {
2636 GEN12_OAR_OACONTROL,
2637 GEN12_OAR_OACONTROL_OFFSET + 1,
2638 (format << GEN12_OAR_OACONTROL_COUNTER_FORMAT_SHIFT) |
2639 (active ? GEN12_OAR_OACONTROL_COUNTER_ENABLE : 0)
2642 RING_CONTEXT_CONTROL(ce->engine->mmio_base),
2643 CTX_CONTEXT_CONTROL,
2644 _MASKED_FIELD(GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE,
2646 GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE :
2651 /* Modify the context image of pinned context with regs_context */
2652 err = intel_context_lock_pinned(ce);
2656 err = gen8_modify_context(ce, regs_context,
2657 ARRAY_SIZE(regs_context));
2658 intel_context_unlock_pinned(ce);
2662 /* Apply regs_lri using LRI with pinned context */
2663 return gen8_modify_self(ce, regs_lri, ARRAY_SIZE(regs_lri), active);
2667 * Manages updating the per-context aspects of the OA stream
2668 * configuration across all contexts.
2670 * The awkward consideration here is that OACTXCONTROL controls the
2671 * exponent for periodic sampling which is primarily used for system
2672 * wide profiling where we'd like a consistent sampling period even in
2673 * the face of context switches.
2675 * Our approach of updating the register state context (as opposed to
2676 * say using a workaround batch buffer) ensures that the hardware
2677 * won't automatically reload an out-of-date timer exponent even
2678 * transiently before a WA BB could be parsed.
2680 * This function needs to:
2681 * - Ensure the currently running context's per-context OA state is
2683 * - Ensure that all existing contexts will have the correct per-context
2684 * OA state if they are scheduled for use.
2685 * - Ensure any new contexts will be initialized with the correct
2686 * per-context OA state.
2688 * Note: it's only the RCS/Render context that has any OA state.
2689 * Note: the first flex register passed must always be R_PWR_CLK_STATE
2692 oa_configure_all_contexts(struct i915_perf_stream *stream,
2695 struct i915_active *active)
2697 struct drm_i915_private *i915 = stream->perf->i915;
2698 struct intel_engine_cs *engine;
2699 struct intel_gt *gt = stream->engine->gt;
2700 struct i915_gem_context *ctx, *cn;
2703 lockdep_assert_held(>->perf.lock);
2706 * The OA register config is setup through the context image. This image
2707 * might be written to by the GPU on context switch (in particular on
2708 * lite-restore). This means we can't safely update a context's image,
2709 * if this context is scheduled/submitted to run on the GPU.
2711 * We could emit the OA register config through the batch buffer but
2712 * this might leave small interval of time where the OA unit is
2713 * configured at an invalid sampling period.
2715 * Note that since we emit all requests from a single ring, there
2716 * is still an implicit global barrier here that may cause a high
2717 * priority context to wait for an otherwise independent low priority
2718 * context. Contexts idle at the time of reconfiguration are not
2719 * trapped behind the barrier.
2721 spin_lock(&i915->gem.contexts.lock);
2722 list_for_each_entry_safe(ctx, cn, &i915->gem.contexts.list, link) {
2723 if (!kref_get_unless_zero(&ctx->ref))
2726 spin_unlock(&i915->gem.contexts.lock);
2728 err = gen8_configure_context(stream, ctx, regs, num_regs);
2730 i915_gem_context_put(ctx);
2734 spin_lock(&i915->gem.contexts.lock);
2735 list_safe_reset_next(ctx, cn, link);
2736 i915_gem_context_put(ctx);
2738 spin_unlock(&i915->gem.contexts.lock);
2741 * After updating all other contexts, we need to modify ourselves.
2742 * If we don't modify the kernel_context, we do not get events while
2745 for_each_uabi_engine(engine, i915) {
2746 struct intel_context *ce = engine->kernel_context;
2748 if (engine->class != RENDER_CLASS)
2751 regs[0].value = intel_sseu_make_rpcs(engine->gt, &ce->sseu);
2753 err = gen8_modify_self(ce, regs, num_regs, active);
2762 gen12_configure_all_contexts(struct i915_perf_stream *stream,
2763 const struct i915_oa_config *oa_config,
2764 struct i915_active *active)
2766 struct flex regs[] = {
2768 GEN8_R_PWR_CLK_STATE(RENDER_RING_BASE),
2769 CTX_R_PWR_CLK_STATE,
2773 if (stream->engine->class != RENDER_CLASS)
2776 return oa_configure_all_contexts(stream,
2777 regs, ARRAY_SIZE(regs),
2782 lrc_configure_all_contexts(struct i915_perf_stream *stream,
2783 const struct i915_oa_config *oa_config,
2784 struct i915_active *active)
2786 u32 ctx_oactxctrl = stream->perf->ctx_oactxctrl_offset;
2787 /* The MMIO offsets for Flex EU registers aren't contiguous */
2788 const u32 ctx_flexeu0 = stream->perf->ctx_flexeu0_offset;
2789 #define ctx_flexeuN(N) (ctx_flexeu0 + 2 * (N) + 1)
2790 struct flex regs[] = {
2792 GEN8_R_PWR_CLK_STATE(RENDER_RING_BASE),
2793 CTX_R_PWR_CLK_STATE,
2799 { EU_PERF_CNTL0, ctx_flexeuN(0) },
2800 { EU_PERF_CNTL1, ctx_flexeuN(1) },
2801 { EU_PERF_CNTL2, ctx_flexeuN(2) },
2802 { EU_PERF_CNTL3, ctx_flexeuN(3) },
2803 { EU_PERF_CNTL4, ctx_flexeuN(4) },
2804 { EU_PERF_CNTL5, ctx_flexeuN(5) },
2805 { EU_PERF_CNTL6, ctx_flexeuN(6) },
2811 (stream->period_exponent << GEN8_OA_TIMER_PERIOD_SHIFT) |
2812 (stream->periodic ? GEN8_OA_TIMER_ENABLE : 0) |
2813 GEN8_OA_COUNTER_RESUME;
2815 for (i = 2; i < ARRAY_SIZE(regs); i++)
2816 regs[i].value = oa_config_flex_reg(oa_config, regs[i].reg);
2818 return oa_configure_all_contexts(stream,
2819 regs, ARRAY_SIZE(regs),
2824 gen8_enable_metric_set(struct i915_perf_stream *stream,
2825 struct i915_active *active)
2827 struct intel_uncore *uncore = stream->uncore;
2828 struct i915_oa_config *oa_config = stream->oa_config;
2832 * We disable slice/unslice clock ratio change reports on SKL since
2833 * they are too noisy. The HW generates a lot of redundant reports
2834 * where the ratio hasn't really changed causing a lot of redundant
2835 * work to processes and increasing the chances we'll hit buffer
2838 * Although we don't currently use the 'disable overrun' OABUFFER
2839 * feature it's worth noting that clock ratio reports have to be
2840 * disabled before considering to use that feature since the HW doesn't
2841 * correctly block these reports.
2843 * Currently none of the high-level metrics we have depend on knowing
2844 * this ratio to normalize.
2846 * Note: This register is not power context saved and restored, but
2847 * that's OK considering that we disable RC6 while the OA unit is
2850 * The _INCLUDE_CLK_RATIO bit allows the slice/unslice frequency to
2851 * be read back from automatically triggered reports, as part of the
2854 if (IS_GRAPHICS_VER(stream->perf->i915, 9, 11)) {
2855 intel_uncore_write(uncore, GEN8_OA_DEBUG,
2856 _MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
2857 GEN9_OA_DEBUG_INCLUDE_CLK_RATIO));
2861 * Update all contexts prior writing the mux configurations as we need
2862 * to make sure all slices/subslices are ON before writing to NOA
2865 ret = lrc_configure_all_contexts(stream, oa_config, active);
2869 return emit_oa_config(stream,
2870 stream->oa_config, oa_context(stream),
2874 static u32 oag_report_ctx_switches(const struct i915_perf_stream *stream)
2876 return _MASKED_FIELD(GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS,
2877 (stream->sample_flags & SAMPLE_OA_REPORT) ?
2878 0 : GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS);
2882 gen12_enable_metric_set(struct i915_perf_stream *stream,
2883 struct i915_active *active)
2885 struct drm_i915_private *i915 = stream->perf->i915;
2886 struct intel_uncore *uncore = stream->uncore;
2887 struct i915_oa_config *oa_config = stream->oa_config;
2888 bool periodic = stream->periodic;
2889 u32 period_exponent = stream->period_exponent;
2894 * Wa_1508761755:xehpsdv, dg2
2895 * EU NOA signals behave incorrectly if EU clock gating is enabled.
2896 * Disable thread stall DOP gating and EU DOP gating.
2898 if (IS_XEHPSDV(i915) || IS_DG2(i915)) {
2899 intel_gt_mcr_multicast_write(uncore->gt, GEN8_ROW_CHICKEN,
2900 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
2901 intel_uncore_write(uncore, GEN7_ROW_CHICKEN2,
2902 _MASKED_BIT_ENABLE(GEN12_DISABLE_DOP_GATING));
2905 intel_uncore_write(uncore, __oa_regs(stream)->oa_debug,
2906 /* Disable clk ratio reports, like previous Gens. */
2907 _MASKED_BIT_ENABLE(GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
2908 GEN12_OAG_OA_DEBUG_INCLUDE_CLK_RATIO) |
2910 * If the user didn't require OA reports, instruct
2911 * the hardware not to emit ctx switch reports.
2913 oag_report_ctx_switches(stream));
2915 intel_uncore_write(uncore, __oa_regs(stream)->oa_ctx_ctrl, periodic ?
2916 (GEN12_OAG_OAGLBCTXCTRL_COUNTER_RESUME |
2917 GEN12_OAG_OAGLBCTXCTRL_TIMER_ENABLE |
2918 (period_exponent << GEN12_OAG_OAGLBCTXCTRL_TIMER_PERIOD_SHIFT))
2922 * Initialize Super Queue Internal Cnt Register
2923 * Set PMON Enable in order to collect valid metrics.
2924 * Enable byets per clock reporting in OA for XEHPSDV onward.
2926 sqcnt1 = GEN12_SQCNT1_PMON_ENABLE |
2927 (HAS_OA_BPC_REPORTING(i915) ? GEN12_SQCNT1_OABPC : 0);
2929 intel_uncore_rmw(uncore, GEN12_SQCNT1, 0, sqcnt1);
2932 * Update all contexts prior writing the mux configurations as we need
2933 * to make sure all slices/subslices are ON before writing to NOA
2936 ret = gen12_configure_all_contexts(stream, oa_config, active);
2941 * For Gen12, performance counters are context
2942 * saved/restored. Only enable it for the context that
2946 ret = gen12_configure_oar_context(stream, active);
2951 return emit_oa_config(stream,
2952 stream->oa_config, oa_context(stream),
2956 static void gen8_disable_metric_set(struct i915_perf_stream *stream)
2958 struct intel_uncore *uncore = stream->uncore;
2960 /* Reset all contexts' slices/subslices configurations. */
2961 lrc_configure_all_contexts(stream, NULL, NULL);
2963 intel_uncore_rmw(uncore, GDT_CHICKEN_BITS, GT_NOA_ENABLE, 0);
2966 static void gen11_disable_metric_set(struct i915_perf_stream *stream)
2968 struct intel_uncore *uncore = stream->uncore;
2970 /* Reset all contexts' slices/subslices configurations. */
2971 lrc_configure_all_contexts(stream, NULL, NULL);
2973 /* Make sure we disable noa to save power. */
2974 intel_uncore_rmw(uncore, RPM_CONFIG1, GEN10_GT_NOA_ENABLE, 0);
2977 static void gen12_disable_metric_set(struct i915_perf_stream *stream)
2979 struct intel_uncore *uncore = stream->uncore;
2980 struct drm_i915_private *i915 = stream->perf->i915;
2984 * Wa_1508761755:xehpsdv, dg2
2985 * Enable thread stall DOP gating and EU DOP gating.
2987 if (IS_XEHPSDV(i915) || IS_DG2(i915)) {
2988 intel_gt_mcr_multicast_write(uncore->gt, GEN8_ROW_CHICKEN,
2989 _MASKED_BIT_DISABLE(STALL_DOP_GATING_DISABLE));
2990 intel_uncore_write(uncore, GEN7_ROW_CHICKEN2,
2991 _MASKED_BIT_DISABLE(GEN12_DISABLE_DOP_GATING));
2994 /* Reset all contexts' slices/subslices configurations. */
2995 gen12_configure_all_contexts(stream, NULL, NULL);
2997 /* disable the context save/restore or OAR counters */
2999 gen12_configure_oar_context(stream, NULL);
3001 /* Make sure we disable noa to save power. */
3002 intel_uncore_rmw(uncore, RPM_CONFIG1, GEN10_GT_NOA_ENABLE, 0);
3004 sqcnt1 = GEN12_SQCNT1_PMON_ENABLE |
3005 (HAS_OA_BPC_REPORTING(i915) ? GEN12_SQCNT1_OABPC : 0);
3007 /* Reset PMON Enable to save power. */
3008 intel_uncore_rmw(uncore, GEN12_SQCNT1, sqcnt1, 0);
3011 static void gen7_oa_enable(struct i915_perf_stream *stream)
3013 struct intel_uncore *uncore = stream->uncore;
3014 struct i915_gem_context *ctx = stream->ctx;
3015 u32 ctx_id = stream->specific_ctx_id;
3016 bool periodic = stream->periodic;
3017 u32 period_exponent = stream->period_exponent;
3018 u32 report_format = stream->oa_buffer.format->format;
3021 * Reset buf pointers so we don't forward reports from before now.
3023 * Think carefully if considering trying to avoid this, since it
3024 * also ensures status flags and the buffer itself are cleared
3025 * in error paths, and we have checks for invalid reports based
3026 * on the assumption that certain fields are written to zeroed
3027 * memory which this helps maintains.
3029 gen7_init_oa_buffer(stream);
3031 intel_uncore_write(uncore, GEN7_OACONTROL,
3032 (ctx_id & GEN7_OACONTROL_CTX_MASK) |
3034 GEN7_OACONTROL_TIMER_PERIOD_SHIFT) |
3035 (periodic ? GEN7_OACONTROL_TIMER_ENABLE : 0) |
3036 (report_format << GEN7_OACONTROL_FORMAT_SHIFT) |
3037 (ctx ? GEN7_OACONTROL_PER_CTX_ENABLE : 0) |
3038 GEN7_OACONTROL_ENABLE);
3041 static void gen8_oa_enable(struct i915_perf_stream *stream)
3043 struct intel_uncore *uncore = stream->uncore;
3044 u32 report_format = stream->oa_buffer.format->format;
3047 * Reset buf pointers so we don't forward reports from before now.
3049 * Think carefully if considering trying to avoid this, since it
3050 * also ensures status flags and the buffer itself are cleared
3051 * in error paths, and we have checks for invalid reports based
3052 * on the assumption that certain fields are written to zeroed
3053 * memory which this helps maintains.
3055 gen8_init_oa_buffer(stream);
3058 * Note: we don't rely on the hardware to perform single context
3059 * filtering and instead filter on the cpu based on the context-id
3062 intel_uncore_write(uncore, GEN8_OACONTROL,
3063 (report_format << GEN8_OA_REPORT_FORMAT_SHIFT) |
3064 GEN8_OA_COUNTER_ENABLE);
3067 static void gen12_oa_enable(struct i915_perf_stream *stream)
3069 const struct i915_perf_regs *regs;
3073 * If we don't want OA reports from the OA buffer, then we don't even
3074 * need to program the OAG unit.
3076 if (!(stream->sample_flags & SAMPLE_OA_REPORT))
3079 gen12_init_oa_buffer(stream);
3081 regs = __oa_regs(stream);
3082 val = (stream->oa_buffer.format->format << regs->oa_ctrl_counter_format_shift) |
3083 GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE;
3085 intel_uncore_write(stream->uncore, regs->oa_ctrl, val);
3089 * i915_oa_stream_enable - handle `I915_PERF_IOCTL_ENABLE` for OA stream
3090 * @stream: An i915 perf stream opened for OA metrics
3092 * [Re]enables hardware periodic sampling according to the period configured
3093 * when opening the stream. This also starts a hrtimer that will periodically
3094 * check for data in the circular OA buffer for notifying userspace (e.g.
3095 * during a read() or poll()).
3097 static void i915_oa_stream_enable(struct i915_perf_stream *stream)
3099 stream->pollin = false;
3101 stream->perf->ops.oa_enable(stream);
3103 if (stream->sample_flags & SAMPLE_OA_REPORT)
3104 hrtimer_start(&stream->poll_check_timer,
3105 ns_to_ktime(stream->poll_oa_period),
3106 HRTIMER_MODE_REL_PINNED);
3109 static void gen7_oa_disable(struct i915_perf_stream *stream)
3111 struct intel_uncore *uncore = stream->uncore;
3113 intel_uncore_write(uncore, GEN7_OACONTROL, 0);
3114 if (intel_wait_for_register(uncore,
3115 GEN7_OACONTROL, GEN7_OACONTROL_ENABLE, 0,
3117 drm_err(&stream->perf->i915->drm,
3118 "wait for OA to be disabled timed out\n");
3121 static void gen8_oa_disable(struct i915_perf_stream *stream)
3123 struct intel_uncore *uncore = stream->uncore;
3125 intel_uncore_write(uncore, GEN8_OACONTROL, 0);
3126 if (intel_wait_for_register(uncore,
3127 GEN8_OACONTROL, GEN8_OA_COUNTER_ENABLE, 0,
3129 drm_err(&stream->perf->i915->drm,
3130 "wait for OA to be disabled timed out\n");
3133 static void gen12_oa_disable(struct i915_perf_stream *stream)
3135 struct intel_uncore *uncore = stream->uncore;
3137 intel_uncore_write(uncore, __oa_regs(stream)->oa_ctrl, 0);
3138 if (intel_wait_for_register(uncore,
3139 __oa_regs(stream)->oa_ctrl,
3140 GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE, 0,
3142 drm_err(&stream->perf->i915->drm,
3143 "wait for OA to be disabled timed out\n");
3145 intel_uncore_write(uncore, GEN12_OA_TLB_INV_CR, 1);
3146 if (intel_wait_for_register(uncore,
3147 GEN12_OA_TLB_INV_CR,
3150 drm_err(&stream->perf->i915->drm,
3151 "wait for OA tlb invalidate timed out\n");
3155 * i915_oa_stream_disable - handle `I915_PERF_IOCTL_DISABLE` for OA stream
3156 * @stream: An i915 perf stream opened for OA metrics
3158 * Stops the OA unit from periodically writing counter reports into the
3159 * circular OA buffer. This also stops the hrtimer that periodically checks for
3160 * data in the circular OA buffer, for notifying userspace.
3162 static void i915_oa_stream_disable(struct i915_perf_stream *stream)
3164 stream->perf->ops.oa_disable(stream);
3166 if (stream->sample_flags & SAMPLE_OA_REPORT)
3167 hrtimer_cancel(&stream->poll_check_timer);
3170 static const struct i915_perf_stream_ops i915_oa_stream_ops = {
3171 .destroy = i915_oa_stream_destroy,
3172 .enable = i915_oa_stream_enable,
3173 .disable = i915_oa_stream_disable,
3174 .wait_unlocked = i915_oa_wait_unlocked,
3175 .poll_wait = i915_oa_poll_wait,
3176 .read = i915_oa_read,
3179 static int i915_perf_stream_enable_sync(struct i915_perf_stream *stream)
3181 struct i915_active *active;
3184 active = i915_active_create();
3188 err = stream->perf->ops.enable_metric_set(stream, active);
3190 __i915_active_wait(active, TASK_UNINTERRUPTIBLE);
3192 i915_active_put(active);
3197 get_default_sseu_config(struct intel_sseu *out_sseu,
3198 struct intel_engine_cs *engine)
3200 const struct sseu_dev_info *devinfo_sseu = &engine->gt->info.sseu;
3202 *out_sseu = intel_sseu_from_device_info(devinfo_sseu);
3204 if (GRAPHICS_VER(engine->i915) == 11) {
3206 * We only need subslice count so it doesn't matter which ones
3207 * we select - just turn off low bits in the amount of half of
3208 * all available subslices per slice.
3210 out_sseu->subslice_mask =
3211 ~(~0 << (hweight8(out_sseu->subslice_mask) / 2));
3212 out_sseu->slice_mask = 0x1;
3217 get_sseu_config(struct intel_sseu *out_sseu,
3218 struct intel_engine_cs *engine,
3219 const struct drm_i915_gem_context_param_sseu *drm_sseu)
3221 if (drm_sseu->engine.engine_class != engine->uabi_class ||
3222 drm_sseu->engine.engine_instance != engine->uabi_instance)
3225 return i915_gem_user_to_context_sseu(engine->gt, drm_sseu, out_sseu);
3229 * OA timestamp frequency = CS timestamp frequency in most platforms. On some
3230 * platforms OA unit ignores the CTC_SHIFT and the 2 timestamps differ. In such
3231 * cases, return the adjusted CS timestamp frequency to the user.
3233 u32 i915_perf_oa_timestamp_frequency(struct drm_i915_private *i915)
3236 * Wa_18013179988:dg2
3237 * Wa_14015846243:mtl
3239 if (IS_DG2(i915) || IS_METEORLAKE(i915)) {
3240 intel_wakeref_t wakeref;
3243 with_intel_runtime_pm(to_gt(i915)->uncore->rpm, wakeref)
3244 reg = intel_uncore_read(to_gt(i915)->uncore, RPM_CONFIG0);
3246 shift = REG_FIELD_GET(GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK,
3249 return to_gt(i915)->clock_frequency << (3 - shift);
3252 return to_gt(i915)->clock_frequency;
3256 * i915_oa_stream_init - validate combined props for OA stream and init
3257 * @stream: An i915 perf stream
3258 * @param: The open parameters passed to `DRM_I915_PERF_OPEN`
3259 * @props: The property state that configures stream (individually validated)
3261 * While read_properties_unlocked() validates properties in isolation it
3262 * doesn't ensure that the combination necessarily makes sense.
3264 * At this point it has been determined that userspace wants a stream of
3265 * OA metrics, but still we need to further validate the combined
3266 * properties are OK.
3268 * If the configuration makes sense then we can allocate memory for
3269 * a circular OA buffer and apply the requested metric set configuration.
3271 * Returns: zero on success or a negative error code.
3273 static int i915_oa_stream_init(struct i915_perf_stream *stream,
3274 struct drm_i915_perf_open_param *param,
3275 struct perf_open_properties *props)
3277 struct drm_i915_private *i915 = stream->perf->i915;
3278 struct i915_perf *perf = stream->perf;
3279 struct i915_perf_group *g;
3280 struct intel_gt *gt;
3283 if (!props->engine) {
3284 drm_dbg(&stream->perf->i915->drm,
3285 "OA engine not specified\n");
3288 gt = props->engine->gt;
3289 g = props->engine->oa_group;
3292 * If the sysfs metrics/ directory wasn't registered for some
3293 * reason then don't let userspace try their luck with config
3296 if (!perf->metrics_kobj) {
3297 drm_dbg(&stream->perf->i915->drm,
3298 "OA metrics weren't advertised via sysfs\n");
3302 if (!(props->sample_flags & SAMPLE_OA_REPORT) &&
3303 (GRAPHICS_VER(perf->i915) < 12 || !stream->ctx)) {
3304 drm_dbg(&stream->perf->i915->drm,
3305 "Only OA report sampling supported\n");
3309 if (!perf->ops.enable_metric_set) {
3310 drm_dbg(&stream->perf->i915->drm,
3311 "OA unit not supported\n");
3316 * To avoid the complexity of having to accurately filter
3317 * counter reports and marshal to the appropriate client
3318 * we currently only allow exclusive access
3320 if (g->exclusive_stream) {
3321 drm_dbg(&stream->perf->i915->drm,
3322 "OA unit already in use\n");
3326 if (!props->oa_format) {
3327 drm_dbg(&stream->perf->i915->drm,
3328 "OA report format not specified\n");
3332 stream->engine = props->engine;
3333 stream->uncore = stream->engine->gt->uncore;
3335 stream->sample_size = sizeof(struct drm_i915_perf_record_header);
3337 stream->oa_buffer.format = &perf->oa_formats[props->oa_format];
3338 if (drm_WARN_ON(&i915->drm, stream->oa_buffer.format->size == 0))
3341 stream->sample_flags = props->sample_flags;
3342 stream->sample_size += stream->oa_buffer.format->size;
3344 stream->hold_preemption = props->hold_preemption;
3346 stream->periodic = props->oa_periodic;
3347 if (stream->periodic)
3348 stream->period_exponent = props->oa_period_exponent;
3351 ret = oa_get_render_ctx_id(stream);
3353 drm_dbg(&stream->perf->i915->drm,
3354 "Invalid context id to filter with\n");
3359 ret = alloc_noa_wait(stream);
3361 drm_dbg(&stream->perf->i915->drm,
3362 "Unable to allocate NOA wait batch buffer\n");
3363 goto err_noa_wait_alloc;
3366 stream->oa_config = i915_perf_get_oa_config(perf, props->metrics_set);
3367 if (!stream->oa_config) {
3368 drm_dbg(&stream->perf->i915->drm,
3369 "Invalid OA config id=%i\n", props->metrics_set);
3374 /* PRM - observability performance counters:
3376 * OACONTROL, performance counter enable, note:
3378 * "When this bit is set, in order to have coherent counts,
3379 * RC6 power state and trunk clock gating must be disabled.
3380 * This can be achieved by programming MMIO registers as
3381 * 0xA094=0 and 0xA090[31]=1"
3383 * In our case we are expecting that taking pm + FORCEWAKE
3384 * references will effectively disable RC6.
3386 intel_engine_pm_get(stream->engine);
3387 intel_uncore_forcewake_get(stream->uncore, FORCEWAKE_ALL);
3390 * Wa_16011777198:dg2: GuC resets render as part of the Wa. This causes
3391 * OA to lose the configuration state. Prevent this by overriding GUCRC
3394 if (intel_uc_uses_guc_rc(>->uc) &&
3395 (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) ||
3396 IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0))) {
3397 ret = intel_guc_slpc_override_gucrc_mode(>->uc.guc.slpc,
3398 SLPC_GUCRC_MODE_GUCRC_NO_RC6);
3400 drm_dbg(&stream->perf->i915->drm,
3401 "Unable to override gucrc mode\n");
3405 stream->override_gucrc = true;
3408 ret = alloc_oa_buffer(stream);
3410 goto err_oa_buf_alloc;
3412 stream->ops = &i915_oa_stream_ops;
3414 stream->engine->gt->perf.sseu = props->sseu;
3415 WRITE_ONCE(g->exclusive_stream, stream);
3417 ret = i915_perf_stream_enable_sync(stream);
3419 drm_dbg(&stream->perf->i915->drm,
3420 "Unable to enable metric set\n");
3424 drm_dbg(&stream->perf->i915->drm,
3425 "opening stream oa config uuid=%s\n",
3426 stream->oa_config->uuid);
3428 hrtimer_init(&stream->poll_check_timer,
3429 CLOCK_MONOTONIC, HRTIMER_MODE_REL);
3430 stream->poll_check_timer.function = oa_poll_check_timer_cb;
3431 init_waitqueue_head(&stream->poll_wq);
3432 spin_lock_init(&stream->oa_buffer.ptr_lock);
3433 mutex_init(&stream->lock);
3438 WRITE_ONCE(g->exclusive_stream, NULL);
3439 perf->ops.disable_metric_set(stream);
3441 free_oa_buffer(stream);
3444 if (stream->override_gucrc)
3445 intel_guc_slpc_unset_gucrc_mode(>->uc.guc.slpc);
3448 intel_uncore_forcewake_put(stream->uncore, FORCEWAKE_ALL);
3449 intel_engine_pm_put(stream->engine);
3451 free_oa_configs(stream);
3454 free_noa_wait(stream);
3458 oa_put_render_ctx_id(stream);
3463 void i915_oa_init_reg_state(const struct intel_context *ce,
3464 const struct intel_engine_cs *engine)
3466 struct i915_perf_stream *stream;
3468 if (engine->class != RENDER_CLASS)
3471 /* perf.exclusive_stream serialised by lrc_configure_all_contexts() */
3472 stream = READ_ONCE(engine->oa_group->exclusive_stream);
3473 if (stream && GRAPHICS_VER(stream->perf->i915) < 12)
3474 gen8_update_reg_state_unlocked(ce, stream);
3478 * i915_perf_read - handles read() FOP for i915 perf stream FDs
3479 * @file: An i915 perf stream file
3480 * @buf: destination buffer given by userspace
3481 * @count: the number of bytes userspace wants to read
3482 * @ppos: (inout) file seek position (unused)
3484 * The entry point for handling a read() on a stream file descriptor from
3485 * userspace. Most of the work is left to the i915_perf_read_locked() and
3486 * &i915_perf_stream_ops->read but to save having stream implementations (of
3487 * which we might have multiple later) we handle blocking read here.
3489 * We can also consistently treat trying to read from a disabled stream
3490 * as an IO error so implementations can assume the stream is enabled
3493 * Returns: The number of bytes copied or a negative error code on failure.
3495 static ssize_t i915_perf_read(struct file *file,
3500 struct i915_perf_stream *stream = file->private_data;
3504 /* To ensure it's handled consistently we simply treat all reads of a
3505 * disabled stream as an error. In particular it might otherwise lead
3506 * to a deadlock for blocking file descriptors...
3508 if (!stream->enabled || !(stream->sample_flags & SAMPLE_OA_REPORT))
3511 if (!(file->f_flags & O_NONBLOCK)) {
3512 /* There's the small chance of false positives from
3513 * stream->ops->wait_unlocked.
3515 * E.g. with single context filtering since we only wait until
3516 * oabuffer has >= 1 report we don't immediately know whether
3517 * any reports really belong to the current context
3520 ret = stream->ops->wait_unlocked(stream);
3524 mutex_lock(&stream->lock);
3525 ret = stream->ops->read(stream, buf, count, &offset);
3526 mutex_unlock(&stream->lock);
3527 } while (!offset && !ret);
3529 mutex_lock(&stream->lock);
3530 ret = stream->ops->read(stream, buf, count, &offset);
3531 mutex_unlock(&stream->lock);
3534 /* We allow the poll checking to sometimes report false positive EPOLLIN
3535 * events where we might actually report EAGAIN on read() if there's
3536 * not really any data available. In this situation though we don't
3537 * want to enter a busy loop between poll() reporting a EPOLLIN event
3538 * and read() returning -EAGAIN. Clearing the oa.pollin state here
3539 * effectively ensures we back off until the next hrtimer callback
3540 * before reporting another EPOLLIN event.
3541 * The exception to this is if ops->read() returned -ENOSPC which means
3542 * that more OA data is available than could fit in the user provided
3543 * buffer. In this case we want the next poll() call to not block.
3546 stream->pollin = false;
3548 /* Possible values for ret are 0, -EFAULT, -ENOSPC, -EIO, ... */
3549 return offset ?: (ret ?: -EAGAIN);
3552 static enum hrtimer_restart oa_poll_check_timer_cb(struct hrtimer *hrtimer)
3554 struct i915_perf_stream *stream =
3555 container_of(hrtimer, typeof(*stream), poll_check_timer);
3557 if (oa_buffer_check_unlocked(stream)) {
3558 stream->pollin = true;
3559 wake_up(&stream->poll_wq);
3562 hrtimer_forward_now(hrtimer,
3563 ns_to_ktime(stream->poll_oa_period));
3565 return HRTIMER_RESTART;
3569 * i915_perf_poll_locked - poll_wait() with a suitable wait queue for stream
3570 * @stream: An i915 perf stream
3571 * @file: An i915 perf stream file
3572 * @wait: poll() state table
3574 * For handling userspace polling on an i915 perf stream, this calls through to
3575 * &i915_perf_stream_ops->poll_wait to call poll_wait() with a wait queue that
3576 * will be woken for new stream data.
3578 * Returns: any poll events that are ready without sleeping
3580 static __poll_t i915_perf_poll_locked(struct i915_perf_stream *stream,
3584 __poll_t events = 0;
3586 stream->ops->poll_wait(stream, file, wait);
3588 /* Note: we don't explicitly check whether there's something to read
3589 * here since this path may be very hot depending on what else
3590 * userspace is polling, or on the timeout in use. We rely solely on
3591 * the hrtimer/oa_poll_check_timer_cb to notify us when there are
3601 * i915_perf_poll - call poll_wait() with a suitable wait queue for stream
3602 * @file: An i915 perf stream file
3603 * @wait: poll() state table
3605 * For handling userspace polling on an i915 perf stream, this ensures
3606 * poll_wait() gets called with a wait queue that will be woken for new stream
3609 * Note: Implementation deferred to i915_perf_poll_locked()
3611 * Returns: any poll events that are ready without sleeping
3613 static __poll_t i915_perf_poll(struct file *file, poll_table *wait)
3615 struct i915_perf_stream *stream = file->private_data;
3618 mutex_lock(&stream->lock);
3619 ret = i915_perf_poll_locked(stream, file, wait);
3620 mutex_unlock(&stream->lock);
3626 * i915_perf_enable_locked - handle `I915_PERF_IOCTL_ENABLE` ioctl
3627 * @stream: A disabled i915 perf stream
3629 * [Re]enables the associated capture of data for this stream.
3631 * If a stream was previously enabled then there's currently no intention
3632 * to provide userspace any guarantee about the preservation of previously
3635 static void i915_perf_enable_locked(struct i915_perf_stream *stream)
3637 if (stream->enabled)
3640 /* Allow stream->ops->enable() to refer to this */
3641 stream->enabled = true;
3643 if (stream->ops->enable)
3644 stream->ops->enable(stream);
3646 if (stream->hold_preemption)
3647 intel_context_set_nopreempt(stream->pinned_ctx);
3651 * i915_perf_disable_locked - handle `I915_PERF_IOCTL_DISABLE` ioctl
3652 * @stream: An enabled i915 perf stream
3654 * Disables the associated capture of data for this stream.
3656 * The intention is that disabling an re-enabling a stream will ideally be
3657 * cheaper than destroying and re-opening a stream with the same configuration,
3658 * though there are no formal guarantees about what state or buffered data
3659 * must be retained between disabling and re-enabling a stream.
3661 * Note: while a stream is disabled it's considered an error for userspace
3662 * to attempt to read from the stream (-EIO).
3664 static void i915_perf_disable_locked(struct i915_perf_stream *stream)
3666 if (!stream->enabled)
3669 /* Allow stream->ops->disable() to refer to this */
3670 stream->enabled = false;
3672 if (stream->hold_preemption)
3673 intel_context_clear_nopreempt(stream->pinned_ctx);
3675 if (stream->ops->disable)
3676 stream->ops->disable(stream);
3679 static long i915_perf_config_locked(struct i915_perf_stream *stream,
3680 unsigned long metrics_set)
3682 struct i915_oa_config *config;
3683 long ret = stream->oa_config->id;
3685 config = i915_perf_get_oa_config(stream->perf, metrics_set);
3689 if (config != stream->oa_config) {
3693 * If OA is bound to a specific context, emit the
3694 * reconfiguration inline from that context. The update
3695 * will then be ordered with respect to submission on that
3698 * When set globally, we use a low priority kernel context,
3699 * so it will effectively take effect when idle.
3701 err = emit_oa_config(stream, config, oa_context(stream), NULL);
3703 config = xchg(&stream->oa_config, config);
3708 i915_oa_config_put(config);
3714 * i915_perf_ioctl_locked - support ioctl() usage with i915 perf stream FDs
3715 * @stream: An i915 perf stream
3716 * @cmd: the ioctl request
3717 * @arg: the ioctl data
3719 * Returns: zero on success or a negative error code. Returns -EINVAL for
3720 * an unknown ioctl request.
3722 static long i915_perf_ioctl_locked(struct i915_perf_stream *stream,
3727 case I915_PERF_IOCTL_ENABLE:
3728 i915_perf_enable_locked(stream);
3730 case I915_PERF_IOCTL_DISABLE:
3731 i915_perf_disable_locked(stream);
3733 case I915_PERF_IOCTL_CONFIG:
3734 return i915_perf_config_locked(stream, arg);
3741 * i915_perf_ioctl - support ioctl() usage with i915 perf stream FDs
3742 * @file: An i915 perf stream file
3743 * @cmd: the ioctl request
3744 * @arg: the ioctl data
3746 * Implementation deferred to i915_perf_ioctl_locked().
3748 * Returns: zero on success or a negative error code. Returns -EINVAL for
3749 * an unknown ioctl request.
3751 static long i915_perf_ioctl(struct file *file,
3755 struct i915_perf_stream *stream = file->private_data;
3758 mutex_lock(&stream->lock);
3759 ret = i915_perf_ioctl_locked(stream, cmd, arg);
3760 mutex_unlock(&stream->lock);
3766 * i915_perf_destroy_locked - destroy an i915 perf stream
3767 * @stream: An i915 perf stream
3769 * Frees all resources associated with the given i915 perf @stream, disabling
3770 * any associated data capture in the process.
3772 * Note: The >->perf.lock mutex has been taken to serialize
3773 * with any non-file-operation driver hooks.
3775 static void i915_perf_destroy_locked(struct i915_perf_stream *stream)
3777 if (stream->enabled)
3778 i915_perf_disable_locked(stream);
3780 if (stream->ops->destroy)
3781 stream->ops->destroy(stream);
3784 i915_gem_context_put(stream->ctx);
3790 * i915_perf_release - handles userspace close() of a stream file
3791 * @inode: anonymous inode associated with file
3792 * @file: An i915 perf stream file
3794 * Cleans up any resources associated with an open i915 perf stream file.
3796 * NB: close() can't really fail from the userspace point of view.
3798 * Returns: zero on success or a negative error code.
3800 static int i915_perf_release(struct inode *inode, struct file *file)
3802 struct i915_perf_stream *stream = file->private_data;
3803 struct i915_perf *perf = stream->perf;
3804 struct intel_gt *gt = stream->engine->gt;
3807 * Within this call, we know that the fd is being closed and we have no
3808 * other user of stream->lock. Use the perf lock to destroy the stream
3811 mutex_lock(>->perf.lock);
3812 i915_perf_destroy_locked(stream);
3813 mutex_unlock(>->perf.lock);
3815 /* Release the reference the perf stream kept on the driver. */
3816 drm_dev_put(&perf->i915->drm);
3822 static const struct file_operations fops = {
3823 .owner = THIS_MODULE,
3824 .llseek = no_llseek,
3825 .release = i915_perf_release,
3826 .poll = i915_perf_poll,
3827 .read = i915_perf_read,
3828 .unlocked_ioctl = i915_perf_ioctl,
3829 /* Our ioctl have no arguments, so it's safe to use the same function
3830 * to handle 32bits compatibility.
3832 .compat_ioctl = i915_perf_ioctl,
3837 * i915_perf_open_ioctl_locked - DRM ioctl() for userspace to open a stream FD
3838 * @perf: i915 perf instance
3839 * @param: The open parameters passed to 'DRM_I915_PERF_OPEN`
3840 * @props: individually validated u64 property value pairs
3843 * See i915_perf_ioctl_open() for interface details.
3845 * Implements further stream config validation and stream initialization on
3846 * behalf of i915_perf_open_ioctl() with the >->perf.lock mutex
3847 * taken to serialize with any non-file-operation driver hooks.
3849 * Note: at this point the @props have only been validated in isolation and
3850 * it's still necessary to validate that the combination of properties makes
3853 * In the case where userspace is interested in OA unit metrics then further
3854 * config validation and stream initialization details will be handled by
3855 * i915_oa_stream_init(). The code here should only validate config state that
3856 * will be relevant to all stream types / backends.
3858 * Returns: zero on success or a negative error code.
3861 i915_perf_open_ioctl_locked(struct i915_perf *perf,
3862 struct drm_i915_perf_open_param *param,
3863 struct perf_open_properties *props,
3864 struct drm_file *file)
3866 struct i915_gem_context *specific_ctx = NULL;
3867 struct i915_perf_stream *stream = NULL;
3868 unsigned long f_flags = 0;
3869 bool privileged_op = true;
3873 if (props->single_context) {
3874 u32 ctx_handle = props->ctx_handle;
3875 struct drm_i915_file_private *file_priv = file->driver_priv;
3877 specific_ctx = i915_gem_context_lookup(file_priv, ctx_handle);
3878 if (IS_ERR(specific_ctx)) {
3879 drm_dbg(&perf->i915->drm,
3880 "Failed to look up context with ID %u for opening perf stream\n",
3882 ret = PTR_ERR(specific_ctx);
3888 * On Haswell the OA unit supports clock gating off for a specific
3889 * context and in this mode there's no visibility of metrics for the
3890 * rest of the system, which we consider acceptable for a
3891 * non-privileged client.
3893 * For Gen8->11 the OA unit no longer supports clock gating off for a
3894 * specific context and the kernel can't securely stop the counters
3895 * from updating as system-wide / global values. Even though we can
3896 * filter reports based on the included context ID we can't block
3897 * clients from seeing the raw / global counter values via
3898 * MI_REPORT_PERF_COUNT commands and so consider it a privileged op to
3899 * enable the OA unit by default.
3901 * For Gen12+ we gain a new OAR unit that only monitors the RCS on a
3902 * per context basis. So we can relax requirements there if the user
3903 * doesn't request global stream access (i.e. query based sampling
3904 * using MI_RECORD_PERF_COUNT.
3906 if (IS_HASWELL(perf->i915) && specific_ctx)
3907 privileged_op = false;
3908 else if (GRAPHICS_VER(perf->i915) == 12 && specific_ctx &&
3909 (props->sample_flags & SAMPLE_OA_REPORT) == 0)
3910 privileged_op = false;
3912 if (props->hold_preemption) {
3913 if (!props->single_context) {
3914 drm_dbg(&perf->i915->drm,
3915 "preemption disable with no context\n");
3919 privileged_op = true;
3923 * Asking for SSEU configuration is a priviliged operation.
3925 if (props->has_sseu)
3926 privileged_op = true;
3928 get_default_sseu_config(&props->sseu, props->engine);
3930 /* Similar to perf's kernel.perf_paranoid_cpu sysctl option
3931 * we check a dev.i915.perf_stream_paranoid sysctl option
3932 * to determine if it's ok to access system wide OA counters
3933 * without CAP_PERFMON or CAP_SYS_ADMIN privileges.
3935 if (privileged_op &&
3936 i915_perf_stream_paranoid && !perfmon_capable()) {
3937 drm_dbg(&perf->i915->drm,
3938 "Insufficient privileges to open i915 perf stream\n");
3943 stream = kzalloc(sizeof(*stream), GFP_KERNEL);
3949 stream->perf = perf;
3950 stream->ctx = specific_ctx;
3951 stream->poll_oa_period = props->poll_oa_period;
3953 ret = i915_oa_stream_init(stream, param, props);
3957 /* we avoid simply assigning stream->sample_flags = props->sample_flags
3958 * to have _stream_init check the combination of sample flags more
3959 * thoroughly, but still this is the expected result at this point.
3961 if (WARN_ON(stream->sample_flags != props->sample_flags)) {
3966 if (param->flags & I915_PERF_FLAG_FD_CLOEXEC)
3967 f_flags |= O_CLOEXEC;
3968 if (param->flags & I915_PERF_FLAG_FD_NONBLOCK)
3969 f_flags |= O_NONBLOCK;
3971 stream_fd = anon_inode_getfd("[i915_perf]", &fops, stream, f_flags);
3972 if (stream_fd < 0) {
3977 if (!(param->flags & I915_PERF_FLAG_DISABLED))
3978 i915_perf_enable_locked(stream);
3980 /* Take a reference on the driver that will be kept with stream_fd
3981 * until its release.
3983 drm_dev_get(&perf->i915->drm);
3988 if (stream->ops->destroy)
3989 stream->ops->destroy(stream);
3994 i915_gem_context_put(specific_ctx);
3999 static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent)
4001 u64 nom = (2ULL << exponent) * NSEC_PER_SEC;
4002 u32 den = i915_perf_oa_timestamp_frequency(perf->i915);
4004 return div_u64(nom + den - 1, den);
4007 static __always_inline bool
4008 oa_format_valid(struct i915_perf *perf, enum drm_i915_oa_format format)
4010 return test_bit(format, perf->format_mask);
4013 static __always_inline void
4014 oa_format_add(struct i915_perf *perf, enum drm_i915_oa_format format)
4016 __set_bit(format, perf->format_mask);
4020 * read_properties_unlocked - validate + copy userspace stream open properties
4021 * @perf: i915 perf instance
4022 * @uprops: The array of u64 key value pairs given by userspace
4023 * @n_props: The number of key value pairs expected in @uprops
4024 * @props: The stream configuration built up while validating properties
4026 * Note this function only validates properties in isolation it doesn't
4027 * validate that the combination of properties makes sense or that all
4028 * properties necessary for a particular kind of stream have been set.
4030 * Note that there currently aren't any ordering requirements for properties so
4031 * we shouldn't validate or assume anything about ordering here. This doesn't
4032 * rule out defining new properties with ordering requirements in the future.
4034 static int read_properties_unlocked(struct i915_perf *perf,
4037 struct perf_open_properties *props)
4039 struct drm_i915_gem_context_param_sseu user_sseu;
4040 const struct i915_oa_format *f;
4041 u64 __user *uprop = uprops;
4042 bool config_instance = false;
4043 bool config_class = false;
4044 bool config_sseu = false;
4049 memset(props, 0, sizeof(struct perf_open_properties));
4050 props->poll_oa_period = DEFAULT_POLL_PERIOD_NS;
4052 /* Considering that ID = 0 is reserved and assuming that we don't
4053 * (currently) expect any configurations to ever specify duplicate
4054 * values for a particular property ID then the last _PROP_MAX value is
4055 * one greater than the maximum number of properties we expect to get
4058 if (!n_props || n_props >= DRM_I915_PERF_PROP_MAX) {
4059 drm_dbg(&perf->i915->drm,
4060 "Invalid number of i915 perf properties given\n");
4064 /* Defaults when class:instance is not passed */
4065 class = I915_ENGINE_CLASS_RENDER;
4068 for (i = 0; i < n_props; i++) {
4069 u64 oa_period, oa_freq_hz;
4072 ret = get_user(id, uprop);
4076 ret = get_user(value, uprop + 1);
4080 if (id == 0 || id >= DRM_I915_PERF_PROP_MAX) {
4081 drm_dbg(&perf->i915->drm,
4082 "Unknown i915 perf property ID\n");
4086 switch ((enum drm_i915_perf_property_id)id) {
4087 case DRM_I915_PERF_PROP_CTX_HANDLE:
4088 props->single_context = 1;
4089 props->ctx_handle = value;
4091 case DRM_I915_PERF_PROP_SAMPLE_OA:
4093 props->sample_flags |= SAMPLE_OA_REPORT;
4095 case DRM_I915_PERF_PROP_OA_METRICS_SET:
4097 drm_dbg(&perf->i915->drm,
4098 "Unknown OA metric set ID\n");
4101 props->metrics_set = value;
4103 case DRM_I915_PERF_PROP_OA_FORMAT:
4104 if (value == 0 || value >= I915_OA_FORMAT_MAX) {
4105 drm_dbg(&perf->i915->drm,
4106 "Out-of-range OA report format %llu\n",
4110 if (!oa_format_valid(perf, value)) {
4111 drm_dbg(&perf->i915->drm,
4112 "Unsupported OA report format %llu\n",
4116 props->oa_format = value;
4118 case DRM_I915_PERF_PROP_OA_EXPONENT:
4119 if (value > OA_EXPONENT_MAX) {
4120 drm_dbg(&perf->i915->drm,
4121 "OA timer exponent too high (> %u)\n",
4126 /* Theoretically we can program the OA unit to sample
4127 * e.g. every 160ns for HSW, 167ns for BDW/SKL or 104ns
4128 * for BXT. We don't allow such high sampling
4129 * frequencies by default unless root.
4132 BUILD_BUG_ON(sizeof(oa_period) != 8);
4133 oa_period = oa_exponent_to_ns(perf, value);
4135 /* This check is primarily to ensure that oa_period <=
4136 * UINT32_MAX (before passing to do_div which only
4137 * accepts a u32 denominator), but we can also skip
4138 * checking anything < 1Hz which implicitly can't be
4139 * limited via an integer oa_max_sample_rate.
4141 if (oa_period <= NSEC_PER_SEC) {
4142 u64 tmp = NSEC_PER_SEC;
4143 do_div(tmp, oa_period);
4148 if (oa_freq_hz > i915_oa_max_sample_rate && !perfmon_capable()) {
4149 drm_dbg(&perf->i915->drm,
4150 "OA exponent would exceed the max sampling frequency (sysctl dev.i915.oa_max_sample_rate) %uHz without CAP_PERFMON or CAP_SYS_ADMIN privileges\n",
4151 i915_oa_max_sample_rate);
4155 props->oa_periodic = true;
4156 props->oa_period_exponent = value;
4158 case DRM_I915_PERF_PROP_HOLD_PREEMPTION:
4159 props->hold_preemption = !!value;
4161 case DRM_I915_PERF_PROP_GLOBAL_SSEU: {
4162 if (GRAPHICS_VER_FULL(perf->i915) >= IP_VER(12, 50)) {
4163 drm_dbg(&perf->i915->drm,
4164 "SSEU config not supported on gfx %x\n",
4165 GRAPHICS_VER_FULL(perf->i915));
4169 if (copy_from_user(&user_sseu,
4170 u64_to_user_ptr(value),
4171 sizeof(user_sseu))) {
4172 drm_dbg(&perf->i915->drm,
4173 "Unable to copy global sseu parameter\n");
4179 case DRM_I915_PERF_PROP_POLL_OA_PERIOD:
4180 if (value < 100000 /* 100us */) {
4181 drm_dbg(&perf->i915->drm,
4182 "OA availability timer too small (%lluns < 100us)\n",
4186 props->poll_oa_period = value;
4188 case DRM_I915_PERF_PROP_OA_ENGINE_CLASS:
4190 config_class = true;
4192 case DRM_I915_PERF_PROP_OA_ENGINE_INSTANCE:
4193 instance = (u8)value;
4194 config_instance = true;
4204 if ((config_class && !config_instance) ||
4205 (config_instance && !config_class)) {
4206 drm_dbg(&perf->i915->drm,
4207 "OA engine-class and engine-instance parameters must be passed together\n");
4211 props->engine = intel_engine_lookup_user(perf->i915, class, instance);
4212 if (!props->engine) {
4213 drm_dbg(&perf->i915->drm,
4214 "OA engine class and instance invalid %d:%d\n",
4219 if (!engine_supports_oa(props->engine)) {
4220 drm_dbg(&perf->i915->drm,
4221 "Engine not supported by OA %d:%d\n",
4226 i = array_index_nospec(props->oa_format, I915_OA_FORMAT_MAX);
4227 f = &perf->oa_formats[i];
4228 if (!engine_supports_oa_format(props->engine, f->type)) {
4229 drm_dbg(&perf->i915->drm,
4230 "Invalid OA format %d for class %d\n",
4231 f->type, props->engine->class);
4236 ret = get_sseu_config(&props->sseu, props->engine, &user_sseu);
4238 drm_dbg(&perf->i915->drm,
4239 "Invalid SSEU configuration\n");
4242 props->has_sseu = true;
4249 * i915_perf_open_ioctl - DRM ioctl() for userspace to open a stream FD
4251 * @data: ioctl data copied from userspace (unvalidated)
4254 * Validates the stream open parameters given by userspace including flags
4255 * and an array of u64 key, value pair properties.
4257 * Very little is assumed up front about the nature of the stream being
4258 * opened (for instance we don't assume it's for periodic OA unit metrics). An
4259 * i915-perf stream is expected to be a suitable interface for other forms of
4260 * buffered data written by the GPU besides periodic OA metrics.
4262 * Note we copy the properties from userspace outside of the i915 perf
4263 * mutex to avoid an awkward lockdep with mmap_lock.
4265 * Most of the implementation details are handled by
4266 * i915_perf_open_ioctl_locked() after taking the >->perf.lock
4267 * mutex for serializing with any non-file-operation driver hooks.
4269 * Return: A newly opened i915 Perf stream file descriptor or negative
4270 * error code on failure.
4272 int i915_perf_open_ioctl(struct drm_device *dev, void *data,
4273 struct drm_file *file)
4275 struct i915_perf *perf = &to_i915(dev)->perf;
4276 struct drm_i915_perf_open_param *param = data;
4277 struct intel_gt *gt;
4278 struct perf_open_properties props;
4279 u32 known_open_flags;
4283 drm_dbg(&perf->i915->drm,
4284 "i915 perf interface not available for this system\n");
4288 known_open_flags = I915_PERF_FLAG_FD_CLOEXEC |
4289 I915_PERF_FLAG_FD_NONBLOCK |
4290 I915_PERF_FLAG_DISABLED;
4291 if (param->flags & ~known_open_flags) {
4292 drm_dbg(&perf->i915->drm,
4293 "Unknown drm_i915_perf_open_param flag\n");
4297 ret = read_properties_unlocked(perf,
4298 u64_to_user_ptr(param->properties_ptr),
4299 param->num_properties,
4304 gt = props.engine->gt;
4306 mutex_lock(>->perf.lock);
4307 ret = i915_perf_open_ioctl_locked(perf, param, &props, file);
4308 mutex_unlock(>->perf.lock);
4314 * i915_perf_register - exposes i915-perf to userspace
4315 * @i915: i915 device instance
4317 * In particular OA metric sets are advertised under a sysfs metrics/
4318 * directory allowing userspace to enumerate valid IDs that can be
4319 * used to open an i915-perf stream.
4321 void i915_perf_register(struct drm_i915_private *i915)
4323 struct i915_perf *perf = &i915->perf;
4324 struct intel_gt *gt = to_gt(i915);
4329 /* To be sure we're synchronized with an attempted
4330 * i915_perf_open_ioctl(); considering that we register after
4331 * being exposed to userspace.
4333 mutex_lock(>->perf.lock);
4335 perf->metrics_kobj =
4336 kobject_create_and_add("metrics",
4337 &i915->drm.primary->kdev->kobj);
4339 mutex_unlock(>->perf.lock);
4343 * i915_perf_unregister - hide i915-perf from userspace
4344 * @i915: i915 device instance
4346 * i915-perf state cleanup is split up into an 'unregister' and
4347 * 'deinit' phase where the interface is first hidden from
4348 * userspace by i915_perf_unregister() before cleaning up
4349 * remaining state in i915_perf_fini().
4351 void i915_perf_unregister(struct drm_i915_private *i915)
4353 struct i915_perf *perf = &i915->perf;
4355 if (!perf->metrics_kobj)
4358 kobject_put(perf->metrics_kobj);
4359 perf->metrics_kobj = NULL;
4362 static bool gen8_is_valid_flex_addr(struct i915_perf *perf, u32 addr)
4364 static const i915_reg_t flex_eu_regs[] = {
4375 for (i = 0; i < ARRAY_SIZE(flex_eu_regs); i++) {
4376 if (i915_mmio_reg_offset(flex_eu_regs[i]) == addr)
4382 static bool reg_in_range_table(u32 addr, const struct i915_range *table)
4384 while (table->start || table->end) {
4385 if (addr >= table->start && addr <= table->end)
4394 #define REG_EQUAL(addr, mmio) \
4395 ((addr) == i915_mmio_reg_offset(mmio))
4397 static const struct i915_range gen7_oa_b_counters[] = {
4398 { .start = 0x2710, .end = 0x272c }, /* OASTARTTRIG[1-8] */
4399 { .start = 0x2740, .end = 0x275c }, /* OAREPORTTRIG[1-8] */
4400 { .start = 0x2770, .end = 0x27ac }, /* OACEC[0-7][0-1] */
4404 static const struct i915_range gen12_oa_b_counters[] = {
4405 { .start = 0x2b2c, .end = 0x2b2c }, /* GEN12_OAG_OA_PESS */
4406 { .start = 0xd900, .end = 0xd91c }, /* GEN12_OAG_OASTARTTRIG[1-8] */
4407 { .start = 0xd920, .end = 0xd93c }, /* GEN12_OAG_OAREPORTTRIG1[1-8] */
4408 { .start = 0xd940, .end = 0xd97c }, /* GEN12_OAG_CEC[0-7][0-1] */
4409 { .start = 0xdc00, .end = 0xdc3c }, /* GEN12_OAG_SCEC[0-7][0-1] */
4410 { .start = 0xdc40, .end = 0xdc40 }, /* GEN12_OAG_SPCTR_CNF */
4411 { .start = 0xdc44, .end = 0xdc44 }, /* GEN12_OAA_DBG_REG */
4415 static const struct i915_range mtl_oam_b_counters[] = {
4416 { .start = 0x393000, .end = 0x39301c }, /* GEN12_OAM_STARTTRIG1[1-8] */
4417 { .start = 0x393020, .end = 0x39303c }, /* GEN12_OAM_REPORTTRIG1[1-8] */
4418 { .start = 0x393040, .end = 0x39307c }, /* GEN12_OAM_CEC[0-7][0-1] */
4419 { .start = 0x393200, .end = 0x39323C }, /* MPES[0-7] */
4423 static const struct i915_range xehp_oa_b_counters[] = {
4424 { .start = 0xdc48, .end = 0xdc48 }, /* OAA_ENABLE_REG */
4425 { .start = 0xdd00, .end = 0xdd48 }, /* OAG_LCE0_0 - OAA_LENABLE_REG */
4428 static const struct i915_range gen7_oa_mux_regs[] = {
4429 { .start = 0x91b8, .end = 0x91cc }, /* OA_PERFCNT[1-2], OA_PERFMATRIX */
4430 { .start = 0x9800, .end = 0x9888 }, /* MICRO_BP0_0 - NOA_WRITE */
4431 { .start = 0xe180, .end = 0xe180 }, /* HALF_SLICE_CHICKEN2 */
4435 static const struct i915_range hsw_oa_mux_regs[] = {
4436 { .start = 0x09e80, .end = 0x09ea4 }, /* HSW_MBVID2_NOA[0-9] */
4437 { .start = 0x09ec0, .end = 0x09ec0 }, /* HSW_MBVID2_MISR0 */
4438 { .start = 0x25100, .end = 0x2ff90 },
4442 static const struct i915_range chv_oa_mux_regs[] = {
4443 { .start = 0x182300, .end = 0x1823a4 },
4447 static const struct i915_range gen8_oa_mux_regs[] = {
4448 { .start = 0x0d00, .end = 0x0d2c }, /* RPM_CONFIG[0-1], NOA_CONFIG[0-8] */
4449 { .start = 0x20cc, .end = 0x20cc }, /* WAIT_FOR_RC6_EXIT */
4453 static const struct i915_range gen11_oa_mux_regs[] = {
4454 { .start = 0x91c8, .end = 0x91dc }, /* OA_PERFCNT[3-4] */
4458 static const struct i915_range gen12_oa_mux_regs[] = {
4459 { .start = 0x0d00, .end = 0x0d04 }, /* RPM_CONFIG[0-1] */
4460 { .start = 0x0d0c, .end = 0x0d2c }, /* NOA_CONFIG[0-8] */
4461 { .start = 0x9840, .end = 0x9840 }, /* GDT_CHICKEN_BITS */
4462 { .start = 0x9884, .end = 0x9888 }, /* NOA_WRITE */
4463 { .start = 0x20cc, .end = 0x20cc }, /* WAIT_FOR_RC6_EXIT */
4469 * 0x20cc is repurposed on MTL, so use a separate array for MTL.
4471 static const struct i915_range mtl_oa_mux_regs[] = {
4472 { .start = 0x0d00, .end = 0x0d04 }, /* RPM_CONFIG[0-1] */
4473 { .start = 0x0d0c, .end = 0x0d2c }, /* NOA_CONFIG[0-8] */
4474 { .start = 0x9840, .end = 0x9840 }, /* GDT_CHICKEN_BITS */
4475 { .start = 0x9884, .end = 0x9888 }, /* NOA_WRITE */
4476 { .start = 0x38d100, .end = 0x38d114}, /* VISACTL */
4480 static bool gen7_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
4482 return reg_in_range_table(addr, gen7_oa_b_counters);
4485 static bool gen8_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
4487 return reg_in_range_table(addr, gen7_oa_mux_regs) ||
4488 reg_in_range_table(addr, gen8_oa_mux_regs);
4491 static bool gen11_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
4493 return reg_in_range_table(addr, gen7_oa_mux_regs) ||
4494 reg_in_range_table(addr, gen8_oa_mux_regs) ||
4495 reg_in_range_table(addr, gen11_oa_mux_regs);
4498 static bool hsw_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
4500 return reg_in_range_table(addr, gen7_oa_mux_regs) ||
4501 reg_in_range_table(addr, hsw_oa_mux_regs);
4504 static bool chv_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
4506 return reg_in_range_table(addr, gen7_oa_mux_regs) ||
4507 reg_in_range_table(addr, chv_oa_mux_regs);
4510 static bool gen12_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
4512 return reg_in_range_table(addr, gen12_oa_b_counters);
4515 static bool mtl_is_valid_oam_b_counter_addr(struct i915_perf *perf, u32 addr)
4517 if (HAS_OAM(perf->i915) &&
4518 GRAPHICS_VER_FULL(perf->i915) >= IP_VER(12, 70))
4519 return reg_in_range_table(addr, mtl_oam_b_counters);
4524 static bool xehp_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
4526 return reg_in_range_table(addr, xehp_oa_b_counters) ||
4527 reg_in_range_table(addr, gen12_oa_b_counters) ||
4528 mtl_is_valid_oam_b_counter_addr(perf, addr);
4531 static bool gen12_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
4533 if (IS_METEORLAKE(perf->i915))
4534 return reg_in_range_table(addr, mtl_oa_mux_regs);
4536 return reg_in_range_table(addr, gen12_oa_mux_regs);
4539 static u32 mask_reg_value(u32 reg, u32 val)
4541 /* HALF_SLICE_CHICKEN2 is programmed with a the
4542 * WaDisableSTUnitPowerOptimization workaround. Make sure the value
4543 * programmed by userspace doesn't change this.
4545 if (REG_EQUAL(reg, HALF_SLICE_CHICKEN2))
4546 val = val & ~_MASKED_BIT_ENABLE(GEN8_ST_PO_DISABLE);
4548 /* WAIT_FOR_RC6_EXIT has only one bit fullfilling the function
4549 * indicated by its name and a bunch of selection fields used by OA
4552 if (REG_EQUAL(reg, WAIT_FOR_RC6_EXIT))
4553 val = val & ~_MASKED_BIT_ENABLE(HSW_WAIT_FOR_RC6_EXIT_ENABLE);
4558 static struct i915_oa_reg *alloc_oa_regs(struct i915_perf *perf,
4559 bool (*is_valid)(struct i915_perf *perf, u32 addr),
4563 struct i915_oa_reg *oa_regs;
4570 /* No is_valid function means we're not allowing any register to be programmed. */
4571 GEM_BUG_ON(!is_valid);
4573 return ERR_PTR(-EINVAL);
4575 oa_regs = kmalloc_array(n_regs, sizeof(*oa_regs), GFP_KERNEL);
4577 return ERR_PTR(-ENOMEM);
4579 for (i = 0; i < n_regs; i++) {
4582 err = get_user(addr, regs);
4586 if (!is_valid(perf, addr)) {
4587 drm_dbg(&perf->i915->drm,
4588 "Invalid oa_reg address: %X\n", addr);
4593 err = get_user(value, regs + 1);
4597 oa_regs[i].addr = _MMIO(addr);
4598 oa_regs[i].value = mask_reg_value(addr, value);
4607 return ERR_PTR(err);
4610 static ssize_t show_dynamic_id(struct kobject *kobj,
4611 struct kobj_attribute *attr,
4614 struct i915_oa_config *oa_config =
4615 container_of(attr, typeof(*oa_config), sysfs_metric_id);
4617 return sprintf(buf, "%d\n", oa_config->id);
4620 static int create_dynamic_oa_sysfs_entry(struct i915_perf *perf,
4621 struct i915_oa_config *oa_config)
4623 sysfs_attr_init(&oa_config->sysfs_metric_id.attr);
4624 oa_config->sysfs_metric_id.attr.name = "id";
4625 oa_config->sysfs_metric_id.attr.mode = S_IRUGO;
4626 oa_config->sysfs_metric_id.show = show_dynamic_id;
4627 oa_config->sysfs_metric_id.store = NULL;
4629 oa_config->attrs[0] = &oa_config->sysfs_metric_id.attr;
4630 oa_config->attrs[1] = NULL;
4632 oa_config->sysfs_metric.name = oa_config->uuid;
4633 oa_config->sysfs_metric.attrs = oa_config->attrs;
4635 return sysfs_create_group(perf->metrics_kobj,
4636 &oa_config->sysfs_metric);
4640 * i915_perf_add_config_ioctl - DRM ioctl() for userspace to add a new OA config
4642 * @data: ioctl data (pointer to struct drm_i915_perf_oa_config) copied from
4643 * userspace (unvalidated)
4646 * Validates the submitted OA register to be saved into a new OA config that
4647 * can then be used for programming the OA unit and its NOA network.
4649 * Returns: A new allocated config number to be used with the perf open ioctl
4650 * or a negative error code on failure.
4652 int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
4653 struct drm_file *file)
4655 struct i915_perf *perf = &to_i915(dev)->perf;
4656 struct drm_i915_perf_oa_config *args = data;
4657 struct i915_oa_config *oa_config, *tmp;
4658 struct i915_oa_reg *regs;
4662 drm_dbg(&perf->i915->drm,
4663 "i915 perf interface not available for this system\n");
4667 if (!perf->metrics_kobj) {
4668 drm_dbg(&perf->i915->drm,
4669 "OA metrics weren't advertised via sysfs\n");
4673 if (i915_perf_stream_paranoid && !perfmon_capable()) {
4674 drm_dbg(&perf->i915->drm,
4675 "Insufficient privileges to add i915 OA config\n");
4679 if ((!args->mux_regs_ptr || !args->n_mux_regs) &&
4680 (!args->boolean_regs_ptr || !args->n_boolean_regs) &&
4681 (!args->flex_regs_ptr || !args->n_flex_regs)) {
4682 drm_dbg(&perf->i915->drm,
4683 "No OA registers given\n");
4687 oa_config = kzalloc(sizeof(*oa_config), GFP_KERNEL);
4689 drm_dbg(&perf->i915->drm,
4690 "Failed to allocate memory for the OA config\n");
4694 oa_config->perf = perf;
4695 kref_init(&oa_config->ref);
4697 if (!uuid_is_valid(args->uuid)) {
4698 drm_dbg(&perf->i915->drm,
4699 "Invalid uuid format for OA config\n");
4704 /* Last character in oa_config->uuid will be 0 because oa_config is
4707 memcpy(oa_config->uuid, args->uuid, sizeof(args->uuid));
4709 oa_config->mux_regs_len = args->n_mux_regs;
4710 regs = alloc_oa_regs(perf,
4711 perf->ops.is_valid_mux_reg,
4712 u64_to_user_ptr(args->mux_regs_ptr),
4716 drm_dbg(&perf->i915->drm,
4717 "Failed to create OA config for mux_regs\n");
4718 err = PTR_ERR(regs);
4721 oa_config->mux_regs = regs;
4723 oa_config->b_counter_regs_len = args->n_boolean_regs;
4724 regs = alloc_oa_regs(perf,
4725 perf->ops.is_valid_b_counter_reg,
4726 u64_to_user_ptr(args->boolean_regs_ptr),
4727 args->n_boolean_regs);
4730 drm_dbg(&perf->i915->drm,
4731 "Failed to create OA config for b_counter_regs\n");
4732 err = PTR_ERR(regs);
4735 oa_config->b_counter_regs = regs;
4737 if (GRAPHICS_VER(perf->i915) < 8) {
4738 if (args->n_flex_regs != 0) {
4743 oa_config->flex_regs_len = args->n_flex_regs;
4744 regs = alloc_oa_regs(perf,
4745 perf->ops.is_valid_flex_reg,
4746 u64_to_user_ptr(args->flex_regs_ptr),
4750 drm_dbg(&perf->i915->drm,
4751 "Failed to create OA config for flex_regs\n");
4752 err = PTR_ERR(regs);
4755 oa_config->flex_regs = regs;
4758 err = mutex_lock_interruptible(&perf->metrics_lock);
4762 /* We shouldn't have too many configs, so this iteration shouldn't be
4765 idr_for_each_entry(&perf->metrics_idr, tmp, id) {
4766 if (!strcmp(tmp->uuid, oa_config->uuid)) {
4767 drm_dbg(&perf->i915->drm,
4768 "OA config already exists with this uuid\n");
4774 err = create_dynamic_oa_sysfs_entry(perf, oa_config);
4776 drm_dbg(&perf->i915->drm,
4777 "Failed to create sysfs entry for OA config\n");
4781 /* Config id 0 is invalid, id 1 for kernel stored test config. */
4782 oa_config->id = idr_alloc(&perf->metrics_idr,
4785 if (oa_config->id < 0) {
4786 drm_dbg(&perf->i915->drm,
4787 "Failed to create sysfs entry for OA config\n");
4788 err = oa_config->id;
4792 mutex_unlock(&perf->metrics_lock);
4794 drm_dbg(&perf->i915->drm,
4795 "Added config %s id=%i\n", oa_config->uuid, oa_config->id);
4797 return oa_config->id;
4800 mutex_unlock(&perf->metrics_lock);
4802 i915_oa_config_put(oa_config);
4803 drm_dbg(&perf->i915->drm,
4804 "Failed to add new OA config\n");
4809 * i915_perf_remove_config_ioctl - DRM ioctl() for userspace to remove an OA config
4811 * @data: ioctl data (pointer to u64 integer) copied from userspace
4814 * Configs can be removed while being used, the will stop appearing in sysfs
4815 * and their content will be freed when the stream using the config is closed.
4817 * Returns: 0 on success or a negative error code on failure.
4819 int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data,
4820 struct drm_file *file)
4822 struct i915_perf *perf = &to_i915(dev)->perf;
4824 struct i915_oa_config *oa_config;
4828 drm_dbg(&perf->i915->drm,
4829 "i915 perf interface not available for this system\n");
4833 if (i915_perf_stream_paranoid && !perfmon_capable()) {
4834 drm_dbg(&perf->i915->drm,
4835 "Insufficient privileges to remove i915 OA config\n");
4839 ret = mutex_lock_interruptible(&perf->metrics_lock);
4843 oa_config = idr_find(&perf->metrics_idr, *arg);
4845 drm_dbg(&perf->i915->drm,
4846 "Failed to remove unknown OA config\n");
4851 GEM_BUG_ON(*arg != oa_config->id);
4853 sysfs_remove_group(perf->metrics_kobj, &oa_config->sysfs_metric);
4855 idr_remove(&perf->metrics_idr, *arg);
4857 mutex_unlock(&perf->metrics_lock);
4859 drm_dbg(&perf->i915->drm,
4860 "Removed config %s id=%i\n", oa_config->uuid, oa_config->id);
4862 i915_oa_config_put(oa_config);
4867 mutex_unlock(&perf->metrics_lock);
4871 static struct ctl_table oa_table[] = {
4873 .procname = "perf_stream_paranoid",
4874 .data = &i915_perf_stream_paranoid,
4875 .maxlen = sizeof(i915_perf_stream_paranoid),
4877 .proc_handler = proc_dointvec_minmax,
4878 .extra1 = SYSCTL_ZERO,
4879 .extra2 = SYSCTL_ONE,
4882 .procname = "oa_max_sample_rate",
4883 .data = &i915_oa_max_sample_rate,
4884 .maxlen = sizeof(i915_oa_max_sample_rate),
4886 .proc_handler = proc_dointvec_minmax,
4887 .extra1 = SYSCTL_ZERO,
4888 .extra2 = &oa_sample_rate_hard_limit,
4893 static u32 num_perf_groups_per_gt(struct intel_gt *gt)
4898 static u32 __oam_engine_group(struct intel_engine_cs *engine)
4900 if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70)) {
4902 * There's 1 SAMEDIA gt and 1 OAM per SAMEDIA gt. All media slices
4903 * within the gt use the same OAM. All MTL SKUs list 1 SA MEDIA.
4905 drm_WARN_ON(&engine->i915->drm,
4906 engine->gt->type != GT_MEDIA);
4908 return PERF_GROUP_OAM_SAMEDIA_0;
4911 return PERF_GROUP_INVALID;
4914 static u32 __oa_engine_group(struct intel_engine_cs *engine)
4916 switch (engine->class) {
4918 return PERF_GROUP_OAG;
4920 case VIDEO_DECODE_CLASS:
4921 case VIDEO_ENHANCEMENT_CLASS:
4922 return __oam_engine_group(engine);
4925 return PERF_GROUP_INVALID;
4929 static struct i915_perf_regs __oam_regs(u32 base)
4931 return (struct i915_perf_regs) {
4933 GEN12_OAM_HEAD_POINTER(base),
4934 GEN12_OAM_TAIL_POINTER(base),
4935 GEN12_OAM_BUFFER(base),
4936 GEN12_OAM_CONTEXT_CONTROL(base),
4937 GEN12_OAM_CONTROL(base),
4938 GEN12_OAM_DEBUG(base),
4939 GEN12_OAM_STATUS(base),
4940 GEN12_OAM_CONTROL_COUNTER_FORMAT_SHIFT,
4944 static struct i915_perf_regs __oag_regs(void)
4946 return (struct i915_perf_regs) {
4948 GEN12_OAG_OAHEADPTR,
4949 GEN12_OAG_OATAILPTR,
4951 GEN12_OAG_OAGLBCTXCTRL,
4952 GEN12_OAG_OACONTROL,
4955 GEN12_OAG_OACONTROL_OA_COUNTER_FORMAT_SHIFT,
4959 static void oa_init_groups(struct intel_gt *gt)
4961 int i, num_groups = gt->perf.num_perf_groups;
4963 for (i = 0; i < num_groups; i++) {
4964 struct i915_perf_group *g = >->perf.group[i];
4966 /* Fused off engines can result in a group with num_engines == 0 */
4967 if (g->num_engines == 0)
4970 if (i == PERF_GROUP_OAG && gt->type != GT_MEDIA) {
4971 g->regs = __oag_regs();
4973 } else if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)) {
4974 g->regs = __oam_regs(mtl_oa_base[i]);
4980 static int oa_init_gt(struct intel_gt *gt)
4982 u32 num_groups = num_perf_groups_per_gt(gt);
4983 struct intel_engine_cs *engine;
4984 struct i915_perf_group *g;
4985 intel_engine_mask_t tmp;
4987 g = kcalloc(num_groups, sizeof(*g), GFP_KERNEL);
4991 for_each_engine_masked(engine, gt, ALL_ENGINES, tmp) {
4992 u32 index = __oa_engine_group(engine);
4994 engine->oa_group = NULL;
4995 if (index < num_groups) {
4996 g[index].num_engines++;
4997 engine->oa_group = &g[index];
5001 gt->perf.num_perf_groups = num_groups;
5009 static int oa_init_engine_groups(struct i915_perf *perf)
5011 struct intel_gt *gt;
5014 for_each_gt(gt, perf->i915, i) {
5015 ret = oa_init_gt(gt);
5023 static void oa_init_supported_formats(struct i915_perf *perf)
5025 struct drm_i915_private *i915 = perf->i915;
5026 enum intel_platform platform = INTEL_INFO(i915)->platform;
5030 oa_format_add(perf, I915_OA_FORMAT_A13);
5031 oa_format_add(perf, I915_OA_FORMAT_A13);
5032 oa_format_add(perf, I915_OA_FORMAT_A29);
5033 oa_format_add(perf, I915_OA_FORMAT_A13_B8_C8);
5034 oa_format_add(perf, I915_OA_FORMAT_B4_C8);
5035 oa_format_add(perf, I915_OA_FORMAT_A45_B8_C8);
5036 oa_format_add(perf, I915_OA_FORMAT_B4_C8_A16);
5037 oa_format_add(perf, I915_OA_FORMAT_C4_B8);
5040 case INTEL_BROADWELL:
5041 case INTEL_CHERRYVIEW:
5044 case INTEL_KABYLAKE:
5045 case INTEL_GEMINILAKE:
5046 case INTEL_COFFEELAKE:
5047 case INTEL_COMETLAKE:
5049 case INTEL_ELKHARTLAKE:
5050 case INTEL_JASPERLAKE:
5051 case INTEL_TIGERLAKE:
5052 case INTEL_ROCKETLAKE:
5054 case INTEL_ALDERLAKE_S:
5055 case INTEL_ALDERLAKE_P:
5056 oa_format_add(perf, I915_OA_FORMAT_A12);
5057 oa_format_add(perf, I915_OA_FORMAT_A12_B8_C8);
5058 oa_format_add(perf, I915_OA_FORMAT_A32u40_A4u32_B8_C8);
5059 oa_format_add(perf, I915_OA_FORMAT_C4_B8);
5063 oa_format_add(perf, I915_OAR_FORMAT_A32u40_A4u32_B8_C8);
5064 oa_format_add(perf, I915_OA_FORMAT_A24u40_A14u32_B8_C8);
5067 case INTEL_METEORLAKE:
5068 oa_format_add(perf, I915_OAR_FORMAT_A32u40_A4u32_B8_C8);
5069 oa_format_add(perf, I915_OA_FORMAT_A24u40_A14u32_B8_C8);
5070 oa_format_add(perf, I915_OAM_FORMAT_MPEC8u64_B8_C8);
5071 oa_format_add(perf, I915_OAM_FORMAT_MPEC8u32_B8_C8);
5075 MISSING_CASE(platform);
5079 static void i915_perf_init_info(struct drm_i915_private *i915)
5081 struct i915_perf *perf = &i915->perf;
5083 switch (GRAPHICS_VER(i915)) {
5085 perf->ctx_oactxctrl_offset = 0x120;
5086 perf->ctx_flexeu0_offset = 0x2ce;
5087 perf->gen8_valid_ctx_bit = BIT(25);
5090 perf->ctx_oactxctrl_offset = 0x128;
5091 perf->ctx_flexeu0_offset = 0x3de;
5092 perf->gen8_valid_ctx_bit = BIT(16);
5095 perf->ctx_oactxctrl_offset = 0x124;
5096 perf->ctx_flexeu0_offset = 0x78e;
5097 perf->gen8_valid_ctx_bit = BIT(16);
5101 * Calculate offset at runtime in oa_pin_context for gen12 and
5102 * cache the value in perf->ctx_oactxctrl_offset.
5106 MISSING_CASE(GRAPHICS_VER(i915));
5111 * i915_perf_init - initialize i915-perf state on module bind
5112 * @i915: i915 device instance
5114 * Initializes i915-perf state without exposing anything to userspace.
5116 * Note: i915-perf initialization is split into an 'init' and 'register'
5117 * phase with the i915_perf_register() exposing state to userspace.
5119 int i915_perf_init(struct drm_i915_private *i915)
5121 struct i915_perf *perf = &i915->perf;
5123 perf->oa_formats = oa_formats;
5124 if (IS_HASWELL(i915)) {
5125 perf->ops.is_valid_b_counter_reg = gen7_is_valid_b_counter_addr;
5126 perf->ops.is_valid_mux_reg = hsw_is_valid_mux_addr;
5127 perf->ops.is_valid_flex_reg = NULL;
5128 perf->ops.enable_metric_set = hsw_enable_metric_set;
5129 perf->ops.disable_metric_set = hsw_disable_metric_set;
5130 perf->ops.oa_enable = gen7_oa_enable;
5131 perf->ops.oa_disable = gen7_oa_disable;
5132 perf->ops.read = gen7_oa_read;
5133 perf->ops.oa_hw_tail_read = gen7_oa_hw_tail_read;
5134 } else if (HAS_LOGICAL_RING_CONTEXTS(i915)) {
5135 /* Note: that although we could theoretically also support the
5136 * legacy ringbuffer mode on BDW (and earlier iterations of
5137 * this driver, before upstreaming did this) it didn't seem
5138 * worth the complexity to maintain now that BDW+ enable
5139 * execlist mode by default.
5141 perf->ops.read = gen8_oa_read;
5142 i915_perf_init_info(i915);
5144 if (IS_GRAPHICS_VER(i915, 8, 9)) {
5145 perf->ops.is_valid_b_counter_reg =
5146 gen7_is_valid_b_counter_addr;
5147 perf->ops.is_valid_mux_reg =
5148 gen8_is_valid_mux_addr;
5149 perf->ops.is_valid_flex_reg =
5150 gen8_is_valid_flex_addr;
5152 if (IS_CHERRYVIEW(i915)) {
5153 perf->ops.is_valid_mux_reg =
5154 chv_is_valid_mux_addr;
5157 perf->ops.oa_enable = gen8_oa_enable;
5158 perf->ops.oa_disable = gen8_oa_disable;
5159 perf->ops.enable_metric_set = gen8_enable_metric_set;
5160 perf->ops.disable_metric_set = gen8_disable_metric_set;
5161 perf->ops.oa_hw_tail_read = gen8_oa_hw_tail_read;
5162 } else if (GRAPHICS_VER(i915) == 11) {
5163 perf->ops.is_valid_b_counter_reg =
5164 gen7_is_valid_b_counter_addr;
5165 perf->ops.is_valid_mux_reg =
5166 gen11_is_valid_mux_addr;
5167 perf->ops.is_valid_flex_reg =
5168 gen8_is_valid_flex_addr;
5170 perf->ops.oa_enable = gen8_oa_enable;
5171 perf->ops.oa_disable = gen8_oa_disable;
5172 perf->ops.enable_metric_set = gen8_enable_metric_set;
5173 perf->ops.disable_metric_set = gen11_disable_metric_set;
5174 perf->ops.oa_hw_tail_read = gen8_oa_hw_tail_read;
5175 } else if (GRAPHICS_VER(i915) == 12) {
5176 perf->ops.is_valid_b_counter_reg =
5177 HAS_OA_SLICE_CONTRIB_LIMITS(i915) ?
5178 xehp_is_valid_b_counter_addr :
5179 gen12_is_valid_b_counter_addr;
5180 perf->ops.is_valid_mux_reg =
5181 gen12_is_valid_mux_addr;
5182 perf->ops.is_valid_flex_reg =
5183 gen8_is_valid_flex_addr;
5185 perf->ops.oa_enable = gen12_oa_enable;
5186 perf->ops.oa_disable = gen12_oa_disable;
5187 perf->ops.enable_metric_set = gen12_enable_metric_set;
5188 perf->ops.disable_metric_set = gen12_disable_metric_set;
5189 perf->ops.oa_hw_tail_read = gen12_oa_hw_tail_read;
5193 if (perf->ops.enable_metric_set) {
5194 struct intel_gt *gt;
5197 for_each_gt(gt, i915, i)
5198 mutex_init(>->perf.lock);
5200 /* Choose a representative limit */
5201 oa_sample_rate_hard_limit = to_gt(i915)->clock_frequency / 2;
5203 mutex_init(&perf->metrics_lock);
5204 idr_init_base(&perf->metrics_idr, 1);
5206 /* We set up some ratelimit state to potentially throttle any
5207 * _NOTES about spurious, invalid OA reports which we don't
5208 * forward to userspace.
5210 * We print a _NOTE about any throttling when closing the
5211 * stream instead of waiting until driver _fini which no one
5214 * Using the same limiting factors as printk_ratelimit()
5216 ratelimit_state_init(&perf->spurious_report_rs, 5 * HZ, 10);
5217 /* Since we use a DRM_NOTE for spurious reports it would be
5218 * inconsistent to let __ratelimit() automatically print a
5219 * warning for throttling.
5221 ratelimit_set_flags(&perf->spurious_report_rs,
5222 RATELIMIT_MSG_ON_RELEASE);
5224 ratelimit_state_init(&perf->tail_pointer_race,
5226 ratelimit_set_flags(&perf->tail_pointer_race,
5227 RATELIMIT_MSG_ON_RELEASE);
5229 atomic64_set(&perf->noa_programming_delay,
5230 500 * 1000 /* 500us */);
5234 ret = oa_init_engine_groups(perf);
5237 "OA initialization failed %d\n", ret);
5241 oa_init_supported_formats(perf);
5247 static int destroy_config(int id, void *p, void *data)
5249 i915_oa_config_put(p);
5253 int i915_perf_sysctl_register(void)
5255 sysctl_header = register_sysctl("dev/i915", oa_table);
5259 void i915_perf_sysctl_unregister(void)
5261 unregister_sysctl_table(sysctl_header);
5265 * i915_perf_fini - Counter part to i915_perf_init()
5266 * @i915: i915 device instance
5268 void i915_perf_fini(struct drm_i915_private *i915)
5270 struct i915_perf *perf = &i915->perf;
5271 struct intel_gt *gt;
5277 for_each_gt(gt, perf->i915, i)
5278 kfree(gt->perf.group);
5280 idr_for_each(&perf->metrics_idr, destroy_config, perf);
5281 idr_destroy(&perf->metrics_idr);
5283 memset(&perf->ops, 0, sizeof(perf->ops));
5288 * i915_perf_ioctl_version - Version of the i915-perf subsystem
5290 * This version number is used by userspace to detect available features.
5292 int i915_perf_ioctl_version(void)
5295 * 1: Initial version
5296 * I915_PERF_IOCTL_ENABLE
5297 * I915_PERF_IOCTL_DISABLE
5299 * 2: Added runtime modification of OA config.
5300 * I915_PERF_IOCTL_CONFIG
5302 * 3: Add DRM_I915_PERF_PROP_HOLD_PREEMPTION parameter to hold
5303 * preemption on a particular context so that performance data is
5304 * accessible from a delta of MI_RPC reports without looking at the
5307 * 4: Add DRM_I915_PERF_PROP_ALLOWED_SSEU to limit what contexts can
5308 * be run for the duration of the performance recording based on
5309 * their SSEU configuration.
5311 * 5: Add DRM_I915_PERF_PROP_POLL_OA_PERIOD parameter that controls the
5312 * interval for the hrtimer used to check for OA data.
5314 * 6: Add DRM_I915_PERF_PROP_OA_ENGINE_CLASS and
5315 * DRM_I915_PERF_PROP_OA_ENGINE_INSTANCE
5317 * 7: Add support for video decode and enhancement classes.
5322 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
5323 #include "selftests/i915_perf.c"