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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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24 * Robert Bragg <robert@sixbynine.org>
29 * DOC: i915 Perf Overview
31 * Gen graphics supports a large number of performance counters that can help
32 * driver and application developers understand and optimize their use of the
35 * This i915 perf interface enables userspace to configure and open a file
36 * descriptor representing a stream of GPU metrics which can then be read() as
37 * a stream of sample records.
39 * The interface is particularly suited to exposing buffered metrics that are
40 * captured by DMA from the GPU, unsynchronized with and unrelated to the CPU.
42 * Streams representing a single context are accessible to applications with a
43 * corresponding drm file descriptor, such that OpenGL can use the interface
44 * without special privileges. Access to system-wide metrics requires root
45 * privileges by default, unless changed via the dev.i915.perf_event_paranoid
51 * DOC: i915 Perf History and Comparison with Core Perf
53 * The interface was initially inspired by the core Perf infrastructure but
54 * some notable differences are:
56 * i915 perf file descriptors represent a "stream" instead of an "event"; where
57 * a perf event primarily corresponds to a single 64bit value, while a stream
58 * might sample sets of tightly-coupled counters, depending on the
59 * configuration. For example the Gen OA unit isn't designed to support
60 * orthogonal configurations of individual counters; it's configured for a set
61 * of related counters. Samples for an i915 perf stream capturing OA metrics
62 * will include a set of counter values packed in a compact HW specific format.
63 * The OA unit supports a number of different packing formats which can be
64 * selected by the user opening the stream. Perf has support for grouping
65 * events, but each event in the group is configured, validated and
66 * authenticated individually with separate system calls.
68 * i915 perf stream configurations are provided as an array of u64 (key,value)
69 * pairs, instead of a fixed struct with multiple miscellaneous config members,
70 * interleaved with event-type specific members.
72 * i915 perf doesn't support exposing metrics via an mmap'd circular buffer.
73 * The supported metrics are being written to memory by the GPU unsynchronized
74 * with the CPU, using HW specific packing formats for counter sets. Sometimes
75 * the constraints on HW configuration require reports to be filtered before it
76 * would be acceptable to expose them to unprivileged applications - to hide
77 * the metrics of other processes/contexts. For these use cases a read() based
78 * interface is a good fit, and provides an opportunity to filter data as it
79 * gets copied from the GPU mapped buffers to userspace buffers.
82 * Issues hit with first prototype based on Core Perf
83 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
85 * The first prototype of this driver was based on the core perf
86 * infrastructure, and while we did make that mostly work, with some changes to
87 * perf, we found we were breaking or working around too many assumptions baked
88 * into perf's currently cpu centric design.
90 * In the end we didn't see a clear benefit to making perf's implementation and
91 * interface more complex by changing design assumptions while we knew we still
92 * wouldn't be able to use any existing perf based userspace tools.
94 * Also considering the Gen specific nature of the Observability hardware and
95 * how userspace will sometimes need to combine i915 perf OA metrics with
96 * side-band OA data captured via MI_REPORT_PERF_COUNT commands; we're
97 * expecting the interface to be used by a platform specific userspace such as
98 * OpenGL or tools. This is to say; we aren't inherently missing out on having
99 * a standard vendor/architecture agnostic interface by not using perf.
102 * For posterity, in case we might re-visit trying to adapt core perf to be
103 * better suited to exposing i915 metrics these were the main pain points we
106 * - The perf based OA PMU driver broke some significant design assumptions:
108 * Existing perf pmus are used for profiling work on a cpu and we were
109 * introducing the idea of _IS_DEVICE pmus with different security
110 * implications, the need to fake cpu-related data (such as user/kernel
111 * registers) to fit with perf's current design, and adding _DEVICE records
112 * as a way to forward device-specific status records.
114 * The OA unit writes reports of counters into a circular buffer, without
115 * involvement from the CPU, making our PMU driver the first of a kind.
117 * Given the way we were periodically forward data from the GPU-mapped, OA
118 * buffer to perf's buffer, those bursts of sample writes looked to perf like
119 * we were sampling too fast and so we had to subvert its throttling checks.
121 * Perf supports groups of counters and allows those to be read via
122 * transactions internally but transactions currently seem designed to be
123 * explicitly initiated from the cpu (say in response to a userspace read())
124 * and while we could pull a report out of the OA buffer we can't
125 * trigger a report from the cpu on demand.
127 * Related to being report based; the OA counters are configured in HW as a
128 * set while perf generally expects counter configurations to be orthogonal.
129 * Although counters can be associated with a group leader as they are
130 * opened, there's no clear precedent for being able to provide group-wide
131 * configuration attributes (for example we want to let userspace choose the
132 * OA unit report format used to capture all counters in a set, or specify a
133 * GPU context to filter metrics on). We avoided using perf's grouping
134 * feature and forwarded OA reports to userspace via perf's 'raw' sample
135 * field. This suited our userspace well considering how coupled the counters
136 * are when dealing with normalizing. It would be inconvenient to split
137 * counters up into separate events, only to require userspace to recombine
138 * them. For Mesa it's also convenient to be forwarded raw, periodic reports
139 * for combining with the side-band raw reports it captures using
140 * MI_REPORT_PERF_COUNT commands.
142 * - As a side note on perf's grouping feature; there was also some concern
143 * that using PERF_FORMAT_GROUP as a way to pack together counter values
144 * would quite drastically inflate our sample sizes, which would likely
145 * lower the effective sampling resolutions we could use when the available
146 * memory bandwidth is limited.
148 * With the OA unit's report formats, counters are packed together as 32
149 * or 40bit values, with the largest report size being 256 bytes.
151 * PERF_FORMAT_GROUP values are 64bit, but there doesn't appear to be a
152 * documented ordering to the values, implying PERF_FORMAT_ID must also be
153 * used to add a 64bit ID before each value; giving 16 bytes per counter.
155 * Related to counter orthogonality; we can't time share the OA unit, while
156 * event scheduling is a central design idea within perf for allowing
157 * userspace to open + enable more events than can be configured in HW at any
158 * one time. The OA unit is not designed to allow re-configuration while in
159 * use. We can't reconfigure the OA unit without losing internal OA unit
160 * state which we can't access explicitly to save and restore. Reconfiguring
161 * the OA unit is also relatively slow, involving ~100 register writes. From
162 * userspace Mesa also depends on a stable OA configuration when emitting
163 * MI_REPORT_PERF_COUNT commands and importantly the OA unit can't be
164 * disabled while there are outstanding MI_RPC commands lest we hang the
167 * The contents of sample records aren't extensible by device drivers (i.e.
168 * the sample_type bits). As an example; Sourab Gupta had been looking to
169 * attach GPU timestamps to our OA samples. We were shoehorning OA reports
170 * into sample records by using the 'raw' field, but it's tricky to pack more
171 * than one thing into this field because events/core.c currently only lets a
172 * pmu give a single raw data pointer plus len which will be copied into the
173 * ring buffer. To include more than the OA report we'd have to copy the
174 * report into an intermediate larger buffer. I'd been considering allowing a
175 * vector of data+len values to be specified for copying the raw data, but
176 * it felt like a kludge to being using the raw field for this purpose.
178 * - It felt like our perf based PMU was making some technical compromises
179 * just for the sake of using perf:
181 * perf_event_open() requires events to either relate to a pid or a specific
182 * cpu core, while our device pmu related to neither. Events opened with a
183 * pid will be automatically enabled/disabled according to the scheduling of
184 * that process - so not appropriate for us. When an event is related to a
185 * cpu id, perf ensures pmu methods will be invoked via an inter process
186 * interrupt on that core. To avoid invasive changes our userspace opened OA
187 * perf events for a specific cpu. This was workable but it meant the
188 * majority of the OA driver ran in atomic context, including all OA report
189 * forwarding, which wasn't really necessary in our case and seems to make
190 * our locking requirements somewhat complex as we handled the interaction
191 * with the rest of the i915 driver.
194 #include <linux/anon_inodes.h>
195 #include <linux/sizes.h>
196 #include <linux/uuid.h>
198 #include "gem/i915_gem_context.h"
199 #include "gt/intel_engine_pm.h"
200 #include "gt/intel_engine_user.h"
201 #include "gt/intel_execlists_submission.h"
202 #include "gt/intel_gpu_commands.h"
203 #include "gt/intel_gt.h"
204 #include "gt/intel_gt_clock_utils.h"
205 #include "gt/intel_lrc.h"
206 #include "gt/intel_ring.h"
208 #include "i915_drv.h"
209 #include "i915_perf.h"
211 /* HW requires this to be a power of two, between 128k and 16M, though driver
212 * is currently generally designed assuming the largest 16M size is used such
213 * that the overflow cases are unlikely in normal operation.
215 #define OA_BUFFER_SIZE SZ_16M
217 #define OA_TAKEN(tail, head) ((tail - head) & (OA_BUFFER_SIZE - 1))
220 * DOC: OA Tail Pointer Race
222 * There's a HW race condition between OA unit tail pointer register updates and
223 * writes to memory whereby the tail pointer can sometimes get ahead of what's
224 * been written out to the OA buffer so far (in terms of what's visible to the
227 * Although this can be observed explicitly while copying reports to userspace
228 * by checking for a zeroed report-id field in tail reports, we want to account
229 * for this earlier, as part of the oa_buffer_check_unlocked to avoid lots of
230 * redundant read() attempts.
232 * We workaround this issue in oa_buffer_check_unlocked() by reading the reports
233 * in the OA buffer, starting from the tail reported by the HW until we find a
234 * report with its first 2 dwords not 0 meaning its previous report is
235 * completely in memory and ready to be read. Those dwords are also set to 0
236 * once read and the whole buffer is cleared upon OA buffer initialization. The
237 * first dword is the reason for this report while the second is the timestamp,
238 * making the chances of having those 2 fields at 0 fairly unlikely. A more
239 * detailed explanation is available in oa_buffer_check_unlocked().
241 * Most of the implementation details for this workaround are in
242 * oa_buffer_check_unlocked() and _append_oa_reports()
244 * Note for posterity: previously the driver used to define an effective tail
245 * pointer that lagged the real pointer by a 'tail margin' measured in bytes
246 * derived from %OA_TAIL_MARGIN_NSEC and the configured sampling frequency.
247 * This was flawed considering that the OA unit may also automatically generate
248 * non-periodic reports (such as on context switch) or the OA unit may be
249 * enabled without any periodic sampling.
251 #define OA_TAIL_MARGIN_NSEC 100000ULL
252 #define INVALID_TAIL_PTR 0xffffffff
254 /* The default frequency for checking whether the OA unit has written new
255 * reports to the circular OA buffer...
257 #define DEFAULT_POLL_FREQUENCY_HZ 200
258 #define DEFAULT_POLL_PERIOD_NS (NSEC_PER_SEC / DEFAULT_POLL_FREQUENCY_HZ)
260 /* for sysctl proc_dointvec_minmax of dev.i915.perf_stream_paranoid */
261 static u32 i915_perf_stream_paranoid = true;
263 /* The maximum exponent the hardware accepts is 63 (essentially it selects one
264 * of the 64bit timestamp bits to trigger reports from) but there's currently
265 * no known use case for sampling as infrequently as once per 47 thousand years.
267 * Since the timestamps included in OA reports are only 32bits it seems
268 * reasonable to limit the OA exponent where it's still possible to account for
269 * overflow in OA report timestamps.
271 #define OA_EXPONENT_MAX 31
273 #define INVALID_CTX_ID 0xffffffff
275 /* On Gen8+ automatically triggered OA reports include a 'reason' field... */
276 #define OAREPORT_REASON_MASK 0x3f
277 #define OAREPORT_REASON_MASK_EXTENDED 0x7f
278 #define OAREPORT_REASON_SHIFT 19
279 #define OAREPORT_REASON_TIMER (1<<0)
280 #define OAREPORT_REASON_CTX_SWITCH (1<<3)
281 #define OAREPORT_REASON_CLK_RATIO (1<<5)
284 /* For sysctl proc_dointvec_minmax of i915_oa_max_sample_rate
286 * The highest sampling frequency we can theoretically program the OA unit
287 * with is always half the timestamp frequency: E.g. 6.25Mhz for Haswell.
289 * Initialized just before we register the sysctl parameter.
291 static int oa_sample_rate_hard_limit;
293 /* Theoretically we can program the OA unit to sample every 160ns but don't
294 * allow that by default unless root...
296 * The default threshold of 100000Hz is based on perf's similar
297 * kernel.perf_event_max_sample_rate sysctl parameter.
299 static u32 i915_oa_max_sample_rate = 100000;
301 /* XXX: beware if future OA HW adds new report formats that the current
302 * code assumes all reports have a power-of-two size and ~(size - 1) can
303 * be used as a mask to align the OA tail pointer.
305 static const struct i915_oa_format oa_formats[I915_OA_FORMAT_MAX] = {
306 [I915_OA_FORMAT_A13] = { 0, 64 },
307 [I915_OA_FORMAT_A29] = { 1, 128 },
308 [I915_OA_FORMAT_A13_B8_C8] = { 2, 128 },
309 /* A29_B8_C8 Disallowed as 192 bytes doesn't factor into buffer size */
310 [I915_OA_FORMAT_B4_C8] = { 4, 64 },
311 [I915_OA_FORMAT_A45_B8_C8] = { 5, 256 },
312 [I915_OA_FORMAT_B4_C8_A16] = { 6, 128 },
313 [I915_OA_FORMAT_C4_B8] = { 7, 64 },
314 [I915_OA_FORMAT_A12] = { 0, 64 },
315 [I915_OA_FORMAT_A12_B8_C8] = { 2, 128 },
316 [I915_OA_FORMAT_A32u40_A4u32_B8_C8] = { 5, 256 },
319 #define SAMPLE_OA_REPORT (1<<0)
322 * struct perf_open_properties - for validated properties given to open a stream
323 * @sample_flags: `DRM_I915_PERF_PROP_SAMPLE_*` properties are tracked as flags
324 * @single_context: Whether a single or all gpu contexts should be monitored
325 * @hold_preemption: Whether the preemption is disabled for the filtered
327 * @ctx_handle: A gem ctx handle for use with @single_context
328 * @metrics_set: An ID for an OA unit metric set advertised via sysfs
329 * @oa_format: An OA unit HW report format
330 * @oa_periodic: Whether to enable periodic OA unit sampling
331 * @oa_period_exponent: The OA unit sampling period is derived from this
332 * @engine: The engine (typically rcs0) being monitored by the OA unit
333 * @has_sseu: Whether @sseu was specified by userspace
334 * @sseu: internal SSEU configuration computed either from the userspace
335 * specified configuration in the opening parameters or a default value
336 * (see get_default_sseu_config())
337 * @poll_oa_period: The period in nanoseconds at which the CPU will check for OA
340 * As read_properties_unlocked() enumerates and validates the properties given
341 * to open a stream of metrics the configuration is built up in the structure
342 * which starts out zero initialized.
344 struct perf_open_properties {
347 u64 single_context:1;
348 u64 hold_preemption:1;
351 /* OA sampling state */
355 int oa_period_exponent;
357 struct intel_engine_cs *engine;
360 struct intel_sseu sseu;
365 struct i915_oa_config_bo {
366 struct llist_node node;
368 struct i915_oa_config *oa_config;
369 struct i915_vma *vma;
372 static struct ctl_table_header *sysctl_header;
374 static enum hrtimer_restart oa_poll_check_timer_cb(struct hrtimer *hrtimer);
376 void i915_oa_config_release(struct kref *ref)
378 struct i915_oa_config *oa_config =
379 container_of(ref, typeof(*oa_config), ref);
381 kfree(oa_config->flex_regs);
382 kfree(oa_config->b_counter_regs);
383 kfree(oa_config->mux_regs);
385 kfree_rcu(oa_config, rcu);
388 struct i915_oa_config *
389 i915_perf_get_oa_config(struct i915_perf *perf, int metrics_set)
391 struct i915_oa_config *oa_config;
394 oa_config = idr_find(&perf->metrics_idr, metrics_set);
396 oa_config = i915_oa_config_get(oa_config);
402 static void free_oa_config_bo(struct i915_oa_config_bo *oa_bo)
404 i915_oa_config_put(oa_bo->oa_config);
405 i915_vma_put(oa_bo->vma);
409 static u32 gen12_oa_hw_tail_read(struct i915_perf_stream *stream)
411 struct intel_uncore *uncore = stream->uncore;
413 return intel_uncore_read(uncore, GEN12_OAG_OATAILPTR) &
414 GEN12_OAG_OATAILPTR_MASK;
417 static u32 gen8_oa_hw_tail_read(struct i915_perf_stream *stream)
419 struct intel_uncore *uncore = stream->uncore;
421 return intel_uncore_read(uncore, GEN8_OATAILPTR) & GEN8_OATAILPTR_MASK;
424 static u32 gen7_oa_hw_tail_read(struct i915_perf_stream *stream)
426 struct intel_uncore *uncore = stream->uncore;
427 u32 oastatus1 = intel_uncore_read(uncore, GEN7_OASTATUS1);
429 return oastatus1 & GEN7_OASTATUS1_TAIL_MASK;
433 * oa_buffer_check_unlocked - check for data and update tail ptr state
434 * @stream: i915 stream instance
436 * This is either called via fops (for blocking reads in user ctx) or the poll
437 * check hrtimer (atomic ctx) to check the OA buffer tail pointer and check
438 * if there is data available for userspace to read.
440 * This function is central to providing a workaround for the OA unit tail
441 * pointer having a race with respect to what data is visible to the CPU.
442 * It is responsible for reading tail pointers from the hardware and giving
443 * the pointers time to 'age' before they are made available for reading.
444 * (See description of OA_TAIL_MARGIN_NSEC above for further details.)
446 * Besides returning true when there is data available to read() this function
447 * also updates the tail, aging_tail and aging_timestamp in the oa_buffer
450 * Note: It's safe to read OA config state here unlocked, assuming that this is
451 * only called while the stream is enabled, while the global OA configuration
454 * Returns: %true if the OA buffer contains data, else %false
456 static bool oa_buffer_check_unlocked(struct i915_perf_stream *stream)
458 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
459 int report_size = stream->oa_buffer.format_size;
465 /* We have to consider the (unlikely) possibility that read() errors
466 * could result in an OA buffer reset which might reset the head and
469 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
471 hw_tail = stream->perf->ops.oa_hw_tail_read(stream);
473 /* The tail pointer increases in 64 byte increments,
474 * not in report_size steps...
476 hw_tail &= ~(report_size - 1);
478 now = ktime_get_mono_fast_ns();
480 if (hw_tail == stream->oa_buffer.aging_tail &&
481 (now - stream->oa_buffer.aging_timestamp) > OA_TAIL_MARGIN_NSEC) {
482 /* If the HW tail hasn't move since the last check and the HW
483 * tail has been aging for long enough, declare it the new
486 stream->oa_buffer.tail = stream->oa_buffer.aging_tail;
488 u32 head, tail, aged_tail;
490 /* NB: The head we observe here might effectively be a little
491 * out of date. If a read() is in progress, the head could be
492 * anywhere between this head and stream->oa_buffer.tail.
494 head = stream->oa_buffer.head - gtt_offset;
495 aged_tail = stream->oa_buffer.tail - gtt_offset;
497 hw_tail -= gtt_offset;
500 /* Walk the stream backward until we find a report with dword 0
501 * & 1 not at 0. Since the circular buffer pointers progress by
502 * increments of 64 bytes and that reports can be up to 256
503 * bytes long, we can't tell whether a report has fully landed
504 * in memory before the first 2 dwords of the following report
505 * have effectively landed.
507 * This is assuming that the writes of the OA unit land in
508 * memory in the order they were written to.
509 * If not : (╯°□°)╯︵ ┻━┻
511 while (OA_TAKEN(tail, aged_tail) >= report_size) {
512 u32 *report32 = (void *)(stream->oa_buffer.vaddr + tail);
514 if (report32[0] != 0 || report32[1] != 0)
517 tail = (tail - report_size) & (OA_BUFFER_SIZE - 1);
520 if (OA_TAKEN(hw_tail, tail) > report_size &&
521 __ratelimit(&stream->perf->tail_pointer_race))
522 DRM_NOTE("unlanded report(s) head=0x%x "
523 "tail=0x%x hw_tail=0x%x\n",
524 head, tail, hw_tail);
526 stream->oa_buffer.tail = gtt_offset + tail;
527 stream->oa_buffer.aging_tail = gtt_offset + hw_tail;
528 stream->oa_buffer.aging_timestamp = now;
531 pollin = OA_TAKEN(stream->oa_buffer.tail - gtt_offset,
532 stream->oa_buffer.head - gtt_offset) >= report_size;
534 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
540 * append_oa_status - Appends a status record to a userspace read() buffer.
541 * @stream: An i915-perf stream opened for OA metrics
542 * @buf: destination buffer given by userspace
543 * @count: the number of bytes userspace wants to read
544 * @offset: (inout): the current position for writing into @buf
545 * @type: The kind of status to report to userspace
547 * Writes a status record (such as `DRM_I915_PERF_RECORD_OA_REPORT_LOST`)
548 * into the userspace read() buffer.
550 * The @buf @offset will only be updated on success.
552 * Returns: 0 on success, negative error code on failure.
554 static int append_oa_status(struct i915_perf_stream *stream,
558 enum drm_i915_perf_record_type type)
560 struct drm_i915_perf_record_header header = { type, 0, sizeof(header) };
562 if ((count - *offset) < header.size)
565 if (copy_to_user(buf + *offset, &header, sizeof(header)))
568 (*offset) += header.size;
574 * append_oa_sample - Copies single OA report into userspace read() buffer.
575 * @stream: An i915-perf stream opened for OA metrics
576 * @buf: destination buffer given by userspace
577 * @count: the number of bytes userspace wants to read
578 * @offset: (inout): the current position for writing into @buf
579 * @report: A single OA report to (optionally) include as part of the sample
581 * The contents of a sample are configured through `DRM_I915_PERF_PROP_SAMPLE_*`
582 * properties when opening a stream, tracked as `stream->sample_flags`. This
583 * function copies the requested components of a single sample to the given
586 * The @buf @offset will only be updated on success.
588 * Returns: 0 on success, negative error code on failure.
590 static int append_oa_sample(struct i915_perf_stream *stream,
596 int report_size = stream->oa_buffer.format_size;
597 struct drm_i915_perf_record_header header;
599 header.type = DRM_I915_PERF_RECORD_SAMPLE;
601 header.size = stream->sample_size;
603 if ((count - *offset) < header.size)
607 if (copy_to_user(buf, &header, sizeof(header)))
609 buf += sizeof(header);
611 if (copy_to_user(buf, report, report_size))
614 (*offset) += header.size;
620 * gen8_append_oa_reports - Copies all buffered OA reports into
621 * userspace read() buffer.
622 * @stream: An i915-perf stream opened for OA metrics
623 * @buf: destination buffer given by userspace
624 * @count: the number of bytes userspace wants to read
625 * @offset: (inout): the current position for writing into @buf
627 * Notably any error condition resulting in a short read (-%ENOSPC or
628 * -%EFAULT) will be returned even though one or more records may
629 * have been successfully copied. In this case it's up to the caller
630 * to decide if the error should be squashed before returning to
633 * Note: reports are consumed from the head, and appended to the
634 * tail, so the tail chases the head?... If you think that's mad
635 * and back-to-front you're not alone, but this follows the
636 * Gen PRM naming convention.
638 * Returns: 0 on success, negative error code on failure.
640 static int gen8_append_oa_reports(struct i915_perf_stream *stream,
645 struct intel_uncore *uncore = stream->uncore;
646 int report_size = stream->oa_buffer.format_size;
647 u8 *oa_buf_base = stream->oa_buffer.vaddr;
648 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
649 u32 mask = (OA_BUFFER_SIZE - 1);
650 size_t start_offset = *offset;
656 if (drm_WARN_ON(&uncore->i915->drm, !stream->enabled))
659 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
661 head = stream->oa_buffer.head;
662 tail = stream->oa_buffer.tail;
664 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
667 * NB: oa_buffer.head/tail include the gtt_offset which we don't want
668 * while indexing relative to oa_buf_base.
674 * An out of bounds or misaligned head or tail pointer implies a driver
675 * bug since we validate + align the tail pointers we read from the
676 * hardware and we are in full control of the head pointer which should
677 * only be incremented by multiples of the report size (notably also
678 * all a power of two).
680 if (drm_WARN_ONCE(&uncore->i915->drm,
681 head > OA_BUFFER_SIZE || head % report_size ||
682 tail > OA_BUFFER_SIZE || tail % report_size,
683 "Inconsistent OA buffer pointers: head = %u, tail = %u\n",
689 (taken = OA_TAKEN(tail, head));
690 head = (head + report_size) & mask) {
691 u8 *report = oa_buf_base + head;
692 u32 *report32 = (void *)report;
697 * All the report sizes factor neatly into the buffer
698 * size so we never expect to see a report split
699 * between the beginning and end of the buffer.
701 * Given the initial alignment check a misalignment
702 * here would imply a driver bug that would result
705 if (drm_WARN_ON(&uncore->i915->drm,
706 (OA_BUFFER_SIZE - head) < report_size)) {
707 drm_err(&uncore->i915->drm,
708 "Spurious OA head ptr: non-integral report offset\n");
713 * The reason field includes flags identifying what
714 * triggered this specific report (mostly timer
715 * triggered or e.g. due to a context switch).
717 * This field is never expected to be zero so we can
718 * check that the report isn't invalid before copying
721 reason = ((report32[0] >> OAREPORT_REASON_SHIFT) &
722 (GRAPHICS_VER(stream->perf->i915) == 12 ?
723 OAREPORT_REASON_MASK_EXTENDED :
724 OAREPORT_REASON_MASK));
726 ctx_id = report32[2] & stream->specific_ctx_id_mask;
729 * Squash whatever is in the CTX_ID field if it's marked as
730 * invalid to be sure we avoid false-positive, single-context
733 * Note: that we don't clear the valid_ctx_bit so userspace can
734 * understand that the ID has been squashed by the kernel.
736 if (!(report32[0] & stream->perf->gen8_valid_ctx_bit) &&
737 GRAPHICS_VER(stream->perf->i915) <= 11)
738 ctx_id = report32[2] = INVALID_CTX_ID;
741 * NB: For Gen 8 the OA unit no longer supports clock gating
742 * off for a specific context and the kernel can't securely
743 * stop the counters from updating as system-wide / global
746 * Automatic reports now include a context ID so reports can be
747 * filtered on the cpu but it's not worth trying to
748 * automatically subtract/hide counter progress for other
749 * contexts while filtering since we can't stop userspace
750 * issuing MI_REPORT_PERF_COUNT commands which would still
751 * provide a side-band view of the real values.
753 * To allow userspace (such as Mesa/GL_INTEL_performance_query)
754 * to normalize counters for a single filtered context then it
755 * needs be forwarded bookend context-switch reports so that it
756 * can track switches in between MI_REPORT_PERF_COUNT commands
757 * and can itself subtract/ignore the progress of counters
758 * associated with other contexts. Note that the hardware
759 * automatically triggers reports when switching to a new
760 * context which are tagged with the ID of the newly active
761 * context. To avoid the complexity (and likely fragility) of
762 * reading ahead while parsing reports to try and minimize
763 * forwarding redundant context switch reports (i.e. between
764 * other, unrelated contexts) we simply elect to forward them
767 * We don't rely solely on the reason field to identify context
768 * switches since it's not-uncommon for periodic samples to
769 * identify a switch before any 'context switch' report.
771 if (!stream->perf->exclusive_stream->ctx ||
772 stream->specific_ctx_id == ctx_id ||
773 stream->oa_buffer.last_ctx_id == stream->specific_ctx_id ||
774 reason & OAREPORT_REASON_CTX_SWITCH) {
777 * While filtering for a single context we avoid
778 * leaking the IDs of other contexts.
780 if (stream->perf->exclusive_stream->ctx &&
781 stream->specific_ctx_id != ctx_id) {
782 report32[2] = INVALID_CTX_ID;
785 ret = append_oa_sample(stream, buf, count, offset,
790 stream->oa_buffer.last_ctx_id = ctx_id;
794 * Clear out the first 2 dword as a mean to detect unlanded
801 if (start_offset != *offset) {
802 i915_reg_t oaheadptr;
804 oaheadptr = GRAPHICS_VER(stream->perf->i915) == 12 ?
805 GEN12_OAG_OAHEADPTR : GEN8_OAHEADPTR;
807 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
810 * We removed the gtt_offset for the copy loop above, indexing
811 * relative to oa_buf_base so put back here...
814 intel_uncore_write(uncore, oaheadptr,
815 head & GEN12_OAG_OAHEADPTR_MASK);
816 stream->oa_buffer.head = head;
818 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
825 * gen8_oa_read - copy status records then buffered OA reports
826 * @stream: An i915-perf stream opened for OA metrics
827 * @buf: destination buffer given by userspace
828 * @count: the number of bytes userspace wants to read
829 * @offset: (inout): the current position for writing into @buf
831 * Checks OA unit status registers and if necessary appends corresponding
832 * status records for userspace (such as for a buffer full condition) and then
833 * initiate appending any buffered OA reports.
835 * Updates @offset according to the number of bytes successfully copied into
836 * the userspace buffer.
838 * NB: some data may be successfully copied to the userspace buffer
839 * even if an error is returned, and this is reflected in the
842 * Returns: zero on success or a negative error code
844 static int gen8_oa_read(struct i915_perf_stream *stream,
849 struct intel_uncore *uncore = stream->uncore;
851 i915_reg_t oastatus_reg;
854 if (drm_WARN_ON(&uncore->i915->drm, !stream->oa_buffer.vaddr))
857 oastatus_reg = GRAPHICS_VER(stream->perf->i915) == 12 ?
858 GEN12_OAG_OASTATUS : GEN8_OASTATUS;
860 oastatus = intel_uncore_read(uncore, oastatus_reg);
863 * We treat OABUFFER_OVERFLOW as a significant error:
865 * Although theoretically we could handle this more gracefully
866 * sometimes, some Gens don't correctly suppress certain
867 * automatically triggered reports in this condition and so we
868 * have to assume that old reports are now being trampled
871 * Considering how we don't currently give userspace control
872 * over the OA buffer size and always configure a large 16MB
873 * buffer, then a buffer overflow does anyway likely indicate
874 * that something has gone quite badly wrong.
876 if (oastatus & GEN8_OASTATUS_OABUFFER_OVERFLOW) {
877 ret = append_oa_status(stream, buf, count, offset,
878 DRM_I915_PERF_RECORD_OA_BUFFER_LOST);
882 DRM_DEBUG("OA buffer overflow (exponent = %d): force restart\n",
883 stream->period_exponent);
885 stream->perf->ops.oa_disable(stream);
886 stream->perf->ops.oa_enable(stream);
889 * Note: .oa_enable() is expected to re-init the oabuffer and
890 * reset GEN8_OASTATUS for us
892 oastatus = intel_uncore_read(uncore, oastatus_reg);
895 if (oastatus & GEN8_OASTATUS_REPORT_LOST) {
896 ret = append_oa_status(stream, buf, count, offset,
897 DRM_I915_PERF_RECORD_OA_REPORT_LOST);
901 intel_uncore_rmw(uncore, oastatus_reg,
902 GEN8_OASTATUS_COUNTER_OVERFLOW |
903 GEN8_OASTATUS_REPORT_LOST,
904 IS_GRAPHICS_VER(uncore->i915, 8, 11) ?
905 (GEN8_OASTATUS_HEAD_POINTER_WRAP |
906 GEN8_OASTATUS_TAIL_POINTER_WRAP) : 0);
909 return gen8_append_oa_reports(stream, buf, count, offset);
913 * gen7_append_oa_reports - Copies all buffered OA reports into
914 * userspace read() buffer.
915 * @stream: An i915-perf stream opened for OA metrics
916 * @buf: destination buffer given by userspace
917 * @count: the number of bytes userspace wants to read
918 * @offset: (inout): the current position for writing into @buf
920 * Notably any error condition resulting in a short read (-%ENOSPC or
921 * -%EFAULT) will be returned even though one or more records may
922 * have been successfully copied. In this case it's up to the caller
923 * to decide if the error should be squashed before returning to
926 * Note: reports are consumed from the head, and appended to the
927 * tail, so the tail chases the head?... If you think that's mad
928 * and back-to-front you're not alone, but this follows the
929 * Gen PRM naming convention.
931 * Returns: 0 on success, negative error code on failure.
933 static int gen7_append_oa_reports(struct i915_perf_stream *stream,
938 struct intel_uncore *uncore = stream->uncore;
939 int report_size = stream->oa_buffer.format_size;
940 u8 *oa_buf_base = stream->oa_buffer.vaddr;
941 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
942 u32 mask = (OA_BUFFER_SIZE - 1);
943 size_t start_offset = *offset;
949 if (drm_WARN_ON(&uncore->i915->drm, !stream->enabled))
952 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
954 head = stream->oa_buffer.head;
955 tail = stream->oa_buffer.tail;
957 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
959 /* NB: oa_buffer.head/tail include the gtt_offset which we don't want
960 * while indexing relative to oa_buf_base.
965 /* An out of bounds or misaligned head or tail pointer implies a driver
966 * bug since we validate + align the tail pointers we read from the
967 * hardware and we are in full control of the head pointer which should
968 * only be incremented by multiples of the report size (notably also
969 * all a power of two).
971 if (drm_WARN_ONCE(&uncore->i915->drm,
972 head > OA_BUFFER_SIZE || head % report_size ||
973 tail > OA_BUFFER_SIZE || tail % report_size,
974 "Inconsistent OA buffer pointers: head = %u, tail = %u\n",
980 (taken = OA_TAKEN(tail, head));
981 head = (head + report_size) & mask) {
982 u8 *report = oa_buf_base + head;
983 u32 *report32 = (void *)report;
985 /* All the report sizes factor neatly into the buffer
986 * size so we never expect to see a report split
987 * between the beginning and end of the buffer.
989 * Given the initial alignment check a misalignment
990 * here would imply a driver bug that would result
993 if (drm_WARN_ON(&uncore->i915->drm,
994 (OA_BUFFER_SIZE - head) < report_size)) {
995 drm_err(&uncore->i915->drm,
996 "Spurious OA head ptr: non-integral report offset\n");
1000 /* The report-ID field for periodic samples includes
1001 * some undocumented flags related to what triggered
1002 * the report and is never expected to be zero so we
1003 * can check that the report isn't invalid before
1004 * copying it to userspace...
1006 if (report32[0] == 0) {
1007 if (__ratelimit(&stream->perf->spurious_report_rs))
1008 DRM_NOTE("Skipping spurious, invalid OA report\n");
1012 ret = append_oa_sample(stream, buf, count, offset, report);
1016 /* Clear out the first 2 dwords as a mean to detect unlanded
1023 if (start_offset != *offset) {
1024 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
1026 /* We removed the gtt_offset for the copy loop above, indexing
1027 * relative to oa_buf_base so put back here...
1031 intel_uncore_write(uncore, GEN7_OASTATUS2,
1032 (head & GEN7_OASTATUS2_HEAD_MASK) |
1033 GEN7_OASTATUS2_MEM_SELECT_GGTT);
1034 stream->oa_buffer.head = head;
1036 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
1043 * gen7_oa_read - copy status records then buffered OA reports
1044 * @stream: An i915-perf stream opened for OA metrics
1045 * @buf: destination buffer given by userspace
1046 * @count: the number of bytes userspace wants to read
1047 * @offset: (inout): the current position for writing into @buf
1049 * Checks Gen 7 specific OA unit status registers and if necessary appends
1050 * corresponding status records for userspace (such as for a buffer full
1051 * condition) and then initiate appending any buffered OA reports.
1053 * Updates @offset according to the number of bytes successfully copied into
1054 * the userspace buffer.
1056 * Returns: zero on success or a negative error code
1058 static int gen7_oa_read(struct i915_perf_stream *stream,
1063 struct intel_uncore *uncore = stream->uncore;
1067 if (drm_WARN_ON(&uncore->i915->drm, !stream->oa_buffer.vaddr))
1070 oastatus1 = intel_uncore_read(uncore, GEN7_OASTATUS1);
1072 /* XXX: On Haswell we don't have a safe way to clear oastatus1
1073 * bits while the OA unit is enabled (while the tail pointer
1074 * may be updated asynchronously) so we ignore status bits
1075 * that have already been reported to userspace.
1077 oastatus1 &= ~stream->perf->gen7_latched_oastatus1;
1079 /* We treat OABUFFER_OVERFLOW as a significant error:
1081 * - The status can be interpreted to mean that the buffer is
1082 * currently full (with a higher precedence than OA_TAKEN()
1083 * which will start to report a near-empty buffer after an
1084 * overflow) but it's awkward that we can't clear the status
1085 * on Haswell, so without a reset we won't be able to catch
1088 * - Since it also implies the HW has started overwriting old
1089 * reports it may also affect our sanity checks for invalid
1090 * reports when copying to userspace that assume new reports
1091 * are being written to cleared memory.
1093 * - In the future we may want to introduce a flight recorder
1094 * mode where the driver will automatically maintain a safe
1095 * guard band between head/tail, avoiding this overflow
1096 * condition, but we avoid the added driver complexity for
1099 if (unlikely(oastatus1 & GEN7_OASTATUS1_OABUFFER_OVERFLOW)) {
1100 ret = append_oa_status(stream, buf, count, offset,
1101 DRM_I915_PERF_RECORD_OA_BUFFER_LOST);
1105 DRM_DEBUG("OA buffer overflow (exponent = %d): force restart\n",
1106 stream->period_exponent);
1108 stream->perf->ops.oa_disable(stream);
1109 stream->perf->ops.oa_enable(stream);
1111 oastatus1 = intel_uncore_read(uncore, GEN7_OASTATUS1);
1114 if (unlikely(oastatus1 & GEN7_OASTATUS1_REPORT_LOST)) {
1115 ret = append_oa_status(stream, buf, count, offset,
1116 DRM_I915_PERF_RECORD_OA_REPORT_LOST);
1119 stream->perf->gen7_latched_oastatus1 |=
1120 GEN7_OASTATUS1_REPORT_LOST;
1123 return gen7_append_oa_reports(stream, buf, count, offset);
1127 * i915_oa_wait_unlocked - handles blocking IO until OA data available
1128 * @stream: An i915-perf stream opened for OA metrics
1130 * Called when userspace tries to read() from a blocking stream FD opened
1131 * for OA metrics. It waits until the hrtimer callback finds a non-empty
1132 * OA buffer and wakes us.
1134 * Note: it's acceptable to have this return with some false positives
1135 * since any subsequent read handling will return -EAGAIN if there isn't
1136 * really data ready for userspace yet.
1138 * Returns: zero on success or a negative error code
1140 static int i915_oa_wait_unlocked(struct i915_perf_stream *stream)
1142 /* We would wait indefinitely if periodic sampling is not enabled */
1143 if (!stream->periodic)
1146 return wait_event_interruptible(stream->poll_wq,
1147 oa_buffer_check_unlocked(stream));
1151 * i915_oa_poll_wait - call poll_wait() for an OA stream poll()
1152 * @stream: An i915-perf stream opened for OA metrics
1153 * @file: An i915 perf stream file
1154 * @wait: poll() state table
1156 * For handling userspace polling on an i915 perf stream opened for OA metrics,
1157 * this starts a poll_wait with the wait queue that our hrtimer callback wakes
1158 * when it sees data ready to read in the circular OA buffer.
1160 static void i915_oa_poll_wait(struct i915_perf_stream *stream,
1164 poll_wait(file, &stream->poll_wq, wait);
1168 * i915_oa_read - just calls through to &i915_oa_ops->read
1169 * @stream: An i915-perf stream opened for OA metrics
1170 * @buf: destination buffer given by userspace
1171 * @count: the number of bytes userspace wants to read
1172 * @offset: (inout): the current position for writing into @buf
1174 * Updates @offset according to the number of bytes successfully copied into
1175 * the userspace buffer.
1177 * Returns: zero on success or a negative error code
1179 static int i915_oa_read(struct i915_perf_stream *stream,
1184 return stream->perf->ops.read(stream, buf, count, offset);
1187 static struct intel_context *oa_pin_context(struct i915_perf_stream *stream)
1189 struct i915_gem_engines_iter it;
1190 struct i915_gem_context *ctx = stream->ctx;
1191 struct intel_context *ce;
1192 struct i915_gem_ww_ctx ww;
1195 for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
1196 if (ce->engine != stream->engine) /* first match! */
1202 i915_gem_context_unlock_engines(ctx);
1205 return ERR_PTR(err);
1207 i915_gem_ww_ctx_init(&ww, true);
1210 * As the ID is the gtt offset of the context's vma we
1211 * pin the vma to ensure the ID remains fixed.
1213 err = intel_context_pin_ww(ce, &ww);
1214 if (err == -EDEADLK) {
1215 err = i915_gem_ww_ctx_backoff(&ww);
1219 i915_gem_ww_ctx_fini(&ww);
1222 return ERR_PTR(err);
1224 stream->pinned_ctx = ce;
1225 return stream->pinned_ctx;
1229 * oa_get_render_ctx_id - determine and hold ctx hw id
1230 * @stream: An i915-perf stream opened for OA metrics
1232 * Determine the render context hw id, and ensure it remains fixed for the
1233 * lifetime of the stream. This ensures that we don't have to worry about
1234 * updating the context ID in OACONTROL on the fly.
1236 * Returns: zero on success or a negative error code
1238 static int oa_get_render_ctx_id(struct i915_perf_stream *stream)
1240 struct intel_context *ce;
1242 ce = oa_pin_context(stream);
1246 switch (GRAPHICS_VER(ce->engine->i915)) {
1249 * On Haswell we don't do any post processing of the reports
1250 * and don't need to use the mask.
1252 stream->specific_ctx_id = i915_ggtt_offset(ce->state);
1253 stream->specific_ctx_id_mask = 0;
1259 if (intel_engine_uses_guc(ce->engine)) {
1261 * When using GuC, the context descriptor we write in
1262 * i915 is read by GuC and rewritten before it's
1263 * actually written into the hardware. The LRCA is
1264 * what is put into the context id field of the
1265 * context descriptor by GuC. Because it's aligned to
1266 * a page, the lower 12bits are always at 0 and
1267 * dropped by GuC. They won't be part of the context
1268 * ID in the OA reports, so squash those lower bits.
1270 stream->specific_ctx_id = ce->lrc.lrca >> 12;
1273 * GuC uses the top bit to signal proxy submission, so
1276 stream->specific_ctx_id_mask =
1277 (1U << (GEN8_CTX_ID_WIDTH - 1)) - 1;
1279 stream->specific_ctx_id_mask =
1280 (1U << GEN8_CTX_ID_WIDTH) - 1;
1281 stream->specific_ctx_id = stream->specific_ctx_id_mask;
1287 stream->specific_ctx_id_mask =
1288 ((1U << GEN11_SW_CTX_ID_WIDTH) - 1) << (GEN11_SW_CTX_ID_SHIFT - 32);
1290 * Pick an unused context id
1291 * 0 - BITS_PER_LONG are used by other contexts
1292 * GEN12_MAX_CONTEXT_HW_ID (0x7ff) is used by idle context
1294 stream->specific_ctx_id = (GEN12_MAX_CONTEXT_HW_ID - 1) << (GEN11_SW_CTX_ID_SHIFT - 32);
1299 MISSING_CASE(GRAPHICS_VER(ce->engine->i915));
1302 ce->tag = stream->specific_ctx_id;
1304 drm_dbg(&stream->perf->i915->drm,
1305 "filtering on ctx_id=0x%x ctx_id_mask=0x%x\n",
1306 stream->specific_ctx_id,
1307 stream->specific_ctx_id_mask);
1313 * oa_put_render_ctx_id - counterpart to oa_get_render_ctx_id releases hold
1314 * @stream: An i915-perf stream opened for OA metrics
1316 * In case anything needed doing to ensure the context HW ID would remain valid
1317 * for the lifetime of the stream, then that can be undone here.
1319 static void oa_put_render_ctx_id(struct i915_perf_stream *stream)
1321 struct intel_context *ce;
1323 ce = fetch_and_zero(&stream->pinned_ctx);
1325 ce->tag = 0; /* recomputed on next submission after parking */
1326 intel_context_unpin(ce);
1329 stream->specific_ctx_id = INVALID_CTX_ID;
1330 stream->specific_ctx_id_mask = 0;
1334 free_oa_buffer(struct i915_perf_stream *stream)
1336 i915_vma_unpin_and_release(&stream->oa_buffer.vma,
1337 I915_VMA_RELEASE_MAP);
1339 stream->oa_buffer.vaddr = NULL;
1343 free_oa_configs(struct i915_perf_stream *stream)
1345 struct i915_oa_config_bo *oa_bo, *tmp;
1347 i915_oa_config_put(stream->oa_config);
1348 llist_for_each_entry_safe(oa_bo, tmp, stream->oa_config_bos.first, node)
1349 free_oa_config_bo(oa_bo);
1353 free_noa_wait(struct i915_perf_stream *stream)
1355 i915_vma_unpin_and_release(&stream->noa_wait, 0);
1358 static void i915_oa_stream_destroy(struct i915_perf_stream *stream)
1360 struct i915_perf *perf = stream->perf;
1362 BUG_ON(stream != perf->exclusive_stream);
1365 * Unset exclusive_stream first, it will be checked while disabling
1366 * the metric set on gen8+.
1368 * See i915_oa_init_reg_state() and lrc_configure_all_contexts()
1370 WRITE_ONCE(perf->exclusive_stream, NULL);
1371 perf->ops.disable_metric_set(stream);
1373 free_oa_buffer(stream);
1375 intel_uncore_forcewake_put(stream->uncore, FORCEWAKE_ALL);
1376 intel_engine_pm_put(stream->engine);
1379 oa_put_render_ctx_id(stream);
1381 free_oa_configs(stream);
1382 free_noa_wait(stream);
1384 if (perf->spurious_report_rs.missed) {
1385 DRM_NOTE("%d spurious OA report notices suppressed due to ratelimiting\n",
1386 perf->spurious_report_rs.missed);
1390 static void gen7_init_oa_buffer(struct i915_perf_stream *stream)
1392 struct intel_uncore *uncore = stream->uncore;
1393 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
1394 unsigned long flags;
1396 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
1398 /* Pre-DevBDW: OABUFFER must be set with counters off,
1399 * before OASTATUS1, but after OASTATUS2
1401 intel_uncore_write(uncore, GEN7_OASTATUS2, /* head */
1402 gtt_offset | GEN7_OASTATUS2_MEM_SELECT_GGTT);
1403 stream->oa_buffer.head = gtt_offset;
1405 intel_uncore_write(uncore, GEN7_OABUFFER, gtt_offset);
1407 intel_uncore_write(uncore, GEN7_OASTATUS1, /* tail */
1408 gtt_offset | OABUFFER_SIZE_16M);
1410 /* Mark that we need updated tail pointers to read from... */
1411 stream->oa_buffer.aging_tail = INVALID_TAIL_PTR;
1412 stream->oa_buffer.tail = gtt_offset;
1414 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
1416 /* On Haswell we have to track which OASTATUS1 flags we've
1417 * already seen since they can't be cleared while periodic
1418 * sampling is enabled.
1420 stream->perf->gen7_latched_oastatus1 = 0;
1422 /* NB: although the OA buffer will initially be allocated
1423 * zeroed via shmfs (and so this memset is redundant when
1424 * first allocating), we may re-init the OA buffer, either
1425 * when re-enabling a stream or in error/reset paths.
1427 * The reason we clear the buffer for each re-init is for the
1428 * sanity check in gen7_append_oa_reports() that looks at the
1429 * report-id field to make sure it's non-zero which relies on
1430 * the assumption that new reports are being written to zeroed
1433 memset(stream->oa_buffer.vaddr, 0, OA_BUFFER_SIZE);
1436 static void gen8_init_oa_buffer(struct i915_perf_stream *stream)
1438 struct intel_uncore *uncore = stream->uncore;
1439 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
1440 unsigned long flags;
1442 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
1444 intel_uncore_write(uncore, GEN8_OASTATUS, 0);
1445 intel_uncore_write(uncore, GEN8_OAHEADPTR, gtt_offset);
1446 stream->oa_buffer.head = gtt_offset;
1448 intel_uncore_write(uncore, GEN8_OABUFFER_UDW, 0);
1453 * "This MMIO must be set before the OATAILPTR
1454 * register and after the OAHEADPTR register. This is
1455 * to enable proper functionality of the overflow
1458 intel_uncore_write(uncore, GEN8_OABUFFER, gtt_offset |
1459 OABUFFER_SIZE_16M | GEN8_OABUFFER_MEM_SELECT_GGTT);
1460 intel_uncore_write(uncore, GEN8_OATAILPTR, gtt_offset & GEN8_OATAILPTR_MASK);
1462 /* Mark that we need updated tail pointers to read from... */
1463 stream->oa_buffer.aging_tail = INVALID_TAIL_PTR;
1464 stream->oa_buffer.tail = gtt_offset;
1467 * Reset state used to recognise context switches, affecting which
1468 * reports we will forward to userspace while filtering for a single
1471 stream->oa_buffer.last_ctx_id = INVALID_CTX_ID;
1473 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
1476 * NB: although the OA buffer will initially be allocated
1477 * zeroed via shmfs (and so this memset is redundant when
1478 * first allocating), we may re-init the OA buffer, either
1479 * when re-enabling a stream or in error/reset paths.
1481 * The reason we clear the buffer for each re-init is for the
1482 * sanity check in gen8_append_oa_reports() that looks at the
1483 * reason field to make sure it's non-zero which relies on
1484 * the assumption that new reports are being written to zeroed
1487 memset(stream->oa_buffer.vaddr, 0, OA_BUFFER_SIZE);
1490 static void gen12_init_oa_buffer(struct i915_perf_stream *stream)
1492 struct intel_uncore *uncore = stream->uncore;
1493 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
1494 unsigned long flags;
1496 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
1498 intel_uncore_write(uncore, GEN12_OAG_OASTATUS, 0);
1499 intel_uncore_write(uncore, GEN12_OAG_OAHEADPTR,
1500 gtt_offset & GEN12_OAG_OAHEADPTR_MASK);
1501 stream->oa_buffer.head = gtt_offset;
1506 * "This MMIO must be set before the OATAILPTR
1507 * register and after the OAHEADPTR register. This is
1508 * to enable proper functionality of the overflow
1511 intel_uncore_write(uncore, GEN12_OAG_OABUFFER, gtt_offset |
1512 OABUFFER_SIZE_16M | GEN8_OABUFFER_MEM_SELECT_GGTT);
1513 intel_uncore_write(uncore, GEN12_OAG_OATAILPTR,
1514 gtt_offset & GEN12_OAG_OATAILPTR_MASK);
1516 /* Mark that we need updated tail pointers to read from... */
1517 stream->oa_buffer.aging_tail = INVALID_TAIL_PTR;
1518 stream->oa_buffer.tail = gtt_offset;
1521 * Reset state used to recognise context switches, affecting which
1522 * reports we will forward to userspace while filtering for a single
1525 stream->oa_buffer.last_ctx_id = INVALID_CTX_ID;
1527 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
1530 * NB: although the OA buffer will initially be allocated
1531 * zeroed via shmfs (and so this memset is redundant when
1532 * first allocating), we may re-init the OA buffer, either
1533 * when re-enabling a stream or in error/reset paths.
1535 * The reason we clear the buffer for each re-init is for the
1536 * sanity check in gen8_append_oa_reports() that looks at the
1537 * reason field to make sure it's non-zero which relies on
1538 * the assumption that new reports are being written to zeroed
1541 memset(stream->oa_buffer.vaddr, 0,
1542 stream->oa_buffer.vma->size);
1545 static int alloc_oa_buffer(struct i915_perf_stream *stream)
1547 struct drm_i915_private *i915 = stream->perf->i915;
1548 struct drm_i915_gem_object *bo;
1549 struct i915_vma *vma;
1552 if (drm_WARN_ON(&i915->drm, stream->oa_buffer.vma))
1555 BUILD_BUG_ON_NOT_POWER_OF_2(OA_BUFFER_SIZE);
1556 BUILD_BUG_ON(OA_BUFFER_SIZE < SZ_128K || OA_BUFFER_SIZE > SZ_16M);
1558 bo = i915_gem_object_create_shmem(stream->perf->i915, OA_BUFFER_SIZE);
1560 drm_err(&i915->drm, "Failed to allocate OA buffer\n");
1564 i915_gem_object_set_cache_coherency(bo, I915_CACHE_LLC);
1566 /* PreHSW required 512K alignment, HSW requires 16M */
1567 vma = i915_gem_object_ggtt_pin(bo, NULL, 0, SZ_16M, 0);
1572 stream->oa_buffer.vma = vma;
1574 stream->oa_buffer.vaddr =
1575 i915_gem_object_pin_map_unlocked(bo, I915_MAP_WB);
1576 if (IS_ERR(stream->oa_buffer.vaddr)) {
1577 ret = PTR_ERR(stream->oa_buffer.vaddr);
1584 __i915_vma_unpin(vma);
1587 i915_gem_object_put(bo);
1589 stream->oa_buffer.vaddr = NULL;
1590 stream->oa_buffer.vma = NULL;
1595 static u32 *save_restore_register(struct i915_perf_stream *stream, u32 *cs,
1596 bool save, i915_reg_t reg, u32 offset,
1602 cmd = save ? MI_STORE_REGISTER_MEM : MI_LOAD_REGISTER_MEM;
1603 cmd |= MI_SRM_LRM_GLOBAL_GTT;
1604 if (GRAPHICS_VER(stream->perf->i915) >= 8)
1607 for (d = 0; d < dword_count; d++) {
1609 *cs++ = i915_mmio_reg_offset(reg) + 4 * d;
1610 *cs++ = intel_gt_scratch_offset(stream->engine->gt,
1618 static int alloc_noa_wait(struct i915_perf_stream *stream)
1620 struct drm_i915_private *i915 = stream->perf->i915;
1621 struct drm_i915_gem_object *bo;
1622 struct i915_vma *vma;
1623 const u64 delay_ticks = 0xffffffffffffffff -
1624 intel_gt_ns_to_clock_interval(stream->perf->i915->ggtt.vm.gt,
1625 atomic64_read(&stream->perf->noa_programming_delay));
1626 const u32 base = stream->engine->mmio_base;
1627 #define CS_GPR(x) GEN8_RING_CS_GPR(base, x)
1628 u32 *batch, *ts0, *cs, *jump;
1629 struct i915_gem_ww_ctx ww;
1640 bo = i915_gem_object_create_internal(i915, 4096);
1643 "Failed to allocate NOA wait batchbuffer\n");
1647 i915_gem_ww_ctx_init(&ww, true);
1649 ret = i915_gem_object_lock(bo, &ww);
1654 * We pin in GGTT because we jump into this buffer now because
1655 * multiple OA config BOs will have a jump to this address and it
1656 * needs to be fixed during the lifetime of the i915/perf stream.
1658 vma = i915_gem_object_ggtt_pin_ww(bo, &ww, NULL, 0, 0, PIN_HIGH);
1664 batch = cs = i915_gem_object_pin_map(bo, I915_MAP_WB);
1665 if (IS_ERR(batch)) {
1666 ret = PTR_ERR(batch);
1670 /* Save registers. */
1671 for (i = 0; i < N_CS_GPR; i++)
1672 cs = save_restore_register(
1673 stream, cs, true /* save */, CS_GPR(i),
1674 INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2);
1675 cs = save_restore_register(
1676 stream, cs, true /* save */, MI_PREDICATE_RESULT_1,
1677 INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1, 1);
1679 /* First timestamp snapshot location. */
1683 * Initial snapshot of the timestamp register to implement the wait.
1684 * We work with 32b values, so clear out the top 32b bits of the
1685 * register because the ALU works 64bits.
1687 *cs++ = MI_LOAD_REGISTER_IMM(1);
1688 *cs++ = i915_mmio_reg_offset(CS_GPR(START_TS)) + 4;
1690 *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
1691 *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(base));
1692 *cs++ = i915_mmio_reg_offset(CS_GPR(START_TS));
1695 * This is the location we're going to jump back into until the
1696 * required amount of time has passed.
1701 * Take another snapshot of the timestamp register. Take care to clear
1702 * up the top 32bits of CS_GPR(1) as we're using it for other
1705 *cs++ = MI_LOAD_REGISTER_IMM(1);
1706 *cs++ = i915_mmio_reg_offset(CS_GPR(NOW_TS)) + 4;
1708 *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
1709 *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(base));
1710 *cs++ = i915_mmio_reg_offset(CS_GPR(NOW_TS));
1713 * Do a diff between the 2 timestamps and store the result back into
1717 *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(NOW_TS));
1718 *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(START_TS));
1719 *cs++ = MI_MATH_SUB;
1720 *cs++ = MI_MATH_STORE(MI_MATH_REG(DELTA_TS), MI_MATH_REG_ACCU);
1721 *cs++ = MI_MATH_STORE(MI_MATH_REG(JUMP_PREDICATE), MI_MATH_REG_CF);
1724 * Transfer the carry flag (set to 1 if ts1 < ts0, meaning the
1725 * timestamp have rolled over the 32bits) into the predicate register
1726 * to be used for the predicated jump.
1728 *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
1729 *cs++ = i915_mmio_reg_offset(CS_GPR(JUMP_PREDICATE));
1730 *cs++ = i915_mmio_reg_offset(MI_PREDICATE_RESULT_1);
1732 /* Restart from the beginning if we had timestamps roll over. */
1733 *cs++ = (GRAPHICS_VER(i915) < 8 ?
1734 MI_BATCH_BUFFER_START :
1735 MI_BATCH_BUFFER_START_GEN8) |
1737 *cs++ = i915_ggtt_offset(vma) + (ts0 - batch) * 4;
1741 * Now add the diff between to previous timestamps and add it to :
1742 * (((1 * << 64) - 1) - delay_ns)
1744 * When the Carry Flag contains 1 this means the elapsed time is
1745 * longer than the expected delay, and we can exit the wait loop.
1747 *cs++ = MI_LOAD_REGISTER_IMM(2);
1748 *cs++ = i915_mmio_reg_offset(CS_GPR(DELTA_TARGET));
1749 *cs++ = lower_32_bits(delay_ticks);
1750 *cs++ = i915_mmio_reg_offset(CS_GPR(DELTA_TARGET)) + 4;
1751 *cs++ = upper_32_bits(delay_ticks);
1754 *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(DELTA_TS));
1755 *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(DELTA_TARGET));
1756 *cs++ = MI_MATH_ADD;
1757 *cs++ = MI_MATH_STOREINV(MI_MATH_REG(JUMP_PREDICATE), MI_MATH_REG_CF);
1759 *cs++ = MI_ARB_CHECK;
1762 * Transfer the result into the predicate register to be used for the
1765 *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
1766 *cs++ = i915_mmio_reg_offset(CS_GPR(JUMP_PREDICATE));
1767 *cs++ = i915_mmio_reg_offset(MI_PREDICATE_RESULT_1);
1769 /* Predicate the jump. */
1770 *cs++ = (GRAPHICS_VER(i915) < 8 ?
1771 MI_BATCH_BUFFER_START :
1772 MI_BATCH_BUFFER_START_GEN8) |
1774 *cs++ = i915_ggtt_offset(vma) + (jump - batch) * 4;
1777 /* Restore registers. */
1778 for (i = 0; i < N_CS_GPR; i++)
1779 cs = save_restore_register(
1780 stream, cs, false /* restore */, CS_GPR(i),
1781 INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2);
1782 cs = save_restore_register(
1783 stream, cs, false /* restore */, MI_PREDICATE_RESULT_1,
1784 INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1, 1);
1786 /* And return to the ring. */
1787 *cs++ = MI_BATCH_BUFFER_END;
1789 GEM_BUG_ON(cs - batch > PAGE_SIZE / sizeof(*batch));
1791 i915_gem_object_flush_map(bo);
1792 __i915_gem_object_release_map(bo);
1794 stream->noa_wait = vma;
1798 i915_vma_unpin_and_release(&vma, 0);
1800 if (ret == -EDEADLK) {
1801 ret = i915_gem_ww_ctx_backoff(&ww);
1805 i915_gem_ww_ctx_fini(&ww);
1807 i915_gem_object_put(bo);
1811 static u32 *write_cs_mi_lri(u32 *cs,
1812 const struct i915_oa_reg *reg_data,
1817 for (i = 0; i < n_regs; i++) {
1818 if ((i % MI_LOAD_REGISTER_IMM_MAX_REGS) == 0) {
1819 u32 n_lri = min_t(u32,
1821 MI_LOAD_REGISTER_IMM_MAX_REGS);
1823 *cs++ = MI_LOAD_REGISTER_IMM(n_lri);
1825 *cs++ = i915_mmio_reg_offset(reg_data[i].addr);
1826 *cs++ = reg_data[i].value;
1832 static int num_lri_dwords(int num_regs)
1837 count += DIV_ROUND_UP(num_regs, MI_LOAD_REGISTER_IMM_MAX_REGS);
1838 count += num_regs * 2;
1844 static struct i915_oa_config_bo *
1845 alloc_oa_config_buffer(struct i915_perf_stream *stream,
1846 struct i915_oa_config *oa_config)
1848 struct drm_i915_gem_object *obj;
1849 struct i915_oa_config_bo *oa_bo;
1850 struct i915_gem_ww_ctx ww;
1851 size_t config_length = 0;
1855 oa_bo = kzalloc(sizeof(*oa_bo), GFP_KERNEL);
1857 return ERR_PTR(-ENOMEM);
1859 config_length += num_lri_dwords(oa_config->mux_regs_len);
1860 config_length += num_lri_dwords(oa_config->b_counter_regs_len);
1861 config_length += num_lri_dwords(oa_config->flex_regs_len);
1862 config_length += 3; /* MI_BATCH_BUFFER_START */
1863 config_length = ALIGN(sizeof(u32) * config_length, I915_GTT_PAGE_SIZE);
1865 obj = i915_gem_object_create_shmem(stream->perf->i915, config_length);
1871 i915_gem_ww_ctx_init(&ww, true);
1873 err = i915_gem_object_lock(obj, &ww);
1877 cs = i915_gem_object_pin_map(obj, I915_MAP_WB);
1883 cs = write_cs_mi_lri(cs,
1884 oa_config->mux_regs,
1885 oa_config->mux_regs_len);
1886 cs = write_cs_mi_lri(cs,
1887 oa_config->b_counter_regs,
1888 oa_config->b_counter_regs_len);
1889 cs = write_cs_mi_lri(cs,
1890 oa_config->flex_regs,
1891 oa_config->flex_regs_len);
1893 /* Jump into the active wait. */
1894 *cs++ = (GRAPHICS_VER(stream->perf->i915) < 8 ?
1895 MI_BATCH_BUFFER_START :
1896 MI_BATCH_BUFFER_START_GEN8);
1897 *cs++ = i915_ggtt_offset(stream->noa_wait);
1900 i915_gem_object_flush_map(obj);
1901 __i915_gem_object_release_map(obj);
1903 oa_bo->vma = i915_vma_instance(obj,
1904 &stream->engine->gt->ggtt->vm,
1906 if (IS_ERR(oa_bo->vma)) {
1907 err = PTR_ERR(oa_bo->vma);
1911 oa_bo->oa_config = i915_oa_config_get(oa_config);
1912 llist_add(&oa_bo->node, &stream->oa_config_bos);
1915 if (err == -EDEADLK) {
1916 err = i915_gem_ww_ctx_backoff(&ww);
1920 i915_gem_ww_ctx_fini(&ww);
1923 i915_gem_object_put(obj);
1927 return ERR_PTR(err);
1932 static struct i915_vma *
1933 get_oa_vma(struct i915_perf_stream *stream, struct i915_oa_config *oa_config)
1935 struct i915_oa_config_bo *oa_bo;
1938 * Look for the buffer in the already allocated BOs attached
1941 llist_for_each_entry(oa_bo, stream->oa_config_bos.first, node) {
1942 if (oa_bo->oa_config == oa_config &&
1943 memcmp(oa_bo->oa_config->uuid,
1945 sizeof(oa_config->uuid)) == 0)
1949 oa_bo = alloc_oa_config_buffer(stream, oa_config);
1951 return ERR_CAST(oa_bo);
1954 return i915_vma_get(oa_bo->vma);
1958 emit_oa_config(struct i915_perf_stream *stream,
1959 struct i915_oa_config *oa_config,
1960 struct intel_context *ce,
1961 struct i915_active *active)
1963 struct i915_request *rq;
1964 struct i915_vma *vma;
1965 struct i915_gem_ww_ctx ww;
1968 vma = get_oa_vma(stream, oa_config);
1970 return PTR_ERR(vma);
1972 i915_gem_ww_ctx_init(&ww, true);
1974 err = i915_gem_object_lock(vma->obj, &ww);
1978 err = i915_vma_pin_ww(vma, &ww, 0, 0, PIN_GLOBAL | PIN_HIGH);
1982 intel_engine_pm_get(ce->engine);
1983 rq = i915_request_create(ce);
1984 intel_engine_pm_put(ce->engine);
1990 if (!IS_ERR_OR_NULL(active)) {
1991 /* After all individual context modifications */
1992 err = i915_request_await_active(rq, active,
1993 I915_ACTIVE_AWAIT_ACTIVE);
1995 goto err_add_request;
1997 err = i915_active_add_request(active, rq);
1999 goto err_add_request;
2002 err = i915_request_await_object(rq, vma->obj, 0);
2004 err = i915_vma_move_to_active(vma, rq, 0);
2006 goto err_add_request;
2008 err = rq->engine->emit_bb_start(rq,
2010 I915_DISPATCH_SECURE);
2012 goto err_add_request;
2015 i915_request_add(rq);
2017 i915_vma_unpin(vma);
2019 if (err == -EDEADLK) {
2020 err = i915_gem_ww_ctx_backoff(&ww);
2025 i915_gem_ww_ctx_fini(&ww);
2030 static struct intel_context *oa_context(struct i915_perf_stream *stream)
2032 return stream->pinned_ctx ?: stream->engine->kernel_context;
2036 hsw_enable_metric_set(struct i915_perf_stream *stream,
2037 struct i915_active *active)
2039 struct intel_uncore *uncore = stream->uncore;
2044 * OA unit is using “crclk” for its functionality. When trunk
2045 * level clock gating takes place, OA clock would be gated,
2046 * unable to count the events from non-render clock domain.
2047 * Render clock gating must be disabled when OA is enabled to
2048 * count the events from non-render domain. Unit level clock
2049 * gating for RCS should also be disabled.
2051 intel_uncore_rmw(uncore, GEN7_MISCCPCTL,
2052 GEN7_DOP_CLOCK_GATE_ENABLE, 0);
2053 intel_uncore_rmw(uncore, GEN6_UCGCTL1,
2054 0, GEN6_CSUNIT_CLOCK_GATE_DISABLE);
2056 return emit_oa_config(stream,
2057 stream->oa_config, oa_context(stream),
2061 static void hsw_disable_metric_set(struct i915_perf_stream *stream)
2063 struct intel_uncore *uncore = stream->uncore;
2065 intel_uncore_rmw(uncore, GEN6_UCGCTL1,
2066 GEN6_CSUNIT_CLOCK_GATE_DISABLE, 0);
2067 intel_uncore_rmw(uncore, GEN7_MISCCPCTL,
2068 0, GEN7_DOP_CLOCK_GATE_ENABLE);
2070 intel_uncore_rmw(uncore, GDT_CHICKEN_BITS, GT_NOA_ENABLE, 0);
2073 static u32 oa_config_flex_reg(const struct i915_oa_config *oa_config,
2076 u32 mmio = i915_mmio_reg_offset(reg);
2080 * This arbitrary default will select the 'EU FPU0 Pipeline
2081 * Active' event. In the future it's anticipated that there
2082 * will be an explicit 'No Event' we can select, but not yet...
2087 for (i = 0; i < oa_config->flex_regs_len; i++) {
2088 if (i915_mmio_reg_offset(oa_config->flex_regs[i].addr) == mmio)
2089 return oa_config->flex_regs[i].value;
2095 * NB: It must always remain pointer safe to run this even if the OA unit
2096 * has been disabled.
2098 * It's fine to put out-of-date values into these per-context registers
2099 * in the case that the OA unit has been disabled.
2102 gen8_update_reg_state_unlocked(const struct intel_context *ce,
2103 const struct i915_perf_stream *stream)
2105 u32 ctx_oactxctrl = stream->perf->ctx_oactxctrl_offset;
2106 u32 ctx_flexeu0 = stream->perf->ctx_flexeu0_offset;
2107 /* The MMIO offsets for Flex EU registers aren't contiguous */
2108 i915_reg_t flex_regs[] = {
2117 u32 *reg_state = ce->lrc_reg_state;
2120 reg_state[ctx_oactxctrl + 1] =
2121 (stream->period_exponent << GEN8_OA_TIMER_PERIOD_SHIFT) |
2122 (stream->periodic ? GEN8_OA_TIMER_ENABLE : 0) |
2123 GEN8_OA_COUNTER_RESUME;
2125 for (i = 0; i < ARRAY_SIZE(flex_regs); i++)
2126 reg_state[ctx_flexeu0 + i * 2 + 1] =
2127 oa_config_flex_reg(stream->oa_config, flex_regs[i]);
2137 gen8_store_flex(struct i915_request *rq,
2138 struct intel_context *ce,
2139 const struct flex *flex, unsigned int count)
2144 cs = intel_ring_begin(rq, 4 * count);
2148 offset = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET;
2150 *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
2151 *cs++ = offset + flex->offset * sizeof(u32);
2153 *cs++ = flex->value;
2154 } while (flex++, --count);
2156 intel_ring_advance(rq, cs);
2162 gen8_load_flex(struct i915_request *rq,
2163 struct intel_context *ce,
2164 const struct flex *flex, unsigned int count)
2168 GEM_BUG_ON(!count || count > 63);
2170 cs = intel_ring_begin(rq, 2 * count + 2);
2174 *cs++ = MI_LOAD_REGISTER_IMM(count);
2176 *cs++ = i915_mmio_reg_offset(flex->reg);
2177 *cs++ = flex->value;
2178 } while (flex++, --count);
2181 intel_ring_advance(rq, cs);
2186 static int gen8_modify_context(struct intel_context *ce,
2187 const struct flex *flex, unsigned int count)
2189 struct i915_request *rq;
2192 rq = intel_engine_create_kernel_request(ce->engine);
2196 /* Serialise with the remote context */
2197 err = intel_context_prepare_remote_request(ce, rq);
2199 err = gen8_store_flex(rq, ce, flex, count);
2201 i915_request_add(rq);
2206 gen8_modify_self(struct intel_context *ce,
2207 const struct flex *flex, unsigned int count,
2208 struct i915_active *active)
2210 struct i915_request *rq;
2213 intel_engine_pm_get(ce->engine);
2214 rq = i915_request_create(ce);
2215 intel_engine_pm_put(ce->engine);
2219 if (!IS_ERR_OR_NULL(active)) {
2220 err = i915_active_add_request(active, rq);
2222 goto err_add_request;
2225 err = gen8_load_flex(rq, ce, flex, count);
2227 goto err_add_request;
2230 i915_request_add(rq);
2234 static int gen8_configure_context(struct i915_gem_context *ctx,
2235 struct flex *flex, unsigned int count)
2237 struct i915_gem_engines_iter it;
2238 struct intel_context *ce;
2241 for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
2242 GEM_BUG_ON(ce == ce->engine->kernel_context);
2244 if (ce->engine->class != RENDER_CLASS)
2247 /* Otherwise OA settings will be set upon first use */
2248 if (!intel_context_pin_if_active(ce))
2251 flex->value = intel_sseu_make_rpcs(ce->engine->gt, &ce->sseu);
2252 err = gen8_modify_context(ce, flex, count);
2254 intel_context_unpin(ce);
2258 i915_gem_context_unlock_engines(ctx);
2263 static int gen12_configure_oar_context(struct i915_perf_stream *stream,
2264 struct i915_active *active)
2267 struct intel_context *ce = stream->pinned_ctx;
2268 u32 format = stream->oa_buffer.format;
2269 struct flex regs_context[] = {
2272 stream->perf->ctx_oactxctrl_offset + 1,
2273 active ? GEN8_OA_COUNTER_RESUME : 0,
2276 /* Offsets in regs_lri are not used since this configuration is only
2277 * applied using LRI. Initialize the correct offsets for posterity.
2279 #define GEN12_OAR_OACONTROL_OFFSET 0x5B0
2280 struct flex regs_lri[] = {
2282 GEN12_OAR_OACONTROL,
2283 GEN12_OAR_OACONTROL_OFFSET + 1,
2284 (format << GEN12_OAR_OACONTROL_COUNTER_FORMAT_SHIFT) |
2285 (active ? GEN12_OAR_OACONTROL_COUNTER_ENABLE : 0)
2288 RING_CONTEXT_CONTROL(ce->engine->mmio_base),
2289 CTX_CONTEXT_CONTROL,
2290 _MASKED_FIELD(GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE,
2292 GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE :
2297 /* Modify the context image of pinned context with regs_context*/
2298 err = intel_context_lock_pinned(ce);
2302 err = gen8_modify_context(ce, regs_context, ARRAY_SIZE(regs_context));
2303 intel_context_unlock_pinned(ce);
2307 /* Apply regs_lri using LRI with pinned context */
2308 return gen8_modify_self(ce, regs_lri, ARRAY_SIZE(regs_lri), active);
2312 * Manages updating the per-context aspects of the OA stream
2313 * configuration across all contexts.
2315 * The awkward consideration here is that OACTXCONTROL controls the
2316 * exponent for periodic sampling which is primarily used for system
2317 * wide profiling where we'd like a consistent sampling period even in
2318 * the face of context switches.
2320 * Our approach of updating the register state context (as opposed to
2321 * say using a workaround batch buffer) ensures that the hardware
2322 * won't automatically reload an out-of-date timer exponent even
2323 * transiently before a WA BB could be parsed.
2325 * This function needs to:
2326 * - Ensure the currently running context's per-context OA state is
2328 * - Ensure that all existing contexts will have the correct per-context
2329 * OA state if they are scheduled for use.
2330 * - Ensure any new contexts will be initialized with the correct
2331 * per-context OA state.
2333 * Note: it's only the RCS/Render context that has any OA state.
2334 * Note: the first flex register passed must always be R_PWR_CLK_STATE
2337 oa_configure_all_contexts(struct i915_perf_stream *stream,
2340 struct i915_active *active)
2342 struct drm_i915_private *i915 = stream->perf->i915;
2343 struct intel_engine_cs *engine;
2344 struct i915_gem_context *ctx, *cn;
2347 lockdep_assert_held(&stream->perf->lock);
2350 * The OA register config is setup through the context image. This image
2351 * might be written to by the GPU on context switch (in particular on
2352 * lite-restore). This means we can't safely update a context's image,
2353 * if this context is scheduled/submitted to run on the GPU.
2355 * We could emit the OA register config through the batch buffer but
2356 * this might leave small interval of time where the OA unit is
2357 * configured at an invalid sampling period.
2359 * Note that since we emit all requests from a single ring, there
2360 * is still an implicit global barrier here that may cause a high
2361 * priority context to wait for an otherwise independent low priority
2362 * context. Contexts idle at the time of reconfiguration are not
2363 * trapped behind the barrier.
2365 spin_lock(&i915->gem.contexts.lock);
2366 list_for_each_entry_safe(ctx, cn, &i915->gem.contexts.list, link) {
2367 if (!kref_get_unless_zero(&ctx->ref))
2370 spin_unlock(&i915->gem.contexts.lock);
2372 err = gen8_configure_context(ctx, regs, num_regs);
2374 i915_gem_context_put(ctx);
2378 spin_lock(&i915->gem.contexts.lock);
2379 list_safe_reset_next(ctx, cn, link);
2380 i915_gem_context_put(ctx);
2382 spin_unlock(&i915->gem.contexts.lock);
2385 * After updating all other contexts, we need to modify ourselves.
2386 * If we don't modify the kernel_context, we do not get events while
2389 for_each_uabi_engine(engine, i915) {
2390 struct intel_context *ce = engine->kernel_context;
2392 if (engine->class != RENDER_CLASS)
2395 regs[0].value = intel_sseu_make_rpcs(engine->gt, &ce->sseu);
2397 err = gen8_modify_self(ce, regs, num_regs, active);
2406 gen12_configure_all_contexts(struct i915_perf_stream *stream,
2407 const struct i915_oa_config *oa_config,
2408 struct i915_active *active)
2410 struct flex regs[] = {
2412 GEN8_R_PWR_CLK_STATE,
2413 CTX_R_PWR_CLK_STATE,
2417 return oa_configure_all_contexts(stream,
2418 regs, ARRAY_SIZE(regs),
2423 lrc_configure_all_contexts(struct i915_perf_stream *stream,
2424 const struct i915_oa_config *oa_config,
2425 struct i915_active *active)
2427 /* The MMIO offsets for Flex EU registers aren't contiguous */
2428 const u32 ctx_flexeu0 = stream->perf->ctx_flexeu0_offset;
2429 #define ctx_flexeuN(N) (ctx_flexeu0 + 2 * (N) + 1)
2430 struct flex regs[] = {
2432 GEN8_R_PWR_CLK_STATE,
2433 CTX_R_PWR_CLK_STATE,
2437 stream->perf->ctx_oactxctrl_offset + 1,
2439 { EU_PERF_CNTL0, ctx_flexeuN(0) },
2440 { EU_PERF_CNTL1, ctx_flexeuN(1) },
2441 { EU_PERF_CNTL2, ctx_flexeuN(2) },
2442 { EU_PERF_CNTL3, ctx_flexeuN(3) },
2443 { EU_PERF_CNTL4, ctx_flexeuN(4) },
2444 { EU_PERF_CNTL5, ctx_flexeuN(5) },
2445 { EU_PERF_CNTL6, ctx_flexeuN(6) },
2451 (stream->period_exponent << GEN8_OA_TIMER_PERIOD_SHIFT) |
2452 (stream->periodic ? GEN8_OA_TIMER_ENABLE : 0) |
2453 GEN8_OA_COUNTER_RESUME;
2455 for (i = 2; i < ARRAY_SIZE(regs); i++)
2456 regs[i].value = oa_config_flex_reg(oa_config, regs[i].reg);
2458 return oa_configure_all_contexts(stream,
2459 regs, ARRAY_SIZE(regs),
2464 gen8_enable_metric_set(struct i915_perf_stream *stream,
2465 struct i915_active *active)
2467 struct intel_uncore *uncore = stream->uncore;
2468 struct i915_oa_config *oa_config = stream->oa_config;
2472 * We disable slice/unslice clock ratio change reports on SKL since
2473 * they are too noisy. The HW generates a lot of redundant reports
2474 * where the ratio hasn't really changed causing a lot of redundant
2475 * work to processes and increasing the chances we'll hit buffer
2478 * Although we don't currently use the 'disable overrun' OABUFFER
2479 * feature it's worth noting that clock ratio reports have to be
2480 * disabled before considering to use that feature since the HW doesn't
2481 * correctly block these reports.
2483 * Currently none of the high-level metrics we have depend on knowing
2484 * this ratio to normalize.
2486 * Note: This register is not power context saved and restored, but
2487 * that's OK considering that we disable RC6 while the OA unit is
2490 * The _INCLUDE_CLK_RATIO bit allows the slice/unslice frequency to
2491 * be read back from automatically triggered reports, as part of the
2494 if (IS_GRAPHICS_VER(stream->perf->i915, 9, 11)) {
2495 intel_uncore_write(uncore, GEN8_OA_DEBUG,
2496 _MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
2497 GEN9_OA_DEBUG_INCLUDE_CLK_RATIO));
2501 * Update all contexts prior writing the mux configurations as we need
2502 * to make sure all slices/subslices are ON before writing to NOA
2505 ret = lrc_configure_all_contexts(stream, oa_config, active);
2509 return emit_oa_config(stream,
2510 stream->oa_config, oa_context(stream),
2514 static u32 oag_report_ctx_switches(const struct i915_perf_stream *stream)
2516 return _MASKED_FIELD(GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS,
2517 (stream->sample_flags & SAMPLE_OA_REPORT) ?
2518 0 : GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS);
2522 gen12_enable_metric_set(struct i915_perf_stream *stream,
2523 struct i915_active *active)
2525 struct intel_uncore *uncore = stream->uncore;
2526 struct i915_oa_config *oa_config = stream->oa_config;
2527 bool periodic = stream->periodic;
2528 u32 period_exponent = stream->period_exponent;
2531 intel_uncore_write(uncore, GEN12_OAG_OA_DEBUG,
2532 /* Disable clk ratio reports, like previous Gens. */
2533 _MASKED_BIT_ENABLE(GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
2534 GEN12_OAG_OA_DEBUG_INCLUDE_CLK_RATIO) |
2536 * If the user didn't require OA reports, instruct
2537 * the hardware not to emit ctx switch reports.
2539 oag_report_ctx_switches(stream));
2541 intel_uncore_write(uncore, GEN12_OAG_OAGLBCTXCTRL, periodic ?
2542 (GEN12_OAG_OAGLBCTXCTRL_COUNTER_RESUME |
2543 GEN12_OAG_OAGLBCTXCTRL_TIMER_ENABLE |
2544 (period_exponent << GEN12_OAG_OAGLBCTXCTRL_TIMER_PERIOD_SHIFT))
2548 * Update all contexts prior writing the mux configurations as we need
2549 * to make sure all slices/subslices are ON before writing to NOA
2552 ret = gen12_configure_all_contexts(stream, oa_config, active);
2557 * For Gen12, performance counters are context
2558 * saved/restored. Only enable it for the context that
2562 ret = gen12_configure_oar_context(stream, active);
2567 return emit_oa_config(stream,
2568 stream->oa_config, oa_context(stream),
2572 static void gen8_disable_metric_set(struct i915_perf_stream *stream)
2574 struct intel_uncore *uncore = stream->uncore;
2576 /* Reset all contexts' slices/subslices configurations. */
2577 lrc_configure_all_contexts(stream, NULL, NULL);
2579 intel_uncore_rmw(uncore, GDT_CHICKEN_BITS, GT_NOA_ENABLE, 0);
2582 static void gen11_disable_metric_set(struct i915_perf_stream *stream)
2584 struct intel_uncore *uncore = stream->uncore;
2586 /* Reset all contexts' slices/subslices configurations. */
2587 lrc_configure_all_contexts(stream, NULL, NULL);
2589 /* Make sure we disable noa to save power. */
2590 intel_uncore_rmw(uncore, RPM_CONFIG1, GEN10_GT_NOA_ENABLE, 0);
2593 static void gen12_disable_metric_set(struct i915_perf_stream *stream)
2595 struct intel_uncore *uncore = stream->uncore;
2597 /* Reset all contexts' slices/subslices configurations. */
2598 gen12_configure_all_contexts(stream, NULL, NULL);
2600 /* disable the context save/restore or OAR counters */
2602 gen12_configure_oar_context(stream, NULL);
2604 /* Make sure we disable noa to save power. */
2605 intel_uncore_rmw(uncore, RPM_CONFIG1, GEN10_GT_NOA_ENABLE, 0);
2608 static void gen7_oa_enable(struct i915_perf_stream *stream)
2610 struct intel_uncore *uncore = stream->uncore;
2611 struct i915_gem_context *ctx = stream->ctx;
2612 u32 ctx_id = stream->specific_ctx_id;
2613 bool periodic = stream->periodic;
2614 u32 period_exponent = stream->period_exponent;
2615 u32 report_format = stream->oa_buffer.format;
2618 * Reset buf pointers so we don't forward reports from before now.
2620 * Think carefully if considering trying to avoid this, since it
2621 * also ensures status flags and the buffer itself are cleared
2622 * in error paths, and we have checks for invalid reports based
2623 * on the assumption that certain fields are written to zeroed
2624 * memory which this helps maintains.
2626 gen7_init_oa_buffer(stream);
2628 intel_uncore_write(uncore, GEN7_OACONTROL,
2629 (ctx_id & GEN7_OACONTROL_CTX_MASK) |
2631 GEN7_OACONTROL_TIMER_PERIOD_SHIFT) |
2632 (periodic ? GEN7_OACONTROL_TIMER_ENABLE : 0) |
2633 (report_format << GEN7_OACONTROL_FORMAT_SHIFT) |
2634 (ctx ? GEN7_OACONTROL_PER_CTX_ENABLE : 0) |
2635 GEN7_OACONTROL_ENABLE);
2638 static void gen8_oa_enable(struct i915_perf_stream *stream)
2640 struct intel_uncore *uncore = stream->uncore;
2641 u32 report_format = stream->oa_buffer.format;
2644 * Reset buf pointers so we don't forward reports from before now.
2646 * Think carefully if considering trying to avoid this, since it
2647 * also ensures status flags and the buffer itself are cleared
2648 * in error paths, and we have checks for invalid reports based
2649 * on the assumption that certain fields are written to zeroed
2650 * memory which this helps maintains.
2652 gen8_init_oa_buffer(stream);
2655 * Note: we don't rely on the hardware to perform single context
2656 * filtering and instead filter on the cpu based on the context-id
2659 intel_uncore_write(uncore, GEN8_OACONTROL,
2660 (report_format << GEN8_OA_REPORT_FORMAT_SHIFT) |
2661 GEN8_OA_COUNTER_ENABLE);
2664 static void gen12_oa_enable(struct i915_perf_stream *stream)
2666 struct intel_uncore *uncore = stream->uncore;
2667 u32 report_format = stream->oa_buffer.format;
2670 * If we don't want OA reports from the OA buffer, then we don't even
2671 * need to program the OAG unit.
2673 if (!(stream->sample_flags & SAMPLE_OA_REPORT))
2676 gen12_init_oa_buffer(stream);
2678 intel_uncore_write(uncore, GEN12_OAG_OACONTROL,
2679 (report_format << GEN12_OAG_OACONTROL_OA_COUNTER_FORMAT_SHIFT) |
2680 GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE);
2684 * i915_oa_stream_enable - handle `I915_PERF_IOCTL_ENABLE` for OA stream
2685 * @stream: An i915 perf stream opened for OA metrics
2687 * [Re]enables hardware periodic sampling according to the period configured
2688 * when opening the stream. This also starts a hrtimer that will periodically
2689 * check for data in the circular OA buffer for notifying userspace (e.g.
2690 * during a read() or poll()).
2692 static void i915_oa_stream_enable(struct i915_perf_stream *stream)
2694 stream->pollin = false;
2696 stream->perf->ops.oa_enable(stream);
2698 if (stream->sample_flags & SAMPLE_OA_REPORT)
2699 hrtimer_start(&stream->poll_check_timer,
2700 ns_to_ktime(stream->poll_oa_period),
2701 HRTIMER_MODE_REL_PINNED);
2704 static void gen7_oa_disable(struct i915_perf_stream *stream)
2706 struct intel_uncore *uncore = stream->uncore;
2708 intel_uncore_write(uncore, GEN7_OACONTROL, 0);
2709 if (intel_wait_for_register(uncore,
2710 GEN7_OACONTROL, GEN7_OACONTROL_ENABLE, 0,
2712 drm_err(&stream->perf->i915->drm,
2713 "wait for OA to be disabled timed out\n");
2716 static void gen8_oa_disable(struct i915_perf_stream *stream)
2718 struct intel_uncore *uncore = stream->uncore;
2720 intel_uncore_write(uncore, GEN8_OACONTROL, 0);
2721 if (intel_wait_for_register(uncore,
2722 GEN8_OACONTROL, GEN8_OA_COUNTER_ENABLE, 0,
2724 drm_err(&stream->perf->i915->drm,
2725 "wait for OA to be disabled timed out\n");
2728 static void gen12_oa_disable(struct i915_perf_stream *stream)
2730 struct intel_uncore *uncore = stream->uncore;
2732 intel_uncore_write(uncore, GEN12_OAG_OACONTROL, 0);
2733 if (intel_wait_for_register(uncore,
2734 GEN12_OAG_OACONTROL,
2735 GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE, 0,
2737 drm_err(&stream->perf->i915->drm,
2738 "wait for OA to be disabled timed out\n");
2740 intel_uncore_write(uncore, GEN12_OA_TLB_INV_CR, 1);
2741 if (intel_wait_for_register(uncore,
2742 GEN12_OA_TLB_INV_CR,
2745 drm_err(&stream->perf->i915->drm,
2746 "wait for OA tlb invalidate timed out\n");
2750 * i915_oa_stream_disable - handle `I915_PERF_IOCTL_DISABLE` for OA stream
2751 * @stream: An i915 perf stream opened for OA metrics
2753 * Stops the OA unit from periodically writing counter reports into the
2754 * circular OA buffer. This also stops the hrtimer that periodically checks for
2755 * data in the circular OA buffer, for notifying userspace.
2757 static void i915_oa_stream_disable(struct i915_perf_stream *stream)
2759 stream->perf->ops.oa_disable(stream);
2761 if (stream->sample_flags & SAMPLE_OA_REPORT)
2762 hrtimer_cancel(&stream->poll_check_timer);
2765 static const struct i915_perf_stream_ops i915_oa_stream_ops = {
2766 .destroy = i915_oa_stream_destroy,
2767 .enable = i915_oa_stream_enable,
2768 .disable = i915_oa_stream_disable,
2769 .wait_unlocked = i915_oa_wait_unlocked,
2770 .poll_wait = i915_oa_poll_wait,
2771 .read = i915_oa_read,
2774 static int i915_perf_stream_enable_sync(struct i915_perf_stream *stream)
2776 struct i915_active *active;
2779 active = i915_active_create();
2783 err = stream->perf->ops.enable_metric_set(stream, active);
2785 __i915_active_wait(active, TASK_UNINTERRUPTIBLE);
2787 i915_active_put(active);
2792 get_default_sseu_config(struct intel_sseu *out_sseu,
2793 struct intel_engine_cs *engine)
2795 const struct sseu_dev_info *devinfo_sseu = &engine->gt->info.sseu;
2797 *out_sseu = intel_sseu_from_device_info(devinfo_sseu);
2799 if (GRAPHICS_VER(engine->i915) == 11) {
2801 * We only need subslice count so it doesn't matter which ones
2802 * we select - just turn off low bits in the amount of half of
2803 * all available subslices per slice.
2805 out_sseu->subslice_mask =
2806 ~(~0 << (hweight8(out_sseu->subslice_mask) / 2));
2807 out_sseu->slice_mask = 0x1;
2812 get_sseu_config(struct intel_sseu *out_sseu,
2813 struct intel_engine_cs *engine,
2814 const struct drm_i915_gem_context_param_sseu *drm_sseu)
2816 if (drm_sseu->engine.engine_class != engine->uabi_class ||
2817 drm_sseu->engine.engine_instance != engine->uabi_instance)
2820 return i915_gem_user_to_context_sseu(engine->gt, drm_sseu, out_sseu);
2824 * i915_oa_stream_init - validate combined props for OA stream and init
2825 * @stream: An i915 perf stream
2826 * @param: The open parameters passed to `DRM_I915_PERF_OPEN`
2827 * @props: The property state that configures stream (individually validated)
2829 * While read_properties_unlocked() validates properties in isolation it
2830 * doesn't ensure that the combination necessarily makes sense.
2832 * At this point it has been determined that userspace wants a stream of
2833 * OA metrics, but still we need to further validate the combined
2834 * properties are OK.
2836 * If the configuration makes sense then we can allocate memory for
2837 * a circular OA buffer and apply the requested metric set configuration.
2839 * Returns: zero on success or a negative error code.
2841 static int i915_oa_stream_init(struct i915_perf_stream *stream,
2842 struct drm_i915_perf_open_param *param,
2843 struct perf_open_properties *props)
2845 struct drm_i915_private *i915 = stream->perf->i915;
2846 struct i915_perf *perf = stream->perf;
2850 if (!props->engine) {
2851 DRM_DEBUG("OA engine not specified\n");
2856 * If the sysfs metrics/ directory wasn't registered for some
2857 * reason then don't let userspace try their luck with config
2860 if (!perf->metrics_kobj) {
2861 DRM_DEBUG("OA metrics weren't advertised via sysfs\n");
2865 if (!(props->sample_flags & SAMPLE_OA_REPORT) &&
2866 (GRAPHICS_VER(perf->i915) < 12 || !stream->ctx)) {
2867 DRM_DEBUG("Only OA report sampling supported\n");
2871 if (!perf->ops.enable_metric_set) {
2872 DRM_DEBUG("OA unit not supported\n");
2877 * To avoid the complexity of having to accurately filter
2878 * counter reports and marshal to the appropriate client
2879 * we currently only allow exclusive access
2881 if (perf->exclusive_stream) {
2882 DRM_DEBUG("OA unit already in use\n");
2886 if (!props->oa_format) {
2887 DRM_DEBUG("OA report format not specified\n");
2891 stream->engine = props->engine;
2892 stream->uncore = stream->engine->gt->uncore;
2894 stream->sample_size = sizeof(struct drm_i915_perf_record_header);
2896 format_size = perf->oa_formats[props->oa_format].size;
2898 stream->sample_flags = props->sample_flags;
2899 stream->sample_size += format_size;
2901 stream->oa_buffer.format_size = format_size;
2902 if (drm_WARN_ON(&i915->drm, stream->oa_buffer.format_size == 0))
2905 stream->hold_preemption = props->hold_preemption;
2907 stream->oa_buffer.format =
2908 perf->oa_formats[props->oa_format].format;
2910 stream->periodic = props->oa_periodic;
2911 if (stream->periodic)
2912 stream->period_exponent = props->oa_period_exponent;
2915 ret = oa_get_render_ctx_id(stream);
2917 DRM_DEBUG("Invalid context id to filter with\n");
2922 ret = alloc_noa_wait(stream);
2924 DRM_DEBUG("Unable to allocate NOA wait batch buffer\n");
2925 goto err_noa_wait_alloc;
2928 stream->oa_config = i915_perf_get_oa_config(perf, props->metrics_set);
2929 if (!stream->oa_config) {
2930 DRM_DEBUG("Invalid OA config id=%i\n", props->metrics_set);
2935 /* PRM - observability performance counters:
2937 * OACONTROL, performance counter enable, note:
2939 * "When this bit is set, in order to have coherent counts,
2940 * RC6 power state and trunk clock gating must be disabled.
2941 * This can be achieved by programming MMIO registers as
2942 * 0xA094=0 and 0xA090[31]=1"
2944 * In our case we are expecting that taking pm + FORCEWAKE
2945 * references will effectively disable RC6.
2947 intel_engine_pm_get(stream->engine);
2948 intel_uncore_forcewake_get(stream->uncore, FORCEWAKE_ALL);
2950 ret = alloc_oa_buffer(stream);
2952 goto err_oa_buf_alloc;
2954 stream->ops = &i915_oa_stream_ops;
2956 perf->sseu = props->sseu;
2957 WRITE_ONCE(perf->exclusive_stream, stream);
2959 ret = i915_perf_stream_enable_sync(stream);
2961 DRM_DEBUG("Unable to enable metric set\n");
2965 DRM_DEBUG("opening stream oa config uuid=%s\n",
2966 stream->oa_config->uuid);
2968 hrtimer_init(&stream->poll_check_timer,
2969 CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2970 stream->poll_check_timer.function = oa_poll_check_timer_cb;
2971 init_waitqueue_head(&stream->poll_wq);
2972 spin_lock_init(&stream->oa_buffer.ptr_lock);
2977 WRITE_ONCE(perf->exclusive_stream, NULL);
2978 perf->ops.disable_metric_set(stream);
2980 free_oa_buffer(stream);
2983 free_oa_configs(stream);
2985 intel_uncore_forcewake_put(stream->uncore, FORCEWAKE_ALL);
2986 intel_engine_pm_put(stream->engine);
2989 free_noa_wait(stream);
2993 oa_put_render_ctx_id(stream);
2998 void i915_oa_init_reg_state(const struct intel_context *ce,
2999 const struct intel_engine_cs *engine)
3001 struct i915_perf_stream *stream;
3003 if (engine->class != RENDER_CLASS)
3006 /* perf.exclusive_stream serialised by lrc_configure_all_contexts() */
3007 stream = READ_ONCE(engine->i915->perf.exclusive_stream);
3008 if (stream && GRAPHICS_VER(stream->perf->i915) < 12)
3009 gen8_update_reg_state_unlocked(ce, stream);
3013 * i915_perf_read - handles read() FOP for i915 perf stream FDs
3014 * @file: An i915 perf stream file
3015 * @buf: destination buffer given by userspace
3016 * @count: the number of bytes userspace wants to read
3017 * @ppos: (inout) file seek position (unused)
3019 * The entry point for handling a read() on a stream file descriptor from
3020 * userspace. Most of the work is left to the i915_perf_read_locked() and
3021 * &i915_perf_stream_ops->read but to save having stream implementations (of
3022 * which we might have multiple later) we handle blocking read here.
3024 * We can also consistently treat trying to read from a disabled stream
3025 * as an IO error so implementations can assume the stream is enabled
3028 * Returns: The number of bytes copied or a negative error code on failure.
3030 static ssize_t i915_perf_read(struct file *file,
3035 struct i915_perf_stream *stream = file->private_data;
3036 struct i915_perf *perf = stream->perf;
3040 /* To ensure it's handled consistently we simply treat all reads of a
3041 * disabled stream as an error. In particular it might otherwise lead
3042 * to a deadlock for blocking file descriptors...
3044 if (!stream->enabled || !(stream->sample_flags & SAMPLE_OA_REPORT))
3047 if (!(file->f_flags & O_NONBLOCK)) {
3048 /* There's the small chance of false positives from
3049 * stream->ops->wait_unlocked.
3051 * E.g. with single context filtering since we only wait until
3052 * oabuffer has >= 1 report we don't immediately know whether
3053 * any reports really belong to the current context
3056 ret = stream->ops->wait_unlocked(stream);
3060 mutex_lock(&perf->lock);
3061 ret = stream->ops->read(stream, buf, count, &offset);
3062 mutex_unlock(&perf->lock);
3063 } while (!offset && !ret);
3065 mutex_lock(&perf->lock);
3066 ret = stream->ops->read(stream, buf, count, &offset);
3067 mutex_unlock(&perf->lock);
3070 /* We allow the poll checking to sometimes report false positive EPOLLIN
3071 * events where we might actually report EAGAIN on read() if there's
3072 * not really any data available. In this situation though we don't
3073 * want to enter a busy loop between poll() reporting a EPOLLIN event
3074 * and read() returning -EAGAIN. Clearing the oa.pollin state here
3075 * effectively ensures we back off until the next hrtimer callback
3076 * before reporting another EPOLLIN event.
3077 * The exception to this is if ops->read() returned -ENOSPC which means
3078 * that more OA data is available than could fit in the user provided
3079 * buffer. In this case we want the next poll() call to not block.
3082 stream->pollin = false;
3084 /* Possible values for ret are 0, -EFAULT, -ENOSPC, -EIO, ... */
3085 return offset ?: (ret ?: -EAGAIN);
3088 static enum hrtimer_restart oa_poll_check_timer_cb(struct hrtimer *hrtimer)
3090 struct i915_perf_stream *stream =
3091 container_of(hrtimer, typeof(*stream), poll_check_timer);
3093 if (oa_buffer_check_unlocked(stream)) {
3094 stream->pollin = true;
3095 wake_up(&stream->poll_wq);
3098 hrtimer_forward_now(hrtimer,
3099 ns_to_ktime(stream->poll_oa_period));
3101 return HRTIMER_RESTART;
3105 * i915_perf_poll_locked - poll_wait() with a suitable wait queue for stream
3106 * @stream: An i915 perf stream
3107 * @file: An i915 perf stream file
3108 * @wait: poll() state table
3110 * For handling userspace polling on an i915 perf stream, this calls through to
3111 * &i915_perf_stream_ops->poll_wait to call poll_wait() with a wait queue that
3112 * will be woken for new stream data.
3114 * Note: The &perf->lock mutex has been taken to serialize
3115 * with any non-file-operation driver hooks.
3117 * Returns: any poll events that are ready without sleeping
3119 static __poll_t i915_perf_poll_locked(struct i915_perf_stream *stream,
3123 __poll_t events = 0;
3125 stream->ops->poll_wait(stream, file, wait);
3127 /* Note: we don't explicitly check whether there's something to read
3128 * here since this path may be very hot depending on what else
3129 * userspace is polling, or on the timeout in use. We rely solely on
3130 * the hrtimer/oa_poll_check_timer_cb to notify us when there are
3140 * i915_perf_poll - call poll_wait() with a suitable wait queue for stream
3141 * @file: An i915 perf stream file
3142 * @wait: poll() state table
3144 * For handling userspace polling on an i915 perf stream, this ensures
3145 * poll_wait() gets called with a wait queue that will be woken for new stream
3148 * Note: Implementation deferred to i915_perf_poll_locked()
3150 * Returns: any poll events that are ready without sleeping
3152 static __poll_t i915_perf_poll(struct file *file, poll_table *wait)
3154 struct i915_perf_stream *stream = file->private_data;
3155 struct i915_perf *perf = stream->perf;
3158 mutex_lock(&perf->lock);
3159 ret = i915_perf_poll_locked(stream, file, wait);
3160 mutex_unlock(&perf->lock);
3166 * i915_perf_enable_locked - handle `I915_PERF_IOCTL_ENABLE` ioctl
3167 * @stream: A disabled i915 perf stream
3169 * [Re]enables the associated capture of data for this stream.
3171 * If a stream was previously enabled then there's currently no intention
3172 * to provide userspace any guarantee about the preservation of previously
3175 static void i915_perf_enable_locked(struct i915_perf_stream *stream)
3177 if (stream->enabled)
3180 /* Allow stream->ops->enable() to refer to this */
3181 stream->enabled = true;
3183 if (stream->ops->enable)
3184 stream->ops->enable(stream);
3186 if (stream->hold_preemption)
3187 intel_context_set_nopreempt(stream->pinned_ctx);
3191 * i915_perf_disable_locked - handle `I915_PERF_IOCTL_DISABLE` ioctl
3192 * @stream: An enabled i915 perf stream
3194 * Disables the associated capture of data for this stream.
3196 * The intention is that disabling an re-enabling a stream will ideally be
3197 * cheaper than destroying and re-opening a stream with the same configuration,
3198 * though there are no formal guarantees about what state or buffered data
3199 * must be retained between disabling and re-enabling a stream.
3201 * Note: while a stream is disabled it's considered an error for userspace
3202 * to attempt to read from the stream (-EIO).
3204 static void i915_perf_disable_locked(struct i915_perf_stream *stream)
3206 if (!stream->enabled)
3209 /* Allow stream->ops->disable() to refer to this */
3210 stream->enabled = false;
3212 if (stream->hold_preemption)
3213 intel_context_clear_nopreempt(stream->pinned_ctx);
3215 if (stream->ops->disable)
3216 stream->ops->disable(stream);
3219 static long i915_perf_config_locked(struct i915_perf_stream *stream,
3220 unsigned long metrics_set)
3222 struct i915_oa_config *config;
3223 long ret = stream->oa_config->id;
3225 config = i915_perf_get_oa_config(stream->perf, metrics_set);
3229 if (config != stream->oa_config) {
3233 * If OA is bound to a specific context, emit the
3234 * reconfiguration inline from that context. The update
3235 * will then be ordered with respect to submission on that
3238 * When set globally, we use a low priority kernel context,
3239 * so it will effectively take effect when idle.
3241 err = emit_oa_config(stream, config, oa_context(stream), NULL);
3243 config = xchg(&stream->oa_config, config);
3248 i915_oa_config_put(config);
3254 * i915_perf_ioctl_locked - support ioctl() usage with i915 perf stream FDs
3255 * @stream: An i915 perf stream
3256 * @cmd: the ioctl request
3257 * @arg: the ioctl data
3259 * Note: The &perf->lock mutex has been taken to serialize
3260 * with any non-file-operation driver hooks.
3262 * Returns: zero on success or a negative error code. Returns -EINVAL for
3263 * an unknown ioctl request.
3265 static long i915_perf_ioctl_locked(struct i915_perf_stream *stream,
3270 case I915_PERF_IOCTL_ENABLE:
3271 i915_perf_enable_locked(stream);
3273 case I915_PERF_IOCTL_DISABLE:
3274 i915_perf_disable_locked(stream);
3276 case I915_PERF_IOCTL_CONFIG:
3277 return i915_perf_config_locked(stream, arg);
3284 * i915_perf_ioctl - support ioctl() usage with i915 perf stream FDs
3285 * @file: An i915 perf stream file
3286 * @cmd: the ioctl request
3287 * @arg: the ioctl data
3289 * Implementation deferred to i915_perf_ioctl_locked().
3291 * Returns: zero on success or a negative error code. Returns -EINVAL for
3292 * an unknown ioctl request.
3294 static long i915_perf_ioctl(struct file *file,
3298 struct i915_perf_stream *stream = file->private_data;
3299 struct i915_perf *perf = stream->perf;
3302 mutex_lock(&perf->lock);
3303 ret = i915_perf_ioctl_locked(stream, cmd, arg);
3304 mutex_unlock(&perf->lock);
3310 * i915_perf_destroy_locked - destroy an i915 perf stream
3311 * @stream: An i915 perf stream
3313 * Frees all resources associated with the given i915 perf @stream, disabling
3314 * any associated data capture in the process.
3316 * Note: The &perf->lock mutex has been taken to serialize
3317 * with any non-file-operation driver hooks.
3319 static void i915_perf_destroy_locked(struct i915_perf_stream *stream)
3321 if (stream->enabled)
3322 i915_perf_disable_locked(stream);
3324 if (stream->ops->destroy)
3325 stream->ops->destroy(stream);
3328 i915_gem_context_put(stream->ctx);
3334 * i915_perf_release - handles userspace close() of a stream file
3335 * @inode: anonymous inode associated with file
3336 * @file: An i915 perf stream file
3338 * Cleans up any resources associated with an open i915 perf stream file.
3340 * NB: close() can't really fail from the userspace point of view.
3342 * Returns: zero on success or a negative error code.
3344 static int i915_perf_release(struct inode *inode, struct file *file)
3346 struct i915_perf_stream *stream = file->private_data;
3347 struct i915_perf *perf = stream->perf;
3349 mutex_lock(&perf->lock);
3350 i915_perf_destroy_locked(stream);
3351 mutex_unlock(&perf->lock);
3353 /* Release the reference the perf stream kept on the driver. */
3354 drm_dev_put(&perf->i915->drm);
3360 static const struct file_operations fops = {
3361 .owner = THIS_MODULE,
3362 .llseek = no_llseek,
3363 .release = i915_perf_release,
3364 .poll = i915_perf_poll,
3365 .read = i915_perf_read,
3366 .unlocked_ioctl = i915_perf_ioctl,
3367 /* Our ioctl have no arguments, so it's safe to use the same function
3368 * to handle 32bits compatibility.
3370 .compat_ioctl = i915_perf_ioctl,
3375 * i915_perf_open_ioctl_locked - DRM ioctl() for userspace to open a stream FD
3376 * @perf: i915 perf instance
3377 * @param: The open parameters passed to 'DRM_I915_PERF_OPEN`
3378 * @props: individually validated u64 property value pairs
3381 * See i915_perf_ioctl_open() for interface details.
3383 * Implements further stream config validation and stream initialization on
3384 * behalf of i915_perf_open_ioctl() with the &perf->lock mutex
3385 * taken to serialize with any non-file-operation driver hooks.
3387 * Note: at this point the @props have only been validated in isolation and
3388 * it's still necessary to validate that the combination of properties makes
3391 * In the case where userspace is interested in OA unit metrics then further
3392 * config validation and stream initialization details will be handled by
3393 * i915_oa_stream_init(). The code here should only validate config state that
3394 * will be relevant to all stream types / backends.
3396 * Returns: zero on success or a negative error code.
3399 i915_perf_open_ioctl_locked(struct i915_perf *perf,
3400 struct drm_i915_perf_open_param *param,
3401 struct perf_open_properties *props,
3402 struct drm_file *file)
3404 struct i915_gem_context *specific_ctx = NULL;
3405 struct i915_perf_stream *stream = NULL;
3406 unsigned long f_flags = 0;
3407 bool privileged_op = true;
3411 if (props->single_context) {
3412 u32 ctx_handle = props->ctx_handle;
3413 struct drm_i915_file_private *file_priv = file->driver_priv;
3415 specific_ctx = i915_gem_context_lookup(file_priv, ctx_handle);
3416 if (!specific_ctx) {
3417 DRM_DEBUG("Failed to look up context with ID %u for opening perf stream\n",
3425 * On Haswell the OA unit supports clock gating off for a specific
3426 * context and in this mode there's no visibility of metrics for the
3427 * rest of the system, which we consider acceptable for a
3428 * non-privileged client.
3430 * For Gen8->11 the OA unit no longer supports clock gating off for a
3431 * specific context and the kernel can't securely stop the counters
3432 * from updating as system-wide / global values. Even though we can
3433 * filter reports based on the included context ID we can't block
3434 * clients from seeing the raw / global counter values via
3435 * MI_REPORT_PERF_COUNT commands and so consider it a privileged op to
3436 * enable the OA unit by default.
3438 * For Gen12+ we gain a new OAR unit that only monitors the RCS on a
3439 * per context basis. So we can relax requirements there if the user
3440 * doesn't request global stream access (i.e. query based sampling
3441 * using MI_RECORD_PERF_COUNT.
3443 if (IS_HASWELL(perf->i915) && specific_ctx)
3444 privileged_op = false;
3445 else if (GRAPHICS_VER(perf->i915) == 12 && specific_ctx &&
3446 (props->sample_flags & SAMPLE_OA_REPORT) == 0)
3447 privileged_op = false;
3449 if (props->hold_preemption) {
3450 if (!props->single_context) {
3451 DRM_DEBUG("preemption disable with no context\n");
3455 privileged_op = true;
3459 * Asking for SSEU configuration is a priviliged operation.
3461 if (props->has_sseu)
3462 privileged_op = true;
3464 get_default_sseu_config(&props->sseu, props->engine);
3466 /* Similar to perf's kernel.perf_paranoid_cpu sysctl option
3467 * we check a dev.i915.perf_stream_paranoid sysctl option
3468 * to determine if it's ok to access system wide OA counters
3469 * without CAP_PERFMON or CAP_SYS_ADMIN privileges.
3471 if (privileged_op &&
3472 i915_perf_stream_paranoid && !perfmon_capable()) {
3473 DRM_DEBUG("Insufficient privileges to open i915 perf stream\n");
3478 stream = kzalloc(sizeof(*stream), GFP_KERNEL);
3484 stream->perf = perf;
3485 stream->ctx = specific_ctx;
3486 stream->poll_oa_period = props->poll_oa_period;
3488 ret = i915_oa_stream_init(stream, param, props);
3492 /* we avoid simply assigning stream->sample_flags = props->sample_flags
3493 * to have _stream_init check the combination of sample flags more
3494 * thoroughly, but still this is the expected result at this point.
3496 if (WARN_ON(stream->sample_flags != props->sample_flags)) {
3501 if (param->flags & I915_PERF_FLAG_FD_CLOEXEC)
3502 f_flags |= O_CLOEXEC;
3503 if (param->flags & I915_PERF_FLAG_FD_NONBLOCK)
3504 f_flags |= O_NONBLOCK;
3506 stream_fd = anon_inode_getfd("[i915_perf]", &fops, stream, f_flags);
3507 if (stream_fd < 0) {
3512 if (!(param->flags & I915_PERF_FLAG_DISABLED))
3513 i915_perf_enable_locked(stream);
3515 /* Take a reference on the driver that will be kept with stream_fd
3516 * until its release.
3518 drm_dev_get(&perf->i915->drm);
3523 if (stream->ops->destroy)
3524 stream->ops->destroy(stream);
3529 i915_gem_context_put(specific_ctx);
3534 static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent)
3536 return intel_gt_clock_interval_to_ns(perf->i915->ggtt.vm.gt,
3540 static __always_inline bool
3541 oa_format_valid(struct i915_perf *perf, enum drm_i915_oa_format format)
3543 return test_bit(format, perf->format_mask);
3546 static __always_inline void
3547 oa_format_add(struct i915_perf *perf, enum drm_i915_oa_format format)
3549 __set_bit(format, perf->format_mask);
3553 * read_properties_unlocked - validate + copy userspace stream open properties
3554 * @perf: i915 perf instance
3555 * @uprops: The array of u64 key value pairs given by userspace
3556 * @n_props: The number of key value pairs expected in @uprops
3557 * @props: The stream configuration built up while validating properties
3559 * Note this function only validates properties in isolation it doesn't
3560 * validate that the combination of properties makes sense or that all
3561 * properties necessary for a particular kind of stream have been set.
3563 * Note that there currently aren't any ordering requirements for properties so
3564 * we shouldn't validate or assume anything about ordering here. This doesn't
3565 * rule out defining new properties with ordering requirements in the future.
3567 static int read_properties_unlocked(struct i915_perf *perf,
3570 struct perf_open_properties *props)
3572 u64 __user *uprop = uprops;
3576 memset(props, 0, sizeof(struct perf_open_properties));
3577 props->poll_oa_period = DEFAULT_POLL_PERIOD_NS;
3580 DRM_DEBUG("No i915 perf properties given\n");
3584 /* At the moment we only support using i915-perf on the RCS. */
3585 props->engine = intel_engine_lookup_user(perf->i915,
3586 I915_ENGINE_CLASS_RENDER,
3588 if (!props->engine) {
3589 DRM_DEBUG("No RENDER-capable engines\n");
3593 /* Considering that ID = 0 is reserved and assuming that we don't
3594 * (currently) expect any configurations to ever specify duplicate
3595 * values for a particular property ID then the last _PROP_MAX value is
3596 * one greater than the maximum number of properties we expect to get
3599 if (n_props >= DRM_I915_PERF_PROP_MAX) {
3600 DRM_DEBUG("More i915 perf properties specified than exist\n");
3604 for (i = 0; i < n_props; i++) {
3605 u64 oa_period, oa_freq_hz;
3608 ret = get_user(id, uprop);
3612 ret = get_user(value, uprop + 1);
3616 if (id == 0 || id >= DRM_I915_PERF_PROP_MAX) {
3617 DRM_DEBUG("Unknown i915 perf property ID\n");
3621 switch ((enum drm_i915_perf_property_id)id) {
3622 case DRM_I915_PERF_PROP_CTX_HANDLE:
3623 props->single_context = 1;
3624 props->ctx_handle = value;
3626 case DRM_I915_PERF_PROP_SAMPLE_OA:
3628 props->sample_flags |= SAMPLE_OA_REPORT;
3630 case DRM_I915_PERF_PROP_OA_METRICS_SET:
3632 DRM_DEBUG("Unknown OA metric set ID\n");
3635 props->metrics_set = value;
3637 case DRM_I915_PERF_PROP_OA_FORMAT:
3638 if (value == 0 || value >= I915_OA_FORMAT_MAX) {
3639 DRM_DEBUG("Out-of-range OA report format %llu\n",
3643 if (!oa_format_valid(perf, value)) {
3644 DRM_DEBUG("Unsupported OA report format %llu\n",
3648 props->oa_format = value;
3650 case DRM_I915_PERF_PROP_OA_EXPONENT:
3651 if (value > OA_EXPONENT_MAX) {
3652 DRM_DEBUG("OA timer exponent too high (> %u)\n",
3657 /* Theoretically we can program the OA unit to sample
3658 * e.g. every 160ns for HSW, 167ns for BDW/SKL or 104ns
3659 * for BXT. We don't allow such high sampling
3660 * frequencies by default unless root.
3663 BUILD_BUG_ON(sizeof(oa_period) != 8);
3664 oa_period = oa_exponent_to_ns(perf, value);
3666 /* This check is primarily to ensure that oa_period <=
3667 * UINT32_MAX (before passing to do_div which only
3668 * accepts a u32 denominator), but we can also skip
3669 * checking anything < 1Hz which implicitly can't be
3670 * limited via an integer oa_max_sample_rate.
3672 if (oa_period <= NSEC_PER_SEC) {
3673 u64 tmp = NSEC_PER_SEC;
3674 do_div(tmp, oa_period);
3679 if (oa_freq_hz > i915_oa_max_sample_rate && !perfmon_capable()) {
3680 DRM_DEBUG("OA exponent would exceed the max sampling frequency (sysctl dev.i915.oa_max_sample_rate) %uHz without CAP_PERFMON or CAP_SYS_ADMIN privileges\n",
3681 i915_oa_max_sample_rate);
3685 props->oa_periodic = true;
3686 props->oa_period_exponent = value;
3688 case DRM_I915_PERF_PROP_HOLD_PREEMPTION:
3689 props->hold_preemption = !!value;
3691 case DRM_I915_PERF_PROP_GLOBAL_SSEU: {
3692 struct drm_i915_gem_context_param_sseu user_sseu;
3694 if (copy_from_user(&user_sseu,
3695 u64_to_user_ptr(value),
3696 sizeof(user_sseu))) {
3697 DRM_DEBUG("Unable to copy global sseu parameter\n");
3701 ret = get_sseu_config(&props->sseu, props->engine, &user_sseu);
3703 DRM_DEBUG("Invalid SSEU configuration\n");
3706 props->has_sseu = true;
3709 case DRM_I915_PERF_PROP_POLL_OA_PERIOD:
3710 if (value < 100000 /* 100us */) {
3711 DRM_DEBUG("OA availability timer too small (%lluns < 100us)\n",
3715 props->poll_oa_period = value;
3717 case DRM_I915_PERF_PROP_MAX:
3729 * i915_perf_open_ioctl - DRM ioctl() for userspace to open a stream FD
3731 * @data: ioctl data copied from userspace (unvalidated)
3734 * Validates the stream open parameters given by userspace including flags
3735 * and an array of u64 key, value pair properties.
3737 * Very little is assumed up front about the nature of the stream being
3738 * opened (for instance we don't assume it's for periodic OA unit metrics). An
3739 * i915-perf stream is expected to be a suitable interface for other forms of
3740 * buffered data written by the GPU besides periodic OA metrics.
3742 * Note we copy the properties from userspace outside of the i915 perf
3743 * mutex to avoid an awkward lockdep with mmap_lock.
3745 * Most of the implementation details are handled by
3746 * i915_perf_open_ioctl_locked() after taking the &perf->lock
3747 * mutex for serializing with any non-file-operation driver hooks.
3749 * Return: A newly opened i915 Perf stream file descriptor or negative
3750 * error code on failure.
3752 int i915_perf_open_ioctl(struct drm_device *dev, void *data,
3753 struct drm_file *file)
3755 struct i915_perf *perf = &to_i915(dev)->perf;
3756 struct drm_i915_perf_open_param *param = data;
3757 struct perf_open_properties props;
3758 u32 known_open_flags;
3762 DRM_DEBUG("i915 perf interface not available for this system\n");
3766 known_open_flags = I915_PERF_FLAG_FD_CLOEXEC |
3767 I915_PERF_FLAG_FD_NONBLOCK |
3768 I915_PERF_FLAG_DISABLED;
3769 if (param->flags & ~known_open_flags) {
3770 DRM_DEBUG("Unknown drm_i915_perf_open_param flag\n");
3774 ret = read_properties_unlocked(perf,
3775 u64_to_user_ptr(param->properties_ptr),
3776 param->num_properties,
3781 mutex_lock(&perf->lock);
3782 ret = i915_perf_open_ioctl_locked(perf, param, &props, file);
3783 mutex_unlock(&perf->lock);
3789 * i915_perf_register - exposes i915-perf to userspace
3790 * @i915: i915 device instance
3792 * In particular OA metric sets are advertised under a sysfs metrics/
3793 * directory allowing userspace to enumerate valid IDs that can be
3794 * used to open an i915-perf stream.
3796 void i915_perf_register(struct drm_i915_private *i915)
3798 struct i915_perf *perf = &i915->perf;
3803 /* To be sure we're synchronized with an attempted
3804 * i915_perf_open_ioctl(); considering that we register after
3805 * being exposed to userspace.
3807 mutex_lock(&perf->lock);
3809 perf->metrics_kobj =
3810 kobject_create_and_add("metrics",
3811 &i915->drm.primary->kdev->kobj);
3813 mutex_unlock(&perf->lock);
3817 * i915_perf_unregister - hide i915-perf from userspace
3818 * @i915: i915 device instance
3820 * i915-perf state cleanup is split up into an 'unregister' and
3821 * 'deinit' phase where the interface is first hidden from
3822 * userspace by i915_perf_unregister() before cleaning up
3823 * remaining state in i915_perf_fini().
3825 void i915_perf_unregister(struct drm_i915_private *i915)
3827 struct i915_perf *perf = &i915->perf;
3829 if (!perf->metrics_kobj)
3832 kobject_put(perf->metrics_kobj);
3833 perf->metrics_kobj = NULL;
3836 static bool gen8_is_valid_flex_addr(struct i915_perf *perf, u32 addr)
3838 static const i915_reg_t flex_eu_regs[] = {
3849 for (i = 0; i < ARRAY_SIZE(flex_eu_regs); i++) {
3850 if (i915_mmio_reg_offset(flex_eu_regs[i]) == addr)
3856 #define ADDR_IN_RANGE(addr, start, end) \
3857 ((addr) >= (start) && \
3860 #define REG_IN_RANGE(addr, start, end) \
3861 ((addr) >= i915_mmio_reg_offset(start) && \
3862 (addr) <= i915_mmio_reg_offset(end))
3864 #define REG_EQUAL(addr, mmio) \
3865 ((addr) == i915_mmio_reg_offset(mmio))
3867 static bool gen7_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
3869 return REG_IN_RANGE(addr, OASTARTTRIG1, OASTARTTRIG8) ||
3870 REG_IN_RANGE(addr, OAREPORTTRIG1, OAREPORTTRIG8) ||
3871 REG_IN_RANGE(addr, OACEC0_0, OACEC7_1);
3874 static bool gen7_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
3876 return REG_EQUAL(addr, HALF_SLICE_CHICKEN2) ||
3877 REG_IN_RANGE(addr, MICRO_BP0_0, NOA_WRITE) ||
3878 REG_IN_RANGE(addr, OA_PERFCNT1_LO, OA_PERFCNT2_HI) ||
3879 REG_IN_RANGE(addr, OA_PERFMATRIX_LO, OA_PERFMATRIX_HI);
3882 static bool gen8_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
3884 return gen7_is_valid_mux_addr(perf, addr) ||
3885 REG_EQUAL(addr, WAIT_FOR_RC6_EXIT) ||
3886 REG_IN_RANGE(addr, RPM_CONFIG0, NOA_CONFIG(8));
3889 static bool gen11_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
3891 return gen8_is_valid_mux_addr(perf, addr) ||
3892 REG_EQUAL(addr, GEN10_NOA_WRITE_HIGH) ||
3893 REG_IN_RANGE(addr, OA_PERFCNT3_LO, OA_PERFCNT4_HI);
3896 static bool hsw_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
3898 return gen7_is_valid_mux_addr(perf, addr) ||
3899 ADDR_IN_RANGE(addr, 0x25100, 0x2FF90) ||
3900 REG_IN_RANGE(addr, HSW_MBVID2_NOA0, HSW_MBVID2_NOA9) ||
3901 REG_EQUAL(addr, HSW_MBVID2_MISR0);
3904 static bool chv_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
3906 return gen7_is_valid_mux_addr(perf, addr) ||
3907 ADDR_IN_RANGE(addr, 0x182300, 0x1823A4);
3910 static bool gen12_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
3912 return REG_IN_RANGE(addr, GEN12_OAG_OASTARTTRIG1, GEN12_OAG_OASTARTTRIG8) ||
3913 REG_IN_RANGE(addr, GEN12_OAG_OAREPORTTRIG1, GEN12_OAG_OAREPORTTRIG8) ||
3914 REG_IN_RANGE(addr, GEN12_OAG_CEC0_0, GEN12_OAG_CEC7_1) ||
3915 REG_IN_RANGE(addr, GEN12_OAG_SCEC0_0, GEN12_OAG_SCEC7_1) ||
3916 REG_EQUAL(addr, GEN12_OAA_DBG_REG) ||
3917 REG_EQUAL(addr, GEN12_OAG_OA_PESS) ||
3918 REG_EQUAL(addr, GEN12_OAG_SPCTR_CNF);
3921 static bool gen12_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
3923 return REG_EQUAL(addr, NOA_WRITE) ||
3924 REG_EQUAL(addr, GEN10_NOA_WRITE_HIGH) ||
3925 REG_EQUAL(addr, GDT_CHICKEN_BITS) ||
3926 REG_EQUAL(addr, WAIT_FOR_RC6_EXIT) ||
3927 REG_EQUAL(addr, RPM_CONFIG0) ||
3928 REG_EQUAL(addr, RPM_CONFIG1) ||
3929 REG_IN_RANGE(addr, NOA_CONFIG(0), NOA_CONFIG(8));
3932 static u32 mask_reg_value(u32 reg, u32 val)
3934 /* HALF_SLICE_CHICKEN2 is programmed with a the
3935 * WaDisableSTUnitPowerOptimization workaround. Make sure the value
3936 * programmed by userspace doesn't change this.
3938 if (REG_EQUAL(reg, HALF_SLICE_CHICKEN2))
3939 val = val & ~_MASKED_BIT_ENABLE(GEN8_ST_PO_DISABLE);
3941 /* WAIT_FOR_RC6_EXIT has only one bit fullfilling the function
3942 * indicated by its name and a bunch of selection fields used by OA
3945 if (REG_EQUAL(reg, WAIT_FOR_RC6_EXIT))
3946 val = val & ~_MASKED_BIT_ENABLE(HSW_WAIT_FOR_RC6_EXIT_ENABLE);
3951 static struct i915_oa_reg *alloc_oa_regs(struct i915_perf *perf,
3952 bool (*is_valid)(struct i915_perf *perf, u32 addr),
3956 struct i915_oa_reg *oa_regs;
3963 /* No is_valid function means we're not allowing any register to be programmed. */
3964 GEM_BUG_ON(!is_valid);
3966 return ERR_PTR(-EINVAL);
3968 oa_regs = kmalloc_array(n_regs, sizeof(*oa_regs), GFP_KERNEL);
3970 return ERR_PTR(-ENOMEM);
3972 for (i = 0; i < n_regs; i++) {
3975 err = get_user(addr, regs);
3979 if (!is_valid(perf, addr)) {
3980 DRM_DEBUG("Invalid oa_reg address: %X\n", addr);
3985 err = get_user(value, regs + 1);
3989 oa_regs[i].addr = _MMIO(addr);
3990 oa_regs[i].value = mask_reg_value(addr, value);
3999 return ERR_PTR(err);
4002 static ssize_t show_dynamic_id(struct device *dev,
4003 struct device_attribute *attr,
4006 struct i915_oa_config *oa_config =
4007 container_of(attr, typeof(*oa_config), sysfs_metric_id);
4009 return sprintf(buf, "%d\n", oa_config->id);
4012 static int create_dynamic_oa_sysfs_entry(struct i915_perf *perf,
4013 struct i915_oa_config *oa_config)
4015 sysfs_attr_init(&oa_config->sysfs_metric_id.attr);
4016 oa_config->sysfs_metric_id.attr.name = "id";
4017 oa_config->sysfs_metric_id.attr.mode = S_IRUGO;
4018 oa_config->sysfs_metric_id.show = show_dynamic_id;
4019 oa_config->sysfs_metric_id.store = NULL;
4021 oa_config->attrs[0] = &oa_config->sysfs_metric_id.attr;
4022 oa_config->attrs[1] = NULL;
4024 oa_config->sysfs_metric.name = oa_config->uuid;
4025 oa_config->sysfs_metric.attrs = oa_config->attrs;
4027 return sysfs_create_group(perf->metrics_kobj,
4028 &oa_config->sysfs_metric);
4032 * i915_perf_add_config_ioctl - DRM ioctl() for userspace to add a new OA config
4034 * @data: ioctl data (pointer to struct drm_i915_perf_oa_config) copied from
4035 * userspace (unvalidated)
4038 * Validates the submitted OA register to be saved into a new OA config that
4039 * can then be used for programming the OA unit and its NOA network.
4041 * Returns: A new allocated config number to be used with the perf open ioctl
4042 * or a negative error code on failure.
4044 int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
4045 struct drm_file *file)
4047 struct i915_perf *perf = &to_i915(dev)->perf;
4048 struct drm_i915_perf_oa_config *args = data;
4049 struct i915_oa_config *oa_config, *tmp;
4050 struct i915_oa_reg *regs;
4054 DRM_DEBUG("i915 perf interface not available for this system\n");
4058 if (!perf->metrics_kobj) {
4059 DRM_DEBUG("OA metrics weren't advertised via sysfs\n");
4063 if (i915_perf_stream_paranoid && !perfmon_capable()) {
4064 DRM_DEBUG("Insufficient privileges to add i915 OA config\n");
4068 if ((!args->mux_regs_ptr || !args->n_mux_regs) &&
4069 (!args->boolean_regs_ptr || !args->n_boolean_regs) &&
4070 (!args->flex_regs_ptr || !args->n_flex_regs)) {
4071 DRM_DEBUG("No OA registers given\n");
4075 oa_config = kzalloc(sizeof(*oa_config), GFP_KERNEL);
4077 DRM_DEBUG("Failed to allocate memory for the OA config\n");
4081 oa_config->perf = perf;
4082 kref_init(&oa_config->ref);
4084 if (!uuid_is_valid(args->uuid)) {
4085 DRM_DEBUG("Invalid uuid format for OA config\n");
4090 /* Last character in oa_config->uuid will be 0 because oa_config is
4093 memcpy(oa_config->uuid, args->uuid, sizeof(args->uuid));
4095 oa_config->mux_regs_len = args->n_mux_regs;
4096 regs = alloc_oa_regs(perf,
4097 perf->ops.is_valid_mux_reg,
4098 u64_to_user_ptr(args->mux_regs_ptr),
4102 DRM_DEBUG("Failed to create OA config for mux_regs\n");
4103 err = PTR_ERR(regs);
4106 oa_config->mux_regs = regs;
4108 oa_config->b_counter_regs_len = args->n_boolean_regs;
4109 regs = alloc_oa_regs(perf,
4110 perf->ops.is_valid_b_counter_reg,
4111 u64_to_user_ptr(args->boolean_regs_ptr),
4112 args->n_boolean_regs);
4115 DRM_DEBUG("Failed to create OA config for b_counter_regs\n");
4116 err = PTR_ERR(regs);
4119 oa_config->b_counter_regs = regs;
4121 if (GRAPHICS_VER(perf->i915) < 8) {
4122 if (args->n_flex_regs != 0) {
4127 oa_config->flex_regs_len = args->n_flex_regs;
4128 regs = alloc_oa_regs(perf,
4129 perf->ops.is_valid_flex_reg,
4130 u64_to_user_ptr(args->flex_regs_ptr),
4134 DRM_DEBUG("Failed to create OA config for flex_regs\n");
4135 err = PTR_ERR(regs);
4138 oa_config->flex_regs = regs;
4141 err = mutex_lock_interruptible(&perf->metrics_lock);
4145 /* We shouldn't have too many configs, so this iteration shouldn't be
4148 idr_for_each_entry(&perf->metrics_idr, tmp, id) {
4149 if (!strcmp(tmp->uuid, oa_config->uuid)) {
4150 DRM_DEBUG("OA config already exists with this uuid\n");
4156 err = create_dynamic_oa_sysfs_entry(perf, oa_config);
4158 DRM_DEBUG("Failed to create sysfs entry for OA config\n");
4162 /* Config id 0 is invalid, id 1 for kernel stored test config. */
4163 oa_config->id = idr_alloc(&perf->metrics_idr,
4166 if (oa_config->id < 0) {
4167 DRM_DEBUG("Failed to create sysfs entry for OA config\n");
4168 err = oa_config->id;
4172 mutex_unlock(&perf->metrics_lock);
4174 DRM_DEBUG("Added config %s id=%i\n", oa_config->uuid, oa_config->id);
4176 return oa_config->id;
4179 mutex_unlock(&perf->metrics_lock);
4181 i915_oa_config_put(oa_config);
4182 DRM_DEBUG("Failed to add new OA config\n");
4187 * i915_perf_remove_config_ioctl - DRM ioctl() for userspace to remove an OA config
4189 * @data: ioctl data (pointer to u64 integer) copied from userspace
4192 * Configs can be removed while being used, the will stop appearing in sysfs
4193 * and their content will be freed when the stream using the config is closed.
4195 * Returns: 0 on success or a negative error code on failure.
4197 int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data,
4198 struct drm_file *file)
4200 struct i915_perf *perf = &to_i915(dev)->perf;
4202 struct i915_oa_config *oa_config;
4206 DRM_DEBUG("i915 perf interface not available for this system\n");
4210 if (i915_perf_stream_paranoid && !perfmon_capable()) {
4211 DRM_DEBUG("Insufficient privileges to remove i915 OA config\n");
4215 ret = mutex_lock_interruptible(&perf->metrics_lock);
4219 oa_config = idr_find(&perf->metrics_idr, *arg);
4221 DRM_DEBUG("Failed to remove unknown OA config\n");
4226 GEM_BUG_ON(*arg != oa_config->id);
4228 sysfs_remove_group(perf->metrics_kobj, &oa_config->sysfs_metric);
4230 idr_remove(&perf->metrics_idr, *arg);
4232 mutex_unlock(&perf->metrics_lock);
4234 DRM_DEBUG("Removed config %s id=%i\n", oa_config->uuid, oa_config->id);
4236 i915_oa_config_put(oa_config);
4241 mutex_unlock(&perf->metrics_lock);
4245 static struct ctl_table oa_table[] = {
4247 .procname = "perf_stream_paranoid",
4248 .data = &i915_perf_stream_paranoid,
4249 .maxlen = sizeof(i915_perf_stream_paranoid),
4251 .proc_handler = proc_dointvec_minmax,
4252 .extra1 = SYSCTL_ZERO,
4253 .extra2 = SYSCTL_ONE,
4256 .procname = "oa_max_sample_rate",
4257 .data = &i915_oa_max_sample_rate,
4258 .maxlen = sizeof(i915_oa_max_sample_rate),
4260 .proc_handler = proc_dointvec_minmax,
4261 .extra1 = SYSCTL_ZERO,
4262 .extra2 = &oa_sample_rate_hard_limit,
4267 static struct ctl_table i915_root[] = {
4277 static struct ctl_table dev_root[] = {
4287 static void oa_init_supported_formats(struct i915_perf *perf)
4289 struct drm_i915_private *i915 = perf->i915;
4290 enum intel_platform platform = INTEL_INFO(i915)->platform;
4294 oa_format_add(perf, I915_OA_FORMAT_A13);
4295 oa_format_add(perf, I915_OA_FORMAT_A13);
4296 oa_format_add(perf, I915_OA_FORMAT_A29);
4297 oa_format_add(perf, I915_OA_FORMAT_A13_B8_C8);
4298 oa_format_add(perf, I915_OA_FORMAT_B4_C8);
4299 oa_format_add(perf, I915_OA_FORMAT_A45_B8_C8);
4300 oa_format_add(perf, I915_OA_FORMAT_B4_C8_A16);
4301 oa_format_add(perf, I915_OA_FORMAT_C4_B8);
4304 case INTEL_BROADWELL:
4305 case INTEL_CHERRYVIEW:
4308 case INTEL_KABYLAKE:
4309 case INTEL_GEMINILAKE:
4310 case INTEL_COFFEELAKE:
4311 case INTEL_COMETLAKE:
4312 case INTEL_CANNONLAKE:
4314 case INTEL_ELKHARTLAKE:
4315 case INTEL_JASPERLAKE:
4316 case INTEL_TIGERLAKE:
4317 case INTEL_ROCKETLAKE:
4319 case INTEL_ALDERLAKE_S:
4320 case INTEL_ALDERLAKE_P:
4321 oa_format_add(perf, I915_OA_FORMAT_A12);
4322 oa_format_add(perf, I915_OA_FORMAT_A12_B8_C8);
4323 oa_format_add(perf, I915_OA_FORMAT_A32u40_A4u32_B8_C8);
4324 oa_format_add(perf, I915_OA_FORMAT_C4_B8);
4328 MISSING_CASE(platform);
4333 * i915_perf_init - initialize i915-perf state on module bind
4334 * @i915: i915 device instance
4336 * Initializes i915-perf state without exposing anything to userspace.
4338 * Note: i915-perf initialization is split into an 'init' and 'register'
4339 * phase with the i915_perf_register() exposing state to userspace.
4341 void i915_perf_init(struct drm_i915_private *i915)
4343 struct i915_perf *perf = &i915->perf;
4345 /* XXX const struct i915_perf_ops! */
4347 perf->oa_formats = oa_formats;
4348 if (IS_HASWELL(i915)) {
4349 perf->ops.is_valid_b_counter_reg = gen7_is_valid_b_counter_addr;
4350 perf->ops.is_valid_mux_reg = hsw_is_valid_mux_addr;
4351 perf->ops.is_valid_flex_reg = NULL;
4352 perf->ops.enable_metric_set = hsw_enable_metric_set;
4353 perf->ops.disable_metric_set = hsw_disable_metric_set;
4354 perf->ops.oa_enable = gen7_oa_enable;
4355 perf->ops.oa_disable = gen7_oa_disable;
4356 perf->ops.read = gen7_oa_read;
4357 perf->ops.oa_hw_tail_read = gen7_oa_hw_tail_read;
4358 } else if (HAS_LOGICAL_RING_CONTEXTS(i915)) {
4359 /* Note: that although we could theoretically also support the
4360 * legacy ringbuffer mode on BDW (and earlier iterations of
4361 * this driver, before upstreaming did this) it didn't seem
4362 * worth the complexity to maintain now that BDW+ enable
4363 * execlist mode by default.
4365 perf->ops.read = gen8_oa_read;
4367 if (IS_GRAPHICS_VER(i915, 8, 9)) {
4368 perf->ops.is_valid_b_counter_reg =
4369 gen7_is_valid_b_counter_addr;
4370 perf->ops.is_valid_mux_reg =
4371 gen8_is_valid_mux_addr;
4372 perf->ops.is_valid_flex_reg =
4373 gen8_is_valid_flex_addr;
4375 if (IS_CHERRYVIEW(i915)) {
4376 perf->ops.is_valid_mux_reg =
4377 chv_is_valid_mux_addr;
4380 perf->ops.oa_enable = gen8_oa_enable;
4381 perf->ops.oa_disable = gen8_oa_disable;
4382 perf->ops.enable_metric_set = gen8_enable_metric_set;
4383 perf->ops.disable_metric_set = gen8_disable_metric_set;
4384 perf->ops.oa_hw_tail_read = gen8_oa_hw_tail_read;
4386 if (GRAPHICS_VER(i915) == 8) {
4387 perf->ctx_oactxctrl_offset = 0x120;
4388 perf->ctx_flexeu0_offset = 0x2ce;
4390 perf->gen8_valid_ctx_bit = BIT(25);
4392 perf->ctx_oactxctrl_offset = 0x128;
4393 perf->ctx_flexeu0_offset = 0x3de;
4395 perf->gen8_valid_ctx_bit = BIT(16);
4397 } else if (GRAPHICS_VER(i915) == 11) {
4398 perf->ops.is_valid_b_counter_reg =
4399 gen7_is_valid_b_counter_addr;
4400 perf->ops.is_valid_mux_reg =
4401 gen11_is_valid_mux_addr;
4402 perf->ops.is_valid_flex_reg =
4403 gen8_is_valid_flex_addr;
4405 perf->ops.oa_enable = gen8_oa_enable;
4406 perf->ops.oa_disable = gen8_oa_disable;
4407 perf->ops.enable_metric_set = gen8_enable_metric_set;
4408 perf->ops.disable_metric_set = gen11_disable_metric_set;
4409 perf->ops.oa_hw_tail_read = gen8_oa_hw_tail_read;
4411 perf->ctx_oactxctrl_offset = 0x124;
4412 perf->ctx_flexeu0_offset = 0x78e;
4414 perf->gen8_valid_ctx_bit = BIT(16);
4415 } else if (GRAPHICS_VER(i915) == 12) {
4416 perf->ops.is_valid_b_counter_reg =
4417 gen12_is_valid_b_counter_addr;
4418 perf->ops.is_valid_mux_reg =
4419 gen12_is_valid_mux_addr;
4420 perf->ops.is_valid_flex_reg =
4421 gen8_is_valid_flex_addr;
4423 perf->ops.oa_enable = gen12_oa_enable;
4424 perf->ops.oa_disable = gen12_oa_disable;
4425 perf->ops.enable_metric_set = gen12_enable_metric_set;
4426 perf->ops.disable_metric_set = gen12_disable_metric_set;
4427 perf->ops.oa_hw_tail_read = gen12_oa_hw_tail_read;
4429 perf->ctx_flexeu0_offset = 0;
4430 perf->ctx_oactxctrl_offset = 0x144;
4434 if (perf->ops.enable_metric_set) {
4435 mutex_init(&perf->lock);
4437 /* Choose a representative limit */
4438 oa_sample_rate_hard_limit = i915->gt.clock_frequency / 2;
4440 mutex_init(&perf->metrics_lock);
4441 idr_init_base(&perf->metrics_idr, 1);
4443 /* We set up some ratelimit state to potentially throttle any
4444 * _NOTES about spurious, invalid OA reports which we don't
4445 * forward to userspace.
4447 * We print a _NOTE about any throttling when closing the
4448 * stream instead of waiting until driver _fini which no one
4451 * Using the same limiting factors as printk_ratelimit()
4453 ratelimit_state_init(&perf->spurious_report_rs, 5 * HZ, 10);
4454 /* Since we use a DRM_NOTE for spurious reports it would be
4455 * inconsistent to let __ratelimit() automatically print a
4456 * warning for throttling.
4458 ratelimit_set_flags(&perf->spurious_report_rs,
4459 RATELIMIT_MSG_ON_RELEASE);
4461 ratelimit_state_init(&perf->tail_pointer_race,
4463 ratelimit_set_flags(&perf->tail_pointer_race,
4464 RATELIMIT_MSG_ON_RELEASE);
4466 atomic64_set(&perf->noa_programming_delay,
4467 500 * 1000 /* 500us */);
4471 oa_init_supported_formats(perf);
4475 static int destroy_config(int id, void *p, void *data)
4477 i915_oa_config_put(p);
4481 void i915_perf_sysctl_register(void)
4483 sysctl_header = register_sysctl_table(dev_root);
4486 void i915_perf_sysctl_unregister(void)
4488 unregister_sysctl_table(sysctl_header);
4492 * i915_perf_fini - Counter part to i915_perf_init()
4493 * @i915: i915 device instance
4495 void i915_perf_fini(struct drm_i915_private *i915)
4497 struct i915_perf *perf = &i915->perf;
4502 idr_for_each(&perf->metrics_idr, destroy_config, perf);
4503 idr_destroy(&perf->metrics_idr);
4505 memset(&perf->ops, 0, sizeof(perf->ops));
4510 * i915_perf_ioctl_version - Version of the i915-perf subsystem
4512 * This version number is used by userspace to detect available features.
4514 int i915_perf_ioctl_version(void)
4517 * 1: Initial version
4518 * I915_PERF_IOCTL_ENABLE
4519 * I915_PERF_IOCTL_DISABLE
4521 * 2: Added runtime modification of OA config.
4522 * I915_PERF_IOCTL_CONFIG
4524 * 3: Add DRM_I915_PERF_PROP_HOLD_PREEMPTION parameter to hold
4525 * preemption on a particular context so that performance data is
4526 * accessible from a delta of MI_RPC reports without looking at the
4529 * 4: Add DRM_I915_PERF_PROP_ALLOWED_SSEU to limit what contexts can
4530 * be run for the duration of the performance recording based on
4531 * their SSEU configuration.
4533 * 5: Add DRM_I915_PERF_PROP_POLL_OA_PERIOD parameter that controls the
4534 * interval for the hrtimer used to check for OA data.
4539 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
4540 #include "selftests/i915_perf.c"