2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include <linux/console.h>
26 #include <linux/vgaarb.h>
27 #include <linux/vga_switcheroo.h>
29 #include <drm/drm_drv.h>
31 #include "display/intel_fbdev.h"
34 #include "i915_globals.h"
35 #include "i915_selftest.h"
37 #define PLATFORM(x) .platform = (x)
38 #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
40 #define I845_PIPE_OFFSETS \
42 [TRANSCODER_A] = PIPE_A_OFFSET, \
45 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
48 #define I9XX_PIPE_OFFSETS \
50 [TRANSCODER_A] = PIPE_A_OFFSET, \
51 [TRANSCODER_B] = PIPE_B_OFFSET, \
54 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
55 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
58 #define IVB_PIPE_OFFSETS \
60 [TRANSCODER_A] = PIPE_A_OFFSET, \
61 [TRANSCODER_B] = PIPE_B_OFFSET, \
62 [TRANSCODER_C] = PIPE_C_OFFSET, \
65 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
66 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
67 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
70 #define HSW_PIPE_OFFSETS \
72 [TRANSCODER_A] = PIPE_A_OFFSET, \
73 [TRANSCODER_B] = PIPE_B_OFFSET, \
74 [TRANSCODER_C] = PIPE_C_OFFSET, \
75 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
78 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
79 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
80 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
81 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
84 #define CHV_PIPE_OFFSETS \
86 [TRANSCODER_A] = PIPE_A_OFFSET, \
87 [TRANSCODER_B] = PIPE_B_OFFSET, \
88 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
91 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
92 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
93 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
96 #define I845_CURSOR_OFFSETS \
98 [PIPE_A] = CURSOR_A_OFFSET, \
101 #define I9XX_CURSOR_OFFSETS \
102 .cursor_offsets = { \
103 [PIPE_A] = CURSOR_A_OFFSET, \
104 [PIPE_B] = CURSOR_B_OFFSET, \
107 #define CHV_CURSOR_OFFSETS \
108 .cursor_offsets = { \
109 [PIPE_A] = CURSOR_A_OFFSET, \
110 [PIPE_B] = CURSOR_B_OFFSET, \
111 [PIPE_C] = CHV_CURSOR_C_OFFSET, \
114 #define IVB_CURSOR_OFFSETS \
115 .cursor_offsets = { \
116 [PIPE_A] = CURSOR_A_OFFSET, \
117 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
118 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
121 #define I9XX_COLORS \
122 .color = { .gamma_lut_size = 256 }
123 #define I965_COLORS \
124 .color = { .gamma_lut_size = 129, \
125 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
128 .color = { .gamma_lut_size = 1024 }
130 .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
132 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \
133 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
134 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
137 .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024, \
138 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
139 DRM_COLOR_LUT_EQUAL_CHANNELS, \
142 /* Keep in gen based order, and chronological order within a gen */
144 #define GEN_DEFAULT_PAGE_SIZES \
145 .page_sizes = I915_GTT_PAGE_SIZE_4K
147 #define I830_FEATURES \
151 .display.has_overlay = 1, \
152 .display.cursor_needs_physical = 1, \
153 .display.overlay_needs_physical = 1, \
154 .display.has_gmch = 1, \
155 .gpu_reset_clobbers_display = true, \
156 .hws_needs_physical = 1, \
157 .unfenced_needs_alignment = 1, \
158 .engine_mask = BIT(RCS0), \
160 .has_coherent_ggtt = false, \
162 I9XX_CURSOR_OFFSETS, \
164 GEN_DEFAULT_PAGE_SIZES
166 #define I845_FEATURES \
169 .display.has_overlay = 1, \
170 .display.overlay_needs_physical = 1, \
171 .display.has_gmch = 1, \
172 .gpu_reset_clobbers_display = true, \
173 .hws_needs_physical = 1, \
174 .unfenced_needs_alignment = 1, \
175 .engine_mask = BIT(RCS0), \
177 .has_coherent_ggtt = false, \
179 I845_CURSOR_OFFSETS, \
181 GEN_DEFAULT_PAGE_SIZES
183 static const struct intel_device_info intel_i830_info = {
185 PLATFORM(INTEL_I830),
188 static const struct intel_device_info intel_i845g_info = {
190 PLATFORM(INTEL_I845G),
193 static const struct intel_device_info intel_i85x_info = {
195 PLATFORM(INTEL_I85X),
196 .display.has_fbc = 1,
199 static const struct intel_device_info intel_i865g_info = {
201 PLATFORM(INTEL_I865G),
204 #define GEN3_FEATURES \
207 .display.has_gmch = 1, \
208 .gpu_reset_clobbers_display = true, \
209 .engine_mask = BIT(RCS0), \
211 .has_coherent_ggtt = true, \
213 I9XX_CURSOR_OFFSETS, \
215 GEN_DEFAULT_PAGE_SIZES
217 static const struct intel_device_info intel_i915g_info = {
219 PLATFORM(INTEL_I915G),
220 .has_coherent_ggtt = false,
221 .display.cursor_needs_physical = 1,
222 .display.has_overlay = 1,
223 .display.overlay_needs_physical = 1,
224 .hws_needs_physical = 1,
225 .unfenced_needs_alignment = 1,
228 static const struct intel_device_info intel_i915gm_info = {
230 PLATFORM(INTEL_I915GM),
232 .display.cursor_needs_physical = 1,
233 .display.has_overlay = 1,
234 .display.overlay_needs_physical = 1,
235 .display.supports_tv = 1,
236 .display.has_fbc = 1,
237 .hws_needs_physical = 1,
238 .unfenced_needs_alignment = 1,
241 static const struct intel_device_info intel_i945g_info = {
243 PLATFORM(INTEL_I945G),
244 .display.has_hotplug = 1,
245 .display.cursor_needs_physical = 1,
246 .display.has_overlay = 1,
247 .display.overlay_needs_physical = 1,
248 .hws_needs_physical = 1,
249 .unfenced_needs_alignment = 1,
252 static const struct intel_device_info intel_i945gm_info = {
254 PLATFORM(INTEL_I945GM),
256 .display.has_hotplug = 1,
257 .display.cursor_needs_physical = 1,
258 .display.has_overlay = 1,
259 .display.overlay_needs_physical = 1,
260 .display.supports_tv = 1,
261 .display.has_fbc = 1,
262 .hws_needs_physical = 1,
263 .unfenced_needs_alignment = 1,
266 static const struct intel_device_info intel_g33_info = {
269 .display.has_hotplug = 1,
270 .display.has_overlay = 1,
273 static const struct intel_device_info intel_pineview_g_info = {
275 PLATFORM(INTEL_PINEVIEW),
276 .display.has_hotplug = 1,
277 .display.has_overlay = 1,
280 static const struct intel_device_info intel_pineview_m_info = {
282 PLATFORM(INTEL_PINEVIEW),
284 .display.has_hotplug = 1,
285 .display.has_overlay = 1,
288 #define GEN4_FEATURES \
291 .display.has_hotplug = 1, \
292 .display.has_gmch = 1, \
293 .gpu_reset_clobbers_display = true, \
294 .engine_mask = BIT(RCS0), \
296 .has_coherent_ggtt = true, \
298 I9XX_CURSOR_OFFSETS, \
300 GEN_DEFAULT_PAGE_SIZES
302 static const struct intel_device_info intel_i965g_info = {
304 PLATFORM(INTEL_I965G),
305 .display.has_overlay = 1,
306 .hws_needs_physical = 1,
310 static const struct intel_device_info intel_i965gm_info = {
312 PLATFORM(INTEL_I965GM),
314 .display.has_fbc = 1,
315 .display.has_overlay = 1,
316 .display.supports_tv = 1,
317 .hws_needs_physical = 1,
321 static const struct intel_device_info intel_g45_info = {
324 .engine_mask = BIT(RCS0) | BIT(VCS0),
325 .gpu_reset_clobbers_display = false,
328 static const struct intel_device_info intel_gm45_info = {
330 PLATFORM(INTEL_GM45),
332 .display.has_fbc = 1,
333 .display.supports_tv = 1,
334 .engine_mask = BIT(RCS0) | BIT(VCS0),
335 .gpu_reset_clobbers_display = false,
338 #define GEN5_FEATURES \
341 .display.has_hotplug = 1, \
342 .engine_mask = BIT(RCS0) | BIT(VCS0), \
344 .has_coherent_ggtt = true, \
345 /* ilk does support rc6, but we do not implement [power] contexts */ \
348 I9XX_CURSOR_OFFSETS, \
350 GEN_DEFAULT_PAGE_SIZES
352 static const struct intel_device_info intel_ironlake_d_info = {
354 PLATFORM(INTEL_IRONLAKE),
357 static const struct intel_device_info intel_ironlake_m_info = {
359 PLATFORM(INTEL_IRONLAKE),
361 .display.has_fbc = 1,
364 #define GEN6_FEATURES \
367 .display.has_hotplug = 1, \
368 .display.has_fbc = 1, \
369 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
370 .has_coherent_ggtt = true, \
375 .ppgtt_type = INTEL_PPGTT_ALIASING, \
378 I9XX_CURSOR_OFFSETS, \
380 GEN_DEFAULT_PAGE_SIZES
382 #define SNB_D_PLATFORM \
384 PLATFORM(INTEL_SANDYBRIDGE)
386 static const struct intel_device_info intel_sandybridge_d_gt1_info = {
391 static const struct intel_device_info intel_sandybridge_d_gt2_info = {
396 #define SNB_M_PLATFORM \
398 PLATFORM(INTEL_SANDYBRIDGE), \
402 static const struct intel_device_info intel_sandybridge_m_gt1_info = {
407 static const struct intel_device_info intel_sandybridge_m_gt2_info = {
412 #define GEN7_FEATURES \
415 .display.has_hotplug = 1, \
416 .display.has_fbc = 1, \
417 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
418 .has_coherent_ggtt = true, \
423 .ppgtt_type = INTEL_PPGTT_FULL, \
426 IVB_CURSOR_OFFSETS, \
428 GEN_DEFAULT_PAGE_SIZES
430 #define IVB_D_PLATFORM \
432 PLATFORM(INTEL_IVYBRIDGE), \
435 static const struct intel_device_info intel_ivybridge_d_gt1_info = {
440 static const struct intel_device_info intel_ivybridge_d_gt2_info = {
445 #define IVB_M_PLATFORM \
447 PLATFORM(INTEL_IVYBRIDGE), \
451 static const struct intel_device_info intel_ivybridge_m_gt1_info = {
456 static const struct intel_device_info intel_ivybridge_m_gt2_info = {
461 static const struct intel_device_info intel_ivybridge_q_info = {
463 PLATFORM(INTEL_IVYBRIDGE),
465 .num_pipes = 0, /* legal, last one wins */
469 static const struct intel_device_info intel_valleyview_info = {
470 PLATFORM(INTEL_VALLEYVIEW),
477 .display.has_gmch = 1,
478 .display.has_hotplug = 1,
479 .ppgtt_type = INTEL_PPGTT_FULL,
482 .has_coherent_ggtt = false,
483 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
484 .display_mmio_offset = VLV_DISPLAY_BASE,
488 GEN_DEFAULT_PAGE_SIZES,
491 #define G75_FEATURES \
493 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
494 .display.has_ddi = 1, \
496 .display.has_psr = 1, \
497 .display.has_dp_mst = 1, \
498 .has_rc6p = 0 /* RC6p removed-by HSW */, \
502 #define HSW_PLATFORM \
504 PLATFORM(INTEL_HASWELL), \
507 static const struct intel_device_info intel_haswell_gt1_info = {
512 static const struct intel_device_info intel_haswell_gt2_info = {
517 static const struct intel_device_info intel_haswell_gt3_info = {
522 #define GEN8_FEATURES \
525 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
526 I915_GTT_PAGE_SIZE_2M, \
527 .has_logical_ring_contexts = 1, \
528 .ppgtt_type = INTEL_PPGTT_FULL, \
530 .has_64bit_reloc = 1, \
531 .has_reset_engine = 1
533 #define BDW_PLATFORM \
535 PLATFORM(INTEL_BROADWELL)
537 static const struct intel_device_info intel_broadwell_gt1_info = {
542 static const struct intel_device_info intel_broadwell_gt2_info = {
547 static const struct intel_device_info intel_broadwell_rsvd_info = {
550 /* According to the device ID those devices are GT3, they were
551 * previously treated as not GT3, keep it like that.
555 static const struct intel_device_info intel_broadwell_gt3_info = {
559 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
562 static const struct intel_device_info intel_cherryview_info = {
563 PLATFORM(INTEL_CHERRYVIEW),
566 .display.has_hotplug = 1,
568 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
569 .has_64bit_reloc = 1,
573 .has_logical_ring_contexts = 1,
574 .display.has_gmch = 1,
575 .ppgtt_type = INTEL_PPGTT_FULL,
577 .has_reset_engine = 1,
579 .has_coherent_ggtt = false,
580 .display_mmio_offset = VLV_DISPLAY_BASE,
584 GEN_DEFAULT_PAGE_SIZES,
587 #define GEN9_DEFAULT_PAGE_SIZES \
588 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
589 I915_GTT_PAGE_SIZE_64K | \
590 I915_GTT_PAGE_SIZE_2M
592 #define GEN9_FEATURES \
595 GEN9_DEFAULT_PAGE_SIZES, \
596 .has_logical_ring_preemption = 1, \
597 .display.has_csr = 1, \
599 .display.has_ipc = 1, \
602 #define SKL_PLATFORM \
604 PLATFORM(INTEL_SKYLAKE)
606 static const struct intel_device_info intel_skylake_gt1_info = {
611 static const struct intel_device_info intel_skylake_gt2_info = {
616 #define SKL_GT3_PLUS_PLATFORM \
619 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
622 static const struct intel_device_info intel_skylake_gt3_info = {
623 SKL_GT3_PLUS_PLATFORM,
627 static const struct intel_device_info intel_skylake_gt4_info = {
628 SKL_GT3_PLUS_PLATFORM,
632 #define GEN9_LP_FEATURES \
635 .display.has_hotplug = 1, \
636 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
638 .has_64bit_reloc = 1, \
639 .display.has_ddi = 1, \
641 .display.has_fbc = 1, \
642 .display.has_psr = 1, \
643 .has_runtime_pm = 1, \
644 .display.has_csr = 1, \
647 .display.has_dp_mst = 1, \
648 .has_logical_ring_contexts = 1, \
649 .has_logical_ring_preemption = 1, \
651 .ppgtt_type = INTEL_PPGTT_FULL, \
653 .has_reset_engine = 1, \
655 .has_coherent_ggtt = false, \
656 .display.has_ipc = 1, \
658 IVB_CURSOR_OFFSETS, \
660 GEN9_DEFAULT_PAGE_SIZES
662 static const struct intel_device_info intel_broxton_info = {
664 PLATFORM(INTEL_BROXTON),
668 static const struct intel_device_info intel_geminilake_info = {
670 PLATFORM(INTEL_GEMINILAKE),
675 #define KBL_PLATFORM \
677 PLATFORM(INTEL_KABYLAKE)
679 static const struct intel_device_info intel_kabylake_gt1_info = {
684 static const struct intel_device_info intel_kabylake_gt2_info = {
689 static const struct intel_device_info intel_kabylake_gt3_info = {
693 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
696 #define CFL_PLATFORM \
698 PLATFORM(INTEL_COFFEELAKE)
700 static const struct intel_device_info intel_coffeelake_gt1_info = {
705 static const struct intel_device_info intel_coffeelake_gt2_info = {
710 static const struct intel_device_info intel_coffeelake_gt3_info = {
714 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
717 #define GEN10_FEATURES \
721 .has_coherent_ggtt = false, \
724 static const struct intel_device_info intel_cannonlake_info = {
726 PLATFORM(INTEL_CANNONLAKE),
730 #define GEN11_FEATURES \
733 [TRANSCODER_A] = PIPE_A_OFFSET, \
734 [TRANSCODER_B] = PIPE_B_OFFSET, \
735 [TRANSCODER_C] = PIPE_C_OFFSET, \
736 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
737 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
738 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
741 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
742 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
743 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
744 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
745 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
746 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
750 .has_logical_ring_elsq = 1, \
751 .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }
753 static const struct intel_device_info intel_icelake_11_info = {
755 PLATFORM(INTEL_ICELAKE),
757 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
760 static const struct intel_device_info intel_elkhartlake_info = {
762 PLATFORM(INTEL_ELKHARTLAKE),
763 .require_force_probe = 1,
764 .engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
768 #define GEN12_FEATURES \
772 [TRANSCODER_A] = PIPE_A_OFFSET, \
773 [TRANSCODER_B] = PIPE_B_OFFSET, \
774 [TRANSCODER_C] = PIPE_C_OFFSET, \
775 [TRANSCODER_D] = PIPE_D_OFFSET, \
776 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
777 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
780 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
781 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
782 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
783 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
784 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
785 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
788 static const struct intel_device_info intel_tigerlake_12_info = {
790 PLATFORM(INTEL_TIGERLAKE),
792 .require_force_probe = 1,
793 .display.has_modular_fia = 1,
795 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
802 * Make sure any device matches here are from most specific to most
803 * general. For example, since the Quanta match is based on the subsystem
804 * and subvendor IDs, we need it to come before the more general IVB
805 * PCI ID matches, otherwise we'll use the wrong info struct above.
807 static const struct pci_device_id pciidlist[] = {
808 INTEL_I830_IDS(&intel_i830_info),
809 INTEL_I845G_IDS(&intel_i845g_info),
810 INTEL_I85X_IDS(&intel_i85x_info),
811 INTEL_I865G_IDS(&intel_i865g_info),
812 INTEL_I915G_IDS(&intel_i915g_info),
813 INTEL_I915GM_IDS(&intel_i915gm_info),
814 INTEL_I945G_IDS(&intel_i945g_info),
815 INTEL_I945GM_IDS(&intel_i945gm_info),
816 INTEL_I965G_IDS(&intel_i965g_info),
817 INTEL_G33_IDS(&intel_g33_info),
818 INTEL_I965GM_IDS(&intel_i965gm_info),
819 INTEL_GM45_IDS(&intel_gm45_info),
820 INTEL_G45_IDS(&intel_g45_info),
821 INTEL_PINEVIEW_G_IDS(&intel_pineview_g_info),
822 INTEL_PINEVIEW_M_IDS(&intel_pineview_m_info),
823 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
824 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
825 INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info),
826 INTEL_SNB_D_GT2_IDS(&intel_sandybridge_d_gt2_info),
827 INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info),
828 INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info),
829 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
830 INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info),
831 INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info),
832 INTEL_IVB_D_GT1_IDS(&intel_ivybridge_d_gt1_info),
833 INTEL_IVB_D_GT2_IDS(&intel_ivybridge_d_gt2_info),
834 INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info),
835 INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info),
836 INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info),
837 INTEL_VLV_IDS(&intel_valleyview_info),
838 INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info),
839 INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info),
840 INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
841 INTEL_BDW_RSVD_IDS(&intel_broadwell_rsvd_info),
842 INTEL_CHV_IDS(&intel_cherryview_info),
843 INTEL_SKL_GT1_IDS(&intel_skylake_gt1_info),
844 INTEL_SKL_GT2_IDS(&intel_skylake_gt2_info),
845 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
846 INTEL_SKL_GT4_IDS(&intel_skylake_gt4_info),
847 INTEL_BXT_IDS(&intel_broxton_info),
848 INTEL_GLK_IDS(&intel_geminilake_info),
849 INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info),
850 INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info),
851 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
852 INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
853 INTEL_AML_KBL_GT2_IDS(&intel_kabylake_gt2_info),
854 INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info),
855 INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),
856 INTEL_CFL_H_GT1_IDS(&intel_coffeelake_gt1_info),
857 INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),
858 INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info),
859 INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
860 INTEL_WHL_U_GT1_IDS(&intel_coffeelake_gt1_info),
861 INTEL_WHL_U_GT2_IDS(&intel_coffeelake_gt2_info),
862 INTEL_AML_CFL_GT2_IDS(&intel_coffeelake_gt2_info),
863 INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info),
864 INTEL_CML_GT1_IDS(&intel_coffeelake_gt1_info),
865 INTEL_CML_GT2_IDS(&intel_coffeelake_gt2_info),
866 INTEL_CNL_IDS(&intel_cannonlake_info),
867 INTEL_ICL_11_IDS(&intel_icelake_11_info),
868 INTEL_EHL_IDS(&intel_elkhartlake_info),
869 INTEL_TGL_12_IDS(&intel_tigerlake_12_info),
872 MODULE_DEVICE_TABLE(pci, pciidlist);
874 static void i915_pci_remove(struct pci_dev *pdev)
876 struct drm_device *dev;
878 dev = pci_get_drvdata(pdev);
879 if (!dev) /* driver load aborted, nothing to cleanup */
882 i915_driver_remove(dev);
885 pci_set_drvdata(pdev, NULL);
888 /* is device_id present in comma separated list of ids */
889 static bool force_probe(u16 device_id, const char *devices)
894 /* FIXME: transitional */
895 if (i915_modparams.alpha_support) {
896 DRM_INFO("i915.alpha_support is deprecated, use i915.force_probe=%04x instead\n",
901 if (!devices || !*devices)
904 /* match everything */
905 if (strcmp(devices, "*") == 0)
908 s = kstrdup(devices, GFP_KERNEL);
912 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) {
915 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) {
926 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
928 struct intel_device_info *intel_info =
929 (struct intel_device_info *) ent->driver_data;
932 if (intel_info->require_force_probe &&
933 !force_probe(pdev->device, i915_modparams.force_probe)) {
934 DRM_INFO("Your graphics device %04x is not properly supported by the driver in this\n"
935 "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n"
936 "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n"
937 "or (recommended) check for kernel updates.\n",
938 pdev->device, pdev->device, pdev->device);
942 /* Only bind to function 0 of the device. Early generations
943 * used function 1 as a placeholder for multi-head. This causes
944 * us confusion instead, especially on the systems where both
945 * functions have the same PCI-ID!
947 if (PCI_FUNC(pdev->devfn))
951 * apple-gmux is needed on dual GPU MacBook Pro
952 * to probe the panel if we're the inactive GPU.
954 if (vga_switcheroo_client_probe_defer(pdev))
955 return -EPROBE_DEFER;
957 err = i915_driver_probe(pdev, ent);
961 if (i915_inject_probe_failure()) {
962 i915_pci_remove(pdev);
966 err = i915_live_selftests(pdev);
968 i915_pci_remove(pdev);
969 return err > 0 ? -ENOTTY : err;
975 static struct pci_driver i915_pci_driver = {
977 .id_table = pciidlist,
978 .probe = i915_pci_probe,
979 .remove = i915_pci_remove,
980 .driver.pm = &i915_pm_ops,
983 static int __init i915_init(void)
988 err = i915_globals_init();
992 err = i915_mock_selftests();
994 return err > 0 ? 0 : err;
997 * Enable KMS by default, unless explicitly overriden by
998 * either the i915.modeset prarameter or by the
999 * vga_text_mode_force boot option.
1002 if (i915_modparams.modeset == 0)
1005 if (vgacon_text_force() && i915_modparams.modeset == -1)
1009 /* Silently fail loading to not upset userspace. */
1010 DRM_DEBUG_DRIVER("KMS disabled.\n");
1014 return pci_register_driver(&i915_pci_driver);
1017 static void __exit i915_exit(void)
1019 if (!i915_pci_driver.driver.owner)
1022 pci_unregister_driver(&i915_pci_driver);
1023 i915_globals_exit();
1026 module_init(i915_init);
1027 module_exit(i915_exit);
1029 MODULE_AUTHOR("Tungsten Graphics, Inc.");
1030 MODULE_AUTHOR("Intel Corporation");
1032 MODULE_DESCRIPTION(DRIVER_DESC);
1033 MODULE_LICENSE("GPL and additional rights");