drivers/gpu/drm/i915/i915_pci.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <linux/vga_switcheroo.h>
  26
  27 #include <drm/drm_drv.h>
  28 #include <drm/i915_pciids.h>
  29
  30 #include "i915_drv.h"
  31 #include "i915_pci.h"
  32
  33 #define PLATFORM(x) .platform = (x)
  34 #define GEN(x) \
  35         .graphics_ver = (x), \
  36         .media_ver = (x), \
  37         .display.ver = (x)
  38
  39 #define I845_PIPE_OFFSETS \
  40         .pipe_offsets = { \
  41                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  42         }, \
  43         .trans_offsets = { \
  44                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  45         }
  46
  47 #define I9XX_PIPE_OFFSETS \
  48         .pipe_offsets = { \
  49                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  50                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  51         }, \
  52         .trans_offsets = { \
  53                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  54                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  55         }
  56
  57 #define IVB_PIPE_OFFSETS \
  58         .pipe_offsets = { \
  59                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  60                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  61                 [TRANSCODER_C] = PIPE_C_OFFSET, \
  62         }, \
  63         .trans_offsets = { \
  64                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  65                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  66                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
  67         }
  68
  69 #define HSW_PIPE_OFFSETS \
  70         .pipe_offsets = { \
  71                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  72                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  73                 [TRANSCODER_C] = PIPE_C_OFFSET, \
  74                 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
  75         }, \
  76         .trans_offsets = { \
  77                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  78                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  79                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
  80                 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
  81         }
  82
  83 #define CHV_PIPE_OFFSETS \
  84         .pipe_offsets = { \
  85                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  86                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  87                 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
  88         }, \
  89         .trans_offsets = { \
  90                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  91                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  92                 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
  93         }
  94
  95 #define I845_CURSOR_OFFSETS \
  96         .cursor_offsets = { \
  97                 [PIPE_A] = CURSOR_A_OFFSET, \
  98         }
  99
 100 #define I9XX_CURSOR_OFFSETS \
 101         .cursor_offsets = { \
 102                 [PIPE_A] = CURSOR_A_OFFSET, \
 103                 [PIPE_B] = CURSOR_B_OFFSET, \
 104         }
 105
 106 #define CHV_CURSOR_OFFSETS \
 107         .cursor_offsets = { \
 108                 [PIPE_A] = CURSOR_A_OFFSET, \
 109                 [PIPE_B] = CURSOR_B_OFFSET, \
 110                 [PIPE_C] = CHV_CURSOR_C_OFFSET, \
 111         }
 112
 113 #define IVB_CURSOR_OFFSETS \
 114         .cursor_offsets = { \
 115                 [PIPE_A] = CURSOR_A_OFFSET, \
 116                 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
 117                 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
 118         }
 119
 120 #define TGL_CURSOR_OFFSETS \
 121         .cursor_offsets = { \
 122                 [PIPE_A] = CURSOR_A_OFFSET, \
 123                 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
 124                 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
 125                 [PIPE_D] = TGL_CURSOR_D_OFFSET, \
 126         }
 127
 128 #define I9XX_COLORS \
 129         .color = { .gamma_lut_size = 256 }
 130 #define I965_COLORS \
 131         .color = { .gamma_lut_size = 129, \
 132                    .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
 133         }
 134 #define ILK_COLORS \
 135         .color = { .gamma_lut_size = 1024 }
 136 #define IVB_COLORS \
 137         .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
 138 #define CHV_COLORS \
 139         .color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \
 140                    .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
 141                    .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
 142         }
 143 #define GLK_COLORS \
 144         .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024, \
 145                    .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
 146                                         DRM_COLOR_LUT_EQUAL_CHANNELS, \
 147         }
 148
 149 /* Keep in gen based order, and chronological order within a gen */
 150
 151 #define GEN_DEFAULT_PAGE_SIZES \
 152         .page_sizes = I915_GTT_PAGE_SIZE_4K
 153
 154 #define GEN_DEFAULT_REGIONS \
 155         .memory_regions = REGION_SMEM | REGION_STOLEN_SMEM
 156
 157 #define I830_FEATURES \
 158         GEN(2), \
 159         .is_mobile = 1, \
 160         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 161         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 162         .display.has_overlay = 1, \
 163         .display.cursor_needs_physical = 1, \
 164         .display.overlay_needs_physical = 1, \
 165         .display.has_gmch = 1, \
 166         .gpu_reset_clobbers_display = true, \
 167         .hws_needs_physical = 1, \
 168         .unfenced_needs_alignment = 1, \
 169         .platform_engine_mask = BIT(RCS0), \
 170         .has_snoop = true, \
 171         .has_coherent_ggtt = false, \
 172         .dma_mask_size = 32, \
 173         I9XX_PIPE_OFFSETS, \
 174         I9XX_CURSOR_OFFSETS, \
 175         I9XX_COLORS, \
 176         GEN_DEFAULT_PAGE_SIZES, \
 177         GEN_DEFAULT_REGIONS
 178
 179 #define I845_FEATURES \
 180         GEN(2), \
 181         .pipe_mask = BIT(PIPE_A), \
 182         .cpu_transcoder_mask = BIT(TRANSCODER_A), \
 183         .display.has_overlay = 1, \
 184         .display.overlay_needs_physical = 1, \
 185         .display.has_gmch = 1, \
 186         .gpu_reset_clobbers_display = true, \
 187         .hws_needs_physical = 1, \
 188         .unfenced_needs_alignment = 1, \
 189         .platform_engine_mask = BIT(RCS0), \
 190         .has_snoop = true, \
 191         .has_coherent_ggtt = false, \
 192         .dma_mask_size = 32, \
 193         I845_PIPE_OFFSETS, \
 194         I845_CURSOR_OFFSETS, \
 195         I9XX_COLORS, \
 196         GEN_DEFAULT_PAGE_SIZES, \
 197         GEN_DEFAULT_REGIONS
 198
 199 static const struct intel_device_info i830_info = {
 200         I830_FEATURES,
 201         PLATFORM(INTEL_I830),
 202 };
 203
 204 static const struct intel_device_info i845g_info = {
 205         I845_FEATURES,
 206         PLATFORM(INTEL_I845G),
 207 };
 208
 209 static const struct intel_device_info i85x_info = {
 210         I830_FEATURES,
 211         PLATFORM(INTEL_I85X),
 212         .display.has_fbc = 1,
 213 };
 214
 215 static const struct intel_device_info i865g_info = {
 216         I845_FEATURES,
 217         PLATFORM(INTEL_I865G),
 218         .display.has_fbc = 1,
 219 };
 220
 221 #define GEN3_FEATURES \
 222         GEN(3), \
 223         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 224         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 225         .display.has_gmch = 1, \
 226         .gpu_reset_clobbers_display = true, \
 227         .platform_engine_mask = BIT(RCS0), \
 228         .has_snoop = true, \
 229         .has_coherent_ggtt = true, \
 230         .dma_mask_size = 32, \
 231         I9XX_PIPE_OFFSETS, \
 232         I9XX_CURSOR_OFFSETS, \
 233         I9XX_COLORS, \
 234         GEN_DEFAULT_PAGE_SIZES, \
 235         GEN_DEFAULT_REGIONS
 236
 237 static const struct intel_device_info i915g_info = {
 238         GEN3_FEATURES,
 239         PLATFORM(INTEL_I915G),
 240         .has_coherent_ggtt = false,
 241         .display.cursor_needs_physical = 1,
 242         .display.has_overlay = 1,
 243         .display.overlay_needs_physical = 1,
 244         .hws_needs_physical = 1,
 245         .unfenced_needs_alignment = 1,
 246 };
 247
 248 static const struct intel_device_info i915gm_info = {
 249         GEN3_FEATURES,
 250         PLATFORM(INTEL_I915GM),
 251         .is_mobile = 1,
 252         .display.cursor_needs_physical = 1,
 253         .display.has_overlay = 1,
 254         .display.overlay_needs_physical = 1,
 255         .display.supports_tv = 1,
 256         .display.has_fbc = 1,
 257         .hws_needs_physical = 1,
 258         .unfenced_needs_alignment = 1,
 259 };
 260
 261 static const struct intel_device_info i945g_info = {
 262         GEN3_FEATURES,
 263         PLATFORM(INTEL_I945G),
 264         .display.has_hotplug = 1,
 265         .display.cursor_needs_physical = 1,
 266         .display.has_overlay = 1,
 267         .display.overlay_needs_physical = 1,
 268         .hws_needs_physical = 1,
 269         .unfenced_needs_alignment = 1,
 270 };
 271
 272 static const struct intel_device_info i945gm_info = {
 273         GEN3_FEATURES,
 274         PLATFORM(INTEL_I945GM),
 275         .is_mobile = 1,
 276         .display.has_hotplug = 1,
 277         .display.cursor_needs_physical = 1,
 278         .display.has_overlay = 1,
 279         .display.overlay_needs_physical = 1,
 280         .display.supports_tv = 1,
 281         .display.has_fbc = 1,
 282         .hws_needs_physical = 1,
 283         .unfenced_needs_alignment = 1,
 284 };
 285
 286 static const struct intel_device_info g33_info = {
 287         GEN3_FEATURES,
 288         PLATFORM(INTEL_G33),
 289         .display.has_hotplug = 1,
 290         .display.has_overlay = 1,
 291         .dma_mask_size = 36,
 292 };
 293
 294 static const struct intel_device_info pnv_g_info = {
 295         GEN3_FEATURES,
 296         PLATFORM(INTEL_PINEVIEW),
 297         .display.has_hotplug = 1,
 298         .display.has_overlay = 1,
 299         .dma_mask_size = 36,
 300 };
 301
 302 static const struct intel_device_info pnv_m_info = {
 303         GEN3_FEATURES,
 304         PLATFORM(INTEL_PINEVIEW),
 305         .is_mobile = 1,
 306         .display.has_hotplug = 1,
 307         .display.has_overlay = 1,
 308         .dma_mask_size = 36,
 309 };
 310
 311 #define GEN4_FEATURES \
 312         GEN(4), \
 313         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 314         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 315         .display.has_hotplug = 1, \
 316         .display.has_gmch = 1, \
 317         .gpu_reset_clobbers_display = true, \
 318         .platform_engine_mask = BIT(RCS0), \
 319         .has_snoop = true, \
 320         .has_coherent_ggtt = true, \
 321         .dma_mask_size = 36, \
 322         I9XX_PIPE_OFFSETS, \
 323         I9XX_CURSOR_OFFSETS, \
 324         I965_COLORS, \
 325         GEN_DEFAULT_PAGE_SIZES, \
 326         GEN_DEFAULT_REGIONS
 327
 328 static const struct intel_device_info i965g_info = {
 329         GEN4_FEATURES,
 330         PLATFORM(INTEL_I965G),
 331         .display.has_overlay = 1,
 332         .hws_needs_physical = 1,
 333         .has_snoop = false,
 334 };
 335
 336 static const struct intel_device_info i965gm_info = {
 337         GEN4_FEATURES,
 338         PLATFORM(INTEL_I965GM),
 339         .is_mobile = 1,
 340         .display.has_fbc = 1,
 341         .display.has_overlay = 1,
 342         .display.supports_tv = 1,
 343         .hws_needs_physical = 1,
 344         .has_snoop = false,
 345 };
 346
 347 static const struct intel_device_info g45_info = {
 348         GEN4_FEATURES,
 349         PLATFORM(INTEL_G45),
 350         .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
 351         .gpu_reset_clobbers_display = false,
 352 };
 353
 354 static const struct intel_device_info gm45_info = {
 355         GEN4_FEATURES,
 356         PLATFORM(INTEL_GM45),
 357         .is_mobile = 1,
 358         .display.has_fbc = 1,
 359         .display.supports_tv = 1,
 360         .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
 361         .gpu_reset_clobbers_display = false,
 362 };
 363
 364 #define GEN5_FEATURES \
 365         GEN(5), \
 366         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 367         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 368         .display.has_hotplug = 1, \
 369         .platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
 370         .has_snoop = true, \
 371         .has_coherent_ggtt = true, \
 372         /* ilk does support rc6, but we do not implement [power] contexts */ \
 373         .has_rc6 = 0, \
 374         .dma_mask_size = 36, \
 375         I9XX_PIPE_OFFSETS, \
 376         I9XX_CURSOR_OFFSETS, \
 377         ILK_COLORS, \
 378         GEN_DEFAULT_PAGE_SIZES, \
 379         GEN_DEFAULT_REGIONS
 380
 381 static const struct intel_device_info ilk_d_info = {
 382         GEN5_FEATURES,
 383         PLATFORM(INTEL_IRONLAKE),
 384 };
 385
 386 static const struct intel_device_info ilk_m_info = {
 387         GEN5_FEATURES,
 388         PLATFORM(INTEL_IRONLAKE),
 389         .is_mobile = 1,
 390         .has_rps = true,
 391         .display.has_fbc = 1,
 392 };
 393
 394 #define GEN6_FEATURES \
 395         GEN(6), \
 396         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 397         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 398         .display.has_hotplug = 1, \
 399         .display.has_fbc = 1, \
 400         .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
 401         .has_coherent_ggtt = true, \
 402         .has_llc = 1, \
 403         .has_rc6 = 1, \
 404         .has_rc6p = 1, \
 405         .has_rps = true, \
 406         .dma_mask_size = 40, \
 407         .ppgtt_type = INTEL_PPGTT_ALIASING, \
 408         .ppgtt_size = 31, \
 409         I9XX_PIPE_OFFSETS, \
 410         I9XX_CURSOR_OFFSETS, \
 411         ILK_COLORS, \
 412         GEN_DEFAULT_PAGE_SIZES, \
 413         GEN_DEFAULT_REGIONS
 414
 415 #define SNB_D_PLATFORM \
 416         GEN6_FEATURES, \
 417         PLATFORM(INTEL_SANDYBRIDGE)
 418
 419 static const struct intel_device_info snb_d_gt1_info = {
 420         SNB_D_PLATFORM,
 421         .gt = 1,
 422 };
 423
 424 static const struct intel_device_info snb_d_gt2_info = {
 425         SNB_D_PLATFORM,
 426         .gt = 2,
 427 };
 428
 429 #define SNB_M_PLATFORM \
 430         GEN6_FEATURES, \
 431         PLATFORM(INTEL_SANDYBRIDGE), \
 432         .is_mobile = 1
 433
 434
 435 static const struct intel_device_info snb_m_gt1_info = {
 436         SNB_M_PLATFORM,
 437         .gt = 1,
 438 };
 439
 440 static const struct intel_device_info snb_m_gt2_info = {
 441         SNB_M_PLATFORM,
 442         .gt = 2,
 443 };
 444
 445 #define GEN7_FEATURES  \
 446         GEN(7), \
 447         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
 448         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
 449         .display.has_hotplug = 1, \
 450         .display.has_fbc = 1, \
 451         .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
 452         .has_coherent_ggtt = true, \
 453         .has_llc = 1, \
 454         .has_rc6 = 1, \
 455         .has_rc6p = 1, \
 456         .has_reset_engine = true, \
 457         .has_rps = true, \
 458         .dma_mask_size = 40, \
 459         .ppgtt_type = INTEL_PPGTT_ALIASING, \
 460         .ppgtt_size = 31, \
 461         IVB_PIPE_OFFSETS, \
 462         IVB_CURSOR_OFFSETS, \
 463         IVB_COLORS, \
 464         GEN_DEFAULT_PAGE_SIZES, \
 465         GEN_DEFAULT_REGIONS
 466
 467 #define IVB_D_PLATFORM \
 468         GEN7_FEATURES, \
 469         PLATFORM(INTEL_IVYBRIDGE), \
 470         .has_l3_dpf = 1
 471
 472 static const struct intel_device_info ivb_d_gt1_info = {
 473         IVB_D_PLATFORM,
 474         .gt = 1,
 475 };
 476
 477 static const struct intel_device_info ivb_d_gt2_info = {
 478         IVB_D_PLATFORM,
 479         .gt = 2,
 480 };
 481
 482 #define IVB_M_PLATFORM \
 483         GEN7_FEATURES, \
 484         PLATFORM(INTEL_IVYBRIDGE), \
 485         .is_mobile = 1, \
 486         .has_l3_dpf = 1
 487
 488 static const struct intel_device_info ivb_m_gt1_info = {
 489         IVB_M_PLATFORM,
 490         .gt = 1,
 491 };
 492
 493 static const struct intel_device_info ivb_m_gt2_info = {
 494         IVB_M_PLATFORM,
 495         .gt = 2,
 496 };
 497
 498 static const struct intel_device_info ivb_q_info = {
 499         GEN7_FEATURES,
 500         PLATFORM(INTEL_IVYBRIDGE),
 501         .gt = 2,
 502         .pipe_mask = 0, /* legal, last one wins */
 503         .cpu_transcoder_mask = 0,
 504         .has_l3_dpf = 1,
 505 };
 506
 507 static const struct intel_device_info vlv_info = {
 508         PLATFORM(INTEL_VALLEYVIEW),
 509         GEN(7),
 510         .is_lp = 1,
 511         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
 512         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
 513         .has_runtime_pm = 1,
 514         .has_rc6 = 1,
 515         .has_reset_engine = true,
 516         .has_rps = true,
 517         .display.has_gmch = 1,
 518         .display.has_hotplug = 1,
 519         .dma_mask_size = 40,
 520         .ppgtt_type = INTEL_PPGTT_ALIASING,
 521         .ppgtt_size = 31,
 522         .has_snoop = true,
 523         .has_coherent_ggtt = false,
 524         .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
 525         .display_mmio_offset = VLV_DISPLAY_BASE,
 526         I9XX_PIPE_OFFSETS,
 527         I9XX_CURSOR_OFFSETS,
 528         I965_COLORS,
 529         GEN_DEFAULT_PAGE_SIZES,
 530         GEN_DEFAULT_REGIONS,
 531 };
 532
 533 #define G75_FEATURES  \
 534         GEN7_FEATURES, \
 535         .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
 536         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 537                 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
 538         .display.has_ddi = 1, \
 539         .display.has_fpga_dbg = 1, \
 540         .display.has_psr = 1, \
 541         .display.has_psr_hw_tracking = 1, \
 542         .display.has_dp_mst = 1, \
 543         .has_rc6p = 0 /* RC6p removed-by HSW */, \
 544         HSW_PIPE_OFFSETS, \
 545         .has_runtime_pm = 1
 546
 547 #define HSW_PLATFORM \
 548         G75_FEATURES, \
 549         PLATFORM(INTEL_HASWELL), \
 550         .has_l3_dpf = 1
 551
 552 static const struct intel_device_info hsw_gt1_info = {
 553         HSW_PLATFORM,
 554         .gt = 1,
 555 };
 556
 557 static const struct intel_device_info hsw_gt2_info = {
 558         HSW_PLATFORM,
 559         .gt = 2,
 560 };
 561
 562 static const struct intel_device_info hsw_gt3_info = {
 563         HSW_PLATFORM,
 564         .gt = 3,
 565 };
 566
 567 #define GEN8_FEATURES \
 568         G75_FEATURES, \
 569         GEN(8), \
 570         .has_logical_ring_contexts = 1, \
 571         .dma_mask_size = 39, \
 572         .ppgtt_type = INTEL_PPGTT_FULL, \
 573         .ppgtt_size = 48, \
 574         .has_64bit_reloc = 1
 575
 576 #define BDW_PLATFORM \
 577         GEN8_FEATURES, \
 578         PLATFORM(INTEL_BROADWELL)
 579
 580 static const struct intel_device_info bdw_gt1_info = {
 581         BDW_PLATFORM,
 582         .gt = 1,
 583 };
 584
 585 static const struct intel_device_info bdw_gt2_info = {
 586         BDW_PLATFORM,
 587         .gt = 2,
 588 };
 589
 590 static const struct intel_device_info bdw_rsvd_info = {
 591         BDW_PLATFORM,
 592         .gt = 3,
 593         /* According to the device ID those devices are GT3, they were
 594          * previously treated as not GT3, keep it like that.
 595          */
 596 };
 597
 598 static const struct intel_device_info bdw_gt3_info = {
 599         BDW_PLATFORM,
 600         .gt = 3,
 601         .platform_engine_mask =
 602                 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
 603 };
 604
 605 static const struct intel_device_info chv_info = {
 606         PLATFORM(INTEL_CHERRYVIEW),
 607         GEN(8),
 608         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
 609         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
 610         .display.has_hotplug = 1,
 611         .is_lp = 1,
 612         .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
 613         .has_64bit_reloc = 1,
 614         .has_runtime_pm = 1,
 615         .has_rc6 = 1,
 616         .has_rps = true,
 617         .has_logical_ring_contexts = 1,
 618         .display.has_gmch = 1,
 619         .dma_mask_size = 39,
 620         .ppgtt_type = INTEL_PPGTT_FULL,
 621         .ppgtt_size = 32,
 622         .has_reset_engine = 1,
 623         .has_snoop = true,
 624         .has_coherent_ggtt = false,
 625         .display_mmio_offset = VLV_DISPLAY_BASE,
 626         CHV_PIPE_OFFSETS,
 627         CHV_CURSOR_OFFSETS,
 628         CHV_COLORS,
 629         GEN_DEFAULT_PAGE_SIZES,
 630         GEN_DEFAULT_REGIONS,
 631 };
 632
 633 #define GEN9_DEFAULT_PAGE_SIZES \
 634         .page_sizes = I915_GTT_PAGE_SIZE_4K | \
 635                       I915_GTT_PAGE_SIZE_64K
 636
 637 #define GEN9_FEATURES \
 638         GEN8_FEATURES, \
 639         GEN(9), \
 640         GEN9_DEFAULT_PAGE_SIZES, \
 641         .display.has_dmc = 1, \
 642         .has_gt_uc = 1, \
 643         .display.has_hdcp = 1, \
 644         .display.has_ipc = 1, \
 645         .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
 646         .dbuf.slice_mask = BIT(DBUF_S1)
 647
 648 #define SKL_PLATFORM \
 649         GEN9_FEATURES, \
 650         PLATFORM(INTEL_SKYLAKE)
 651
 652 static const struct intel_device_info skl_gt1_info = {
 653         SKL_PLATFORM,
 654         .gt = 1,
 655 };
 656
 657 static const struct intel_device_info skl_gt2_info = {
 658         SKL_PLATFORM,
 659         .gt = 2,
 660 };
 661
 662 #define SKL_GT3_PLUS_PLATFORM \
 663         SKL_PLATFORM, \
 664         .platform_engine_mask = \
 665                 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
 666
 667
 668 static const struct intel_device_info skl_gt3_info = {
 669         SKL_GT3_PLUS_PLATFORM,
 670         .gt = 3,
 671 };
 672
 673 static const struct intel_device_info skl_gt4_info = {
 674         SKL_GT3_PLUS_PLATFORM,
 675         .gt = 4,
 676 };
 677
 678 #define GEN9_LP_FEATURES \
 679         GEN(9), \
 680         .is_lp = 1, \
 681         .dbuf.slice_mask = BIT(DBUF_S1), \
 682         .display.has_hotplug = 1, \
 683         .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
 684         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
 685         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 686                 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
 687                 BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
 688         .has_64bit_reloc = 1, \
 689         .display.has_ddi = 1, \
 690         .display.has_fpga_dbg = 1, \
 691         .display.has_fbc = 1, \
 692         .display.has_hdcp = 1, \
 693         .display.has_psr = 1, \
 694         .display.has_psr_hw_tracking = 1, \
 695         .has_runtime_pm = 1, \
 696         .display.has_dmc = 1, \
 697         .has_rc6 = 1, \
 698         .has_rps = true, \
 699         .display.has_dp_mst = 1, \
 700         .has_logical_ring_contexts = 1, \
 701         .has_gt_uc = 1, \
 702         .dma_mask_size = 39, \
 703         .ppgtt_type = INTEL_PPGTT_FULL, \
 704         .ppgtt_size = 48, \
 705         .has_reset_engine = 1, \
 706         .has_snoop = true, \
 707         .has_coherent_ggtt = false, \
 708         .display.has_ipc = 1, \
 709         HSW_PIPE_OFFSETS, \
 710         IVB_CURSOR_OFFSETS, \
 711         IVB_COLORS, \
 712         GEN9_DEFAULT_PAGE_SIZES, \
 713         GEN_DEFAULT_REGIONS
 714
 715 static const struct intel_device_info bxt_info = {
 716         GEN9_LP_FEATURES,
 717         PLATFORM(INTEL_BROXTON),
 718         .dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
 719 };
 720
 721 static const struct intel_device_info glk_info = {
 722         GEN9_LP_FEATURES,
 723         PLATFORM(INTEL_GEMINILAKE),
 724         .display.ver = 10,
 725         .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
 726         GLK_COLORS,
 727 };
 728
 729 #define KBL_PLATFORM \
 730         GEN9_FEATURES, \
 731         PLATFORM(INTEL_KABYLAKE)
 732
 733 static const struct intel_device_info kbl_gt1_info = {
 734         KBL_PLATFORM,
 735         .gt = 1,
 736 };
 737
 738 static const struct intel_device_info kbl_gt2_info = {
 739         KBL_PLATFORM,
 740         .gt = 2,
 741 };
 742
 743 static const struct intel_device_info kbl_gt3_info = {
 744         KBL_PLATFORM,
 745         .gt = 3,
 746         .platform_engine_mask =
 747                 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
 748 };
 749
 750 #define CFL_PLATFORM \
 751         GEN9_FEATURES, \
 752         PLATFORM(INTEL_COFFEELAKE)
 753
 754 static const struct intel_device_info cfl_gt1_info = {
 755         CFL_PLATFORM,
 756         .gt = 1,
 757 };
 758
 759 static const struct intel_device_info cfl_gt2_info = {
 760         CFL_PLATFORM,
 761         .gt = 2,
 762 };
 763
 764 static const struct intel_device_info cfl_gt3_info = {
 765         CFL_PLATFORM,
 766         .gt = 3,
 767         .platform_engine_mask =
 768                 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
 769 };
 770
 771 #define CML_PLATFORM \
 772         GEN9_FEATURES, \
 773         PLATFORM(INTEL_COMETLAKE)
 774
 775 static const struct intel_device_info cml_gt1_info = {
 776         CML_PLATFORM,
 777         .gt = 1,
 778 };
 779
 780 static const struct intel_device_info cml_gt2_info = {
 781         CML_PLATFORM,
 782         .gt = 2,
 783 };
 784
 785 #define GEN11_DEFAULT_PAGE_SIZES \
 786         .page_sizes = I915_GTT_PAGE_SIZE_4K | \
 787                       I915_GTT_PAGE_SIZE_64K | \
 788                       I915_GTT_PAGE_SIZE_2M
 789
 790 #define GEN11_FEATURES \
 791         GEN9_FEATURES, \
 792         GEN11_DEFAULT_PAGE_SIZES, \
 793         .abox_mask = BIT(0), \
 794         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 795                 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
 796                 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
 797         .pipe_offsets = { \
 798                 [TRANSCODER_A] = PIPE_A_OFFSET, \
 799                 [TRANSCODER_B] = PIPE_B_OFFSET, \
 800                 [TRANSCODER_C] = PIPE_C_OFFSET, \
 801                 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
 802                 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
 803                 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
 804         }, \
 805         .trans_offsets = { \
 806                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
 807                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
 808                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
 809                 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
 810                 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
 811                 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
 812         }, \
 813         GEN(11), \
 814         .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }, \
 815         .dbuf.size = 2048, \
 816         .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
 817         .display.has_dsc = 1, \
 818         .has_coherent_ggtt = false, \
 819         .has_logical_ring_elsq = 1
 820
 821 static const struct intel_device_info icl_info = {
 822         GEN11_FEATURES,
 823         PLATFORM(INTEL_ICELAKE),
 824         .platform_engine_mask =
 825                 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
 826 };
 827
 828 static const struct intel_device_info ehl_info = {
 829         GEN11_FEATURES,
 830         PLATFORM(INTEL_ELKHARTLAKE),
 831         .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
 832         .ppgtt_size = 36,
 833 };
 834
 835 static const struct intel_device_info jsl_info = {
 836         GEN11_FEATURES,
 837         PLATFORM(INTEL_JASPERLAKE),
 838         .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
 839         .ppgtt_size = 36,
 840 };
 841
 842 #define GEN12_FEATURES \
 843         GEN11_FEATURES, \
 844         GEN(12), \
 845         .abox_mask = GENMASK(2, 1), \
 846         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
 847         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 848                 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
 849                 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
 850         .pipe_offsets = { \
 851                 [TRANSCODER_A] = PIPE_A_OFFSET, \
 852                 [TRANSCODER_B] = PIPE_B_OFFSET, \
 853                 [TRANSCODER_C] = PIPE_C_OFFSET, \
 854                 [TRANSCODER_D] = PIPE_D_OFFSET, \
 855                 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
 856                 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
 857         }, \
 858         .trans_offsets = { \
 859                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
 860                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
 861                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
 862                 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
 863                 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
 864                 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
 865         }, \
 866         TGL_CURSOR_OFFSETS, \
 867         .has_global_mocs = 1, \
 868         .display.has_dsb = 1
 869
 870 static const struct intel_device_info tgl_info = {
 871         GEN12_FEATURES,
 872         PLATFORM(INTEL_TIGERLAKE),
 873         .display.has_modular_fia = 1,
 874         .platform_engine_mask =
 875                 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
 876 };
 877
 878 static const struct intel_device_info rkl_info = {
 879         GEN12_FEATURES,
 880         PLATFORM(INTEL_ROCKETLAKE),
 881         .abox_mask = BIT(0),
 882         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
 883         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
 884                 BIT(TRANSCODER_C),
 885         .display.has_hti = 1,
 886         .display.has_psr_hw_tracking = 0,
 887         .platform_engine_mask =
 888                 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
 889 };
 890
 891 #define DGFX_FEATURES \
 892         .memory_regions = REGION_SMEM | REGION_LMEM | REGION_STOLEN_LMEM, \
 893         .has_llc = 0, \
 894         .has_snoop = 1, \
 895         .is_dgfx = 1
 896
 897 static const struct intel_device_info dg1_info __maybe_unused = {
 898         GEN12_FEATURES,
 899         DGFX_FEATURES,
 900         .graphics_rel = 10,
 901         PLATFORM(INTEL_DG1),
 902         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
 903         .require_force_probe = 1,
 904         .platform_engine_mask =
 905                 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
 906                 BIT(VCS0) | BIT(VCS2),
 907         /* Wa_16011227922 */
 908         .ppgtt_size = 47,
 909 };
 910
 911 static const struct intel_device_info adl_s_info = {
 912         GEN12_FEATURES,
 913         PLATFORM(INTEL_ALDERLAKE_S),
 914         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
 915         .require_force_probe = 1,
 916         .display.has_hti = 1,
 917         .display.has_psr_hw_tracking = 0,
 918         .platform_engine_mask =
 919                 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
 920         .dma_mask_size = 39,
 921 };
 922
 923 #define XE_LPD_CURSOR_OFFSETS \
 924         .cursor_offsets = { \
 925                 [PIPE_A] = CURSOR_A_OFFSET, \
 926                 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
 927                 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
 928                 [PIPE_D] = TGL_CURSOR_D_OFFSET, \
 929         }
 930
 931 #define XE_LPD_FEATURES \
 932         .abox_mask = GENMASK(1, 0),                                             \
 933         .color = { .degamma_lut_size = 0, .gamma_lut_size = 0 },                \
 934         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |          \
 935                 BIT(TRANSCODER_C) | BIT(TRANSCODER_D),                          \
 936         .dbuf.size = 4096,                                                      \
 937         .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |         \
 938                 BIT(DBUF_S4),                                                   \
 939         .display.has_ddi = 1,                                                   \
 940         .display.has_dmc = 1,                                                   \
 941         .display.has_dp_mst = 1,                                                \
 942         .display.has_dsb = 1,                                                   \
 943         .display.has_dsc = 1,                                                   \
 944         .display.has_fbc = 1,                                                   \
 945         .display.has_fpga_dbg = 1,                                              \
 946         .display.has_hdcp = 1,                                                  \
 947         .display.has_hotplug = 1,                                               \
 948         .display.has_ipc = 1,                                                   \
 949         .display.has_psr = 1,                                                   \
 950         .display.ver = 13,                                                      \
 951         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),     \
 952         .pipe_offsets = {                                                       \
 953                 [TRANSCODER_A] = PIPE_A_OFFSET,                                 \
 954                 [TRANSCODER_B] = PIPE_B_OFFSET,                                 \
 955                 [TRANSCODER_C] = PIPE_C_OFFSET,                                 \
 956                 [TRANSCODER_D] = PIPE_D_OFFSET,                                 \
 957         },                                                                      \
 958         .trans_offsets = {                                                      \
 959                 [TRANSCODER_A] = TRANSCODER_A_OFFSET,                           \
 960                 [TRANSCODER_B] = TRANSCODER_B_OFFSET,                           \
 961                 [TRANSCODER_C] = TRANSCODER_C_OFFSET,                           \
 962                 [TRANSCODER_D] = TRANSCODER_D_OFFSET,                           \
 963         },                                                                      \
 964         XE_LPD_CURSOR_OFFSETS
 965
 966 static const struct intel_device_info adl_p_info = {
 967         GEN12_FEATURES,
 968         XE_LPD_FEATURES,
 969         PLATFORM(INTEL_ALDERLAKE_P),
 970         .require_force_probe = 1,
 971         .display.has_cdclk_crawl = 1,
 972         .display.has_modular_fia = 1,
 973         .display.has_psr_hw_tracking = 0,
 974         .platform_engine_mask =
 975                 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
 976         .ppgtt_size = 48,
 977         .dma_mask_size = 39,
 978 };
 979
 980 #undef GEN
 981
 982 #define XE_HP_PAGE_SIZES \
 983         .page_sizes = I915_GTT_PAGE_SIZE_4K | \
 984                       I915_GTT_PAGE_SIZE_64K | \
 985                       I915_GTT_PAGE_SIZE_2M
 986
 987 #define XE_HP_FEATURES \
 988         .graphics_ver = 12, \
 989         .graphics_rel = 50, \
 990         XE_HP_PAGE_SIZES, \
 991         .dma_mask_size = 46, \
 992         .has_64bit_reloc = 1, \
 993         .has_global_mocs = 1, \
 994         .has_gt_uc = 1, \
 995         .has_llc = 1, \
 996         .has_logical_ring_contexts = 1, \
 997         .has_logical_ring_elsq = 1, \
 998         .has_mslices = 1, \
 999         .has_rc6 = 1, \
1000         .has_reset_engine = 1, \
1001         .has_rps = 1, \
1002         .has_runtime_pm = 1, \
1003         .ppgtt_size = 48, \
1004         .ppgtt_type = INTEL_PPGTT_FULL
1005
1006 #define XE_HPM_FEATURES \
1007         .media_ver = 12, \
1008         .media_rel = 50
1009
1010 __maybe_unused
1011 static const struct intel_device_info xehpsdv_info = {
1012         XE_HP_FEATURES,
1013         XE_HPM_FEATURES,
1014         DGFX_FEATURES,
1015         PLATFORM(INTEL_XEHPSDV),
1016         .display = { },
1017         .pipe_mask = 0,
1018         .platform_engine_mask =
1019                 BIT(RCS0) | BIT(BCS0) |
1020                 BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) |
1021                 BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) |
1022                 BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7),
1023         .require_force_probe = 1,
1024 };
1025
1026 __maybe_unused
1027 static const struct intel_device_info dg2_info = {
1028         XE_HP_FEATURES,
1029         XE_HPM_FEATURES,
1030         XE_LPD_FEATURES,
1031         DGFX_FEATURES,
1032         .graphics_rel = 55,
1033         .media_rel = 55,
1034         PLATFORM(INTEL_DG2),
1035         .platform_engine_mask =
1036                 BIT(RCS0) | BIT(BCS0) |
1037                 BIT(VECS0) | BIT(VECS1) |
1038                 BIT(VCS0) | BIT(VCS2),
1039         .require_force_probe = 1,
1040 };
1041
1042 #undef PLATFORM
1043
1044 /*
1045  * Make sure any device matches here are from most specific to most
1046  * general.  For example, since the Quanta match is based on the subsystem
1047  * and subvendor IDs, we need it to come before the more general IVB
1048  * PCI ID matches, otherwise we'll use the wrong info struct above.
1049  */
1050 static const struct pci_device_id pciidlist[] = {
1051         INTEL_I830_IDS(&i830_info),
1052         INTEL_I845G_IDS(&i845g_info),
1053         INTEL_I85X_IDS(&i85x_info),
1054         INTEL_I865G_IDS(&i865g_info),
1055         INTEL_I915G_IDS(&i915g_info),
1056         INTEL_I915GM_IDS(&i915gm_info),
1057         INTEL_I945G_IDS(&i945g_info),
1058         INTEL_I945GM_IDS(&i945gm_info),
1059         INTEL_I965G_IDS(&i965g_info),
1060         INTEL_G33_IDS(&g33_info),
1061         INTEL_I965GM_IDS(&i965gm_info),
1062         INTEL_GM45_IDS(&gm45_info),
1063         INTEL_G45_IDS(&g45_info),
1064         INTEL_PINEVIEW_G_IDS(&pnv_g_info),
1065         INTEL_PINEVIEW_M_IDS(&pnv_m_info),
1066         INTEL_IRONLAKE_D_IDS(&ilk_d_info),
1067         INTEL_IRONLAKE_M_IDS(&ilk_m_info),
1068         INTEL_SNB_D_GT1_IDS(&snb_d_gt1_info),
1069         INTEL_SNB_D_GT2_IDS(&snb_d_gt2_info),
1070         INTEL_SNB_M_GT1_IDS(&snb_m_gt1_info),
1071         INTEL_SNB_M_GT2_IDS(&snb_m_gt2_info),
1072         INTEL_IVB_Q_IDS(&ivb_q_info), /* must be first IVB */
1073         INTEL_IVB_M_GT1_IDS(&ivb_m_gt1_info),
1074         INTEL_IVB_M_GT2_IDS(&ivb_m_gt2_info),
1075         INTEL_IVB_D_GT1_IDS(&ivb_d_gt1_info),
1076         INTEL_IVB_D_GT2_IDS(&ivb_d_gt2_info),
1077         INTEL_HSW_GT1_IDS(&hsw_gt1_info),
1078         INTEL_HSW_GT2_IDS(&hsw_gt2_info),
1079         INTEL_HSW_GT3_IDS(&hsw_gt3_info),
1080         INTEL_VLV_IDS(&vlv_info),
1081         INTEL_BDW_GT1_IDS(&bdw_gt1_info),
1082         INTEL_BDW_GT2_IDS(&bdw_gt2_info),
1083         INTEL_BDW_GT3_IDS(&bdw_gt3_info),
1084         INTEL_BDW_RSVD_IDS(&bdw_rsvd_info),
1085         INTEL_CHV_IDS(&chv_info),
1086         INTEL_SKL_GT1_IDS(&skl_gt1_info),
1087         INTEL_SKL_GT2_IDS(&skl_gt2_info),
1088         INTEL_SKL_GT3_IDS(&skl_gt3_info),
1089         INTEL_SKL_GT4_IDS(&skl_gt4_info),
1090         INTEL_BXT_IDS(&bxt_info),
1091         INTEL_GLK_IDS(&glk_info),
1092         INTEL_KBL_GT1_IDS(&kbl_gt1_info),
1093         INTEL_KBL_GT2_IDS(&kbl_gt2_info),
1094         INTEL_KBL_GT3_IDS(&kbl_gt3_info),
1095         INTEL_KBL_GT4_IDS(&kbl_gt3_info),
1096         INTEL_AML_KBL_GT2_IDS(&kbl_gt2_info),
1097         INTEL_CFL_S_GT1_IDS(&cfl_gt1_info),
1098         INTEL_CFL_S_GT2_IDS(&cfl_gt2_info),
1099         INTEL_CFL_H_GT1_IDS(&cfl_gt1_info),
1100         INTEL_CFL_H_GT2_IDS(&cfl_gt2_info),
1101         INTEL_CFL_U_GT2_IDS(&cfl_gt2_info),
1102         INTEL_CFL_U_GT3_IDS(&cfl_gt3_info),
1103         INTEL_WHL_U_GT1_IDS(&cfl_gt1_info),
1104         INTEL_WHL_U_GT2_IDS(&cfl_gt2_info),
1105         INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info),
1106         INTEL_WHL_U_GT3_IDS(&cfl_gt3_info),
1107         INTEL_CML_GT1_IDS(&cml_gt1_info),
1108         INTEL_CML_GT2_IDS(&cml_gt2_info),
1109         INTEL_CML_U_GT1_IDS(&cml_gt1_info),
1110         INTEL_CML_U_GT2_IDS(&cml_gt2_info),
1111         INTEL_ICL_11_IDS(&icl_info),
1112         INTEL_EHL_IDS(&ehl_info),
1113         INTEL_JSL_IDS(&jsl_info),
1114         INTEL_TGL_12_IDS(&tgl_info),
1115         INTEL_RKL_IDS(&rkl_info),
1116         INTEL_ADLS_IDS(&adl_s_info),
1117         INTEL_ADLP_IDS(&adl_p_info),
1118         {0, 0, 0}
1119 };
1120 MODULE_DEVICE_TABLE(pci, pciidlist);
1121
1122 static void i915_pci_remove(struct pci_dev *pdev)
1123 {
1124         struct drm_i915_private *i915;
1125
1126         i915 = pci_get_drvdata(pdev);
1127         if (!i915) /* driver load aborted, nothing to cleanup */
1128                 return;
1129
1130         i915_driver_remove(i915);
1131         pci_set_drvdata(pdev, NULL);
1132 }
1133
1134 /* is device_id present in comma separated list of ids */
1135 static bool force_probe(u16 device_id, const char *devices)
1136 {
1137         char *s, *p, *tok;
1138         bool ret;
1139
1140         if (!devices || !*devices)
1141                 return false;
1142
1143         /* match everything */
1144         if (strcmp(devices, "*") == 0)
1145                 return true;
1146
1147         s = kstrdup(devices, GFP_KERNEL);
1148         if (!s)
1149                 return false;
1150
1151         for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) {
1152                 u16 val;
1153
1154                 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) {
1155                         ret = true;
1156                         break;
1157                 }
1158         }
1159
1160         kfree(s);
1161
1162         return ret;
1163 }
1164
1165 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1166 {
1167         struct intel_device_info *intel_info =
1168                 (struct intel_device_info *) ent->driver_data;
1169         int err;
1170
1171         if (intel_info->require_force_probe &&
1172             !force_probe(pdev->device, i915_modparams.force_probe)) {
1173                 dev_info(&pdev->dev,
1174                          "Your graphics device %04x is not properly supported by the driver in this\n"
1175                          "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n"
1176                          "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n"
1177                          "or (recommended) check for kernel updates.\n",
1178                          pdev->device, pdev->device, pdev->device);
1179                 return -ENODEV;
1180         }
1181
1182         /* Only bind to function 0 of the device. Early generations
1183          * used function 1 as a placeholder for multi-head. This causes
1184          * us confusion instead, especially on the systems where both
1185          * functions have the same PCI-ID!
1186          */
1187         if (PCI_FUNC(pdev->devfn))
1188                 return -ENODEV;
1189
1190         /*
1191          * apple-gmux is needed on dual GPU MacBook Pro
1192          * to probe the panel if we're the inactive GPU.
1193          */
1194         if (vga_switcheroo_client_probe_defer(pdev))
1195                 return -EPROBE_DEFER;
1196
1197         err = i915_driver_probe(pdev, ent);
1198         if (err)
1199                 return err;
1200
1201         if (i915_inject_probe_failure(pci_get_drvdata(pdev))) {
1202                 i915_pci_remove(pdev);
1203                 return -ENODEV;
1204         }
1205
1206         err = i915_live_selftests(pdev);
1207         if (err) {
1208                 i915_pci_remove(pdev);
1209                 return err > 0 ? -ENOTTY : err;
1210         }
1211
1212         err = i915_perf_selftests(pdev);
1213         if (err) {
1214                 i915_pci_remove(pdev);
1215                 return err > 0 ? -ENOTTY : err;
1216         }
1217
1218         return 0;
1219 }
1220
1221 static void i915_pci_shutdown(struct pci_dev *pdev)
1222 {
1223         struct drm_i915_private *i915 = pci_get_drvdata(pdev);
1224
1225         i915_driver_shutdown(i915);
1226 }
1227
1228 static struct pci_driver i915_pci_driver = {
1229         .name = DRIVER_NAME,
1230         .id_table = pciidlist,
1231         .probe = i915_pci_probe,
1232         .remove = i915_pci_remove,
1233         .shutdown = i915_pci_shutdown,
1234         .driver.pm = &i915_pm_ops,
1235 };
1236
1237 int i915_register_pci_driver(void)
1238 {
1239         return pci_register_driver(&i915_pci_driver);
1240 }
1241
1242 void i915_unregister_pci_driver(void)
1243 {
1244         pci_unregister_driver(&i915_pci_driver);
1245 }