2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include <linux/console.h>
26 #include <linux/vgaarb.h>
27 #include <linux/vga_switcheroo.h>
29 #include <drm/drm_drv.h>
32 #include "i915_globals.h"
33 #include "i915_selftest.h"
35 #define PLATFORM(x) .platform = (x), .platform_mask = BIT(x)
36 #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
38 #define I845_PIPE_OFFSETS \
40 [TRANSCODER_A] = PIPE_A_OFFSET, \
43 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
46 #define I9XX_PIPE_OFFSETS \
48 [TRANSCODER_A] = PIPE_A_OFFSET, \
49 [TRANSCODER_B] = PIPE_B_OFFSET, \
52 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
53 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
56 #define IVB_PIPE_OFFSETS \
58 [TRANSCODER_A] = PIPE_A_OFFSET, \
59 [TRANSCODER_B] = PIPE_B_OFFSET, \
60 [TRANSCODER_C] = PIPE_C_OFFSET, \
63 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
64 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
65 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
68 #define HSW_PIPE_OFFSETS \
70 [TRANSCODER_A] = PIPE_A_OFFSET, \
71 [TRANSCODER_B] = PIPE_B_OFFSET, \
72 [TRANSCODER_C] = PIPE_C_OFFSET, \
73 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
76 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
77 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
78 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
79 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
82 #define CHV_PIPE_OFFSETS \
84 [TRANSCODER_A] = PIPE_A_OFFSET, \
85 [TRANSCODER_B] = PIPE_B_OFFSET, \
86 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
89 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
90 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
91 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
94 #define I845_CURSOR_OFFSETS \
96 [PIPE_A] = CURSOR_A_OFFSET, \
99 #define I9XX_CURSOR_OFFSETS \
100 .cursor_offsets = { \
101 [PIPE_A] = CURSOR_A_OFFSET, \
102 [PIPE_B] = CURSOR_B_OFFSET, \
105 #define CHV_CURSOR_OFFSETS \
106 .cursor_offsets = { \
107 [PIPE_A] = CURSOR_A_OFFSET, \
108 [PIPE_B] = CURSOR_B_OFFSET, \
109 [PIPE_C] = CHV_CURSOR_C_OFFSET, \
112 #define IVB_CURSOR_OFFSETS \
113 .cursor_offsets = { \
114 [PIPE_A] = CURSOR_A_OFFSET, \
115 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
116 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
120 .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
122 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \
123 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
124 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
127 .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024, \
128 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
129 DRM_COLOR_LUT_EQUAL_CHANNELS, \
132 /* Keep in gen based order, and chronological order within a gen */
134 #define GEN_DEFAULT_PAGE_SIZES \
135 .page_sizes = I915_GTT_PAGE_SIZE_4K
137 #define I830_FEATURES \
141 .display.has_overlay = 1, \
142 .display.cursor_needs_physical = 1, \
143 .display.overlay_needs_physical = 1, \
144 .display.has_gmch = 1, \
145 .gpu_reset_clobbers_display = true, \
146 .hws_needs_physical = 1, \
147 .unfenced_needs_alignment = 1, \
148 .engine_mask = BIT(RCS0), \
150 .has_coherent_ggtt = false, \
152 I9XX_CURSOR_OFFSETS, \
153 GEN_DEFAULT_PAGE_SIZES
155 #define I845_FEATURES \
158 .display.has_overlay = 1, \
159 .display.overlay_needs_physical = 1, \
160 .display.has_gmch = 1, \
161 .gpu_reset_clobbers_display = true, \
162 .hws_needs_physical = 1, \
163 .unfenced_needs_alignment = 1, \
164 .engine_mask = BIT(RCS0), \
166 .has_coherent_ggtt = false, \
168 I845_CURSOR_OFFSETS, \
169 GEN_DEFAULT_PAGE_SIZES
171 static const struct intel_device_info intel_i830_info = {
173 PLATFORM(INTEL_I830),
176 static const struct intel_device_info intel_i845g_info = {
178 PLATFORM(INTEL_I845G),
181 static const struct intel_device_info intel_i85x_info = {
183 PLATFORM(INTEL_I85X),
184 .display.has_fbc = 1,
187 static const struct intel_device_info intel_i865g_info = {
189 PLATFORM(INTEL_I865G),
192 #define GEN3_FEATURES \
195 .display.has_gmch = 1, \
196 .gpu_reset_clobbers_display = true, \
197 .engine_mask = BIT(RCS0), \
199 .has_coherent_ggtt = true, \
201 I9XX_CURSOR_OFFSETS, \
202 GEN_DEFAULT_PAGE_SIZES
204 static const struct intel_device_info intel_i915g_info = {
206 PLATFORM(INTEL_I915G),
207 .has_coherent_ggtt = false,
208 .display.cursor_needs_physical = 1,
209 .display.has_overlay = 1,
210 .display.overlay_needs_physical = 1,
211 .hws_needs_physical = 1,
212 .unfenced_needs_alignment = 1,
215 static const struct intel_device_info intel_i915gm_info = {
217 PLATFORM(INTEL_I915GM),
219 .display.cursor_needs_physical = 1,
220 .display.has_overlay = 1,
221 .display.overlay_needs_physical = 1,
222 .display.supports_tv = 1,
223 .display.has_fbc = 1,
224 .hws_needs_physical = 1,
225 .unfenced_needs_alignment = 1,
228 static const struct intel_device_info intel_i945g_info = {
230 PLATFORM(INTEL_I945G),
231 .display.has_hotplug = 1,
232 .display.cursor_needs_physical = 1,
233 .display.has_overlay = 1,
234 .display.overlay_needs_physical = 1,
235 .hws_needs_physical = 1,
236 .unfenced_needs_alignment = 1,
239 static const struct intel_device_info intel_i945gm_info = {
241 PLATFORM(INTEL_I945GM),
243 .display.has_hotplug = 1,
244 .display.cursor_needs_physical = 1,
245 .display.has_overlay = 1,
246 .display.overlay_needs_physical = 1,
247 .display.supports_tv = 1,
248 .display.has_fbc = 1,
249 .hws_needs_physical = 1,
250 .unfenced_needs_alignment = 1,
253 static const struct intel_device_info intel_g33_info = {
256 .display.has_hotplug = 1,
257 .display.has_overlay = 1,
260 static const struct intel_device_info intel_pineview_info = {
262 PLATFORM(INTEL_PINEVIEW),
264 .display.has_hotplug = 1,
265 .display.has_overlay = 1,
268 #define GEN4_FEATURES \
271 .display.has_hotplug = 1, \
272 .display.has_gmch = 1, \
273 .gpu_reset_clobbers_display = true, \
274 .engine_mask = BIT(RCS0), \
276 .has_coherent_ggtt = true, \
278 I9XX_CURSOR_OFFSETS, \
279 GEN_DEFAULT_PAGE_SIZES
281 static const struct intel_device_info intel_i965g_info = {
283 PLATFORM(INTEL_I965G),
284 .display.has_overlay = 1,
285 .hws_needs_physical = 1,
289 static const struct intel_device_info intel_i965gm_info = {
291 PLATFORM(INTEL_I965GM),
293 .display.has_fbc = 1,
294 .display.has_overlay = 1,
295 .display.supports_tv = 1,
296 .hws_needs_physical = 1,
300 static const struct intel_device_info intel_g45_info = {
303 .engine_mask = BIT(RCS0) | BIT(VCS0),
304 .gpu_reset_clobbers_display = false,
307 static const struct intel_device_info intel_gm45_info = {
309 PLATFORM(INTEL_GM45),
311 .display.has_fbc = 1,
312 .display.supports_tv = 1,
313 .engine_mask = BIT(RCS0) | BIT(VCS0),
314 .gpu_reset_clobbers_display = false,
317 #define GEN5_FEATURES \
320 .display.has_hotplug = 1, \
321 .engine_mask = BIT(RCS0) | BIT(VCS0), \
323 .has_coherent_ggtt = true, \
324 /* ilk does support rc6, but we do not implement [power] contexts */ \
327 I9XX_CURSOR_OFFSETS, \
328 GEN_DEFAULT_PAGE_SIZES
330 static const struct intel_device_info intel_ironlake_d_info = {
332 PLATFORM(INTEL_IRONLAKE),
335 static const struct intel_device_info intel_ironlake_m_info = {
337 PLATFORM(INTEL_IRONLAKE),
339 .display.has_fbc = 1,
342 #define GEN6_FEATURES \
345 .display.has_hotplug = 1, \
346 .display.has_fbc = 1, \
347 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
348 .has_coherent_ggtt = true, \
352 .ppgtt_type = INTEL_PPGTT_ALIASING, \
355 I9XX_CURSOR_OFFSETS, \
356 GEN_DEFAULT_PAGE_SIZES
358 #define SNB_D_PLATFORM \
360 PLATFORM(INTEL_SANDYBRIDGE)
362 static const struct intel_device_info intel_sandybridge_d_gt1_info = {
367 static const struct intel_device_info intel_sandybridge_d_gt2_info = {
372 #define SNB_M_PLATFORM \
374 PLATFORM(INTEL_SANDYBRIDGE), \
378 static const struct intel_device_info intel_sandybridge_m_gt1_info = {
383 static const struct intel_device_info intel_sandybridge_m_gt2_info = {
388 #define GEN7_FEATURES \
391 .display.has_hotplug = 1, \
392 .display.has_fbc = 1, \
393 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
394 .has_coherent_ggtt = true, \
398 .ppgtt_type = INTEL_PPGTT_FULL, \
401 IVB_CURSOR_OFFSETS, \
402 GEN_DEFAULT_PAGE_SIZES
404 #define IVB_D_PLATFORM \
406 PLATFORM(INTEL_IVYBRIDGE), \
409 static const struct intel_device_info intel_ivybridge_d_gt1_info = {
414 static const struct intel_device_info intel_ivybridge_d_gt2_info = {
419 #define IVB_M_PLATFORM \
421 PLATFORM(INTEL_IVYBRIDGE), \
425 static const struct intel_device_info intel_ivybridge_m_gt1_info = {
430 static const struct intel_device_info intel_ivybridge_m_gt2_info = {
435 static const struct intel_device_info intel_ivybridge_q_info = {
437 PLATFORM(INTEL_IVYBRIDGE),
439 .num_pipes = 0, /* legal, last one wins */
443 static const struct intel_device_info intel_valleyview_info = {
444 PLATFORM(INTEL_VALLEYVIEW),
450 .display.has_gmch = 1,
451 .display.has_hotplug = 1,
452 .ppgtt_type = INTEL_PPGTT_FULL,
455 .has_coherent_ggtt = false,
456 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
457 .display_mmio_offset = VLV_DISPLAY_BASE,
460 GEN_DEFAULT_PAGE_SIZES,
463 #define G75_FEATURES \
465 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
466 .display.has_ddi = 1, \
468 .display.has_psr = 1, \
469 .display.has_dp_mst = 1, \
470 .has_rc6p = 0 /* RC6p removed-by HSW */, \
474 #define HSW_PLATFORM \
476 PLATFORM(INTEL_HASWELL), \
479 static const struct intel_device_info intel_haswell_gt1_info = {
484 static const struct intel_device_info intel_haswell_gt2_info = {
489 static const struct intel_device_info intel_haswell_gt3_info = {
494 #define GEN8_FEATURES \
498 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
499 I915_GTT_PAGE_SIZE_2M, \
500 .has_logical_ring_contexts = 1, \
501 .ppgtt_type = INTEL_PPGTT_FULL, \
503 .has_64bit_reloc = 1, \
504 .has_reset_engine = 1
506 #define BDW_PLATFORM \
508 PLATFORM(INTEL_BROADWELL)
510 static const struct intel_device_info intel_broadwell_gt1_info = {
515 static const struct intel_device_info intel_broadwell_gt2_info = {
520 static const struct intel_device_info intel_broadwell_rsvd_info = {
523 /* According to the device ID those devices are GT3, they were
524 * previously treated as not GT3, keep it like that.
528 static const struct intel_device_info intel_broadwell_gt3_info = {
532 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
535 static const struct intel_device_info intel_cherryview_info = {
536 PLATFORM(INTEL_CHERRYVIEW),
539 .display.has_hotplug = 1,
541 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
542 .has_64bit_reloc = 1,
545 .has_logical_ring_contexts = 1,
546 .display.has_gmch = 1,
547 .ppgtt_type = INTEL_PPGTT_FULL,
549 .has_reset_engine = 1,
551 .has_coherent_ggtt = false,
552 .display_mmio_offset = VLV_DISPLAY_BASE,
556 GEN_DEFAULT_PAGE_SIZES,
559 #define GEN9_DEFAULT_PAGE_SIZES \
560 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
561 I915_GTT_PAGE_SIZE_64K | \
562 I915_GTT_PAGE_SIZE_2M
564 #define GEN9_FEATURES \
567 GEN9_DEFAULT_PAGE_SIZES, \
568 .has_logical_ring_preemption = 1, \
569 .display.has_csr = 1, \
571 .display.has_ipc = 1, \
574 #define SKL_PLATFORM \
576 /* Display WA #0477 WaDisableIPC: skl */ \
577 .display.has_ipc = 0, \
578 PLATFORM(INTEL_SKYLAKE)
580 static const struct intel_device_info intel_skylake_gt1_info = {
585 static const struct intel_device_info intel_skylake_gt2_info = {
590 #define SKL_GT3_PLUS_PLATFORM \
593 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
596 static const struct intel_device_info intel_skylake_gt3_info = {
597 SKL_GT3_PLUS_PLATFORM,
601 static const struct intel_device_info intel_skylake_gt4_info = {
602 SKL_GT3_PLUS_PLATFORM,
606 #define GEN9_LP_FEATURES \
609 .display.has_hotplug = 1, \
610 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
612 .has_64bit_reloc = 1, \
613 .display.has_ddi = 1, \
615 .display.has_fbc = 1, \
616 .display.has_psr = 1, \
617 .has_runtime_pm = 1, \
618 .display.has_csr = 1, \
620 .display.has_dp_mst = 1, \
621 .has_logical_ring_contexts = 1, \
622 .has_logical_ring_preemption = 1, \
624 .ppgtt_type = INTEL_PPGTT_FULL, \
626 .has_reset_engine = 1, \
628 .has_coherent_ggtt = false, \
629 .display.has_ipc = 1, \
631 IVB_CURSOR_OFFSETS, \
633 GEN9_DEFAULT_PAGE_SIZES
635 static const struct intel_device_info intel_broxton_info = {
637 PLATFORM(INTEL_BROXTON),
641 static const struct intel_device_info intel_geminilake_info = {
643 PLATFORM(INTEL_GEMINILAKE),
648 #define KBL_PLATFORM \
650 PLATFORM(INTEL_KABYLAKE)
652 static const struct intel_device_info intel_kabylake_gt1_info = {
657 static const struct intel_device_info intel_kabylake_gt2_info = {
662 static const struct intel_device_info intel_kabylake_gt3_info = {
666 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
669 #define CFL_PLATFORM \
671 PLATFORM(INTEL_COFFEELAKE)
673 static const struct intel_device_info intel_coffeelake_gt1_info = {
678 static const struct intel_device_info intel_coffeelake_gt2_info = {
683 static const struct intel_device_info intel_coffeelake_gt3_info = {
687 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
690 #define GEN10_FEATURES \
694 .has_coherent_ggtt = false, \
697 static const struct intel_device_info intel_cannonlake_info = {
699 PLATFORM(INTEL_CANNONLAKE),
703 #define GEN11_FEATURES \
706 [TRANSCODER_A] = PIPE_A_OFFSET, \
707 [TRANSCODER_B] = PIPE_B_OFFSET, \
708 [TRANSCODER_C] = PIPE_C_OFFSET, \
709 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
710 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
711 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
714 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
715 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
716 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
717 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
718 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
719 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
723 .has_logical_ring_elsq = 1, \
724 .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024 }
726 static const struct intel_device_info intel_icelake_11_info = {
728 PLATFORM(INTEL_ICELAKE),
730 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
733 static const struct intel_device_info intel_elkhartlake_info = {
735 PLATFORM(INTEL_ELKHARTLAKE),
736 .is_alpha_support = 1,
737 .engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0),
745 * Make sure any device matches here are from most specific to most
746 * general. For example, since the Quanta match is based on the subsystem
747 * and subvendor IDs, we need it to come before the more general IVB
748 * PCI ID matches, otherwise we'll use the wrong info struct above.
750 static const struct pci_device_id pciidlist[] = {
751 INTEL_I830_IDS(&intel_i830_info),
752 INTEL_I845G_IDS(&intel_i845g_info),
753 INTEL_I85X_IDS(&intel_i85x_info),
754 INTEL_I865G_IDS(&intel_i865g_info),
755 INTEL_I915G_IDS(&intel_i915g_info),
756 INTEL_I915GM_IDS(&intel_i915gm_info),
757 INTEL_I945G_IDS(&intel_i945g_info),
758 INTEL_I945GM_IDS(&intel_i945gm_info),
759 INTEL_I965G_IDS(&intel_i965g_info),
760 INTEL_G33_IDS(&intel_g33_info),
761 INTEL_I965GM_IDS(&intel_i965gm_info),
762 INTEL_GM45_IDS(&intel_gm45_info),
763 INTEL_G45_IDS(&intel_g45_info),
764 INTEL_PINEVIEW_IDS(&intel_pineview_info),
765 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
766 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
767 INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info),
768 INTEL_SNB_D_GT2_IDS(&intel_sandybridge_d_gt2_info),
769 INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info),
770 INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info),
771 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
772 INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info),
773 INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info),
774 INTEL_IVB_D_GT1_IDS(&intel_ivybridge_d_gt1_info),
775 INTEL_IVB_D_GT2_IDS(&intel_ivybridge_d_gt2_info),
776 INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info),
777 INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info),
778 INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info),
779 INTEL_VLV_IDS(&intel_valleyview_info),
780 INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info),
781 INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info),
782 INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
783 INTEL_BDW_RSVD_IDS(&intel_broadwell_rsvd_info),
784 INTEL_CHV_IDS(&intel_cherryview_info),
785 INTEL_SKL_GT1_IDS(&intel_skylake_gt1_info),
786 INTEL_SKL_GT2_IDS(&intel_skylake_gt2_info),
787 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
788 INTEL_SKL_GT4_IDS(&intel_skylake_gt4_info),
789 INTEL_BXT_IDS(&intel_broxton_info),
790 INTEL_GLK_IDS(&intel_geminilake_info),
791 INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info),
792 INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info),
793 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
794 INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
795 INTEL_AML_KBL_GT2_IDS(&intel_kabylake_gt2_info),
796 INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info),
797 INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),
798 INTEL_CFL_H_GT1_IDS(&intel_coffeelake_gt1_info),
799 INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),
800 INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info),
801 INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
802 INTEL_WHL_U_GT1_IDS(&intel_coffeelake_gt1_info),
803 INTEL_WHL_U_GT2_IDS(&intel_coffeelake_gt2_info),
804 INTEL_AML_CFL_GT2_IDS(&intel_coffeelake_gt2_info),
805 INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info),
806 INTEL_CML_GT1_IDS(&intel_coffeelake_gt1_info),
807 INTEL_CML_GT2_IDS(&intel_coffeelake_gt2_info),
808 INTEL_CNL_IDS(&intel_cannonlake_info),
809 INTEL_ICL_11_IDS(&intel_icelake_11_info),
810 INTEL_EHL_IDS(&intel_elkhartlake_info),
813 MODULE_DEVICE_TABLE(pci, pciidlist);
815 static void i915_pci_remove(struct pci_dev *pdev)
817 struct drm_device *dev;
819 dev = pci_get_drvdata(pdev);
820 if (!dev) /* driver load aborted, nothing to cleanup */
823 i915_driver_unload(dev);
826 pci_set_drvdata(pdev, NULL);
829 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
831 struct intel_device_info *intel_info =
832 (struct intel_device_info *) ent->driver_data;
835 if (IS_ALPHA_SUPPORT(intel_info) && !i915_modparams.alpha_support) {
836 DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n"
837 "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n"
838 "to enable support in this kernel version, or check for kernel updates.\n");
842 /* Only bind to function 0 of the device. Early generations
843 * used function 1 as a placeholder for multi-head. This causes
844 * us confusion instead, especially on the systems where both
845 * functions have the same PCI-ID!
847 if (PCI_FUNC(pdev->devfn))
851 * apple-gmux is needed on dual GPU MacBook Pro
852 * to probe the panel if we're the inactive GPU.
854 if (vga_switcheroo_client_probe_defer(pdev))
855 return -EPROBE_DEFER;
857 err = i915_driver_load(pdev, ent);
861 if (i915_inject_load_failure()) {
862 i915_pci_remove(pdev);
866 err = i915_live_selftests(pdev);
868 i915_pci_remove(pdev);
869 return err > 0 ? -ENOTTY : err;
875 static struct pci_driver i915_pci_driver = {
877 .id_table = pciidlist,
878 .probe = i915_pci_probe,
879 .remove = i915_pci_remove,
880 .driver.pm = &i915_pm_ops,
883 static int __init i915_init(void)
888 err = i915_globals_init();
892 err = i915_mock_selftests();
894 return err > 0 ? 0 : err;
897 * Enable KMS by default, unless explicitly overriden by
898 * either the i915.modeset prarameter or by the
899 * vga_text_mode_force boot option.
902 if (i915_modparams.modeset == 0)
905 if (vgacon_text_force() && i915_modparams.modeset == -1)
909 /* Silently fail loading to not upset userspace. */
910 DRM_DEBUG_DRIVER("KMS disabled.\n");
914 return pci_register_driver(&i915_pci_driver);
917 static void __exit i915_exit(void)
919 if (!i915_pci_driver.driver.owner)
922 pci_unregister_driver(&i915_pci_driver);
926 module_init(i915_init);
927 module_exit(i915_exit);
929 MODULE_AUTHOR("Tungsten Graphics, Inc.");
930 MODULE_AUTHOR("Intel Corporation");
932 MODULE_DESCRIPTION(DRIVER_DESC);
933 MODULE_LICENSE("GPL and additional rights");