2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include <linux/console.h>
26 #include <linux/vgaarb.h>
27 #include <linux/vga_switcheroo.h>
29 #include "i915_active.h"
31 #include "i915_selftest.h"
33 #define PLATFORM(x) .platform = (x), .platform_mask = BIT(x)
34 #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
36 #define GEN_DEFAULT_PIPEOFFSETS \
38 [TRANSCODER_A] = PIPE_A_OFFSET, \
39 [TRANSCODER_B] = PIPE_B_OFFSET, \
40 [TRANSCODER_C] = PIPE_C_OFFSET, \
41 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
44 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
45 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
46 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
47 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
50 #define GEN_CHV_PIPEOFFSETS \
52 [TRANSCODER_A] = PIPE_A_OFFSET, \
53 [TRANSCODER_B] = PIPE_B_OFFSET, \
54 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
57 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
58 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
59 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
62 #define CURSOR_OFFSETS \
63 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
65 #define IVB_CURSOR_OFFSETS \
66 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
69 .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
71 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \
72 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
73 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
76 .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024, \
77 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
78 DRM_COLOR_LUT_EQUAL_CHANNELS, \
81 /* Keep in gen based order, and chronological order within a gen */
83 #define GEN_DEFAULT_PAGE_SIZES \
84 .page_sizes = I915_GTT_PAGE_SIZE_4K
86 #define GEN2_FEATURES \
89 .display.has_overlay = 1, \
90 .display.overlay_needs_physical = 1, \
91 .display.has_gmch = 1, \
92 .gpu_reset_clobbers_display = true, \
93 .hws_needs_physical = 1, \
94 .unfenced_needs_alignment = 1, \
95 .ring_mask = RENDER_RING, \
97 .has_coherent_ggtt = false, \
98 GEN_DEFAULT_PIPEOFFSETS, \
99 GEN_DEFAULT_PAGE_SIZES, \
102 static const struct intel_device_info intel_i830_info = {
104 PLATFORM(INTEL_I830),
106 .display.cursor_needs_physical = 1,
107 .num_pipes = 2, /* legal, last one wins */
110 static const struct intel_device_info intel_i845g_info = {
112 PLATFORM(INTEL_I845G),
115 static const struct intel_device_info intel_i85x_info = {
117 PLATFORM(INTEL_I85X),
119 .num_pipes = 2, /* legal, last one wins */
120 .display.cursor_needs_physical = 1,
121 .display.has_fbc = 1,
124 static const struct intel_device_info intel_i865g_info = {
126 PLATFORM(INTEL_I865G),
129 #define GEN3_FEATURES \
132 .display.has_gmch = 1, \
133 .gpu_reset_clobbers_display = true, \
134 .ring_mask = RENDER_RING, \
136 .has_coherent_ggtt = true, \
137 GEN_DEFAULT_PIPEOFFSETS, \
138 GEN_DEFAULT_PAGE_SIZES, \
141 static const struct intel_device_info intel_i915g_info = {
143 PLATFORM(INTEL_I915G),
144 .has_coherent_ggtt = false,
145 .display.cursor_needs_physical = 1,
146 .display.has_overlay = 1,
147 .display.overlay_needs_physical = 1,
148 .hws_needs_physical = 1,
149 .unfenced_needs_alignment = 1,
152 static const struct intel_device_info intel_i915gm_info = {
154 PLATFORM(INTEL_I915GM),
156 .display.cursor_needs_physical = 1,
157 .display.has_overlay = 1,
158 .display.overlay_needs_physical = 1,
159 .display.supports_tv = 1,
160 .display.has_fbc = 1,
161 .hws_needs_physical = 1,
162 .unfenced_needs_alignment = 1,
165 static const struct intel_device_info intel_i945g_info = {
167 PLATFORM(INTEL_I945G),
168 .display.has_hotplug = 1,
169 .display.cursor_needs_physical = 1,
170 .display.has_overlay = 1,
171 .display.overlay_needs_physical = 1,
172 .hws_needs_physical = 1,
173 .unfenced_needs_alignment = 1,
176 static const struct intel_device_info intel_i945gm_info = {
178 PLATFORM(INTEL_I945GM),
180 .display.has_hotplug = 1,
181 .display.cursor_needs_physical = 1,
182 .display.has_overlay = 1,
183 .display.overlay_needs_physical = 1,
184 .display.supports_tv = 1,
185 .display.has_fbc = 1,
186 .hws_needs_physical = 1,
187 .unfenced_needs_alignment = 1,
190 static const struct intel_device_info intel_g33_info = {
193 .display.has_hotplug = 1,
194 .display.has_overlay = 1,
197 static const struct intel_device_info intel_pineview_info = {
199 PLATFORM(INTEL_PINEVIEW),
201 .display.has_hotplug = 1,
202 .display.has_overlay = 1,
205 #define GEN4_FEATURES \
208 .display.has_hotplug = 1, \
209 .display.has_gmch = 1, \
210 .gpu_reset_clobbers_display = true, \
211 .ring_mask = RENDER_RING, \
213 .has_coherent_ggtt = true, \
214 GEN_DEFAULT_PIPEOFFSETS, \
215 GEN_DEFAULT_PAGE_SIZES, \
218 static const struct intel_device_info intel_i965g_info = {
220 PLATFORM(INTEL_I965G),
221 .display.has_overlay = 1,
222 .hws_needs_physical = 1,
226 static const struct intel_device_info intel_i965gm_info = {
228 PLATFORM(INTEL_I965GM),
230 .display.has_fbc = 1,
231 .display.has_overlay = 1,
232 .display.supports_tv = 1,
233 .hws_needs_physical = 1,
237 static const struct intel_device_info intel_g45_info = {
240 .ring_mask = RENDER_RING | BSD_RING,
241 .gpu_reset_clobbers_display = false,
244 static const struct intel_device_info intel_gm45_info = {
246 PLATFORM(INTEL_GM45),
248 .display.has_fbc = 1,
249 .display.supports_tv = 1,
250 .ring_mask = RENDER_RING | BSD_RING,
251 .gpu_reset_clobbers_display = false,
254 #define GEN5_FEATURES \
257 .display.has_hotplug = 1, \
258 .ring_mask = RENDER_RING | BSD_RING, \
260 .has_coherent_ggtt = true, \
261 /* ilk does support rc6, but we do not implement [power] contexts */ \
263 GEN_DEFAULT_PIPEOFFSETS, \
264 GEN_DEFAULT_PAGE_SIZES, \
267 static const struct intel_device_info intel_ironlake_d_info = {
269 PLATFORM(INTEL_IRONLAKE),
272 static const struct intel_device_info intel_ironlake_m_info = {
274 PLATFORM(INTEL_IRONLAKE),
276 .display.has_fbc = 1,
279 #define GEN6_FEATURES \
282 .display.has_hotplug = 1, \
283 .display.has_fbc = 1, \
284 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
285 .has_coherent_ggtt = true, \
289 .ppgtt = INTEL_PPGTT_ALIASING, \
290 GEN_DEFAULT_PIPEOFFSETS, \
291 GEN_DEFAULT_PAGE_SIZES, \
294 #define SNB_D_PLATFORM \
296 PLATFORM(INTEL_SANDYBRIDGE)
298 static const struct intel_device_info intel_sandybridge_d_gt1_info = {
303 static const struct intel_device_info intel_sandybridge_d_gt2_info = {
308 #define SNB_M_PLATFORM \
310 PLATFORM(INTEL_SANDYBRIDGE), \
314 static const struct intel_device_info intel_sandybridge_m_gt1_info = {
319 static const struct intel_device_info intel_sandybridge_m_gt2_info = {
324 #define GEN7_FEATURES \
327 .display.has_hotplug = 1, \
328 .display.has_fbc = 1, \
329 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
330 .has_coherent_ggtt = true, \
334 .ppgtt = INTEL_PPGTT_FULL, \
335 GEN_DEFAULT_PIPEOFFSETS, \
336 GEN_DEFAULT_PAGE_SIZES, \
339 #define IVB_D_PLATFORM \
341 PLATFORM(INTEL_IVYBRIDGE), \
344 static const struct intel_device_info intel_ivybridge_d_gt1_info = {
349 static const struct intel_device_info intel_ivybridge_d_gt2_info = {
354 #define IVB_M_PLATFORM \
356 PLATFORM(INTEL_IVYBRIDGE), \
360 static const struct intel_device_info intel_ivybridge_m_gt1_info = {
365 static const struct intel_device_info intel_ivybridge_m_gt2_info = {
370 static const struct intel_device_info intel_ivybridge_q_info = {
372 PLATFORM(INTEL_IVYBRIDGE),
374 .num_pipes = 0, /* legal, last one wins */
378 static const struct intel_device_info intel_valleyview_info = {
379 PLATFORM(INTEL_VALLEYVIEW),
385 .display.has_gmch = 1,
386 .display.has_hotplug = 1,
387 .ppgtt = INTEL_PPGTT_FULL,
389 .has_coherent_ggtt = false,
390 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
391 .display_mmio_offset = VLV_DISPLAY_BASE,
392 GEN_DEFAULT_PAGE_SIZES,
393 GEN_DEFAULT_PIPEOFFSETS,
397 #define G75_FEATURES \
399 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
400 .display.has_ddi = 1, \
402 .display.has_psr = 1, \
403 .display.has_dp_mst = 1, \
404 .has_rc6p = 0 /* RC6p removed-by HSW */, \
407 #define HSW_PLATFORM \
409 PLATFORM(INTEL_HASWELL), \
412 static const struct intel_device_info intel_haswell_gt1_info = {
417 static const struct intel_device_info intel_haswell_gt2_info = {
422 static const struct intel_device_info intel_haswell_gt3_info = {
427 #define GEN8_FEATURES \
431 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
432 I915_GTT_PAGE_SIZE_2M, \
433 .has_logical_ring_contexts = 1, \
434 .ppgtt = INTEL_PPGTT_FULL_4LVL, \
435 .has_64bit_reloc = 1, \
436 .has_reset_engine = 1
438 #define BDW_PLATFORM \
440 PLATFORM(INTEL_BROADWELL)
442 static const struct intel_device_info intel_broadwell_gt1_info = {
447 static const struct intel_device_info intel_broadwell_gt2_info = {
452 static const struct intel_device_info intel_broadwell_rsvd_info = {
455 /* According to the device ID those devices are GT3, they were
456 * previously treated as not GT3, keep it like that.
460 static const struct intel_device_info intel_broadwell_gt3_info = {
463 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
466 static const struct intel_device_info intel_cherryview_info = {
467 PLATFORM(INTEL_CHERRYVIEW),
470 .display.has_hotplug = 1,
472 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
473 .has_64bit_reloc = 1,
476 .has_logical_ring_contexts = 1,
477 .display.has_gmch = 1,
478 .ppgtt = INTEL_PPGTT_FULL,
479 .has_reset_engine = 1,
481 .has_coherent_ggtt = false,
482 .display_mmio_offset = VLV_DISPLAY_BASE,
483 GEN_DEFAULT_PAGE_SIZES,
489 #define GEN9_DEFAULT_PAGE_SIZES \
490 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
491 I915_GTT_PAGE_SIZE_64K | \
492 I915_GTT_PAGE_SIZE_2M
494 #define GEN9_FEATURES \
497 GEN9_DEFAULT_PAGE_SIZES, \
498 .has_logical_ring_preemption = 1, \
499 .display.has_csr = 1, \
501 .display.has_ipc = 1, \
504 #define SKL_PLATFORM \
506 /* Display WA #0477 WaDisableIPC: skl */ \
507 .display.has_ipc = 0, \
508 PLATFORM(INTEL_SKYLAKE)
510 static const struct intel_device_info intel_skylake_gt1_info = {
515 static const struct intel_device_info intel_skylake_gt2_info = {
520 #define SKL_GT3_PLUS_PLATFORM \
522 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING
525 static const struct intel_device_info intel_skylake_gt3_info = {
526 SKL_GT3_PLUS_PLATFORM,
530 static const struct intel_device_info intel_skylake_gt4_info = {
531 SKL_GT3_PLUS_PLATFORM,
535 #define GEN9_LP_FEATURES \
538 .display.has_hotplug = 1, \
539 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
541 .has_64bit_reloc = 1, \
542 .display.has_ddi = 1, \
544 .display.has_fbc = 1, \
545 .display.has_psr = 1, \
546 .has_runtime_pm = 1, \
547 .display.has_csr = 1, \
549 .display.has_dp_mst = 1, \
550 .has_logical_ring_contexts = 1, \
551 .has_logical_ring_preemption = 1, \
553 .ppgtt = INTEL_PPGTT_FULL_4LVL, \
554 .has_reset_engine = 1, \
556 .has_coherent_ggtt = false, \
557 .display.has_ipc = 1, \
558 GEN9_DEFAULT_PAGE_SIZES, \
559 GEN_DEFAULT_PIPEOFFSETS, \
560 IVB_CURSOR_OFFSETS, \
563 static const struct intel_device_info intel_broxton_info = {
565 PLATFORM(INTEL_BROXTON),
569 static const struct intel_device_info intel_geminilake_info = {
571 PLATFORM(INTEL_GEMINILAKE),
576 #define KBL_PLATFORM \
578 PLATFORM(INTEL_KABYLAKE)
580 static const struct intel_device_info intel_kabylake_gt1_info = {
585 static const struct intel_device_info intel_kabylake_gt2_info = {
590 static const struct intel_device_info intel_kabylake_gt3_info = {
593 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
596 #define CFL_PLATFORM \
598 PLATFORM(INTEL_COFFEELAKE)
600 static const struct intel_device_info intel_coffeelake_gt1_info = {
605 static const struct intel_device_info intel_coffeelake_gt2_info = {
610 static const struct intel_device_info intel_coffeelake_gt3_info = {
613 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
616 #define GEN10_FEATURES \
620 .has_coherent_ggtt = false, \
623 static const struct intel_device_info intel_cannonlake_info = {
625 PLATFORM(INTEL_CANNONLAKE),
629 #define GEN11_FEATURES \
632 [TRANSCODER_A] = PIPE_A_OFFSET, \
633 [TRANSCODER_B] = PIPE_B_OFFSET, \
634 [TRANSCODER_C] = PIPE_C_OFFSET, \
635 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
636 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
637 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
640 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
641 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
642 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
643 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
644 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
645 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
649 .has_logical_ring_elsq = 1
651 static const struct intel_device_info intel_icelake_11_info = {
653 PLATFORM(INTEL_ICELAKE),
654 .is_alpha_support = 1,
655 .ring_mask = RENDER_RING | BLT_RING | VEBOX_RING | BSD_RING | BSD3_RING,
662 * Make sure any device matches here are from most specific to most
663 * general. For example, since the Quanta match is based on the subsystem
664 * and subvendor IDs, we need it to come before the more general IVB
665 * PCI ID matches, otherwise we'll use the wrong info struct above.
667 static const struct pci_device_id pciidlist[] = {
668 INTEL_I830_IDS(&intel_i830_info),
669 INTEL_I845G_IDS(&intel_i845g_info),
670 INTEL_I85X_IDS(&intel_i85x_info),
671 INTEL_I865G_IDS(&intel_i865g_info),
672 INTEL_I915G_IDS(&intel_i915g_info),
673 INTEL_I915GM_IDS(&intel_i915gm_info),
674 INTEL_I945G_IDS(&intel_i945g_info),
675 INTEL_I945GM_IDS(&intel_i945gm_info),
676 INTEL_I965G_IDS(&intel_i965g_info),
677 INTEL_G33_IDS(&intel_g33_info),
678 INTEL_I965GM_IDS(&intel_i965gm_info),
679 INTEL_GM45_IDS(&intel_gm45_info),
680 INTEL_G45_IDS(&intel_g45_info),
681 INTEL_PINEVIEW_IDS(&intel_pineview_info),
682 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
683 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
684 INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info),
685 INTEL_SNB_D_GT2_IDS(&intel_sandybridge_d_gt2_info),
686 INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info),
687 INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info),
688 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
689 INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info),
690 INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info),
691 INTEL_IVB_D_GT1_IDS(&intel_ivybridge_d_gt1_info),
692 INTEL_IVB_D_GT2_IDS(&intel_ivybridge_d_gt2_info),
693 INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info),
694 INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info),
695 INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info),
696 INTEL_VLV_IDS(&intel_valleyview_info),
697 INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info),
698 INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info),
699 INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
700 INTEL_BDW_RSVD_IDS(&intel_broadwell_rsvd_info),
701 INTEL_CHV_IDS(&intel_cherryview_info),
702 INTEL_SKL_GT1_IDS(&intel_skylake_gt1_info),
703 INTEL_SKL_GT2_IDS(&intel_skylake_gt2_info),
704 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
705 INTEL_SKL_GT4_IDS(&intel_skylake_gt4_info),
706 INTEL_BXT_IDS(&intel_broxton_info),
707 INTEL_GLK_IDS(&intel_geminilake_info),
708 INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info),
709 INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info),
710 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
711 INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
712 INTEL_AML_KBL_GT2_IDS(&intel_kabylake_gt2_info),
713 INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info),
714 INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),
715 INTEL_CFL_H_GT1_IDS(&intel_coffeelake_gt1_info),
716 INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),
717 INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info),
718 INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
719 INTEL_WHL_U_GT1_IDS(&intel_coffeelake_gt1_info),
720 INTEL_WHL_U_GT2_IDS(&intel_coffeelake_gt2_info),
721 INTEL_AML_CFL_GT2_IDS(&intel_coffeelake_gt2_info),
722 INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info),
723 INTEL_CNL_IDS(&intel_cannonlake_info),
724 INTEL_ICL_11_IDS(&intel_icelake_11_info),
727 MODULE_DEVICE_TABLE(pci, pciidlist);
729 static void i915_pci_remove(struct pci_dev *pdev)
731 struct drm_device *dev;
733 dev = pci_get_drvdata(pdev);
734 if (!dev) /* driver load aborted, nothing to cleanup */
737 i915_driver_unload(dev);
740 pci_set_drvdata(pdev, NULL);
743 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
745 struct intel_device_info *intel_info =
746 (struct intel_device_info *) ent->driver_data;
749 if (IS_ALPHA_SUPPORT(intel_info) && !i915_modparams.alpha_support) {
750 DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n"
751 "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n"
752 "to enable support in this kernel version, or check for kernel updates.\n");
756 /* Only bind to function 0 of the device. Early generations
757 * used function 1 as a placeholder for multi-head. This causes
758 * us confusion instead, especially on the systems where both
759 * functions have the same PCI-ID!
761 if (PCI_FUNC(pdev->devfn))
765 * apple-gmux is needed on dual GPU MacBook Pro
766 * to probe the panel if we're the inactive GPU.
768 if (vga_switcheroo_client_probe_defer(pdev))
769 return -EPROBE_DEFER;
771 err = i915_driver_load(pdev, ent);
775 if (i915_inject_load_failure()) {
776 i915_pci_remove(pdev);
780 err = i915_live_selftests(pdev);
782 i915_pci_remove(pdev);
783 return err > 0 ? -ENOTTY : err;
789 static struct pci_driver i915_pci_driver = {
791 .id_table = pciidlist,
792 .probe = i915_pci_probe,
793 .remove = i915_pci_remove,
794 .driver.pm = &i915_pm_ops,
797 static int __init i915_init(void)
802 i915_global_active_init();
804 err = i915_mock_selftests();
806 return err > 0 ? 0 : err;
809 * Enable KMS by default, unless explicitly overriden by
810 * either the i915.modeset prarameter or by the
811 * vga_text_mode_force boot option.
814 if (i915_modparams.modeset == 0)
817 if (vgacon_text_force() && i915_modparams.modeset == -1)
821 /* Silently fail loading to not upset userspace. */
822 DRM_DEBUG_DRIVER("KMS disabled.\n");
826 return pci_register_driver(&i915_pci_driver);
829 static void __exit i915_exit(void)
831 if (!i915_pci_driver.driver.owner)
834 pci_unregister_driver(&i915_pci_driver);
835 i915_global_active_exit();
838 module_init(i915_init);
839 module_exit(i915_exit);
841 MODULE_AUTHOR("Tungsten Graphics, Inc.");
842 MODULE_AUTHOR("Intel Corporation");
844 MODULE_DESCRIPTION(DRIVER_DESC);
845 MODULE_LICENSE("GPL and additional rights");