drivers/gpu/drm/i915/i915_pci.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <linux/console.h>
  26 #include <linux/vgaarb.h>
  27 #include <linux/vga_switcheroo.h>
  28
  29 #include "i915_drv.h"
  30 #include "i915_selftest.h"
  31
  32 #define PLATFORM(x) .platform = (x), .platform_mask = BIT(x)
  33 #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
  34
  35 #define GEN_DEFAULT_PIPEOFFSETS \
  36         .pipe_offsets = { \
  37                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  38                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  39                 [TRANSCODER_C] = PIPE_C_OFFSET, \
  40                 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
  41         }, \
  42         .trans_offsets = { \
  43                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  44                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  45                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
  46                 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
  47         }
  48
  49 #define GEN_CHV_PIPEOFFSETS \
  50         .pipe_offsets = { \
  51                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  52                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  53                 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
  54         }, \
  55         .trans_offsets = { \
  56                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  57                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  58                 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
  59         }
  60
  61 #define CURSOR_OFFSETS \
  62         .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
  63
  64 #define IVB_CURSOR_OFFSETS \
  65         .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
  66
  67 #define BDW_COLORS \
  68         .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
  69 #define CHV_COLORS \
  70         .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
  71 #define GLK_COLORS \
  72         .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
  73
  74 /* Keep in gen based order, and chronological order within a gen */
  75
  76 #define GEN_DEFAULT_PAGE_SIZES \
  77         .page_sizes = I915_GTT_PAGE_SIZE_4K
  78
  79 #define GEN2_FEATURES \
  80         GEN(2), \
  81         .num_pipes = 1, \
  82         .display.has_overlay = 1, \
  83         .display.overlay_needs_physical = 1, \
  84         .display.has_gmch_display = 1, \
  85         .gpu_reset_clobbers_display = true, \
  86         .hws_needs_physical = 1, \
  87         .unfenced_needs_alignment = 1, \
  88         .ring_mask = RENDER_RING, \
  89         .has_snoop = true, \
  90         .has_coherent_ggtt = false, \
  91         GEN_DEFAULT_PIPEOFFSETS, \
  92         GEN_DEFAULT_PAGE_SIZES, \
  93         CURSOR_OFFSETS
  94
  95 static const struct intel_device_info intel_i830_info = {
  96         GEN2_FEATURES,
  97         PLATFORM(INTEL_I830),
  98         .is_mobile = 1,
  99         .display.cursor_needs_physical = 1,
 100         .num_pipes = 2, /* legal, last one wins */
 101 };
 102
 103 static const struct intel_device_info intel_i845g_info = {
 104         GEN2_FEATURES,
 105         PLATFORM(INTEL_I845G),
 106 };
 107
 108 static const struct intel_device_info intel_i85x_info = {
 109         GEN2_FEATURES,
 110         PLATFORM(INTEL_I85X),
 111         .is_mobile = 1,
 112         .num_pipes = 2, /* legal, last one wins */
 113         .display.cursor_needs_physical = 1,
 114         .display.has_fbc = 1,
 115 };
 116
 117 static const struct intel_device_info intel_i865g_info = {
 118         GEN2_FEATURES,
 119         PLATFORM(INTEL_I865G),
 120 };
 121
 122 #define GEN3_FEATURES \
 123         GEN(3), \
 124         .num_pipes = 2, \
 125         .display.has_gmch_display = 1, \
 126         .gpu_reset_clobbers_display = true, \
 127         .ring_mask = RENDER_RING, \
 128         .has_snoop = true, \
 129         .has_coherent_ggtt = true, \
 130         GEN_DEFAULT_PIPEOFFSETS, \
 131         GEN_DEFAULT_PAGE_SIZES, \
 132         CURSOR_OFFSETS
 133
 134 static const struct intel_device_info intel_i915g_info = {
 135         GEN3_FEATURES,
 136         PLATFORM(INTEL_I915G),
 137         .has_coherent_ggtt = false,
 138         .display.cursor_needs_physical = 1,
 139         .display.has_overlay = 1,
 140         .display.overlay_needs_physical = 1,
 141         .hws_needs_physical = 1,
 142         .unfenced_needs_alignment = 1,
 143 };
 144
 145 static const struct intel_device_info intel_i915gm_info = {
 146         GEN3_FEATURES,
 147         PLATFORM(INTEL_I915GM),
 148         .is_mobile = 1,
 149         .display.cursor_needs_physical = 1,
 150         .display.has_overlay = 1,
 151         .display.overlay_needs_physical = 1,
 152         .display.supports_tv = 1,
 153         .display.has_fbc = 1,
 154         .hws_needs_physical = 1,
 155         .unfenced_needs_alignment = 1,
 156 };
 157
 158 static const struct intel_device_info intel_i945g_info = {
 159         GEN3_FEATURES,
 160         PLATFORM(INTEL_I945G),
 161         .display.has_hotplug = 1,
 162         .display.cursor_needs_physical = 1,
 163         .display.has_overlay = 1,
 164         .display.overlay_needs_physical = 1,
 165         .hws_needs_physical = 1,
 166         .unfenced_needs_alignment = 1,
 167 };
 168
 169 static const struct intel_device_info intel_i945gm_info = {
 170         GEN3_FEATURES,
 171         PLATFORM(INTEL_I945GM),
 172         .is_mobile = 1,
 173         .display.has_hotplug = 1,
 174         .display.cursor_needs_physical = 1,
 175         .display.has_overlay = 1,
 176         .display.overlay_needs_physical = 1,
 177         .display.supports_tv = 1,
 178         .display.has_fbc = 1,
 179         .hws_needs_physical = 1,
 180         .unfenced_needs_alignment = 1,
 181 };
 182
 183 static const struct intel_device_info intel_g33_info = {
 184         GEN3_FEATURES,
 185         PLATFORM(INTEL_G33),
 186         .display.has_hotplug = 1,
 187         .display.has_overlay = 1,
 188 };
 189
 190 static const struct intel_device_info intel_pineview_info = {
 191         GEN3_FEATURES,
 192         PLATFORM(INTEL_PINEVIEW),
 193         .is_mobile = 1,
 194         .display.has_hotplug = 1,
 195         .display.has_overlay = 1,
 196 };
 197
 198 #define GEN4_FEATURES \
 199         GEN(4), \
 200         .num_pipes = 2, \
 201         .display.has_hotplug = 1, \
 202         .display.has_gmch_display = 1, \
 203         .gpu_reset_clobbers_display = true, \
 204         .ring_mask = RENDER_RING, \
 205         .has_snoop = true, \
 206         .has_coherent_ggtt = true, \
 207         GEN_DEFAULT_PIPEOFFSETS, \
 208         GEN_DEFAULT_PAGE_SIZES, \
 209         CURSOR_OFFSETS
 210
 211 static const struct intel_device_info intel_i965g_info = {
 212         GEN4_FEATURES,
 213         PLATFORM(INTEL_I965G),
 214         .display.has_overlay = 1,
 215         .hws_needs_physical = 1,
 216         .has_snoop = false,
 217 };
 218
 219 static const struct intel_device_info intel_i965gm_info = {
 220         GEN4_FEATURES,
 221         PLATFORM(INTEL_I965GM),
 222         .is_mobile = 1,
 223         .display.has_fbc = 1,
 224         .display.has_overlay = 1,
 225         .display.supports_tv = 1,
 226         .hws_needs_physical = 1,
 227         .has_snoop = false,
 228 };
 229
 230 static const struct intel_device_info intel_g45_info = {
 231         GEN4_FEATURES,
 232         PLATFORM(INTEL_G45),
 233         .ring_mask = RENDER_RING | BSD_RING,
 234         .gpu_reset_clobbers_display = false,
 235 };
 236
 237 static const struct intel_device_info intel_gm45_info = {
 238         GEN4_FEATURES,
 239         PLATFORM(INTEL_GM45),
 240         .is_mobile = 1,
 241         .display.has_fbc = 1,
 242         .display.supports_tv = 1,
 243         .ring_mask = RENDER_RING | BSD_RING,
 244         .gpu_reset_clobbers_display = false,
 245 };
 246
 247 #define GEN5_FEATURES \
 248         GEN(5), \
 249         .num_pipes = 2, \
 250         .display.has_hotplug = 1, \
 251         .ring_mask = RENDER_RING | BSD_RING, \
 252         .has_snoop = true, \
 253         .has_coherent_ggtt = true, \
 254         /* ilk does support rc6, but we do not implement [power] contexts */ \
 255         .has_rc6 = 0, \
 256         GEN_DEFAULT_PIPEOFFSETS, \
 257         GEN_DEFAULT_PAGE_SIZES, \
 258         CURSOR_OFFSETS
 259
 260 static const struct intel_device_info intel_ironlake_d_info = {
 261         GEN5_FEATURES,
 262         PLATFORM(INTEL_IRONLAKE),
 263 };
 264
 265 static const struct intel_device_info intel_ironlake_m_info = {
 266         GEN5_FEATURES,
 267         PLATFORM(INTEL_IRONLAKE),
 268         .is_mobile = 1,
 269         .display.has_fbc = 1,
 270 };
 271
 272 #define GEN6_FEATURES \
 273         GEN(6), \
 274         .num_pipes = 2, \
 275         .display.has_hotplug = 1, \
 276         .display.has_fbc = 1, \
 277         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 278         .has_coherent_ggtt = true, \
 279         .has_llc = 1, \
 280         .has_rc6 = 1, \
 281         .has_rc6p = 1, \
 282         .ppgtt = INTEL_PPGTT_ALIASING, \
 283         GEN_DEFAULT_PIPEOFFSETS, \
 284         GEN_DEFAULT_PAGE_SIZES, \
 285         CURSOR_OFFSETS
 286
 287 #define SNB_D_PLATFORM \
 288         GEN6_FEATURES, \
 289         PLATFORM(INTEL_SANDYBRIDGE)
 290
 291 static const struct intel_device_info intel_sandybridge_d_gt1_info = {
 292         SNB_D_PLATFORM,
 293         .gt = 1,
 294 };
 295
 296 static const struct intel_device_info intel_sandybridge_d_gt2_info = {
 297         SNB_D_PLATFORM,
 298         .gt = 2,
 299 };
 300
 301 #define SNB_M_PLATFORM \
 302         GEN6_FEATURES, \
 303         PLATFORM(INTEL_SANDYBRIDGE), \
 304         .is_mobile = 1
 305
 306
 307 static const struct intel_device_info intel_sandybridge_m_gt1_info = {
 308         SNB_M_PLATFORM,
 309         .gt = 1,
 310 };
 311
 312 static const struct intel_device_info intel_sandybridge_m_gt2_info = {
 313         SNB_M_PLATFORM,
 314         .gt = 2,
 315 };
 316
 317 #define GEN7_FEATURES  \
 318         GEN(7), \
 319         .num_pipes = 3, \
 320         .display.has_hotplug = 1, \
 321         .display.has_fbc = 1, \
 322         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 323         .has_coherent_ggtt = true, \
 324         .has_llc = 1, \
 325         .has_rc6 = 1, \
 326         .has_rc6p = 1, \
 327         .ppgtt = INTEL_PPGTT_FULL, \
 328         GEN_DEFAULT_PIPEOFFSETS, \
 329         GEN_DEFAULT_PAGE_SIZES, \
 330         IVB_CURSOR_OFFSETS
 331
 332 #define IVB_D_PLATFORM \
 333         GEN7_FEATURES, \
 334         PLATFORM(INTEL_IVYBRIDGE), \
 335         .has_l3_dpf = 1
 336
 337 static const struct intel_device_info intel_ivybridge_d_gt1_info = {
 338         IVB_D_PLATFORM,
 339         .gt = 1,
 340 };
 341
 342 static const struct intel_device_info intel_ivybridge_d_gt2_info = {
 343         IVB_D_PLATFORM,
 344         .gt = 2,
 345 };
 346
 347 #define IVB_M_PLATFORM \
 348         GEN7_FEATURES, \
 349         PLATFORM(INTEL_IVYBRIDGE), \
 350         .is_mobile = 1, \
 351         .has_l3_dpf = 1
 352
 353 static const struct intel_device_info intel_ivybridge_m_gt1_info = {
 354         IVB_M_PLATFORM,
 355         .gt = 1,
 356 };
 357
 358 static const struct intel_device_info intel_ivybridge_m_gt2_info = {
 359         IVB_M_PLATFORM,
 360         .gt = 2,
 361 };
 362
 363 static const struct intel_device_info intel_ivybridge_q_info = {
 364         GEN7_FEATURES,
 365         PLATFORM(INTEL_IVYBRIDGE),
 366         .gt = 2,
 367         .num_pipes = 0, /* legal, last one wins */
 368         .has_l3_dpf = 1,
 369 };
 370
 371 static const struct intel_device_info intel_valleyview_info = {
 372         PLATFORM(INTEL_VALLEYVIEW),
 373         GEN(7),
 374         .is_lp = 1,
 375         .num_pipes = 2,
 376         .has_runtime_pm = 1,
 377         .has_rc6 = 1,
 378         .display.has_gmch_display = 1,
 379         .display.has_hotplug = 1,
 380         .ppgtt = INTEL_PPGTT_FULL,
 381         .has_snoop = true,
 382         .has_coherent_ggtt = false,
 383         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 384         .display_mmio_offset = VLV_DISPLAY_BASE,
 385         GEN_DEFAULT_PAGE_SIZES,
 386         GEN_DEFAULT_PIPEOFFSETS,
 387         CURSOR_OFFSETS
 388 };
 389
 390 #define G75_FEATURES  \
 391         GEN7_FEATURES, \
 392         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
 393         .display.has_ddi = 1, \
 394         .has_fpga_dbg = 1, \
 395         .display.has_psr = 1, \
 396         .display.has_dp_mst = 1, \
 397         .has_rc6p = 0 /* RC6p removed-by HSW */, \
 398         .has_runtime_pm = 1
 399
 400 #define HSW_PLATFORM \
 401         G75_FEATURES, \
 402         PLATFORM(INTEL_HASWELL), \
 403         .has_l3_dpf = 1
 404
 405 static const struct intel_device_info intel_haswell_gt1_info = {
 406         HSW_PLATFORM,
 407         .gt = 1,
 408 };
 409
 410 static const struct intel_device_info intel_haswell_gt2_info = {
 411         HSW_PLATFORM,
 412         .gt = 2,
 413 };
 414
 415 static const struct intel_device_info intel_haswell_gt3_info = {
 416         HSW_PLATFORM,
 417         .gt = 3,
 418 };
 419
 420 #define GEN8_FEATURES \
 421         G75_FEATURES, \
 422         GEN(8), \
 423         BDW_COLORS, \
 424         .page_sizes = I915_GTT_PAGE_SIZE_4K | \
 425                       I915_GTT_PAGE_SIZE_2M, \
 426         .has_logical_ring_contexts = 1, \
 427         .ppgtt = INTEL_PPGTT_FULL_4LVL, \
 428         .has_64bit_reloc = 1, \
 429         .has_reset_engine = 1
 430
 431 #define BDW_PLATFORM \
 432         GEN8_FEATURES, \
 433         PLATFORM(INTEL_BROADWELL)
 434
 435 static const struct intel_device_info intel_broadwell_gt1_info = {
 436         BDW_PLATFORM,
 437         .gt = 1,
 438 };
 439
 440 static const struct intel_device_info intel_broadwell_gt2_info = {
 441         BDW_PLATFORM,
 442         .gt = 2,
 443 };
 444
 445 static const struct intel_device_info intel_broadwell_rsvd_info = {
 446         BDW_PLATFORM,
 447         .gt = 3,
 448         /* According to the device ID those devices are GT3, they were
 449          * previously treated as not GT3, keep it like that.
 450          */
 451 };
 452
 453 static const struct intel_device_info intel_broadwell_gt3_info = {
 454         BDW_PLATFORM,
 455         .gt = 3,
 456         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 457 };
 458
 459 static const struct intel_device_info intel_cherryview_info = {
 460         PLATFORM(INTEL_CHERRYVIEW),
 461         GEN(8),
 462         .num_pipes = 3,
 463         .display.has_hotplug = 1,
 464         .is_lp = 1,
 465         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 466         .has_64bit_reloc = 1,
 467         .has_runtime_pm = 1,
 468         .has_rc6 = 1,
 469         .has_logical_ring_contexts = 1,
 470         .display.has_gmch_display = 1,
 471         .ppgtt = INTEL_PPGTT_FULL,
 472         .has_reset_engine = 1,
 473         .has_snoop = true,
 474         .has_coherent_ggtt = false,
 475         .display_mmio_offset = VLV_DISPLAY_BASE,
 476         GEN_DEFAULT_PAGE_SIZES,
 477         GEN_CHV_PIPEOFFSETS,
 478         CURSOR_OFFSETS,
 479         CHV_COLORS,
 480 };
 481
 482 #define GEN9_DEFAULT_PAGE_SIZES \
 483         .page_sizes = I915_GTT_PAGE_SIZE_4K | \
 484                       I915_GTT_PAGE_SIZE_64K | \
 485                       I915_GTT_PAGE_SIZE_2M
 486
 487 #define GEN9_FEATURES \
 488         GEN8_FEATURES, \
 489         GEN(9), \
 490         GEN9_DEFAULT_PAGE_SIZES, \
 491         .has_logical_ring_preemption = 1, \
 492         .display.has_csr = 1, \
 493         .has_guc = 1, \
 494         .display.has_ipc = 1, \
 495         .ddb_size = 896
 496
 497 #define SKL_PLATFORM \
 498         GEN9_FEATURES, \
 499         /* Display WA #0477 WaDisableIPC: skl */ \
 500         .display.has_ipc = 0, \
 501         PLATFORM(INTEL_SKYLAKE)
 502
 503 static const struct intel_device_info intel_skylake_gt1_info = {
 504         SKL_PLATFORM,
 505         .gt = 1,
 506 };
 507
 508 static const struct intel_device_info intel_skylake_gt2_info = {
 509         SKL_PLATFORM,
 510         .gt = 2,
 511 };
 512
 513 #define SKL_GT3_PLUS_PLATFORM \
 514         SKL_PLATFORM, \
 515         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING
 516
 517
 518 static const struct intel_device_info intel_skylake_gt3_info = {
 519         SKL_GT3_PLUS_PLATFORM,
 520         .gt = 3,
 521 };
 522
 523 static const struct intel_device_info intel_skylake_gt4_info = {
 524         SKL_GT3_PLUS_PLATFORM,
 525         .gt = 4,
 526 };
 527
 528 #define GEN9_LP_FEATURES \
 529         GEN(9), \
 530         .is_lp = 1, \
 531         .display.has_hotplug = 1, \
 532         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
 533         .num_pipes = 3, \
 534         .has_64bit_reloc = 1, \
 535         .display.has_ddi = 1, \
 536         .has_fpga_dbg = 1, \
 537         .display.has_fbc = 1, \
 538         .display.has_psr = 1, \
 539         .has_runtime_pm = 1, \
 540         .display.has_csr = 1, \
 541         .has_rc6 = 1, \
 542         .display.has_dp_mst = 1, \
 543         .has_logical_ring_contexts = 1, \
 544         .has_logical_ring_preemption = 1, \
 545         .has_guc = 1, \
 546         .ppgtt = INTEL_PPGTT_FULL_4LVL, \
 547         .has_reset_engine = 1, \
 548         .has_snoop = true, \
 549         .has_coherent_ggtt = false, \
 550         .display.has_ipc = 1, \
 551         GEN9_DEFAULT_PAGE_SIZES, \
 552         GEN_DEFAULT_PIPEOFFSETS, \
 553         IVB_CURSOR_OFFSETS, \
 554         BDW_COLORS
 555
 556 static const struct intel_device_info intel_broxton_info = {
 557         GEN9_LP_FEATURES,
 558         PLATFORM(INTEL_BROXTON),
 559         .ddb_size = 512,
 560 };
 561
 562 static const struct intel_device_info intel_geminilake_info = {
 563         GEN9_LP_FEATURES,
 564         PLATFORM(INTEL_GEMINILAKE),
 565         .ddb_size = 1024,
 566         GLK_COLORS,
 567 };
 568
 569 #define KBL_PLATFORM \
 570         GEN9_FEATURES, \
 571         PLATFORM(INTEL_KABYLAKE)
 572
 573 static const struct intel_device_info intel_kabylake_gt1_info = {
 574         KBL_PLATFORM,
 575         .gt = 1,
 576 };
 577
 578 static const struct intel_device_info intel_kabylake_gt2_info = {
 579         KBL_PLATFORM,
 580         .gt = 2,
 581 };
 582
 583 static const struct intel_device_info intel_kabylake_gt3_info = {
 584         KBL_PLATFORM,
 585         .gt = 3,
 586         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 587 };
 588
 589 #define CFL_PLATFORM \
 590         GEN9_FEATURES, \
 591         PLATFORM(INTEL_COFFEELAKE)
 592
 593 static const struct intel_device_info intel_coffeelake_gt1_info = {
 594         CFL_PLATFORM,
 595         .gt = 1,
 596 };
 597
 598 static const struct intel_device_info intel_coffeelake_gt2_info = {
 599         CFL_PLATFORM,
 600         .gt = 2,
 601 };
 602
 603 static const struct intel_device_info intel_coffeelake_gt3_info = {
 604         CFL_PLATFORM,
 605         .gt = 3,
 606         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 607 };
 608
 609 #define GEN10_FEATURES \
 610         GEN9_FEATURES, \
 611         GEN(10), \
 612         .ddb_size = 1024, \
 613         .has_coherent_ggtt = false, \
 614         GLK_COLORS
 615
 616 static const struct intel_device_info intel_cannonlake_info = {
 617         GEN10_FEATURES,
 618         PLATFORM(INTEL_CANNONLAKE),
 619         .gt = 2,
 620 };
 621
 622 #define GEN11_FEATURES \
 623         GEN10_FEATURES, \
 624         .pipe_offsets = { \
 625                 [TRANSCODER_A] = PIPE_A_OFFSET, \
 626                 [TRANSCODER_B] = PIPE_B_OFFSET, \
 627                 [TRANSCODER_C] = PIPE_C_OFFSET, \
 628                 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
 629                 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
 630                 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
 631         }, \
 632         .trans_offsets = { \
 633                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
 634                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
 635                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
 636                 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
 637                 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
 638                 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
 639         }, \
 640         GEN(11), \
 641         .ddb_size = 2048, \
 642         .has_logical_ring_elsq = 1
 643
 644 static const struct intel_device_info intel_icelake_11_info = {
 645         GEN11_FEATURES,
 646         PLATFORM(INTEL_ICELAKE),
 647         .is_alpha_support = 1,
 648         .ring_mask = RENDER_RING | BLT_RING | VEBOX_RING | BSD_RING | BSD3_RING,
 649 };
 650
 651 #undef GEN
 652 #undef PLATFORM
 653
 654 /*
 655  * Make sure any device matches here are from most specific to most
 656  * general.  For example, since the Quanta match is based on the subsystem
 657  * and subvendor IDs, we need it to come before the more general IVB
 658  * PCI ID matches, otherwise we'll use the wrong info struct above.
 659  */
 660 static const struct pci_device_id pciidlist[] = {
 661         INTEL_I830_IDS(&intel_i830_info),
 662         INTEL_I845G_IDS(&intel_i845g_info),
 663         INTEL_I85X_IDS(&intel_i85x_info),
 664         INTEL_I865G_IDS(&intel_i865g_info),
 665         INTEL_I915G_IDS(&intel_i915g_info),
 666         INTEL_I915GM_IDS(&intel_i915gm_info),
 667         INTEL_I945G_IDS(&intel_i945g_info),
 668         INTEL_I945GM_IDS(&intel_i945gm_info),
 669         INTEL_I965G_IDS(&intel_i965g_info),
 670         INTEL_G33_IDS(&intel_g33_info),
 671         INTEL_I965GM_IDS(&intel_i965gm_info),
 672         INTEL_GM45_IDS(&intel_gm45_info),
 673         INTEL_G45_IDS(&intel_g45_info),
 674         INTEL_PINEVIEW_IDS(&intel_pineview_info),
 675         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
 676         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
 677         INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info),
 678         INTEL_SNB_D_GT2_IDS(&intel_sandybridge_d_gt2_info),
 679         INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info),
 680         INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info),
 681         INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
 682         INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info),
 683         INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info),
 684         INTEL_IVB_D_GT1_IDS(&intel_ivybridge_d_gt1_info),
 685         INTEL_IVB_D_GT2_IDS(&intel_ivybridge_d_gt2_info),
 686         INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info),
 687         INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info),
 688         INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info),
 689         INTEL_VLV_IDS(&intel_valleyview_info),
 690         INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info),
 691         INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info),
 692         INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
 693         INTEL_BDW_RSVD_IDS(&intel_broadwell_rsvd_info),
 694         INTEL_CHV_IDS(&intel_cherryview_info),
 695         INTEL_SKL_GT1_IDS(&intel_skylake_gt1_info),
 696         INTEL_SKL_GT2_IDS(&intel_skylake_gt2_info),
 697         INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
 698         INTEL_SKL_GT4_IDS(&intel_skylake_gt4_info),
 699         INTEL_BXT_IDS(&intel_broxton_info),
 700         INTEL_GLK_IDS(&intel_geminilake_info),
 701         INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info),
 702         INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info),
 703         INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
 704         INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
 705         INTEL_AML_KBL_GT2_IDS(&intel_kabylake_gt2_info),
 706         INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info),
 707         INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),
 708         INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),
 709         INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info),
 710         INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
 711         INTEL_WHL_U_GT1_IDS(&intel_coffeelake_gt1_info),
 712         INTEL_WHL_U_GT2_IDS(&intel_coffeelake_gt2_info),
 713         INTEL_AML_CFL_GT2_IDS(&intel_coffeelake_gt2_info),
 714         INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info),
 715         INTEL_CNL_IDS(&intel_cannonlake_info),
 716         INTEL_ICL_11_IDS(&intel_icelake_11_info),
 717         {0, 0, 0}
 718 };
 719 MODULE_DEVICE_TABLE(pci, pciidlist);
 720
 721 static void i915_pci_remove(struct pci_dev *pdev)
 722 {
 723         struct drm_device *dev;
 724
 725         dev = pci_get_drvdata(pdev);
 726         if (!dev) /* driver load aborted, nothing to cleanup */
 727                 return;
 728
 729         i915_driver_unload(dev);
 730         drm_dev_put(dev);
 731
 732         pci_set_drvdata(pdev, NULL);
 733 }
 734
 735 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 736 {
 737         struct intel_device_info *intel_info =
 738                 (struct intel_device_info *) ent->driver_data;
 739         int err;
 740
 741         if (IS_ALPHA_SUPPORT(intel_info) && !i915_modparams.alpha_support) {
 742                 DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n"
 743                          "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n"
 744                          "to enable support in this kernel version, or check for kernel updates.\n");
 745                 return -ENODEV;
 746         }
 747
 748         /* Only bind to function 0 of the device. Early generations
 749          * used function 1 as a placeholder for multi-head. This causes
 750          * us confusion instead, especially on the systems where both
 751          * functions have the same PCI-ID!
 752          */
 753         if (PCI_FUNC(pdev->devfn))
 754                 return -ENODEV;
 755
 756         /*
 757          * apple-gmux is needed on dual GPU MacBook Pro
 758          * to probe the panel if we're the inactive GPU.
 759          */
 760         if (vga_switcheroo_client_probe_defer(pdev))
 761                 return -EPROBE_DEFER;
 762
 763         err = i915_driver_load(pdev, ent);
 764         if (err)
 765                 return err;
 766
 767         if (i915_inject_load_failure()) {
 768                 i915_pci_remove(pdev);
 769                 return -ENODEV;
 770         }
 771
 772         err = i915_live_selftests(pdev);
 773         if (err) {
 774                 i915_pci_remove(pdev);
 775                 return err > 0 ? -ENOTTY : err;
 776         }
 777
 778         return 0;
 779 }
 780
 781 static struct pci_driver i915_pci_driver = {
 782         .name = DRIVER_NAME,
 783         .id_table = pciidlist,
 784         .probe = i915_pci_probe,
 785         .remove = i915_pci_remove,
 786         .driver.pm = &i915_pm_ops,
 787 };
 788
 789 static int __init i915_init(void)
 790 {
 791         bool use_kms = true;
 792         int err;
 793
 794         err = i915_mock_selftests();
 795         if (err)
 796                 return err > 0 ? 0 : err;
 797
 798         /*
 799          * Enable KMS by default, unless explicitly overriden by
 800          * either the i915.modeset prarameter or by the
 801          * vga_text_mode_force boot option.
 802          */
 803
 804         if (i915_modparams.modeset == 0)
 805                 use_kms = false;
 806
 807         if (vgacon_text_force() && i915_modparams.modeset == -1)
 808                 use_kms = false;
 809
 810         if (!use_kms) {
 811                 /* Silently fail loading to not upset userspace. */
 812                 DRM_DEBUG_DRIVER("KMS disabled.\n");
 813                 return 0;
 814         }
 815
 816         return pci_register_driver(&i915_pci_driver);
 817 }
 818
 819 static void __exit i915_exit(void)
 820 {
 821         if (!i915_pci_driver.driver.owner)
 822                 return;
 823
 824         pci_unregister_driver(&i915_pci_driver);
 825 }
 826
 827 module_init(i915_init);
 828 module_exit(i915_exit);
 829
 830 MODULE_AUTHOR("Tungsten Graphics, Inc.");
 831 MODULE_AUTHOR("Intel Corporation");
 832
 833 MODULE_DESCRIPTION(DRIVER_DESC);
 834 MODULE_LICENSE("GPL and additional rights");