2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include <linux/console.h>
26 #include <linux/vgaarb.h>
27 #include <linux/vga_switcheroo.h>
30 #include "i915_selftest.h"
32 #define PLATFORM(x) .platform = (x), .platform_mask = BIT(x)
33 #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
35 #define GEN_DEFAULT_PIPEOFFSETS \
37 [TRANSCODER_A] = PIPE_A_OFFSET, \
38 [TRANSCODER_B] = PIPE_B_OFFSET, \
39 [TRANSCODER_C] = PIPE_C_OFFSET, \
40 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
43 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
44 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
45 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
46 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
49 #define GEN_CHV_PIPEOFFSETS \
51 [TRANSCODER_A] = PIPE_A_OFFSET, \
52 [TRANSCODER_B] = PIPE_B_OFFSET, \
53 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
56 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
57 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
58 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
61 #define CURSOR_OFFSETS \
62 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
64 #define IVB_CURSOR_OFFSETS \
65 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
68 .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
70 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
72 .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
74 /* Keep in gen based order, and chronological order within a gen */
76 #define GEN_DEFAULT_PAGE_SIZES \
77 .page_sizes = I915_GTT_PAGE_SIZE_4K
79 #define GEN2_FEATURES \
82 .display.has_overlay = 1, \
83 .display.overlay_needs_physical = 1, \
84 .display.has_gmch_display = 1, \
85 .gpu_reset_clobbers_display = true, \
86 .hws_needs_physical = 1, \
87 .unfenced_needs_alignment = 1, \
88 .ring_mask = RENDER_RING, \
90 .has_coherent_ggtt = false, \
91 GEN_DEFAULT_PIPEOFFSETS, \
92 GEN_DEFAULT_PAGE_SIZES, \
95 static const struct intel_device_info intel_i830_info = {
99 .display.cursor_needs_physical = 1,
100 .num_pipes = 2, /* legal, last one wins */
103 static const struct intel_device_info intel_i845g_info = {
105 PLATFORM(INTEL_I845G),
108 static const struct intel_device_info intel_i85x_info = {
110 PLATFORM(INTEL_I85X),
112 .num_pipes = 2, /* legal, last one wins */
113 .display.cursor_needs_physical = 1,
114 .display.has_fbc = 1,
117 static const struct intel_device_info intel_i865g_info = {
119 PLATFORM(INTEL_I865G),
122 #define GEN3_FEATURES \
125 .display.has_gmch_display = 1, \
126 .gpu_reset_clobbers_display = true, \
127 .ring_mask = RENDER_RING, \
129 .has_coherent_ggtt = true, \
130 GEN_DEFAULT_PIPEOFFSETS, \
131 GEN_DEFAULT_PAGE_SIZES, \
134 static const struct intel_device_info intel_i915g_info = {
136 PLATFORM(INTEL_I915G),
137 .has_coherent_ggtt = false,
138 .display.cursor_needs_physical = 1,
139 .display.has_overlay = 1,
140 .display.overlay_needs_physical = 1,
141 .hws_needs_physical = 1,
142 .unfenced_needs_alignment = 1,
145 static const struct intel_device_info intel_i915gm_info = {
147 PLATFORM(INTEL_I915GM),
149 .display.cursor_needs_physical = 1,
150 .display.has_overlay = 1,
151 .display.overlay_needs_physical = 1,
152 .display.supports_tv = 1,
153 .display.has_fbc = 1,
154 .hws_needs_physical = 1,
155 .unfenced_needs_alignment = 1,
158 static const struct intel_device_info intel_i945g_info = {
160 PLATFORM(INTEL_I945G),
161 .display.has_hotplug = 1,
162 .display.cursor_needs_physical = 1,
163 .display.has_overlay = 1,
164 .display.overlay_needs_physical = 1,
165 .hws_needs_physical = 1,
166 .unfenced_needs_alignment = 1,
169 static const struct intel_device_info intel_i945gm_info = {
171 PLATFORM(INTEL_I945GM),
173 .display.has_hotplug = 1,
174 .display.cursor_needs_physical = 1,
175 .display.has_overlay = 1,
176 .display.overlay_needs_physical = 1,
177 .display.supports_tv = 1,
178 .display.has_fbc = 1,
179 .hws_needs_physical = 1,
180 .unfenced_needs_alignment = 1,
183 static const struct intel_device_info intel_g33_info = {
186 .display.has_hotplug = 1,
187 .display.has_overlay = 1,
190 static const struct intel_device_info intel_pineview_info = {
192 PLATFORM(INTEL_PINEVIEW),
194 .display.has_hotplug = 1,
195 .display.has_overlay = 1,
198 #define GEN4_FEATURES \
201 .display.has_hotplug = 1, \
202 .display.has_gmch_display = 1, \
203 .gpu_reset_clobbers_display = true, \
204 .ring_mask = RENDER_RING, \
206 .has_coherent_ggtt = true, \
207 GEN_DEFAULT_PIPEOFFSETS, \
208 GEN_DEFAULT_PAGE_SIZES, \
211 static const struct intel_device_info intel_i965g_info = {
213 PLATFORM(INTEL_I965G),
214 .display.has_overlay = 1,
215 .hws_needs_physical = 1,
219 static const struct intel_device_info intel_i965gm_info = {
221 PLATFORM(INTEL_I965GM),
223 .display.has_fbc = 1,
224 .display.has_overlay = 1,
225 .display.supports_tv = 1,
226 .hws_needs_physical = 1,
230 static const struct intel_device_info intel_g45_info = {
233 .ring_mask = RENDER_RING | BSD_RING,
234 .gpu_reset_clobbers_display = false,
237 static const struct intel_device_info intel_gm45_info = {
239 PLATFORM(INTEL_GM45),
241 .display.has_fbc = 1,
242 .display.supports_tv = 1,
243 .ring_mask = RENDER_RING | BSD_RING,
244 .gpu_reset_clobbers_display = false,
247 #define GEN5_FEATURES \
250 .display.has_hotplug = 1, \
251 .ring_mask = RENDER_RING | BSD_RING, \
253 .has_coherent_ggtt = true, \
254 /* ilk does support rc6, but we do not implement [power] contexts */ \
256 GEN_DEFAULT_PIPEOFFSETS, \
257 GEN_DEFAULT_PAGE_SIZES, \
260 static const struct intel_device_info intel_ironlake_d_info = {
262 PLATFORM(INTEL_IRONLAKE),
265 static const struct intel_device_info intel_ironlake_m_info = {
267 PLATFORM(INTEL_IRONLAKE),
269 .display.has_fbc = 1,
272 #define GEN6_FEATURES \
275 .display.has_hotplug = 1, \
276 .display.has_fbc = 1, \
277 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
278 .has_coherent_ggtt = true, \
282 .ppgtt = INTEL_PPGTT_ALIASING, \
283 GEN_DEFAULT_PIPEOFFSETS, \
284 GEN_DEFAULT_PAGE_SIZES, \
287 #define SNB_D_PLATFORM \
289 PLATFORM(INTEL_SANDYBRIDGE)
291 static const struct intel_device_info intel_sandybridge_d_gt1_info = {
296 static const struct intel_device_info intel_sandybridge_d_gt2_info = {
301 #define SNB_M_PLATFORM \
303 PLATFORM(INTEL_SANDYBRIDGE), \
307 static const struct intel_device_info intel_sandybridge_m_gt1_info = {
312 static const struct intel_device_info intel_sandybridge_m_gt2_info = {
317 #define GEN7_FEATURES \
320 .display.has_hotplug = 1, \
321 .display.has_fbc = 1, \
322 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
323 .has_coherent_ggtt = true, \
327 .ppgtt = INTEL_PPGTT_FULL, \
328 GEN_DEFAULT_PIPEOFFSETS, \
329 GEN_DEFAULT_PAGE_SIZES, \
332 #define IVB_D_PLATFORM \
334 PLATFORM(INTEL_IVYBRIDGE), \
337 static const struct intel_device_info intel_ivybridge_d_gt1_info = {
342 static const struct intel_device_info intel_ivybridge_d_gt2_info = {
347 #define IVB_M_PLATFORM \
349 PLATFORM(INTEL_IVYBRIDGE), \
353 static const struct intel_device_info intel_ivybridge_m_gt1_info = {
358 static const struct intel_device_info intel_ivybridge_m_gt2_info = {
363 static const struct intel_device_info intel_ivybridge_q_info = {
365 PLATFORM(INTEL_IVYBRIDGE),
367 .num_pipes = 0, /* legal, last one wins */
371 static const struct intel_device_info intel_valleyview_info = {
372 PLATFORM(INTEL_VALLEYVIEW),
378 .display.has_gmch_display = 1,
379 .display.has_hotplug = 1,
380 .ppgtt = INTEL_PPGTT_FULL,
382 .has_coherent_ggtt = false,
383 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
384 .display_mmio_offset = VLV_DISPLAY_BASE,
385 GEN_DEFAULT_PAGE_SIZES,
386 GEN_DEFAULT_PIPEOFFSETS,
390 #define G75_FEATURES \
392 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
393 .display.has_ddi = 1, \
395 .display.has_psr = 1, \
396 .display.has_dp_mst = 1, \
397 .has_rc6p = 0 /* RC6p removed-by HSW */, \
400 #define HSW_PLATFORM \
402 PLATFORM(INTEL_HASWELL), \
405 static const struct intel_device_info intel_haswell_gt1_info = {
410 static const struct intel_device_info intel_haswell_gt2_info = {
415 static const struct intel_device_info intel_haswell_gt3_info = {
420 #define GEN8_FEATURES \
424 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
425 I915_GTT_PAGE_SIZE_2M, \
426 .has_logical_ring_contexts = 1, \
427 .ppgtt = INTEL_PPGTT_FULL_4LVL, \
428 .has_64bit_reloc = 1, \
429 .has_reset_engine = 1
431 #define BDW_PLATFORM \
433 PLATFORM(INTEL_BROADWELL)
435 static const struct intel_device_info intel_broadwell_gt1_info = {
440 static const struct intel_device_info intel_broadwell_gt2_info = {
445 static const struct intel_device_info intel_broadwell_rsvd_info = {
448 /* According to the device ID those devices are GT3, they were
449 * previously treated as not GT3, keep it like that.
453 static const struct intel_device_info intel_broadwell_gt3_info = {
456 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
459 static const struct intel_device_info intel_cherryview_info = {
460 PLATFORM(INTEL_CHERRYVIEW),
463 .display.has_hotplug = 1,
465 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
466 .has_64bit_reloc = 1,
469 .has_logical_ring_contexts = 1,
470 .display.has_gmch_display = 1,
471 .ppgtt = INTEL_PPGTT_FULL,
472 .has_reset_engine = 1,
474 .has_coherent_ggtt = false,
475 .display_mmio_offset = VLV_DISPLAY_BASE,
476 GEN_DEFAULT_PAGE_SIZES,
482 #define GEN9_DEFAULT_PAGE_SIZES \
483 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
484 I915_GTT_PAGE_SIZE_64K | \
485 I915_GTT_PAGE_SIZE_2M
487 #define GEN9_FEATURES \
490 GEN9_DEFAULT_PAGE_SIZES, \
491 .has_logical_ring_preemption = 1, \
492 .display.has_csr = 1, \
494 .display.has_ipc = 1, \
497 #define SKL_PLATFORM \
499 /* Display WA #0477 WaDisableIPC: skl */ \
500 .display.has_ipc = 0, \
501 PLATFORM(INTEL_SKYLAKE)
503 static const struct intel_device_info intel_skylake_gt1_info = {
508 static const struct intel_device_info intel_skylake_gt2_info = {
513 #define SKL_GT3_PLUS_PLATFORM \
515 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING
518 static const struct intel_device_info intel_skylake_gt3_info = {
519 SKL_GT3_PLUS_PLATFORM,
523 static const struct intel_device_info intel_skylake_gt4_info = {
524 SKL_GT3_PLUS_PLATFORM,
528 #define GEN9_LP_FEATURES \
531 .display.has_hotplug = 1, \
532 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
534 .has_64bit_reloc = 1, \
535 .display.has_ddi = 1, \
537 .display.has_fbc = 1, \
538 .display.has_psr = 1, \
539 .has_runtime_pm = 1, \
540 .display.has_csr = 1, \
542 .display.has_dp_mst = 1, \
543 .has_logical_ring_contexts = 1, \
544 .has_logical_ring_preemption = 1, \
546 .ppgtt = INTEL_PPGTT_FULL_4LVL, \
547 .has_reset_engine = 1, \
549 .has_coherent_ggtt = false, \
550 .display.has_ipc = 1, \
551 GEN9_DEFAULT_PAGE_SIZES, \
552 GEN_DEFAULT_PIPEOFFSETS, \
553 IVB_CURSOR_OFFSETS, \
556 static const struct intel_device_info intel_broxton_info = {
558 PLATFORM(INTEL_BROXTON),
562 static const struct intel_device_info intel_geminilake_info = {
564 PLATFORM(INTEL_GEMINILAKE),
569 #define KBL_PLATFORM \
571 PLATFORM(INTEL_KABYLAKE)
573 static const struct intel_device_info intel_kabylake_gt1_info = {
578 static const struct intel_device_info intel_kabylake_gt2_info = {
583 static const struct intel_device_info intel_kabylake_gt3_info = {
586 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
589 #define CFL_PLATFORM \
591 PLATFORM(INTEL_COFFEELAKE)
593 static const struct intel_device_info intel_coffeelake_gt1_info = {
598 static const struct intel_device_info intel_coffeelake_gt2_info = {
603 static const struct intel_device_info intel_coffeelake_gt3_info = {
606 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
609 #define GEN10_FEATURES \
613 .has_coherent_ggtt = false, \
616 static const struct intel_device_info intel_cannonlake_info = {
618 PLATFORM(INTEL_CANNONLAKE),
622 #define GEN11_FEATURES \
625 [TRANSCODER_A] = PIPE_A_OFFSET, \
626 [TRANSCODER_B] = PIPE_B_OFFSET, \
627 [TRANSCODER_C] = PIPE_C_OFFSET, \
628 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
629 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
630 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
633 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
634 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
635 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
636 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
637 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
638 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
642 .has_logical_ring_elsq = 1
644 static const struct intel_device_info intel_icelake_11_info = {
646 PLATFORM(INTEL_ICELAKE),
647 .is_alpha_support = 1,
648 .ring_mask = RENDER_RING | BLT_RING | VEBOX_RING | BSD_RING | BSD3_RING,
655 * Make sure any device matches here are from most specific to most
656 * general. For example, since the Quanta match is based on the subsystem
657 * and subvendor IDs, we need it to come before the more general IVB
658 * PCI ID matches, otherwise we'll use the wrong info struct above.
660 static const struct pci_device_id pciidlist[] = {
661 INTEL_I830_IDS(&intel_i830_info),
662 INTEL_I845G_IDS(&intel_i845g_info),
663 INTEL_I85X_IDS(&intel_i85x_info),
664 INTEL_I865G_IDS(&intel_i865g_info),
665 INTEL_I915G_IDS(&intel_i915g_info),
666 INTEL_I915GM_IDS(&intel_i915gm_info),
667 INTEL_I945G_IDS(&intel_i945g_info),
668 INTEL_I945GM_IDS(&intel_i945gm_info),
669 INTEL_I965G_IDS(&intel_i965g_info),
670 INTEL_G33_IDS(&intel_g33_info),
671 INTEL_I965GM_IDS(&intel_i965gm_info),
672 INTEL_GM45_IDS(&intel_gm45_info),
673 INTEL_G45_IDS(&intel_g45_info),
674 INTEL_PINEVIEW_IDS(&intel_pineview_info),
675 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
676 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
677 INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info),
678 INTEL_SNB_D_GT2_IDS(&intel_sandybridge_d_gt2_info),
679 INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info),
680 INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info),
681 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
682 INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info),
683 INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info),
684 INTEL_IVB_D_GT1_IDS(&intel_ivybridge_d_gt1_info),
685 INTEL_IVB_D_GT2_IDS(&intel_ivybridge_d_gt2_info),
686 INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info),
687 INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info),
688 INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info),
689 INTEL_VLV_IDS(&intel_valleyview_info),
690 INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info),
691 INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info),
692 INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
693 INTEL_BDW_RSVD_IDS(&intel_broadwell_rsvd_info),
694 INTEL_CHV_IDS(&intel_cherryview_info),
695 INTEL_SKL_GT1_IDS(&intel_skylake_gt1_info),
696 INTEL_SKL_GT2_IDS(&intel_skylake_gt2_info),
697 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
698 INTEL_SKL_GT4_IDS(&intel_skylake_gt4_info),
699 INTEL_BXT_IDS(&intel_broxton_info),
700 INTEL_GLK_IDS(&intel_geminilake_info),
701 INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info),
702 INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info),
703 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
704 INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
705 INTEL_AML_KBL_GT2_IDS(&intel_kabylake_gt2_info),
706 INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info),
707 INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),
708 INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),
709 INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info),
710 INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
711 INTEL_WHL_U_GT1_IDS(&intel_coffeelake_gt1_info),
712 INTEL_WHL_U_GT2_IDS(&intel_coffeelake_gt2_info),
713 INTEL_AML_CFL_GT2_IDS(&intel_coffeelake_gt2_info),
714 INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info),
715 INTEL_CNL_IDS(&intel_cannonlake_info),
716 INTEL_ICL_11_IDS(&intel_icelake_11_info),
719 MODULE_DEVICE_TABLE(pci, pciidlist);
721 static void i915_pci_remove(struct pci_dev *pdev)
723 struct drm_device *dev;
725 dev = pci_get_drvdata(pdev);
726 if (!dev) /* driver load aborted, nothing to cleanup */
729 i915_driver_unload(dev);
732 pci_set_drvdata(pdev, NULL);
735 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
737 struct intel_device_info *intel_info =
738 (struct intel_device_info *) ent->driver_data;
741 if (IS_ALPHA_SUPPORT(intel_info) && !i915_modparams.alpha_support) {
742 DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n"
743 "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n"
744 "to enable support in this kernel version, or check for kernel updates.\n");
748 /* Only bind to function 0 of the device. Early generations
749 * used function 1 as a placeholder for multi-head. This causes
750 * us confusion instead, especially on the systems where both
751 * functions have the same PCI-ID!
753 if (PCI_FUNC(pdev->devfn))
757 * apple-gmux is needed on dual GPU MacBook Pro
758 * to probe the panel if we're the inactive GPU.
760 if (vga_switcheroo_client_probe_defer(pdev))
761 return -EPROBE_DEFER;
763 err = i915_driver_load(pdev, ent);
767 if (i915_inject_load_failure()) {
768 i915_pci_remove(pdev);
772 err = i915_live_selftests(pdev);
774 i915_pci_remove(pdev);
775 return err > 0 ? -ENOTTY : err;
781 static struct pci_driver i915_pci_driver = {
783 .id_table = pciidlist,
784 .probe = i915_pci_probe,
785 .remove = i915_pci_remove,
786 .driver.pm = &i915_pm_ops,
789 static int __init i915_init(void)
794 err = i915_mock_selftests();
796 return err > 0 ? 0 : err;
799 * Enable KMS by default, unless explicitly overriden by
800 * either the i915.modeset prarameter or by the
801 * vga_text_mode_force boot option.
804 if (i915_modparams.modeset == 0)
807 if (vgacon_text_force() && i915_modparams.modeset == -1)
811 /* Silently fail loading to not upset userspace. */
812 DRM_DEBUG_DRIVER("KMS disabled.\n");
816 return pci_register_driver(&i915_pci_driver);
819 static void __exit i915_exit(void)
821 if (!i915_pci_driver.driver.owner)
824 pci_unregister_driver(&i915_pci_driver);
827 module_init(i915_init);
828 module_exit(i915_exit);
830 MODULE_AUTHOR("Tungsten Graphics, Inc.");
831 MODULE_AUTHOR("Intel Corporation");
833 MODULE_DESCRIPTION(DRIVER_DESC);
834 MODULE_LICENSE("GPL and additional rights");