2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include <linux/console.h>
26 #include <linux/vgaarb.h>
27 #include <linux/vga_switcheroo.h>
29 #include <drm/drm_drv.h>
32 #include "i915_globals.h"
33 #include "i915_selftest.h"
35 #define PLATFORM(x) .platform = (x), .platform_mask = BIT(x)
36 #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
38 #define GEN_DEFAULT_PIPEOFFSETS \
40 [TRANSCODER_A] = PIPE_A_OFFSET, \
41 [TRANSCODER_B] = PIPE_B_OFFSET, \
42 [TRANSCODER_C] = PIPE_C_OFFSET, \
43 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
46 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
47 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
48 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
49 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
52 #define GEN_CHV_PIPEOFFSETS \
54 [TRANSCODER_A] = PIPE_A_OFFSET, \
55 [TRANSCODER_B] = PIPE_B_OFFSET, \
56 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
59 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
60 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
61 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
64 #define CURSOR_OFFSETS \
65 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
67 #define IVB_CURSOR_OFFSETS \
68 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
71 .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
73 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \
74 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
75 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
78 .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024, \
79 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
80 DRM_COLOR_LUT_EQUAL_CHANNELS, \
83 /* Keep in gen based order, and chronological order within a gen */
85 #define GEN_DEFAULT_PAGE_SIZES \
86 .page_sizes = I915_GTT_PAGE_SIZE_4K
88 #define GEN2_FEATURES \
91 .display.has_overlay = 1, \
92 .display.overlay_needs_physical = 1, \
93 .display.has_gmch = 1, \
94 .gpu_reset_clobbers_display = true, \
95 .hws_needs_physical = 1, \
96 .unfenced_needs_alignment = 1, \
97 .ring_mask = RENDER_RING, \
99 .has_coherent_ggtt = false, \
100 GEN_DEFAULT_PIPEOFFSETS, \
101 GEN_DEFAULT_PAGE_SIZES, \
104 static const struct intel_device_info intel_i830_info = {
106 PLATFORM(INTEL_I830),
108 .display.cursor_needs_physical = 1,
109 .num_pipes = 2, /* legal, last one wins */
112 static const struct intel_device_info intel_i845g_info = {
114 PLATFORM(INTEL_I845G),
117 static const struct intel_device_info intel_i85x_info = {
119 PLATFORM(INTEL_I85X),
121 .num_pipes = 2, /* legal, last one wins */
122 .display.cursor_needs_physical = 1,
123 .display.has_fbc = 1,
126 static const struct intel_device_info intel_i865g_info = {
128 PLATFORM(INTEL_I865G),
131 #define GEN3_FEATURES \
134 .display.has_gmch = 1, \
135 .gpu_reset_clobbers_display = true, \
136 .ring_mask = RENDER_RING, \
138 .has_coherent_ggtt = true, \
139 GEN_DEFAULT_PIPEOFFSETS, \
140 GEN_DEFAULT_PAGE_SIZES, \
143 static const struct intel_device_info intel_i915g_info = {
145 PLATFORM(INTEL_I915G),
146 .has_coherent_ggtt = false,
147 .display.cursor_needs_physical = 1,
148 .display.has_overlay = 1,
149 .display.overlay_needs_physical = 1,
150 .hws_needs_physical = 1,
151 .unfenced_needs_alignment = 1,
154 static const struct intel_device_info intel_i915gm_info = {
156 PLATFORM(INTEL_I915GM),
158 .display.cursor_needs_physical = 1,
159 .display.has_overlay = 1,
160 .display.overlay_needs_physical = 1,
161 .display.supports_tv = 1,
162 .display.has_fbc = 1,
163 .hws_needs_physical = 1,
164 .unfenced_needs_alignment = 1,
167 static const struct intel_device_info intel_i945g_info = {
169 PLATFORM(INTEL_I945G),
170 .display.has_hotplug = 1,
171 .display.cursor_needs_physical = 1,
172 .display.has_overlay = 1,
173 .display.overlay_needs_physical = 1,
174 .hws_needs_physical = 1,
175 .unfenced_needs_alignment = 1,
178 static const struct intel_device_info intel_i945gm_info = {
180 PLATFORM(INTEL_I945GM),
182 .display.has_hotplug = 1,
183 .display.cursor_needs_physical = 1,
184 .display.has_overlay = 1,
185 .display.overlay_needs_physical = 1,
186 .display.supports_tv = 1,
187 .display.has_fbc = 1,
188 .hws_needs_physical = 1,
189 .unfenced_needs_alignment = 1,
192 static const struct intel_device_info intel_g33_info = {
195 .display.has_hotplug = 1,
196 .display.has_overlay = 1,
199 static const struct intel_device_info intel_pineview_info = {
201 PLATFORM(INTEL_PINEVIEW),
203 .display.has_hotplug = 1,
204 .display.has_overlay = 1,
207 #define GEN4_FEATURES \
210 .display.has_hotplug = 1, \
211 .display.has_gmch = 1, \
212 .gpu_reset_clobbers_display = true, \
213 .ring_mask = RENDER_RING, \
215 .has_coherent_ggtt = true, \
216 GEN_DEFAULT_PIPEOFFSETS, \
217 GEN_DEFAULT_PAGE_SIZES, \
220 static const struct intel_device_info intel_i965g_info = {
222 PLATFORM(INTEL_I965G),
223 .display.has_overlay = 1,
224 .hws_needs_physical = 1,
228 static const struct intel_device_info intel_i965gm_info = {
230 PLATFORM(INTEL_I965GM),
232 .display.has_fbc = 1,
233 .display.has_overlay = 1,
234 .display.supports_tv = 1,
235 .hws_needs_physical = 1,
239 static const struct intel_device_info intel_g45_info = {
242 .ring_mask = RENDER_RING | BSD_RING,
243 .gpu_reset_clobbers_display = false,
246 static const struct intel_device_info intel_gm45_info = {
248 PLATFORM(INTEL_GM45),
250 .display.has_fbc = 1,
251 .display.supports_tv = 1,
252 .ring_mask = RENDER_RING | BSD_RING,
253 .gpu_reset_clobbers_display = false,
256 #define GEN5_FEATURES \
259 .display.has_hotplug = 1, \
260 .ring_mask = RENDER_RING | BSD_RING, \
262 .has_coherent_ggtt = true, \
263 /* ilk does support rc6, but we do not implement [power] contexts */ \
265 GEN_DEFAULT_PIPEOFFSETS, \
266 GEN_DEFAULT_PAGE_SIZES, \
269 static const struct intel_device_info intel_ironlake_d_info = {
271 PLATFORM(INTEL_IRONLAKE),
274 static const struct intel_device_info intel_ironlake_m_info = {
276 PLATFORM(INTEL_IRONLAKE),
278 .display.has_fbc = 1,
281 #define GEN6_FEATURES \
284 .display.has_hotplug = 1, \
285 .display.has_fbc = 1, \
286 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
287 .has_coherent_ggtt = true, \
291 .ppgtt = INTEL_PPGTT_ALIASING, \
292 GEN_DEFAULT_PIPEOFFSETS, \
293 GEN_DEFAULT_PAGE_SIZES, \
296 #define SNB_D_PLATFORM \
298 PLATFORM(INTEL_SANDYBRIDGE)
300 static const struct intel_device_info intel_sandybridge_d_gt1_info = {
305 static const struct intel_device_info intel_sandybridge_d_gt2_info = {
310 #define SNB_M_PLATFORM \
312 PLATFORM(INTEL_SANDYBRIDGE), \
316 static const struct intel_device_info intel_sandybridge_m_gt1_info = {
321 static const struct intel_device_info intel_sandybridge_m_gt2_info = {
326 #define GEN7_FEATURES \
329 .display.has_hotplug = 1, \
330 .display.has_fbc = 1, \
331 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
332 .has_coherent_ggtt = true, \
336 .ppgtt = INTEL_PPGTT_FULL, \
337 GEN_DEFAULT_PIPEOFFSETS, \
338 GEN_DEFAULT_PAGE_SIZES, \
341 #define IVB_D_PLATFORM \
343 PLATFORM(INTEL_IVYBRIDGE), \
346 static const struct intel_device_info intel_ivybridge_d_gt1_info = {
351 static const struct intel_device_info intel_ivybridge_d_gt2_info = {
356 #define IVB_M_PLATFORM \
358 PLATFORM(INTEL_IVYBRIDGE), \
362 static const struct intel_device_info intel_ivybridge_m_gt1_info = {
367 static const struct intel_device_info intel_ivybridge_m_gt2_info = {
372 static const struct intel_device_info intel_ivybridge_q_info = {
374 PLATFORM(INTEL_IVYBRIDGE),
376 .num_pipes = 0, /* legal, last one wins */
380 static const struct intel_device_info intel_valleyview_info = {
381 PLATFORM(INTEL_VALLEYVIEW),
387 .display.has_gmch = 1,
388 .display.has_hotplug = 1,
389 .ppgtt = INTEL_PPGTT_FULL,
391 .has_coherent_ggtt = false,
392 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
393 .display_mmio_offset = VLV_DISPLAY_BASE,
394 GEN_DEFAULT_PAGE_SIZES,
395 GEN_DEFAULT_PIPEOFFSETS,
399 #define G75_FEATURES \
401 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
402 .display.has_ddi = 1, \
404 .display.has_psr = 1, \
405 .display.has_dp_mst = 1, \
406 .has_rc6p = 0 /* RC6p removed-by HSW */, \
409 #define HSW_PLATFORM \
411 PLATFORM(INTEL_HASWELL), \
414 static const struct intel_device_info intel_haswell_gt1_info = {
419 static const struct intel_device_info intel_haswell_gt2_info = {
424 static const struct intel_device_info intel_haswell_gt3_info = {
429 #define GEN8_FEATURES \
433 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
434 I915_GTT_PAGE_SIZE_2M, \
435 .has_logical_ring_contexts = 1, \
436 .ppgtt = INTEL_PPGTT_FULL_4LVL, \
437 .has_64bit_reloc = 1, \
438 .has_reset_engine = 1
440 #define BDW_PLATFORM \
442 PLATFORM(INTEL_BROADWELL)
444 static const struct intel_device_info intel_broadwell_gt1_info = {
449 static const struct intel_device_info intel_broadwell_gt2_info = {
454 static const struct intel_device_info intel_broadwell_rsvd_info = {
457 /* According to the device ID those devices are GT3, they were
458 * previously treated as not GT3, keep it like that.
462 static const struct intel_device_info intel_broadwell_gt3_info = {
465 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
468 static const struct intel_device_info intel_cherryview_info = {
469 PLATFORM(INTEL_CHERRYVIEW),
472 .display.has_hotplug = 1,
474 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
475 .has_64bit_reloc = 1,
478 .has_logical_ring_contexts = 1,
479 .display.has_gmch = 1,
480 .ppgtt = INTEL_PPGTT_FULL,
481 .has_reset_engine = 1,
483 .has_coherent_ggtt = false,
484 .display_mmio_offset = VLV_DISPLAY_BASE,
485 GEN_DEFAULT_PAGE_SIZES,
491 #define GEN9_DEFAULT_PAGE_SIZES \
492 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
493 I915_GTT_PAGE_SIZE_64K | \
494 I915_GTT_PAGE_SIZE_2M
496 #define GEN9_FEATURES \
499 GEN9_DEFAULT_PAGE_SIZES, \
500 .has_logical_ring_preemption = 1, \
501 .display.has_csr = 1, \
503 .display.has_ipc = 1, \
506 #define SKL_PLATFORM \
508 /* Display WA #0477 WaDisableIPC: skl */ \
509 .display.has_ipc = 0, \
510 PLATFORM(INTEL_SKYLAKE)
512 static const struct intel_device_info intel_skylake_gt1_info = {
517 static const struct intel_device_info intel_skylake_gt2_info = {
522 #define SKL_GT3_PLUS_PLATFORM \
524 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING
527 static const struct intel_device_info intel_skylake_gt3_info = {
528 SKL_GT3_PLUS_PLATFORM,
532 static const struct intel_device_info intel_skylake_gt4_info = {
533 SKL_GT3_PLUS_PLATFORM,
537 #define GEN9_LP_FEATURES \
540 .display.has_hotplug = 1, \
541 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
543 .has_64bit_reloc = 1, \
544 .display.has_ddi = 1, \
546 .display.has_fbc = 1, \
547 .display.has_psr = 1, \
548 .has_runtime_pm = 1, \
549 .display.has_csr = 1, \
551 .display.has_dp_mst = 1, \
552 .has_logical_ring_contexts = 1, \
553 .has_logical_ring_preemption = 1, \
555 .ppgtt = INTEL_PPGTT_FULL_4LVL, \
556 .has_reset_engine = 1, \
558 .has_coherent_ggtt = false, \
559 .display.has_ipc = 1, \
560 GEN9_DEFAULT_PAGE_SIZES, \
561 GEN_DEFAULT_PIPEOFFSETS, \
562 IVB_CURSOR_OFFSETS, \
565 static const struct intel_device_info intel_broxton_info = {
567 PLATFORM(INTEL_BROXTON),
571 static const struct intel_device_info intel_geminilake_info = {
573 PLATFORM(INTEL_GEMINILAKE),
578 #define KBL_PLATFORM \
580 PLATFORM(INTEL_KABYLAKE)
582 static const struct intel_device_info intel_kabylake_gt1_info = {
587 static const struct intel_device_info intel_kabylake_gt2_info = {
592 static const struct intel_device_info intel_kabylake_gt3_info = {
595 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
598 #define CFL_PLATFORM \
600 PLATFORM(INTEL_COFFEELAKE)
602 static const struct intel_device_info intel_coffeelake_gt1_info = {
607 static const struct intel_device_info intel_coffeelake_gt2_info = {
612 static const struct intel_device_info intel_coffeelake_gt3_info = {
615 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
618 #define GEN10_FEATURES \
622 .has_coherent_ggtt = false, \
625 static const struct intel_device_info intel_cannonlake_info = {
627 PLATFORM(INTEL_CANNONLAKE),
631 #define GEN11_FEATURES \
634 [TRANSCODER_A] = PIPE_A_OFFSET, \
635 [TRANSCODER_B] = PIPE_B_OFFSET, \
636 [TRANSCODER_C] = PIPE_C_OFFSET, \
637 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
638 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
639 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
642 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
643 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
644 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
645 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
646 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
647 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
651 .has_logical_ring_elsq = 1, \
652 .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024 }
654 static const struct intel_device_info intel_icelake_11_info = {
656 PLATFORM(INTEL_ICELAKE),
657 .is_alpha_support = 1,
658 .ring_mask = RENDER_RING | BLT_RING | VEBOX_RING | BSD_RING | BSD3_RING,
665 * Make sure any device matches here are from most specific to most
666 * general. For example, since the Quanta match is based on the subsystem
667 * and subvendor IDs, we need it to come before the more general IVB
668 * PCI ID matches, otherwise we'll use the wrong info struct above.
670 static const struct pci_device_id pciidlist[] = {
671 INTEL_I830_IDS(&intel_i830_info),
672 INTEL_I845G_IDS(&intel_i845g_info),
673 INTEL_I85X_IDS(&intel_i85x_info),
674 INTEL_I865G_IDS(&intel_i865g_info),
675 INTEL_I915G_IDS(&intel_i915g_info),
676 INTEL_I915GM_IDS(&intel_i915gm_info),
677 INTEL_I945G_IDS(&intel_i945g_info),
678 INTEL_I945GM_IDS(&intel_i945gm_info),
679 INTEL_I965G_IDS(&intel_i965g_info),
680 INTEL_G33_IDS(&intel_g33_info),
681 INTEL_I965GM_IDS(&intel_i965gm_info),
682 INTEL_GM45_IDS(&intel_gm45_info),
683 INTEL_G45_IDS(&intel_g45_info),
684 INTEL_PINEVIEW_IDS(&intel_pineview_info),
685 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
686 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
687 INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info),
688 INTEL_SNB_D_GT2_IDS(&intel_sandybridge_d_gt2_info),
689 INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info),
690 INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info),
691 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
692 INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info),
693 INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info),
694 INTEL_IVB_D_GT1_IDS(&intel_ivybridge_d_gt1_info),
695 INTEL_IVB_D_GT2_IDS(&intel_ivybridge_d_gt2_info),
696 INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info),
697 INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info),
698 INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info),
699 INTEL_VLV_IDS(&intel_valleyview_info),
700 INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info),
701 INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info),
702 INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
703 INTEL_BDW_RSVD_IDS(&intel_broadwell_rsvd_info),
704 INTEL_CHV_IDS(&intel_cherryview_info),
705 INTEL_SKL_GT1_IDS(&intel_skylake_gt1_info),
706 INTEL_SKL_GT2_IDS(&intel_skylake_gt2_info),
707 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
708 INTEL_SKL_GT4_IDS(&intel_skylake_gt4_info),
709 INTEL_BXT_IDS(&intel_broxton_info),
710 INTEL_GLK_IDS(&intel_geminilake_info),
711 INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info),
712 INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info),
713 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
714 INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
715 INTEL_AML_KBL_GT2_IDS(&intel_kabylake_gt2_info),
716 INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info),
717 INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),
718 INTEL_CFL_H_GT1_IDS(&intel_coffeelake_gt1_info),
719 INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),
720 INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info),
721 INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
722 INTEL_WHL_U_GT1_IDS(&intel_coffeelake_gt1_info),
723 INTEL_WHL_U_GT2_IDS(&intel_coffeelake_gt2_info),
724 INTEL_AML_CFL_GT2_IDS(&intel_coffeelake_gt2_info),
725 INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info),
726 INTEL_CNL_IDS(&intel_cannonlake_info),
727 INTEL_ICL_11_IDS(&intel_icelake_11_info),
730 MODULE_DEVICE_TABLE(pci, pciidlist);
732 static void i915_pci_remove(struct pci_dev *pdev)
734 struct drm_device *dev;
736 dev = pci_get_drvdata(pdev);
737 if (!dev) /* driver load aborted, nothing to cleanup */
740 i915_driver_unload(dev);
743 pci_set_drvdata(pdev, NULL);
746 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
748 struct intel_device_info *intel_info =
749 (struct intel_device_info *) ent->driver_data;
752 if (IS_ALPHA_SUPPORT(intel_info) && !i915_modparams.alpha_support) {
753 DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n"
754 "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n"
755 "to enable support in this kernel version, or check for kernel updates.\n");
759 /* Only bind to function 0 of the device. Early generations
760 * used function 1 as a placeholder for multi-head. This causes
761 * us confusion instead, especially on the systems where both
762 * functions have the same PCI-ID!
764 if (PCI_FUNC(pdev->devfn))
768 * apple-gmux is needed on dual GPU MacBook Pro
769 * to probe the panel if we're the inactive GPU.
771 if (vga_switcheroo_client_probe_defer(pdev))
772 return -EPROBE_DEFER;
774 err = i915_driver_load(pdev, ent);
778 if (i915_inject_load_failure()) {
779 i915_pci_remove(pdev);
783 err = i915_live_selftests(pdev);
785 i915_pci_remove(pdev);
786 return err > 0 ? -ENOTTY : err;
792 static struct pci_driver i915_pci_driver = {
794 .id_table = pciidlist,
795 .probe = i915_pci_probe,
796 .remove = i915_pci_remove,
797 .driver.pm = &i915_pm_ops,
800 static int __init i915_init(void)
805 err = i915_globals_init();
809 err = i915_mock_selftests();
811 return err > 0 ? 0 : err;
814 * Enable KMS by default, unless explicitly overriden by
815 * either the i915.modeset prarameter or by the
816 * vga_text_mode_force boot option.
819 if (i915_modparams.modeset == 0)
822 if (vgacon_text_force() && i915_modparams.modeset == -1)
826 /* Silently fail loading to not upset userspace. */
827 DRM_DEBUG_DRIVER("KMS disabled.\n");
831 return pci_register_driver(&i915_pci_driver);
834 static void __exit i915_exit(void)
836 if (!i915_pci_driver.driver.owner)
839 pci_unregister_driver(&i915_pci_driver);
843 module_init(i915_init);
844 module_exit(i915_exit);
846 MODULE_AUTHOR("Tungsten Graphics, Inc.");
847 MODULE_AUTHOR("Intel Corporation");
849 MODULE_DESCRIPTION(DRIVER_DESC);
850 MODULE_LICENSE("GPL and additional rights");