drivers/gpu/drm/i915/i915_pci.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <linux/console.h>
  26 #include <linux/vgaarb.h>
  27 #include <linux/vga_switcheroo.h>
  28
  29 #include "i915_drv.h"
  30 #include "i915_selftest.h"
  31
  32 #define PLATFORM(x) .platform = (x), .platform_mask = BIT(x)
  33 #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
  34
  35 #define GEN_DEFAULT_PIPEOFFSETS \
  36         .pipe_offsets = { \
  37                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  38                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  39                 [TRANSCODER_C] = PIPE_C_OFFSET, \
  40                 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
  41         }, \
  42         .trans_offsets = { \
  43                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  44                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  45                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
  46                 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
  47         }
  48
  49 #define GEN_CHV_PIPEOFFSETS \
  50         .pipe_offsets = { \
  51                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  52                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  53                 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
  54         }, \
  55         .trans_offsets = { \
  56                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  57                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  58                 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
  59         }
  60
  61 #define CURSOR_OFFSETS \
  62         .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
  63
  64 #define IVB_CURSOR_OFFSETS \
  65         .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
  66
  67 #define BDW_COLORS \
  68         .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
  69 #define CHV_COLORS \
  70         .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
  71 #define GLK_COLORS \
  72         .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
  73
  74 /* Keep in gen based order, and chronological order within a gen */
  75
  76 #define GEN_DEFAULT_PAGE_SIZES \
  77         .page_sizes = I915_GTT_PAGE_SIZE_4K
  78
  79 #define GEN2_FEATURES \
  80         GEN(2), \
  81         .num_pipes = 1, \
  82         .display.has_overlay = 1, \
  83         .display.overlay_needs_physical = 1, \
  84         .display.has_gmch_display = 1, \
  85         .hws_needs_physical = 1, \
  86         .unfenced_needs_alignment = 1, \
  87         .ring_mask = RENDER_RING, \
  88         .has_snoop = true, \
  89         .has_coherent_ggtt = false, \
  90         GEN_DEFAULT_PIPEOFFSETS, \
  91         GEN_DEFAULT_PAGE_SIZES, \
  92         CURSOR_OFFSETS
  93
  94 static const struct intel_device_info intel_i830_info = {
  95         GEN2_FEATURES,
  96         PLATFORM(INTEL_I830),
  97         .is_mobile = 1,
  98         .display.cursor_needs_physical = 1,
  99         .num_pipes = 2, /* legal, last one wins */
 100 };
 101
 102 static const struct intel_device_info intel_i845g_info = {
 103         GEN2_FEATURES,
 104         PLATFORM(INTEL_I845G),
 105 };
 106
 107 static const struct intel_device_info intel_i85x_info = {
 108         GEN2_FEATURES,
 109         PLATFORM(INTEL_I85X),
 110         .is_mobile = 1,
 111         .num_pipes = 2, /* legal, last one wins */
 112         .display.cursor_needs_physical = 1,
 113         .display.has_fbc = 1,
 114 };
 115
 116 static const struct intel_device_info intel_i865g_info = {
 117         GEN2_FEATURES,
 118         PLATFORM(INTEL_I865G),
 119 };
 120
 121 #define GEN3_FEATURES \
 122         GEN(3), \
 123         .num_pipes = 2, \
 124         .display.has_gmch_display = 1, \
 125         .ring_mask = RENDER_RING, \
 126         .has_snoop = true, \
 127         .has_coherent_ggtt = true, \
 128         GEN_DEFAULT_PIPEOFFSETS, \
 129         GEN_DEFAULT_PAGE_SIZES, \
 130         CURSOR_OFFSETS
 131
 132 static const struct intel_device_info intel_i915g_info = {
 133         GEN3_FEATURES,
 134         PLATFORM(INTEL_I915G),
 135         .has_coherent_ggtt = false,
 136         .display.cursor_needs_physical = 1,
 137         .display.has_overlay = 1,
 138         .display.overlay_needs_physical = 1,
 139         .hws_needs_physical = 1,
 140         .unfenced_needs_alignment = 1,
 141 };
 142
 143 static const struct intel_device_info intel_i915gm_info = {
 144         GEN3_FEATURES,
 145         PLATFORM(INTEL_I915GM),
 146         .is_mobile = 1,
 147         .display.cursor_needs_physical = 1,
 148         .display.has_overlay = 1,
 149         .display.overlay_needs_physical = 1,
 150         .display.supports_tv = 1,
 151         .display.has_fbc = 1,
 152         .hws_needs_physical = 1,
 153         .unfenced_needs_alignment = 1,
 154 };
 155
 156 static const struct intel_device_info intel_i945g_info = {
 157         GEN3_FEATURES,
 158         PLATFORM(INTEL_I945G),
 159         .display.has_hotplug = 1,
 160         .display.cursor_needs_physical = 1,
 161         .display.has_overlay = 1,
 162         .display.overlay_needs_physical = 1,
 163         .hws_needs_physical = 1,
 164         .unfenced_needs_alignment = 1,
 165 };
 166
 167 static const struct intel_device_info intel_i945gm_info = {
 168         GEN3_FEATURES,
 169         PLATFORM(INTEL_I945GM),
 170         .is_mobile = 1,
 171         .display.has_hotplug = 1,
 172         .display.cursor_needs_physical = 1,
 173         .display.has_overlay = 1,
 174         .display.overlay_needs_physical = 1,
 175         .display.supports_tv = 1,
 176         .display.has_fbc = 1,
 177         .hws_needs_physical = 1,
 178         .unfenced_needs_alignment = 1,
 179 };
 180
 181 static const struct intel_device_info intel_g33_info = {
 182         GEN3_FEATURES,
 183         PLATFORM(INTEL_G33),
 184         .display.has_hotplug = 1,
 185         .display.has_overlay = 1,
 186 };
 187
 188 static const struct intel_device_info intel_pineview_info = {
 189         GEN3_FEATURES,
 190         PLATFORM(INTEL_PINEVIEW),
 191         .is_mobile = 1,
 192         .display.has_hotplug = 1,
 193         .display.has_overlay = 1,
 194 };
 195
 196 #define GEN4_FEATURES \
 197         GEN(4), \
 198         .num_pipes = 2, \
 199         .display.has_hotplug = 1, \
 200         .display.has_gmch_display = 1, \
 201         .ring_mask = RENDER_RING, \
 202         .has_snoop = true, \
 203         .has_coherent_ggtt = true, \
 204         GEN_DEFAULT_PIPEOFFSETS, \
 205         GEN_DEFAULT_PAGE_SIZES, \
 206         CURSOR_OFFSETS
 207
 208 static const struct intel_device_info intel_i965g_info = {
 209         GEN4_FEATURES,
 210         PLATFORM(INTEL_I965G),
 211         .display.has_overlay = 1,
 212         .hws_needs_physical = 1,
 213         .has_snoop = false,
 214 };
 215
 216 static const struct intel_device_info intel_i965gm_info = {
 217         GEN4_FEATURES,
 218         PLATFORM(INTEL_I965GM),
 219         .is_mobile = 1,
 220         .display.has_fbc = 1,
 221         .display.has_overlay = 1,
 222         .display.supports_tv = 1,
 223         .hws_needs_physical = 1,
 224         .has_snoop = false,
 225 };
 226
 227 static const struct intel_device_info intel_g45_info = {
 228         GEN4_FEATURES,
 229         PLATFORM(INTEL_G45),
 230         .ring_mask = RENDER_RING | BSD_RING,
 231 };
 232
 233 static const struct intel_device_info intel_gm45_info = {
 234         GEN4_FEATURES,
 235         PLATFORM(INTEL_GM45),
 236         .is_mobile = 1,
 237         .display.has_fbc = 1,
 238         .display.supports_tv = 1,
 239         .ring_mask = RENDER_RING | BSD_RING,
 240 };
 241
 242 #define GEN5_FEATURES \
 243         GEN(5), \
 244         .num_pipes = 2, \
 245         .display.has_hotplug = 1, \
 246         .ring_mask = RENDER_RING | BSD_RING, \
 247         .has_snoop = true, \
 248         .has_coherent_ggtt = true, \
 249         /* ilk does support rc6, but we do not implement [power] contexts */ \
 250         .has_rc6 = 0, \
 251         GEN_DEFAULT_PIPEOFFSETS, \
 252         GEN_DEFAULT_PAGE_SIZES, \
 253         CURSOR_OFFSETS
 254
 255 static const struct intel_device_info intel_ironlake_d_info = {
 256         GEN5_FEATURES,
 257         PLATFORM(INTEL_IRONLAKE),
 258 };
 259
 260 static const struct intel_device_info intel_ironlake_m_info = {
 261         GEN5_FEATURES,
 262         PLATFORM(INTEL_IRONLAKE),
 263         .is_mobile = 1,
 264         .display.has_fbc = 1,
 265 };
 266
 267 #define GEN6_FEATURES \
 268         GEN(6), \
 269         .num_pipes = 2, \
 270         .display.has_hotplug = 1, \
 271         .display.has_fbc = 1, \
 272         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 273         .has_coherent_ggtt = true, \
 274         .has_llc = 1, \
 275         .has_rc6 = 1, \
 276         .has_rc6p = 1, \
 277         .ppgtt = INTEL_PPGTT_ALIASING, \
 278         GEN_DEFAULT_PIPEOFFSETS, \
 279         GEN_DEFAULT_PAGE_SIZES, \
 280         CURSOR_OFFSETS
 281
 282 #define SNB_D_PLATFORM \
 283         GEN6_FEATURES, \
 284         PLATFORM(INTEL_SANDYBRIDGE)
 285
 286 static const struct intel_device_info intel_sandybridge_d_gt1_info = {
 287         SNB_D_PLATFORM,
 288         .gt = 1,
 289 };
 290
 291 static const struct intel_device_info intel_sandybridge_d_gt2_info = {
 292         SNB_D_PLATFORM,
 293         .gt = 2,
 294 };
 295
 296 #define SNB_M_PLATFORM \
 297         GEN6_FEATURES, \
 298         PLATFORM(INTEL_SANDYBRIDGE), \
 299         .is_mobile = 1
 300
 301
 302 static const struct intel_device_info intel_sandybridge_m_gt1_info = {
 303         SNB_M_PLATFORM,
 304         .gt = 1,
 305 };
 306
 307 static const struct intel_device_info intel_sandybridge_m_gt2_info = {
 308         SNB_M_PLATFORM,
 309         .gt = 2,
 310 };
 311
 312 #define GEN7_FEATURES  \
 313         GEN(7), \
 314         .num_pipes = 3, \
 315         .display.has_hotplug = 1, \
 316         .display.has_fbc = 1, \
 317         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 318         .has_coherent_ggtt = true, \
 319         .has_llc = 1, \
 320         .has_rc6 = 1, \
 321         .has_rc6p = 1, \
 322         .ppgtt = INTEL_PPGTT_FULL, \
 323         GEN_DEFAULT_PIPEOFFSETS, \
 324         GEN_DEFAULT_PAGE_SIZES, \
 325         IVB_CURSOR_OFFSETS
 326
 327 #define IVB_D_PLATFORM \
 328         GEN7_FEATURES, \
 329         PLATFORM(INTEL_IVYBRIDGE), \
 330         .has_l3_dpf = 1
 331
 332 static const struct intel_device_info intel_ivybridge_d_gt1_info = {
 333         IVB_D_PLATFORM,
 334         .gt = 1,
 335 };
 336
 337 static const struct intel_device_info intel_ivybridge_d_gt2_info = {
 338         IVB_D_PLATFORM,
 339         .gt = 2,
 340 };
 341
 342 #define IVB_M_PLATFORM \
 343         GEN7_FEATURES, \
 344         PLATFORM(INTEL_IVYBRIDGE), \
 345         .is_mobile = 1, \
 346         .has_l3_dpf = 1
 347
 348 static const struct intel_device_info intel_ivybridge_m_gt1_info = {
 349         IVB_M_PLATFORM,
 350         .gt = 1,
 351 };
 352
 353 static const struct intel_device_info intel_ivybridge_m_gt2_info = {
 354         IVB_M_PLATFORM,
 355         .gt = 2,
 356 };
 357
 358 static const struct intel_device_info intel_ivybridge_q_info = {
 359         GEN7_FEATURES,
 360         PLATFORM(INTEL_IVYBRIDGE),
 361         .gt = 2,
 362         .num_pipes = 0, /* legal, last one wins */
 363         .has_l3_dpf = 1,
 364 };
 365
 366 static const struct intel_device_info intel_valleyview_info = {
 367         PLATFORM(INTEL_VALLEYVIEW),
 368         GEN(7),
 369         .is_lp = 1,
 370         .num_pipes = 2,
 371         .has_runtime_pm = 1,
 372         .has_rc6 = 1,
 373         .display.has_gmch_display = 1,
 374         .display.has_hotplug = 1,
 375         .ppgtt = INTEL_PPGTT_FULL,
 376         .has_snoop = true,
 377         .has_coherent_ggtt = false,
 378         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 379         .display_mmio_offset = VLV_DISPLAY_BASE,
 380         GEN_DEFAULT_PAGE_SIZES,
 381         GEN_DEFAULT_PIPEOFFSETS,
 382         CURSOR_OFFSETS
 383 };
 384
 385 #define G75_FEATURES  \
 386         GEN7_FEATURES, \
 387         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
 388         .display.has_ddi = 1, \
 389         .has_fpga_dbg = 1, \
 390         .display.has_psr = 1, \
 391         .display.has_dp_mst = 1, \
 392         .has_rc6p = 0 /* RC6p removed-by HSW */, \
 393         .has_runtime_pm = 1
 394
 395 #define HSW_PLATFORM \
 396         G75_FEATURES, \
 397         PLATFORM(INTEL_HASWELL), \
 398         .has_l3_dpf = 1
 399
 400 static const struct intel_device_info intel_haswell_gt1_info = {
 401         HSW_PLATFORM,
 402         .gt = 1,
 403 };
 404
 405 static const struct intel_device_info intel_haswell_gt2_info = {
 406         HSW_PLATFORM,
 407         .gt = 2,
 408 };
 409
 410 static const struct intel_device_info intel_haswell_gt3_info = {
 411         HSW_PLATFORM,
 412         .gt = 3,
 413 };
 414
 415 #define GEN8_FEATURES \
 416         G75_FEATURES, \
 417         GEN(8), \
 418         BDW_COLORS, \
 419         .page_sizes = I915_GTT_PAGE_SIZE_4K | \
 420                       I915_GTT_PAGE_SIZE_2M, \
 421         .has_logical_ring_contexts = 1, \
 422         .ppgtt = INTEL_PPGTT_FULL_4LVL, \
 423         .has_64bit_reloc = 1, \
 424         .has_reset_engine = 1
 425
 426 #define BDW_PLATFORM \
 427         GEN8_FEATURES, \
 428         PLATFORM(INTEL_BROADWELL)
 429
 430 static const struct intel_device_info intel_broadwell_gt1_info = {
 431         BDW_PLATFORM,
 432         .gt = 1,
 433 };
 434
 435 static const struct intel_device_info intel_broadwell_gt2_info = {
 436         BDW_PLATFORM,
 437         .gt = 2,
 438 };
 439
 440 static const struct intel_device_info intel_broadwell_rsvd_info = {
 441         BDW_PLATFORM,
 442         .gt = 3,
 443         /* According to the device ID those devices are GT3, they were
 444          * previously treated as not GT3, keep it like that.
 445          */
 446 };
 447
 448 static const struct intel_device_info intel_broadwell_gt3_info = {
 449         BDW_PLATFORM,
 450         .gt = 3,
 451         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 452 };
 453
 454 static const struct intel_device_info intel_cherryview_info = {
 455         PLATFORM(INTEL_CHERRYVIEW),
 456         GEN(8),
 457         .num_pipes = 3,
 458         .display.has_hotplug = 1,
 459         .is_lp = 1,
 460         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 461         .has_64bit_reloc = 1,
 462         .has_runtime_pm = 1,
 463         .has_rc6 = 1,
 464         .has_logical_ring_contexts = 1,
 465         .display.has_gmch_display = 1,
 466         .ppgtt = INTEL_PPGTT_FULL,
 467         .has_reset_engine = 1,
 468         .has_snoop = true,
 469         .has_coherent_ggtt = false,
 470         .display_mmio_offset = VLV_DISPLAY_BASE,
 471         GEN_DEFAULT_PAGE_SIZES,
 472         GEN_CHV_PIPEOFFSETS,
 473         CURSOR_OFFSETS,
 474         CHV_COLORS,
 475 };
 476
 477 #define GEN9_DEFAULT_PAGE_SIZES \
 478         .page_sizes = I915_GTT_PAGE_SIZE_4K | \
 479                       I915_GTT_PAGE_SIZE_64K | \
 480                       I915_GTT_PAGE_SIZE_2M
 481
 482 #define GEN9_FEATURES \
 483         GEN8_FEATURES, \
 484         GEN(9), \
 485         GEN9_DEFAULT_PAGE_SIZES, \
 486         .has_logical_ring_preemption = 1, \
 487         .display.has_csr = 1, \
 488         .has_guc = 1, \
 489         .display.has_ipc = 1, \
 490         .ddb_size = 896
 491
 492 #define SKL_PLATFORM \
 493         GEN9_FEATURES, \
 494         /* Display WA #0477 WaDisableIPC: skl */ \
 495         .display.has_ipc = 0, \
 496         PLATFORM(INTEL_SKYLAKE)
 497
 498 static const struct intel_device_info intel_skylake_gt1_info = {
 499         SKL_PLATFORM,
 500         .gt = 1,
 501 };
 502
 503 static const struct intel_device_info intel_skylake_gt2_info = {
 504         SKL_PLATFORM,
 505         .gt = 2,
 506 };
 507
 508 #define SKL_GT3_PLUS_PLATFORM \
 509         SKL_PLATFORM, \
 510         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING
 511
 512
 513 static const struct intel_device_info intel_skylake_gt3_info = {
 514         SKL_GT3_PLUS_PLATFORM,
 515         .gt = 3,
 516 };
 517
 518 static const struct intel_device_info intel_skylake_gt4_info = {
 519         SKL_GT3_PLUS_PLATFORM,
 520         .gt = 4,
 521 };
 522
 523 #define GEN9_LP_FEATURES \
 524         GEN(9), \
 525         .is_lp = 1, \
 526         .display.has_hotplug = 1, \
 527         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
 528         .num_pipes = 3, \
 529         .has_64bit_reloc = 1, \
 530         .display.has_ddi = 1, \
 531         .has_fpga_dbg = 1, \
 532         .display.has_fbc = 1, \
 533         .display.has_psr = 1, \
 534         .has_runtime_pm = 1, \
 535         .has_pooled_eu = 0, \
 536         .display.has_csr = 1, \
 537         .has_rc6 = 1, \
 538         .display.has_dp_mst = 1, \
 539         .has_logical_ring_contexts = 1, \
 540         .has_logical_ring_preemption = 1, \
 541         .has_guc = 1, \
 542         .ppgtt = INTEL_PPGTT_FULL_4LVL, \
 543         .has_reset_engine = 1, \
 544         .has_snoop = true, \
 545         .has_coherent_ggtt = false, \
 546         .display.has_ipc = 1, \
 547         GEN9_DEFAULT_PAGE_SIZES, \
 548         GEN_DEFAULT_PIPEOFFSETS, \
 549         IVB_CURSOR_OFFSETS, \
 550         BDW_COLORS
 551
 552 static const struct intel_device_info intel_broxton_info = {
 553         GEN9_LP_FEATURES,
 554         PLATFORM(INTEL_BROXTON),
 555         .ddb_size = 512,
 556 };
 557
 558 static const struct intel_device_info intel_geminilake_info = {
 559         GEN9_LP_FEATURES,
 560         PLATFORM(INTEL_GEMINILAKE),
 561         .ddb_size = 1024,
 562         GLK_COLORS,
 563 };
 564
 565 #define KBL_PLATFORM \
 566         GEN9_FEATURES, \
 567         PLATFORM(INTEL_KABYLAKE)
 568
 569 static const struct intel_device_info intel_kabylake_gt1_info = {
 570         KBL_PLATFORM,
 571         .gt = 1,
 572 };
 573
 574 static const struct intel_device_info intel_kabylake_gt2_info = {
 575         KBL_PLATFORM,
 576         .gt = 2,
 577 };
 578
 579 static const struct intel_device_info intel_kabylake_gt3_info = {
 580         KBL_PLATFORM,
 581         .gt = 3,
 582         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 583 };
 584
 585 #define CFL_PLATFORM \
 586         GEN9_FEATURES, \
 587         PLATFORM(INTEL_COFFEELAKE)
 588
 589 static const struct intel_device_info intel_coffeelake_gt1_info = {
 590         CFL_PLATFORM,
 591         .gt = 1,
 592 };
 593
 594 static const struct intel_device_info intel_coffeelake_gt2_info = {
 595         CFL_PLATFORM,
 596         .gt = 2,
 597 };
 598
 599 static const struct intel_device_info intel_coffeelake_gt3_info = {
 600         CFL_PLATFORM,
 601         .gt = 3,
 602         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 603 };
 604
 605 #define GEN10_FEATURES \
 606         GEN9_FEATURES, \
 607         GEN(10), \
 608         .ddb_size = 1024, \
 609         .has_coherent_ggtt = false, \
 610         GLK_COLORS
 611
 612 static const struct intel_device_info intel_cannonlake_info = {
 613         GEN10_FEATURES,
 614         PLATFORM(INTEL_CANNONLAKE),
 615         .gt = 2,
 616 };
 617
 618 #define GEN11_FEATURES \
 619         GEN10_FEATURES, \
 620         .pipe_offsets = { \
 621                 [TRANSCODER_A] = PIPE_A_OFFSET, \
 622                 [TRANSCODER_B] = PIPE_B_OFFSET, \
 623                 [TRANSCODER_C] = PIPE_C_OFFSET, \
 624                 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
 625                 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
 626                 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
 627         }, \
 628         .trans_offsets = { \
 629                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
 630                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
 631                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
 632                 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
 633                 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
 634                 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
 635         }, \
 636         GEN(11), \
 637         .ddb_size = 2048, \
 638         .has_logical_ring_elsq = 1
 639
 640 static const struct intel_device_info intel_icelake_11_info = {
 641         GEN11_FEATURES,
 642         PLATFORM(INTEL_ICELAKE),
 643         .is_alpha_support = 1,
 644         .ring_mask = RENDER_RING | BLT_RING | VEBOX_RING | BSD_RING | BSD3_RING,
 645 };
 646
 647 #undef GEN
 648 #undef PLATFORM
 649
 650 /*
 651  * Make sure any device matches here are from most specific to most
 652  * general.  For example, since the Quanta match is based on the subsystem
 653  * and subvendor IDs, we need it to come before the more general IVB
 654  * PCI ID matches, otherwise we'll use the wrong info struct above.
 655  */
 656 static const struct pci_device_id pciidlist[] = {
 657         INTEL_I830_IDS(&intel_i830_info),
 658         INTEL_I845G_IDS(&intel_i845g_info),
 659         INTEL_I85X_IDS(&intel_i85x_info),
 660         INTEL_I865G_IDS(&intel_i865g_info),
 661         INTEL_I915G_IDS(&intel_i915g_info),
 662         INTEL_I915GM_IDS(&intel_i915gm_info),
 663         INTEL_I945G_IDS(&intel_i945g_info),
 664         INTEL_I945GM_IDS(&intel_i945gm_info),
 665         INTEL_I965G_IDS(&intel_i965g_info),
 666         INTEL_G33_IDS(&intel_g33_info),
 667         INTEL_I965GM_IDS(&intel_i965gm_info),
 668         INTEL_GM45_IDS(&intel_gm45_info),
 669         INTEL_G45_IDS(&intel_g45_info),
 670         INTEL_PINEVIEW_IDS(&intel_pineview_info),
 671         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
 672         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
 673         INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info),
 674         INTEL_SNB_D_GT2_IDS(&intel_sandybridge_d_gt2_info),
 675         INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info),
 676         INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info),
 677         INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
 678         INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info),
 679         INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info),
 680         INTEL_IVB_D_GT1_IDS(&intel_ivybridge_d_gt1_info),
 681         INTEL_IVB_D_GT2_IDS(&intel_ivybridge_d_gt2_info),
 682         INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info),
 683         INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info),
 684         INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info),
 685         INTEL_VLV_IDS(&intel_valleyview_info),
 686         INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info),
 687         INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info),
 688         INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
 689         INTEL_BDW_RSVD_IDS(&intel_broadwell_rsvd_info),
 690         INTEL_CHV_IDS(&intel_cherryview_info),
 691         INTEL_SKL_GT1_IDS(&intel_skylake_gt1_info),
 692         INTEL_SKL_GT2_IDS(&intel_skylake_gt2_info),
 693         INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
 694         INTEL_SKL_GT4_IDS(&intel_skylake_gt4_info),
 695         INTEL_BXT_IDS(&intel_broxton_info),
 696         INTEL_GLK_IDS(&intel_geminilake_info),
 697         INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info),
 698         INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info),
 699         INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
 700         INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
 701         INTEL_AML_KBL_GT2_IDS(&intel_kabylake_gt2_info),
 702         INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info),
 703         INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),
 704         INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),
 705         INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info),
 706         INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
 707         INTEL_WHL_U_GT1_IDS(&intel_coffeelake_gt1_info),
 708         INTEL_WHL_U_GT2_IDS(&intel_coffeelake_gt2_info),
 709         INTEL_AML_CFL_GT2_IDS(&intel_coffeelake_gt2_info),
 710         INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info),
 711         INTEL_CNL_IDS(&intel_cannonlake_info),
 712         INTEL_ICL_11_IDS(&intel_icelake_11_info),
 713         {0, 0, 0}
 714 };
 715 MODULE_DEVICE_TABLE(pci, pciidlist);
 716
 717 static void i915_pci_remove(struct pci_dev *pdev)
 718 {
 719         struct drm_device *dev;
 720
 721         dev = pci_get_drvdata(pdev);
 722         if (!dev) /* driver load aborted, nothing to cleanup */
 723                 return;
 724
 725         i915_driver_unload(dev);
 726         drm_dev_put(dev);
 727
 728         pci_set_drvdata(pdev, NULL);
 729 }
 730
 731 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 732 {
 733         struct intel_device_info *intel_info =
 734                 (struct intel_device_info *) ent->driver_data;
 735         int err;
 736
 737         if (IS_ALPHA_SUPPORT(intel_info) && !i915_modparams.alpha_support) {
 738                 DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n"
 739                          "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n"
 740                          "to enable support in this kernel version, or check for kernel updates.\n");
 741                 return -ENODEV;
 742         }
 743
 744         /* Only bind to function 0 of the device. Early generations
 745          * used function 1 as a placeholder for multi-head. This causes
 746          * us confusion instead, especially on the systems where both
 747          * functions have the same PCI-ID!
 748          */
 749         if (PCI_FUNC(pdev->devfn))
 750                 return -ENODEV;
 751
 752         /*
 753          * apple-gmux is needed on dual GPU MacBook Pro
 754          * to probe the panel if we're the inactive GPU.
 755          */
 756         if (vga_switcheroo_client_probe_defer(pdev))
 757                 return -EPROBE_DEFER;
 758
 759         err = i915_driver_load(pdev, ent);
 760         if (err)
 761                 return err;
 762
 763         if (i915_inject_load_failure()) {
 764                 i915_pci_remove(pdev);
 765                 return -ENODEV;
 766         }
 767
 768         err = i915_live_selftests(pdev);
 769         if (err) {
 770                 i915_pci_remove(pdev);
 771                 return err > 0 ? -ENOTTY : err;
 772         }
 773
 774         return 0;
 775 }
 776
 777 static struct pci_driver i915_pci_driver = {
 778         .name = DRIVER_NAME,
 779         .id_table = pciidlist,
 780         .probe = i915_pci_probe,
 781         .remove = i915_pci_remove,
 782         .driver.pm = &i915_pm_ops,
 783 };
 784
 785 static int __init i915_init(void)
 786 {
 787         bool use_kms = true;
 788         int err;
 789
 790         err = i915_mock_selftests();
 791         if (err)
 792                 return err > 0 ? 0 : err;
 793
 794         /*
 795          * Enable KMS by default, unless explicitly overriden by
 796          * either the i915.modeset prarameter or by the
 797          * vga_text_mode_force boot option.
 798          */
 799
 800         if (i915_modparams.modeset == 0)
 801                 use_kms = false;
 802
 803         if (vgacon_text_force() && i915_modparams.modeset == -1)
 804                 use_kms = false;
 805
 806         if (!use_kms) {
 807                 /* Silently fail loading to not upset userspace. */
 808                 DRM_DEBUG_DRIVER("KMS disabled.\n");
 809                 return 0;
 810         }
 811
 812         return pci_register_driver(&i915_pci_driver);
 813 }
 814
 815 static void __exit i915_exit(void)
 816 {
 817         if (!i915_pci_driver.driver.owner)
 818                 return;
 819
 820         pci_unregister_driver(&i915_pci_driver);
 821 }
 822
 823 module_init(i915_init);
 824 module_exit(i915_exit);
 825
 826 MODULE_AUTHOR("Tungsten Graphics, Inc.");
 827 MODULE_AUTHOR("Intel Corporation");
 828
 829 MODULE_DESCRIPTION(DRIVER_DESC);
 830 MODULE_LICENSE("GPL and additional rights");