2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include <linux/console.h>
26 #include <linux/vgaarb.h>
27 #include <linux/vga_switcheroo.h>
30 #include "i915_selftest.h"
32 #define PLATFORM(x) .platform = (x), .platform_mask = BIT(x)
33 #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
35 #define GEN_DEFAULT_PIPEOFFSETS \
37 [TRANSCODER_A] = PIPE_A_OFFSET, \
38 [TRANSCODER_B] = PIPE_B_OFFSET, \
39 [TRANSCODER_C] = PIPE_C_OFFSET, \
40 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
43 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
44 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
45 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
46 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
49 #define GEN_CHV_PIPEOFFSETS \
51 [TRANSCODER_A] = PIPE_A_OFFSET, \
52 [TRANSCODER_B] = PIPE_B_OFFSET, \
53 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
56 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
57 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
58 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
61 #define CURSOR_OFFSETS \
62 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
64 #define IVB_CURSOR_OFFSETS \
65 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
68 .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
70 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
72 .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
74 /* Keep in gen based order, and chronological order within a gen */
76 #define GEN_DEFAULT_PAGE_SIZES \
77 .page_sizes = I915_GTT_PAGE_SIZE_4K
79 #define GEN2_FEATURES \
82 .display.has_overlay = 1, \
83 .display.overlay_needs_physical = 1, \
84 .display.has_gmch_display = 1, \
85 .hws_needs_physical = 1, \
86 .unfenced_needs_alignment = 1, \
87 .ring_mask = RENDER_RING, \
89 .has_coherent_ggtt = false, \
90 GEN_DEFAULT_PIPEOFFSETS, \
91 GEN_DEFAULT_PAGE_SIZES, \
94 static const struct intel_device_info intel_i830_info = {
98 .display.cursor_needs_physical = 1,
99 .num_pipes = 2, /* legal, last one wins */
102 static const struct intel_device_info intel_i845g_info = {
104 PLATFORM(INTEL_I845G),
107 static const struct intel_device_info intel_i85x_info = {
109 PLATFORM(INTEL_I85X),
111 .num_pipes = 2, /* legal, last one wins */
112 .display.cursor_needs_physical = 1,
113 .display.has_fbc = 1,
116 static const struct intel_device_info intel_i865g_info = {
118 PLATFORM(INTEL_I865G),
121 #define GEN3_FEATURES \
124 .display.has_gmch_display = 1, \
125 .ring_mask = RENDER_RING, \
127 .has_coherent_ggtt = true, \
128 GEN_DEFAULT_PIPEOFFSETS, \
129 GEN_DEFAULT_PAGE_SIZES, \
132 static const struct intel_device_info intel_i915g_info = {
134 PLATFORM(INTEL_I915G),
135 .has_coherent_ggtt = false,
136 .display.cursor_needs_physical = 1,
137 .display.has_overlay = 1,
138 .display.overlay_needs_physical = 1,
139 .hws_needs_physical = 1,
140 .unfenced_needs_alignment = 1,
143 static const struct intel_device_info intel_i915gm_info = {
145 PLATFORM(INTEL_I915GM),
147 .display.cursor_needs_physical = 1,
148 .display.has_overlay = 1,
149 .display.overlay_needs_physical = 1,
150 .display.supports_tv = 1,
151 .display.has_fbc = 1,
152 .hws_needs_physical = 1,
153 .unfenced_needs_alignment = 1,
156 static const struct intel_device_info intel_i945g_info = {
158 PLATFORM(INTEL_I945G),
159 .display.has_hotplug = 1,
160 .display.cursor_needs_physical = 1,
161 .display.has_overlay = 1,
162 .display.overlay_needs_physical = 1,
163 .hws_needs_physical = 1,
164 .unfenced_needs_alignment = 1,
167 static const struct intel_device_info intel_i945gm_info = {
169 PLATFORM(INTEL_I945GM),
171 .display.has_hotplug = 1,
172 .display.cursor_needs_physical = 1,
173 .display.has_overlay = 1,
174 .display.overlay_needs_physical = 1,
175 .display.supports_tv = 1,
176 .display.has_fbc = 1,
177 .hws_needs_physical = 1,
178 .unfenced_needs_alignment = 1,
181 static const struct intel_device_info intel_g33_info = {
184 .display.has_hotplug = 1,
185 .display.has_overlay = 1,
188 static const struct intel_device_info intel_pineview_info = {
190 PLATFORM(INTEL_PINEVIEW),
192 .display.has_hotplug = 1,
193 .display.has_overlay = 1,
196 #define GEN4_FEATURES \
199 .display.has_hotplug = 1, \
200 .display.has_gmch_display = 1, \
201 .ring_mask = RENDER_RING, \
203 .has_coherent_ggtt = true, \
204 GEN_DEFAULT_PIPEOFFSETS, \
205 GEN_DEFAULT_PAGE_SIZES, \
208 static const struct intel_device_info intel_i965g_info = {
210 PLATFORM(INTEL_I965G),
211 .display.has_overlay = 1,
212 .hws_needs_physical = 1,
216 static const struct intel_device_info intel_i965gm_info = {
218 PLATFORM(INTEL_I965GM),
220 .display.has_fbc = 1,
221 .display.has_overlay = 1,
222 .display.supports_tv = 1,
223 .hws_needs_physical = 1,
227 static const struct intel_device_info intel_g45_info = {
230 .ring_mask = RENDER_RING | BSD_RING,
233 static const struct intel_device_info intel_gm45_info = {
235 PLATFORM(INTEL_GM45),
237 .display.has_fbc = 1,
238 .display.supports_tv = 1,
239 .ring_mask = RENDER_RING | BSD_RING,
242 #define GEN5_FEATURES \
245 .display.has_hotplug = 1, \
246 .ring_mask = RENDER_RING | BSD_RING, \
248 .has_coherent_ggtt = true, \
249 /* ilk does support rc6, but we do not implement [power] contexts */ \
251 GEN_DEFAULT_PIPEOFFSETS, \
252 GEN_DEFAULT_PAGE_SIZES, \
255 static const struct intel_device_info intel_ironlake_d_info = {
257 PLATFORM(INTEL_IRONLAKE),
260 static const struct intel_device_info intel_ironlake_m_info = {
262 PLATFORM(INTEL_IRONLAKE),
264 .display.has_fbc = 1,
267 #define GEN6_FEATURES \
270 .display.has_hotplug = 1, \
271 .display.has_fbc = 1, \
272 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
273 .has_coherent_ggtt = true, \
277 .ppgtt = INTEL_PPGTT_ALIASING, \
278 GEN_DEFAULT_PIPEOFFSETS, \
279 GEN_DEFAULT_PAGE_SIZES, \
282 #define SNB_D_PLATFORM \
284 PLATFORM(INTEL_SANDYBRIDGE)
286 static const struct intel_device_info intel_sandybridge_d_gt1_info = {
291 static const struct intel_device_info intel_sandybridge_d_gt2_info = {
296 #define SNB_M_PLATFORM \
298 PLATFORM(INTEL_SANDYBRIDGE), \
302 static const struct intel_device_info intel_sandybridge_m_gt1_info = {
307 static const struct intel_device_info intel_sandybridge_m_gt2_info = {
312 #define GEN7_FEATURES \
315 .display.has_hotplug = 1, \
316 .display.has_fbc = 1, \
317 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
318 .has_coherent_ggtt = true, \
322 .ppgtt = INTEL_PPGTT_FULL, \
323 GEN_DEFAULT_PIPEOFFSETS, \
324 GEN_DEFAULT_PAGE_SIZES, \
327 #define IVB_D_PLATFORM \
329 PLATFORM(INTEL_IVYBRIDGE), \
332 static const struct intel_device_info intel_ivybridge_d_gt1_info = {
337 static const struct intel_device_info intel_ivybridge_d_gt2_info = {
342 #define IVB_M_PLATFORM \
344 PLATFORM(INTEL_IVYBRIDGE), \
348 static const struct intel_device_info intel_ivybridge_m_gt1_info = {
353 static const struct intel_device_info intel_ivybridge_m_gt2_info = {
358 static const struct intel_device_info intel_ivybridge_q_info = {
360 PLATFORM(INTEL_IVYBRIDGE),
362 .num_pipes = 0, /* legal, last one wins */
366 static const struct intel_device_info intel_valleyview_info = {
367 PLATFORM(INTEL_VALLEYVIEW),
373 .display.has_gmch_display = 1,
374 .display.has_hotplug = 1,
375 .ppgtt = INTEL_PPGTT_FULL,
377 .has_coherent_ggtt = false,
378 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
379 .display_mmio_offset = VLV_DISPLAY_BASE,
380 GEN_DEFAULT_PAGE_SIZES,
381 GEN_DEFAULT_PIPEOFFSETS,
385 #define G75_FEATURES \
387 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
388 .display.has_ddi = 1, \
390 .display.has_psr = 1, \
391 .display.has_dp_mst = 1, \
392 .has_rc6p = 0 /* RC6p removed-by HSW */, \
395 #define HSW_PLATFORM \
397 PLATFORM(INTEL_HASWELL), \
400 static const struct intel_device_info intel_haswell_gt1_info = {
405 static const struct intel_device_info intel_haswell_gt2_info = {
410 static const struct intel_device_info intel_haswell_gt3_info = {
415 #define GEN8_FEATURES \
419 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
420 I915_GTT_PAGE_SIZE_2M, \
421 .has_logical_ring_contexts = 1, \
422 .ppgtt = INTEL_PPGTT_FULL_4LVL, \
423 .has_64bit_reloc = 1, \
424 .has_reset_engine = 1
426 #define BDW_PLATFORM \
428 PLATFORM(INTEL_BROADWELL)
430 static const struct intel_device_info intel_broadwell_gt1_info = {
435 static const struct intel_device_info intel_broadwell_gt2_info = {
440 static const struct intel_device_info intel_broadwell_rsvd_info = {
443 /* According to the device ID those devices are GT3, they were
444 * previously treated as not GT3, keep it like that.
448 static const struct intel_device_info intel_broadwell_gt3_info = {
451 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
454 static const struct intel_device_info intel_cherryview_info = {
455 PLATFORM(INTEL_CHERRYVIEW),
458 .display.has_hotplug = 1,
460 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
461 .has_64bit_reloc = 1,
464 .has_logical_ring_contexts = 1,
465 .display.has_gmch_display = 1,
466 .ppgtt = INTEL_PPGTT_FULL,
467 .has_reset_engine = 1,
469 .has_coherent_ggtt = false,
470 .display_mmio_offset = VLV_DISPLAY_BASE,
471 GEN_DEFAULT_PAGE_SIZES,
477 #define GEN9_DEFAULT_PAGE_SIZES \
478 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
479 I915_GTT_PAGE_SIZE_64K | \
480 I915_GTT_PAGE_SIZE_2M
482 #define GEN9_FEATURES \
485 GEN9_DEFAULT_PAGE_SIZES, \
486 .has_logical_ring_preemption = 1, \
487 .display.has_csr = 1, \
489 .display.has_ipc = 1, \
492 #define SKL_PLATFORM \
494 /* Display WA #0477 WaDisableIPC: skl */ \
495 .display.has_ipc = 0, \
496 PLATFORM(INTEL_SKYLAKE)
498 static const struct intel_device_info intel_skylake_gt1_info = {
503 static const struct intel_device_info intel_skylake_gt2_info = {
508 #define SKL_GT3_PLUS_PLATFORM \
510 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING
513 static const struct intel_device_info intel_skylake_gt3_info = {
514 SKL_GT3_PLUS_PLATFORM,
518 static const struct intel_device_info intel_skylake_gt4_info = {
519 SKL_GT3_PLUS_PLATFORM,
523 #define GEN9_LP_FEATURES \
526 .display.has_hotplug = 1, \
527 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
529 .has_64bit_reloc = 1, \
530 .display.has_ddi = 1, \
532 .display.has_fbc = 1, \
533 .display.has_psr = 1, \
534 .has_runtime_pm = 1, \
535 .has_pooled_eu = 0, \
536 .display.has_csr = 1, \
538 .display.has_dp_mst = 1, \
539 .has_logical_ring_contexts = 1, \
540 .has_logical_ring_preemption = 1, \
542 .ppgtt = INTEL_PPGTT_FULL_4LVL, \
543 .has_reset_engine = 1, \
545 .has_coherent_ggtt = false, \
546 .display.has_ipc = 1, \
547 GEN9_DEFAULT_PAGE_SIZES, \
548 GEN_DEFAULT_PIPEOFFSETS, \
549 IVB_CURSOR_OFFSETS, \
552 static const struct intel_device_info intel_broxton_info = {
554 PLATFORM(INTEL_BROXTON),
558 static const struct intel_device_info intel_geminilake_info = {
560 PLATFORM(INTEL_GEMINILAKE),
565 #define KBL_PLATFORM \
567 PLATFORM(INTEL_KABYLAKE)
569 static const struct intel_device_info intel_kabylake_gt1_info = {
574 static const struct intel_device_info intel_kabylake_gt2_info = {
579 static const struct intel_device_info intel_kabylake_gt3_info = {
582 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
585 #define CFL_PLATFORM \
587 PLATFORM(INTEL_COFFEELAKE)
589 static const struct intel_device_info intel_coffeelake_gt1_info = {
594 static const struct intel_device_info intel_coffeelake_gt2_info = {
599 static const struct intel_device_info intel_coffeelake_gt3_info = {
602 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
605 #define GEN10_FEATURES \
609 .has_coherent_ggtt = false, \
612 static const struct intel_device_info intel_cannonlake_info = {
614 PLATFORM(INTEL_CANNONLAKE),
618 #define GEN11_FEATURES \
621 [TRANSCODER_A] = PIPE_A_OFFSET, \
622 [TRANSCODER_B] = PIPE_B_OFFSET, \
623 [TRANSCODER_C] = PIPE_C_OFFSET, \
624 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
625 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
626 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
629 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
630 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
631 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
632 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
633 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
634 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
638 .has_logical_ring_elsq = 1
640 static const struct intel_device_info intel_icelake_11_info = {
642 PLATFORM(INTEL_ICELAKE),
643 .is_alpha_support = 1,
644 .ring_mask = RENDER_RING | BLT_RING | VEBOX_RING | BSD_RING | BSD3_RING,
651 * Make sure any device matches here are from most specific to most
652 * general. For example, since the Quanta match is based on the subsystem
653 * and subvendor IDs, we need it to come before the more general IVB
654 * PCI ID matches, otherwise we'll use the wrong info struct above.
656 static const struct pci_device_id pciidlist[] = {
657 INTEL_I830_IDS(&intel_i830_info),
658 INTEL_I845G_IDS(&intel_i845g_info),
659 INTEL_I85X_IDS(&intel_i85x_info),
660 INTEL_I865G_IDS(&intel_i865g_info),
661 INTEL_I915G_IDS(&intel_i915g_info),
662 INTEL_I915GM_IDS(&intel_i915gm_info),
663 INTEL_I945G_IDS(&intel_i945g_info),
664 INTEL_I945GM_IDS(&intel_i945gm_info),
665 INTEL_I965G_IDS(&intel_i965g_info),
666 INTEL_G33_IDS(&intel_g33_info),
667 INTEL_I965GM_IDS(&intel_i965gm_info),
668 INTEL_GM45_IDS(&intel_gm45_info),
669 INTEL_G45_IDS(&intel_g45_info),
670 INTEL_PINEVIEW_IDS(&intel_pineview_info),
671 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
672 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
673 INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info),
674 INTEL_SNB_D_GT2_IDS(&intel_sandybridge_d_gt2_info),
675 INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info),
676 INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info),
677 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
678 INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info),
679 INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info),
680 INTEL_IVB_D_GT1_IDS(&intel_ivybridge_d_gt1_info),
681 INTEL_IVB_D_GT2_IDS(&intel_ivybridge_d_gt2_info),
682 INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info),
683 INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info),
684 INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info),
685 INTEL_VLV_IDS(&intel_valleyview_info),
686 INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info),
687 INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info),
688 INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
689 INTEL_BDW_RSVD_IDS(&intel_broadwell_rsvd_info),
690 INTEL_CHV_IDS(&intel_cherryview_info),
691 INTEL_SKL_GT1_IDS(&intel_skylake_gt1_info),
692 INTEL_SKL_GT2_IDS(&intel_skylake_gt2_info),
693 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
694 INTEL_SKL_GT4_IDS(&intel_skylake_gt4_info),
695 INTEL_BXT_IDS(&intel_broxton_info),
696 INTEL_GLK_IDS(&intel_geminilake_info),
697 INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info),
698 INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info),
699 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
700 INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
701 INTEL_AML_KBL_GT2_IDS(&intel_kabylake_gt2_info),
702 INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info),
703 INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),
704 INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),
705 INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info),
706 INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
707 INTEL_WHL_U_GT1_IDS(&intel_coffeelake_gt1_info),
708 INTEL_WHL_U_GT2_IDS(&intel_coffeelake_gt2_info),
709 INTEL_AML_CFL_GT2_IDS(&intel_coffeelake_gt2_info),
710 INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info),
711 INTEL_CNL_IDS(&intel_cannonlake_info),
712 INTEL_ICL_11_IDS(&intel_icelake_11_info),
715 MODULE_DEVICE_TABLE(pci, pciidlist);
717 static void i915_pci_remove(struct pci_dev *pdev)
719 struct drm_device *dev;
721 dev = pci_get_drvdata(pdev);
722 if (!dev) /* driver load aborted, nothing to cleanup */
725 i915_driver_unload(dev);
728 pci_set_drvdata(pdev, NULL);
731 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
733 struct intel_device_info *intel_info =
734 (struct intel_device_info *) ent->driver_data;
737 if (IS_ALPHA_SUPPORT(intel_info) && !i915_modparams.alpha_support) {
738 DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n"
739 "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n"
740 "to enable support in this kernel version, or check for kernel updates.\n");
744 /* Only bind to function 0 of the device. Early generations
745 * used function 1 as a placeholder for multi-head. This causes
746 * us confusion instead, especially on the systems where both
747 * functions have the same PCI-ID!
749 if (PCI_FUNC(pdev->devfn))
753 * apple-gmux is needed on dual GPU MacBook Pro
754 * to probe the panel if we're the inactive GPU.
756 if (vga_switcheroo_client_probe_defer(pdev))
757 return -EPROBE_DEFER;
759 err = i915_driver_load(pdev, ent);
763 if (i915_inject_load_failure()) {
764 i915_pci_remove(pdev);
768 err = i915_live_selftests(pdev);
770 i915_pci_remove(pdev);
771 return err > 0 ? -ENOTTY : err;
777 static struct pci_driver i915_pci_driver = {
779 .id_table = pciidlist,
780 .probe = i915_pci_probe,
781 .remove = i915_pci_remove,
782 .driver.pm = &i915_pm_ops,
785 static int __init i915_init(void)
790 err = i915_mock_selftests();
792 return err > 0 ? 0 : err;
795 * Enable KMS by default, unless explicitly overriden by
796 * either the i915.modeset prarameter or by the
797 * vga_text_mode_force boot option.
800 if (i915_modparams.modeset == 0)
803 if (vgacon_text_force() && i915_modparams.modeset == -1)
807 /* Silently fail loading to not upset userspace. */
808 DRM_DEBUG_DRIVER("KMS disabled.\n");
812 return pci_register_driver(&i915_pci_driver);
815 static void __exit i915_exit(void)
817 if (!i915_pci_driver.driver.owner)
820 pci_unregister_driver(&i915_pci_driver);
823 module_init(i915_init);
824 module_exit(i915_exit);
826 MODULE_AUTHOR("Tungsten Graphics, Inc.");
827 MODULE_AUTHOR("Intel Corporation");
829 MODULE_DESCRIPTION(DRIVER_DESC);
830 MODULE_LICENSE("GPL and additional rights");