drivers/gpu/drm/i915/i915_pci.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <linux/console.h>
  26 #include <linux/vgaarb.h>
  27 #include <linux/vga_switcheroo.h>
  28
  29 #include <drm/drm_drv.h>
  30
  31 #include "i915_drv.h"
  32 #include "i915_globals.h"
  33 #include "i915_selftest.h"
  34
  35 #define PLATFORM(x) .platform = (x), .platform_mask = BIT(x)
  36 #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
  37
  38 #define I845_PIPE_OFFSETS \
  39         .pipe_offsets = { \
  40                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  41         }, \
  42         .trans_offsets = { \
  43                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  44         }
  45
  46 #define I9XX_PIPE_OFFSETS \
  47         .pipe_offsets = { \
  48                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  49                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  50         }, \
  51         .trans_offsets = { \
  52                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  53                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  54         }
  55
  56 #define IVB_PIPE_OFFSETS \
  57         .pipe_offsets = { \
  58                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  59                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  60                 [TRANSCODER_C] = PIPE_C_OFFSET, \
  61         }, \
  62         .trans_offsets = { \
  63                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  64                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  65                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
  66         }
  67
  68 #define HSW_PIPE_OFFSETS \
  69         .pipe_offsets = { \
  70                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  71                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  72                 [TRANSCODER_C] = PIPE_C_OFFSET, \
  73                 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
  74         }, \
  75         .trans_offsets = { \
  76                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  77                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  78                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
  79                 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
  80         }
  81
  82 #define CHV_PIPE_OFFSETS \
  83         .pipe_offsets = { \
  84                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  85                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  86                 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
  87         }, \
  88         .trans_offsets = { \
  89                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  90                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  91                 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
  92         }
  93
  94 #define I845_CURSOR_OFFSETS \
  95         .cursor_offsets = { \
  96                 [PIPE_A] = CURSOR_A_OFFSET, \
  97         }
  98
  99 #define I9XX_CURSOR_OFFSETS \
 100         .cursor_offsets = { \
 101                 [PIPE_A] = CURSOR_A_OFFSET, \
 102                 [PIPE_B] = CURSOR_B_OFFSET, \
 103         }
 104
 105 #define CHV_CURSOR_OFFSETS \
 106         .cursor_offsets = { \
 107                 [PIPE_A] = CURSOR_A_OFFSET, \
 108                 [PIPE_B] = CURSOR_B_OFFSET, \
 109                 [PIPE_C] = CHV_CURSOR_C_OFFSET, \
 110         }
 111
 112 #define IVB_CURSOR_OFFSETS \
 113         .cursor_offsets = { \
 114                 [PIPE_A] = CURSOR_A_OFFSET, \
 115                 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
 116                 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
 117         }
 118
 119 #define BDW_COLORS \
 120         .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
 121 #define CHV_COLORS \
 122         .color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \
 123                    .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
 124                    .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
 125         }
 126 #define GLK_COLORS \
 127         .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024, \
 128                    .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
 129                                         DRM_COLOR_LUT_EQUAL_CHANNELS, \
 130         }
 131
 132 /* Keep in gen based order, and chronological order within a gen */
 133
 134 #define GEN_DEFAULT_PAGE_SIZES \
 135         .page_sizes = I915_GTT_PAGE_SIZE_4K
 136
 137 #define I830_FEATURES \
 138         GEN(2), \
 139         .is_mobile = 1, \
 140         .num_pipes = 2, \
 141         .display.has_overlay = 1, \
 142         .display.cursor_needs_physical = 1, \
 143         .display.overlay_needs_physical = 1, \
 144         .display.has_gmch = 1, \
 145         .gpu_reset_clobbers_display = true, \
 146         .hws_needs_physical = 1, \
 147         .unfenced_needs_alignment = 1, \
 148         .engine_mask = BIT(RCS0), \
 149         .has_snoop = true, \
 150         .has_coherent_ggtt = false, \
 151         I9XX_PIPE_OFFSETS, \
 152         I9XX_CURSOR_OFFSETS, \
 153         GEN_DEFAULT_PAGE_SIZES
 154
 155 #define I845_FEATURES \
 156         GEN(2), \
 157         .num_pipes = 1, \
 158         .display.has_overlay = 1, \
 159         .display.overlay_needs_physical = 1, \
 160         .display.has_gmch = 1, \
 161         .gpu_reset_clobbers_display = true, \
 162         .hws_needs_physical = 1, \
 163         .unfenced_needs_alignment = 1, \
 164         .engine_mask = BIT(RCS0), \
 165         .has_snoop = true, \
 166         .has_coherent_ggtt = false, \
 167         I845_PIPE_OFFSETS, \
 168         I845_CURSOR_OFFSETS, \
 169         GEN_DEFAULT_PAGE_SIZES
 170
 171 static const struct intel_device_info intel_i830_info = {
 172         I830_FEATURES,
 173         PLATFORM(INTEL_I830),
 174 };
 175
 176 static const struct intel_device_info intel_i845g_info = {
 177         I845_FEATURES,
 178         PLATFORM(INTEL_I845G),
 179 };
 180
 181 static const struct intel_device_info intel_i85x_info = {
 182         I830_FEATURES,
 183         PLATFORM(INTEL_I85X),
 184         .display.has_fbc = 1,
 185 };
 186
 187 static const struct intel_device_info intel_i865g_info = {
 188         I845_FEATURES,
 189         PLATFORM(INTEL_I865G),
 190 };
 191
 192 #define GEN3_FEATURES \
 193         GEN(3), \
 194         .num_pipes = 2, \
 195         .display.has_gmch = 1, \
 196         .gpu_reset_clobbers_display = true, \
 197         .engine_mask = BIT(RCS0), \
 198         .has_snoop = true, \
 199         .has_coherent_ggtt = true, \
 200         I9XX_PIPE_OFFSETS, \
 201         I9XX_CURSOR_OFFSETS, \
 202         GEN_DEFAULT_PAGE_SIZES
 203
 204 static const struct intel_device_info intel_i915g_info = {
 205         GEN3_FEATURES,
 206         PLATFORM(INTEL_I915G),
 207         .has_coherent_ggtt = false,
 208         .display.cursor_needs_physical = 1,
 209         .display.has_overlay = 1,
 210         .display.overlay_needs_physical = 1,
 211         .hws_needs_physical = 1,
 212         .unfenced_needs_alignment = 1,
 213 };
 214
 215 static const struct intel_device_info intel_i915gm_info = {
 216         GEN3_FEATURES,
 217         PLATFORM(INTEL_I915GM),
 218         .is_mobile = 1,
 219         .display.cursor_needs_physical = 1,
 220         .display.has_overlay = 1,
 221         .display.overlay_needs_physical = 1,
 222         .display.supports_tv = 1,
 223         .display.has_fbc = 1,
 224         .hws_needs_physical = 1,
 225         .unfenced_needs_alignment = 1,
 226 };
 227
 228 static const struct intel_device_info intel_i945g_info = {
 229         GEN3_FEATURES,
 230         PLATFORM(INTEL_I945G),
 231         .display.has_hotplug = 1,
 232         .display.cursor_needs_physical = 1,
 233         .display.has_overlay = 1,
 234         .display.overlay_needs_physical = 1,
 235         .hws_needs_physical = 1,
 236         .unfenced_needs_alignment = 1,
 237 };
 238
 239 static const struct intel_device_info intel_i945gm_info = {
 240         GEN3_FEATURES,
 241         PLATFORM(INTEL_I945GM),
 242         .is_mobile = 1,
 243         .display.has_hotplug = 1,
 244         .display.cursor_needs_physical = 1,
 245         .display.has_overlay = 1,
 246         .display.overlay_needs_physical = 1,
 247         .display.supports_tv = 1,
 248         .display.has_fbc = 1,
 249         .hws_needs_physical = 1,
 250         .unfenced_needs_alignment = 1,
 251 };
 252
 253 static const struct intel_device_info intel_g33_info = {
 254         GEN3_FEATURES,
 255         PLATFORM(INTEL_G33),
 256         .display.has_hotplug = 1,
 257         .display.has_overlay = 1,
 258 };
 259
 260 static const struct intel_device_info intel_pineview_info = {
 261         GEN3_FEATURES,
 262         PLATFORM(INTEL_PINEVIEW),
 263         .is_mobile = 1,
 264         .display.has_hotplug = 1,
 265         .display.has_overlay = 1,
 266 };
 267
 268 #define GEN4_FEATURES \
 269         GEN(4), \
 270         .num_pipes = 2, \
 271         .display.has_hotplug = 1, \
 272         .display.has_gmch = 1, \
 273         .gpu_reset_clobbers_display = true, \
 274         .engine_mask = BIT(RCS0), \
 275         .has_snoop = true, \
 276         .has_coherent_ggtt = true, \
 277         I9XX_PIPE_OFFSETS, \
 278         I9XX_CURSOR_OFFSETS, \
 279         GEN_DEFAULT_PAGE_SIZES
 280
 281 static const struct intel_device_info intel_i965g_info = {
 282         GEN4_FEATURES,
 283         PLATFORM(INTEL_I965G),
 284         .display.has_overlay = 1,
 285         .hws_needs_physical = 1,
 286         .has_snoop = false,
 287 };
 288
 289 static const struct intel_device_info intel_i965gm_info = {
 290         GEN4_FEATURES,
 291         PLATFORM(INTEL_I965GM),
 292         .is_mobile = 1,
 293         .display.has_fbc = 1,
 294         .display.has_overlay = 1,
 295         .display.supports_tv = 1,
 296         .hws_needs_physical = 1,
 297         .has_snoop = false,
 298 };
 299
 300 static const struct intel_device_info intel_g45_info = {
 301         GEN4_FEATURES,
 302         PLATFORM(INTEL_G45),
 303         .engine_mask = BIT(RCS0) | BIT(VCS0),
 304         .gpu_reset_clobbers_display = false,
 305 };
 306
 307 static const struct intel_device_info intel_gm45_info = {
 308         GEN4_FEATURES,
 309         PLATFORM(INTEL_GM45),
 310         .is_mobile = 1,
 311         .display.has_fbc = 1,
 312         .display.supports_tv = 1,
 313         .engine_mask = BIT(RCS0) | BIT(VCS0),
 314         .gpu_reset_clobbers_display = false,
 315 };
 316
 317 #define GEN5_FEATURES \
 318         GEN(5), \
 319         .num_pipes = 2, \
 320         .display.has_hotplug = 1, \
 321         .engine_mask = BIT(RCS0) | BIT(VCS0), \
 322         .has_snoop = true, \
 323         .has_coherent_ggtt = true, \
 324         /* ilk does support rc6, but we do not implement [power] contexts */ \
 325         .has_rc6 = 0, \
 326         I9XX_PIPE_OFFSETS, \
 327         I9XX_CURSOR_OFFSETS, \
 328         GEN_DEFAULT_PAGE_SIZES
 329
 330 static const struct intel_device_info intel_ironlake_d_info = {
 331         GEN5_FEATURES,
 332         PLATFORM(INTEL_IRONLAKE),
 333 };
 334
 335 static const struct intel_device_info intel_ironlake_m_info = {
 336         GEN5_FEATURES,
 337         PLATFORM(INTEL_IRONLAKE),
 338         .is_mobile = 1,
 339         .display.has_fbc = 1,
 340 };
 341
 342 #define GEN6_FEATURES \
 343         GEN(6), \
 344         .num_pipes = 2, \
 345         .display.has_hotplug = 1, \
 346         .display.has_fbc = 1, \
 347         .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
 348         .has_coherent_ggtt = true, \
 349         .has_llc = 1, \
 350         .has_rc6 = 1, \
 351         .has_rc6p = 1, \
 352         .ppgtt_type = INTEL_PPGTT_ALIASING, \
 353         .ppgtt_size = 31, \
 354         I9XX_PIPE_OFFSETS, \
 355         I9XX_CURSOR_OFFSETS, \
 356         GEN_DEFAULT_PAGE_SIZES
 357
 358 #define SNB_D_PLATFORM \
 359         GEN6_FEATURES, \
 360         PLATFORM(INTEL_SANDYBRIDGE)
 361
 362 static const struct intel_device_info intel_sandybridge_d_gt1_info = {
 363         SNB_D_PLATFORM,
 364         .gt = 1,
 365 };
 366
 367 static const struct intel_device_info intel_sandybridge_d_gt2_info = {
 368         SNB_D_PLATFORM,
 369         .gt = 2,
 370 };
 371
 372 #define SNB_M_PLATFORM \
 373         GEN6_FEATURES, \
 374         PLATFORM(INTEL_SANDYBRIDGE), \
 375         .is_mobile = 1
 376
 377
 378 static const struct intel_device_info intel_sandybridge_m_gt1_info = {
 379         SNB_M_PLATFORM,
 380         .gt = 1,
 381 };
 382
 383 static const struct intel_device_info intel_sandybridge_m_gt2_info = {
 384         SNB_M_PLATFORM,
 385         .gt = 2,
 386 };
 387
 388 #define GEN7_FEATURES  \
 389         GEN(7), \
 390         .num_pipes = 3, \
 391         .display.has_hotplug = 1, \
 392         .display.has_fbc = 1, \
 393         .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
 394         .has_coherent_ggtt = true, \
 395         .has_llc = 1, \
 396         .has_rc6 = 1, \
 397         .has_rc6p = 1, \
 398         .ppgtt_type = INTEL_PPGTT_FULL, \
 399         .ppgtt_size = 31, \
 400         IVB_PIPE_OFFSETS, \
 401         IVB_CURSOR_OFFSETS, \
 402         GEN_DEFAULT_PAGE_SIZES
 403
 404 #define IVB_D_PLATFORM \
 405         GEN7_FEATURES, \
 406         PLATFORM(INTEL_IVYBRIDGE), \
 407         .has_l3_dpf = 1
 408
 409 static const struct intel_device_info intel_ivybridge_d_gt1_info = {
 410         IVB_D_PLATFORM,
 411         .gt = 1,
 412 };
 413
 414 static const struct intel_device_info intel_ivybridge_d_gt2_info = {
 415         IVB_D_PLATFORM,
 416         .gt = 2,
 417 };
 418
 419 #define IVB_M_PLATFORM \
 420         GEN7_FEATURES, \
 421         PLATFORM(INTEL_IVYBRIDGE), \
 422         .is_mobile = 1, \
 423         .has_l3_dpf = 1
 424
 425 static const struct intel_device_info intel_ivybridge_m_gt1_info = {
 426         IVB_M_PLATFORM,
 427         .gt = 1,
 428 };
 429
 430 static const struct intel_device_info intel_ivybridge_m_gt2_info = {
 431         IVB_M_PLATFORM,
 432         .gt = 2,
 433 };
 434
 435 static const struct intel_device_info intel_ivybridge_q_info = {
 436         GEN7_FEATURES,
 437         PLATFORM(INTEL_IVYBRIDGE),
 438         .gt = 2,
 439         .num_pipes = 0, /* legal, last one wins */
 440         .has_l3_dpf = 1,
 441 };
 442
 443 static const struct intel_device_info intel_valleyview_info = {
 444         PLATFORM(INTEL_VALLEYVIEW),
 445         GEN(7),
 446         .is_lp = 1,
 447         .num_pipes = 2,
 448         .has_runtime_pm = 1,
 449         .has_rc6 = 1,
 450         .display.has_gmch = 1,
 451         .display.has_hotplug = 1,
 452         .ppgtt_type = INTEL_PPGTT_FULL,
 453         .ppgtt_size = 31,
 454         .has_snoop = true,
 455         .has_coherent_ggtt = false,
 456         .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
 457         .display_mmio_offset = VLV_DISPLAY_BASE,
 458         I9XX_PIPE_OFFSETS,
 459         I9XX_CURSOR_OFFSETS,
 460         GEN_DEFAULT_PAGE_SIZES,
 461 };
 462
 463 #define G75_FEATURES  \
 464         GEN7_FEATURES, \
 465         .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
 466         .display.has_ddi = 1, \
 467         .has_fpga_dbg = 1, \
 468         .display.has_psr = 1, \
 469         .display.has_dp_mst = 1, \
 470         .has_rc6p = 0 /* RC6p removed-by HSW */, \
 471         HSW_PIPE_OFFSETS, \
 472         .has_runtime_pm = 1
 473
 474 #define HSW_PLATFORM \
 475         G75_FEATURES, \
 476         PLATFORM(INTEL_HASWELL), \
 477         .has_l3_dpf = 1
 478
 479 static const struct intel_device_info intel_haswell_gt1_info = {
 480         HSW_PLATFORM,
 481         .gt = 1,
 482 };
 483
 484 static const struct intel_device_info intel_haswell_gt2_info = {
 485         HSW_PLATFORM,
 486         .gt = 2,
 487 };
 488
 489 static const struct intel_device_info intel_haswell_gt3_info = {
 490         HSW_PLATFORM,
 491         .gt = 3,
 492 };
 493
 494 #define GEN8_FEATURES \
 495         G75_FEATURES, \
 496         GEN(8), \
 497         BDW_COLORS, \
 498         .page_sizes = I915_GTT_PAGE_SIZE_4K | \
 499                       I915_GTT_PAGE_SIZE_2M, \
 500         .has_logical_ring_contexts = 1, \
 501         .ppgtt_type = INTEL_PPGTT_FULL, \
 502         .ppgtt_size = 48, \
 503         .has_64bit_reloc = 1, \
 504         .has_reset_engine = 1
 505
 506 #define BDW_PLATFORM \
 507         GEN8_FEATURES, \
 508         PLATFORM(INTEL_BROADWELL)
 509
 510 static const struct intel_device_info intel_broadwell_gt1_info = {
 511         BDW_PLATFORM,
 512         .gt = 1,
 513 };
 514
 515 static const struct intel_device_info intel_broadwell_gt2_info = {
 516         BDW_PLATFORM,
 517         .gt = 2,
 518 };
 519
 520 static const struct intel_device_info intel_broadwell_rsvd_info = {
 521         BDW_PLATFORM,
 522         .gt = 3,
 523         /* According to the device ID those devices are GT3, they were
 524          * previously treated as not GT3, keep it like that.
 525          */
 526 };
 527
 528 static const struct intel_device_info intel_broadwell_gt3_info = {
 529         BDW_PLATFORM,
 530         .gt = 3,
 531         .engine_mask =
 532                 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
 533 };
 534
 535 static const struct intel_device_info intel_cherryview_info = {
 536         PLATFORM(INTEL_CHERRYVIEW),
 537         GEN(8),
 538         .num_pipes = 3,
 539         .display.has_hotplug = 1,
 540         .is_lp = 1,
 541         .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
 542         .has_64bit_reloc = 1,
 543         .has_runtime_pm = 1,
 544         .has_rc6 = 1,
 545         .has_logical_ring_contexts = 1,
 546         .display.has_gmch = 1,
 547         .ppgtt_type = INTEL_PPGTT_FULL,
 548         .ppgtt_size = 32,
 549         .has_reset_engine = 1,
 550         .has_snoop = true,
 551         .has_coherent_ggtt = false,
 552         .display_mmio_offset = VLV_DISPLAY_BASE,
 553         CHV_PIPE_OFFSETS,
 554         CHV_CURSOR_OFFSETS,
 555         CHV_COLORS,
 556         GEN_DEFAULT_PAGE_SIZES,
 557 };
 558
 559 #define GEN9_DEFAULT_PAGE_SIZES \
 560         .page_sizes = I915_GTT_PAGE_SIZE_4K | \
 561                       I915_GTT_PAGE_SIZE_64K | \
 562                       I915_GTT_PAGE_SIZE_2M
 563
 564 #define GEN9_FEATURES \
 565         GEN8_FEATURES, \
 566         GEN(9), \
 567         GEN9_DEFAULT_PAGE_SIZES, \
 568         .has_logical_ring_preemption = 1, \
 569         .display.has_csr = 1, \
 570         .has_guc = 1, \
 571         .display.has_ipc = 1, \
 572         .ddb_size = 896
 573
 574 #define SKL_PLATFORM \
 575         GEN9_FEATURES, \
 576         /* Display WA #0477 WaDisableIPC: skl */ \
 577         .display.has_ipc = 0, \
 578         PLATFORM(INTEL_SKYLAKE)
 579
 580 static const struct intel_device_info intel_skylake_gt1_info = {
 581         SKL_PLATFORM,
 582         .gt = 1,
 583 };
 584
 585 static const struct intel_device_info intel_skylake_gt2_info = {
 586         SKL_PLATFORM,
 587         .gt = 2,
 588 };
 589
 590 #define SKL_GT3_PLUS_PLATFORM \
 591         SKL_PLATFORM, \
 592         .engine_mask = \
 593                 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
 594
 595
 596 static const struct intel_device_info intel_skylake_gt3_info = {
 597         SKL_GT3_PLUS_PLATFORM,
 598         .gt = 3,
 599 };
 600
 601 static const struct intel_device_info intel_skylake_gt4_info = {
 602         SKL_GT3_PLUS_PLATFORM,
 603         .gt = 4,
 604 };
 605
 606 #define GEN9_LP_FEATURES \
 607         GEN(9), \
 608         .is_lp = 1, \
 609         .display.has_hotplug = 1, \
 610         .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
 611         .num_pipes = 3, \
 612         .has_64bit_reloc = 1, \
 613         .display.has_ddi = 1, \
 614         .has_fpga_dbg = 1, \
 615         .display.has_fbc = 1, \
 616         .display.has_psr = 1, \
 617         .has_runtime_pm = 1, \
 618         .display.has_csr = 1, \
 619         .has_rc6 = 1, \
 620         .display.has_dp_mst = 1, \
 621         .has_logical_ring_contexts = 1, \
 622         .has_logical_ring_preemption = 1, \
 623         .has_guc = 1, \
 624         .ppgtt_type = INTEL_PPGTT_FULL, \
 625         .ppgtt_size = 48, \
 626         .has_reset_engine = 1, \
 627         .has_snoop = true, \
 628         .has_coherent_ggtt = false, \
 629         .display.has_ipc = 1, \
 630         HSW_PIPE_OFFSETS, \
 631         IVB_CURSOR_OFFSETS, \
 632         BDW_COLORS, \
 633         GEN9_DEFAULT_PAGE_SIZES
 634
 635 static const struct intel_device_info intel_broxton_info = {
 636         GEN9_LP_FEATURES,
 637         PLATFORM(INTEL_BROXTON),
 638         .ddb_size = 512,
 639 };
 640
 641 static const struct intel_device_info intel_geminilake_info = {
 642         GEN9_LP_FEATURES,
 643         PLATFORM(INTEL_GEMINILAKE),
 644         .ddb_size = 1024,
 645         GLK_COLORS,
 646 };
 647
 648 #define KBL_PLATFORM \
 649         GEN9_FEATURES, \
 650         PLATFORM(INTEL_KABYLAKE)
 651
 652 static const struct intel_device_info intel_kabylake_gt1_info = {
 653         KBL_PLATFORM,
 654         .gt = 1,
 655 };
 656
 657 static const struct intel_device_info intel_kabylake_gt2_info = {
 658         KBL_PLATFORM,
 659         .gt = 2,
 660 };
 661
 662 static const struct intel_device_info intel_kabylake_gt3_info = {
 663         KBL_PLATFORM,
 664         .gt = 3,
 665         .engine_mask =
 666                 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
 667 };
 668
 669 #define CFL_PLATFORM \
 670         GEN9_FEATURES, \
 671         PLATFORM(INTEL_COFFEELAKE)
 672
 673 static const struct intel_device_info intel_coffeelake_gt1_info = {
 674         CFL_PLATFORM,
 675         .gt = 1,
 676 };
 677
 678 static const struct intel_device_info intel_coffeelake_gt2_info = {
 679         CFL_PLATFORM,
 680         .gt = 2,
 681 };
 682
 683 static const struct intel_device_info intel_coffeelake_gt3_info = {
 684         CFL_PLATFORM,
 685         .gt = 3,
 686         .engine_mask =
 687                 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
 688 };
 689
 690 #define GEN10_FEATURES \
 691         GEN9_FEATURES, \
 692         GEN(10), \
 693         .ddb_size = 1024, \
 694         .has_coherent_ggtt = false, \
 695         GLK_COLORS
 696
 697 static const struct intel_device_info intel_cannonlake_info = {
 698         GEN10_FEATURES,
 699         PLATFORM(INTEL_CANNONLAKE),
 700         .gt = 2,
 701 };
 702
 703 #define GEN11_FEATURES \
 704         GEN10_FEATURES, \
 705         .pipe_offsets = { \
 706                 [TRANSCODER_A] = PIPE_A_OFFSET, \
 707                 [TRANSCODER_B] = PIPE_B_OFFSET, \
 708                 [TRANSCODER_C] = PIPE_C_OFFSET, \
 709                 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
 710                 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
 711                 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
 712         }, \
 713         .trans_offsets = { \
 714                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
 715                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
 716                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
 717                 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
 718                 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
 719                 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
 720         }, \
 721         GEN(11), \
 722         .ddb_size = 2048, \
 723         .has_logical_ring_elsq = 1, \
 724         .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024 }
 725
 726 static const struct intel_device_info intel_icelake_11_info = {
 727         GEN11_FEATURES,
 728         PLATFORM(INTEL_ICELAKE),
 729         .engine_mask =
 730                 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
 731 };
 732
 733 static const struct intel_device_info intel_elkhartlake_info = {
 734         GEN11_FEATURES,
 735         PLATFORM(INTEL_ICELAKE),
 736         .is_alpha_support = 1,
 737         .engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0),
 738         .ppgtt_size = 36,
 739 };
 740
 741 #undef GEN
 742 #undef PLATFORM
 743
 744 /*
 745  * Make sure any device matches here are from most specific to most
 746  * general.  For example, since the Quanta match is based on the subsystem
 747  * and subvendor IDs, we need it to come before the more general IVB
 748  * PCI ID matches, otherwise we'll use the wrong info struct above.
 749  */
 750 static const struct pci_device_id pciidlist[] = {
 751         INTEL_I830_IDS(&intel_i830_info),
 752         INTEL_I845G_IDS(&intel_i845g_info),
 753         INTEL_I85X_IDS(&intel_i85x_info),
 754         INTEL_I865G_IDS(&intel_i865g_info),
 755         INTEL_I915G_IDS(&intel_i915g_info),
 756         INTEL_I915GM_IDS(&intel_i915gm_info),
 757         INTEL_I945G_IDS(&intel_i945g_info),
 758         INTEL_I945GM_IDS(&intel_i945gm_info),
 759         INTEL_I965G_IDS(&intel_i965g_info),
 760         INTEL_G33_IDS(&intel_g33_info),
 761         INTEL_I965GM_IDS(&intel_i965gm_info),
 762         INTEL_GM45_IDS(&intel_gm45_info),
 763         INTEL_G45_IDS(&intel_g45_info),
 764         INTEL_PINEVIEW_IDS(&intel_pineview_info),
 765         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
 766         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
 767         INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info),
 768         INTEL_SNB_D_GT2_IDS(&intel_sandybridge_d_gt2_info),
 769         INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info),
 770         INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info),
 771         INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
 772         INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info),
 773         INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info),
 774         INTEL_IVB_D_GT1_IDS(&intel_ivybridge_d_gt1_info),
 775         INTEL_IVB_D_GT2_IDS(&intel_ivybridge_d_gt2_info),
 776         INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info),
 777         INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info),
 778         INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info),
 779         INTEL_VLV_IDS(&intel_valleyview_info),
 780         INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info),
 781         INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info),
 782         INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
 783         INTEL_BDW_RSVD_IDS(&intel_broadwell_rsvd_info),
 784         INTEL_CHV_IDS(&intel_cherryview_info),
 785         INTEL_SKL_GT1_IDS(&intel_skylake_gt1_info),
 786         INTEL_SKL_GT2_IDS(&intel_skylake_gt2_info),
 787         INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
 788         INTEL_SKL_GT4_IDS(&intel_skylake_gt4_info),
 789         INTEL_BXT_IDS(&intel_broxton_info),
 790         INTEL_GLK_IDS(&intel_geminilake_info),
 791         INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info),
 792         INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info),
 793         INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
 794         INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
 795         INTEL_AML_KBL_GT2_IDS(&intel_kabylake_gt2_info),
 796         INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info),
 797         INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),
 798         INTEL_CFL_H_GT1_IDS(&intel_coffeelake_gt1_info),
 799         INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),
 800         INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info),
 801         INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
 802         INTEL_WHL_U_GT1_IDS(&intel_coffeelake_gt1_info),
 803         INTEL_WHL_U_GT2_IDS(&intel_coffeelake_gt2_info),
 804         INTEL_AML_CFL_GT2_IDS(&intel_coffeelake_gt2_info),
 805         INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info),
 806         INTEL_CML_GT1_IDS(&intel_coffeelake_gt1_info),
 807         INTEL_CML_GT2_IDS(&intel_coffeelake_gt2_info),
 808         INTEL_CNL_IDS(&intel_cannonlake_info),
 809         INTEL_ICL_11_IDS(&intel_icelake_11_info),
 810         INTEL_EHL_IDS(&intel_elkhartlake_info),
 811         {0, 0, 0}
 812 };
 813 MODULE_DEVICE_TABLE(pci, pciidlist);
 814
 815 static void i915_pci_remove(struct pci_dev *pdev)
 816 {
 817         struct drm_device *dev;
 818
 819         dev = pci_get_drvdata(pdev);
 820         if (!dev) /* driver load aborted, nothing to cleanup */
 821                 return;
 822
 823         i915_driver_unload(dev);
 824         drm_dev_put(dev);
 825
 826         pci_set_drvdata(pdev, NULL);
 827 }
 828
 829 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 830 {
 831         struct intel_device_info *intel_info =
 832                 (struct intel_device_info *) ent->driver_data;
 833         int err;
 834
 835         if (IS_ALPHA_SUPPORT(intel_info) && !i915_modparams.alpha_support) {
 836                 DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n"
 837                          "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n"
 838                          "to enable support in this kernel version, or check for kernel updates.\n");
 839                 return -ENODEV;
 840         }
 841
 842         /* Only bind to function 0 of the device. Early generations
 843          * used function 1 as a placeholder for multi-head. This causes
 844          * us confusion instead, especially on the systems where both
 845          * functions have the same PCI-ID!
 846          */
 847         if (PCI_FUNC(pdev->devfn))
 848                 return -ENODEV;
 849
 850         /*
 851          * apple-gmux is needed on dual GPU MacBook Pro
 852          * to probe the panel if we're the inactive GPU.
 853          */
 854         if (vga_switcheroo_client_probe_defer(pdev))
 855                 return -EPROBE_DEFER;
 856
 857         err = i915_driver_load(pdev, ent);
 858         if (err)
 859                 return err;
 860
 861         if (i915_inject_load_failure()) {
 862                 i915_pci_remove(pdev);
 863                 return -ENODEV;
 864         }
 865
 866         err = i915_live_selftests(pdev);
 867         if (err) {
 868                 i915_pci_remove(pdev);
 869                 return err > 0 ? -ENOTTY : err;
 870         }
 871
 872         return 0;
 873 }
 874
 875 static struct pci_driver i915_pci_driver = {
 876         .name = DRIVER_NAME,
 877         .id_table = pciidlist,
 878         .probe = i915_pci_probe,
 879         .remove = i915_pci_remove,
 880         .driver.pm = &i915_pm_ops,
 881 };
 882
 883 static int __init i915_init(void)
 884 {
 885         bool use_kms = true;
 886         int err;
 887
 888         err = i915_globals_init();
 889         if (err)
 890                 return err;
 891
 892         err = i915_mock_selftests();
 893         if (err)
 894                 return err > 0 ? 0 : err;
 895
 896         /*
 897          * Enable KMS by default, unless explicitly overriden by
 898          * either the i915.modeset prarameter or by the
 899          * vga_text_mode_force boot option.
 900          */
 901
 902         if (i915_modparams.modeset == 0)
 903                 use_kms = false;
 904
 905         if (vgacon_text_force() && i915_modparams.modeset == -1)
 906                 use_kms = false;
 907
 908         if (!use_kms) {
 909                 /* Silently fail loading to not upset userspace. */
 910                 DRM_DEBUG_DRIVER("KMS disabled.\n");
 911                 return 0;
 912         }
 913
 914         return pci_register_driver(&i915_pci_driver);
 915 }
 916
 917 static void __exit i915_exit(void)
 918 {
 919         if (!i915_pci_driver.driver.owner)
 920                 return;
 921
 922         pci_unregister_driver(&i915_pci_driver);
 923         i915_globals_exit();
 924 }
 925
 926 module_init(i915_init);
 927 module_exit(i915_exit);
 928
 929 MODULE_AUTHOR("Tungsten Graphics, Inc.");
 930 MODULE_AUTHOR("Intel Corporation");
 931
 932 MODULE_DESCRIPTION(DRIVER_DESC);
 933 MODULE_LICENSE("GPL and additional rights");