drivers/gpu/drm/i915/i915_pci.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <linux/console.h>
  26 #include <linux/vga_switcheroo.h>
  27
  28 #include <drm/drm_drv.h>
  29 #include <drm/i915_pciids.h>
  30
  31 #include "display/intel_fbdev.h"
  32
  33 #include "i915_drv.h"
  34 #include "i915_perf.h"
  35 #include "i915_globals.h"
  36 #include "i915_selftest.h"
  37
  38 #define PLATFORM(x) .platform = (x)
  39 #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
  40
  41 #define I845_PIPE_OFFSETS \
  42         .pipe_offsets = { \
  43                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  44         }, \
  45         .trans_offsets = { \
  46                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  47         }
  48
  49 #define I9XX_PIPE_OFFSETS \
  50         .pipe_offsets = { \
  51                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  52                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  53         }, \
  54         .trans_offsets = { \
  55                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  56                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  57         }
  58
  59 #define IVB_PIPE_OFFSETS \
  60         .pipe_offsets = { \
  61                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  62                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  63                 [TRANSCODER_C] = PIPE_C_OFFSET, \
  64         }, \
  65         .trans_offsets = { \
  66                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  67                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  68                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
  69         }
  70
  71 #define HSW_PIPE_OFFSETS \
  72         .pipe_offsets = { \
  73                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  74                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  75                 [TRANSCODER_C] = PIPE_C_OFFSET, \
  76                 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
  77         }, \
  78         .trans_offsets = { \
  79                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  80                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  81                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
  82                 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
  83         }
  84
  85 #define CHV_PIPE_OFFSETS \
  86         .pipe_offsets = { \
  87                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  88                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  89                 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
  90         }, \
  91         .trans_offsets = { \
  92                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  93                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  94                 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
  95         }
  96
  97 #define I845_CURSOR_OFFSETS \
  98         .cursor_offsets = { \
  99                 [PIPE_A] = CURSOR_A_OFFSET, \
 100         }
 101
 102 #define I9XX_CURSOR_OFFSETS \
 103         .cursor_offsets = { \
 104                 [PIPE_A] = CURSOR_A_OFFSET, \
 105                 [PIPE_B] = CURSOR_B_OFFSET, \
 106         }
 107
 108 #define CHV_CURSOR_OFFSETS \
 109         .cursor_offsets = { \
 110                 [PIPE_A] = CURSOR_A_OFFSET, \
 111                 [PIPE_B] = CURSOR_B_OFFSET, \
 112                 [PIPE_C] = CHV_CURSOR_C_OFFSET, \
 113         }
 114
 115 #define IVB_CURSOR_OFFSETS \
 116         .cursor_offsets = { \
 117                 [PIPE_A] = CURSOR_A_OFFSET, \
 118                 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
 119                 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
 120         }
 121
 122 #define TGL_CURSOR_OFFSETS \
 123         .cursor_offsets = { \
 124                 [PIPE_A] = CURSOR_A_OFFSET, \
 125                 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
 126                 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
 127                 [PIPE_D] = TGL_CURSOR_D_OFFSET, \
 128         }
 129
 130 #define I9XX_COLORS \
 131         .color = { .gamma_lut_size = 256 }
 132 #define I965_COLORS \
 133         .color = { .gamma_lut_size = 129, \
 134                    .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
 135         }
 136 #define ILK_COLORS \
 137         .color = { .gamma_lut_size = 1024 }
 138 #define IVB_COLORS \
 139         .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
 140 #define CHV_COLORS \
 141         .color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \
 142                    .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
 143                    .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
 144         }
 145 #define GLK_COLORS \
 146         .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024, \
 147                    .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
 148                                         DRM_COLOR_LUT_EQUAL_CHANNELS, \
 149         }
 150
 151 /* Keep in gen based order, and chronological order within a gen */
 152
 153 #define GEN_DEFAULT_PAGE_SIZES \
 154         .page_sizes = I915_GTT_PAGE_SIZE_4K
 155
 156 #define GEN_DEFAULT_REGIONS \
 157         .memory_regions = REGION_SMEM | REGION_STOLEN
 158
 159 #define I830_FEATURES \
 160         GEN(2), \
 161         .is_mobile = 1, \
 162         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 163         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 164         .display.has_overlay = 1, \
 165         .display.cursor_needs_physical = 1, \
 166         .display.overlay_needs_physical = 1, \
 167         .display.has_gmch = 1, \
 168         .gpu_reset_clobbers_display = true, \
 169         .hws_needs_physical = 1, \
 170         .unfenced_needs_alignment = 1, \
 171         .engine_mask = BIT(RCS0), \
 172         .has_snoop = true, \
 173         .has_coherent_ggtt = false, \
 174         .dma_mask_size = 32, \
 175         I9XX_PIPE_OFFSETS, \
 176         I9XX_CURSOR_OFFSETS, \
 177         I9XX_COLORS, \
 178         GEN_DEFAULT_PAGE_SIZES, \
 179         GEN_DEFAULT_REGIONS
 180
 181 #define I845_FEATURES \
 182         GEN(2), \
 183         .pipe_mask = BIT(PIPE_A), \
 184         .cpu_transcoder_mask = BIT(TRANSCODER_A), \
 185         .display.has_overlay = 1, \
 186         .display.overlay_needs_physical = 1, \
 187         .display.has_gmch = 1, \
 188         .gpu_reset_clobbers_display = true, \
 189         .hws_needs_physical = 1, \
 190         .unfenced_needs_alignment = 1, \
 191         .engine_mask = BIT(RCS0), \
 192         .has_snoop = true, \
 193         .has_coherent_ggtt = false, \
 194         .dma_mask_size = 32, \
 195         I845_PIPE_OFFSETS, \
 196         I845_CURSOR_OFFSETS, \
 197         I9XX_COLORS, \
 198         GEN_DEFAULT_PAGE_SIZES, \
 199         GEN_DEFAULT_REGIONS
 200
 201 static const struct intel_device_info i830_info = {
 202         I830_FEATURES,
 203         PLATFORM(INTEL_I830),
 204 };
 205
 206 static const struct intel_device_info i845g_info = {
 207         I845_FEATURES,
 208         PLATFORM(INTEL_I845G),
 209 };
 210
 211 static const struct intel_device_info i85x_info = {
 212         I830_FEATURES,
 213         PLATFORM(INTEL_I85X),
 214         .display.has_fbc = 1,
 215 };
 216
 217 static const struct intel_device_info i865g_info = {
 218         I845_FEATURES,
 219         PLATFORM(INTEL_I865G),
 220 };
 221
 222 #define GEN3_FEATURES \
 223         GEN(3), \
 224         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 225         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 226         .display.has_gmch = 1, \
 227         .gpu_reset_clobbers_display = true, \
 228         .engine_mask = BIT(RCS0), \
 229         .has_snoop = true, \
 230         .has_coherent_ggtt = true, \
 231         .dma_mask_size = 32, \
 232         I9XX_PIPE_OFFSETS, \
 233         I9XX_CURSOR_OFFSETS, \
 234         I9XX_COLORS, \
 235         GEN_DEFAULT_PAGE_SIZES, \
 236         GEN_DEFAULT_REGIONS
 237
 238 static const struct intel_device_info i915g_info = {
 239         GEN3_FEATURES,
 240         PLATFORM(INTEL_I915G),
 241         .has_coherent_ggtt = false,
 242         .display.cursor_needs_physical = 1,
 243         .display.has_overlay = 1,
 244         .display.overlay_needs_physical = 1,
 245         .hws_needs_physical = 1,
 246         .unfenced_needs_alignment = 1,
 247 };
 248
 249 static const struct intel_device_info i915gm_info = {
 250         GEN3_FEATURES,
 251         PLATFORM(INTEL_I915GM),
 252         .is_mobile = 1,
 253         .display.cursor_needs_physical = 1,
 254         .display.has_overlay = 1,
 255         .display.overlay_needs_physical = 1,
 256         .display.supports_tv = 1,
 257         .display.has_fbc = 1,
 258         .hws_needs_physical = 1,
 259         .unfenced_needs_alignment = 1,
 260 };
 261
 262 static const struct intel_device_info i945g_info = {
 263         GEN3_FEATURES,
 264         PLATFORM(INTEL_I945G),
 265         .display.has_hotplug = 1,
 266         .display.cursor_needs_physical = 1,
 267         .display.has_overlay = 1,
 268         .display.overlay_needs_physical = 1,
 269         .hws_needs_physical = 1,
 270         .unfenced_needs_alignment = 1,
 271 };
 272
 273 static const struct intel_device_info i945gm_info = {
 274         GEN3_FEATURES,
 275         PLATFORM(INTEL_I945GM),
 276         .is_mobile = 1,
 277         .display.has_hotplug = 1,
 278         .display.cursor_needs_physical = 1,
 279         .display.has_overlay = 1,
 280         .display.overlay_needs_physical = 1,
 281         .display.supports_tv = 1,
 282         .display.has_fbc = 1,
 283         .hws_needs_physical = 1,
 284         .unfenced_needs_alignment = 1,
 285 };
 286
 287 static const struct intel_device_info g33_info = {
 288         GEN3_FEATURES,
 289         PLATFORM(INTEL_G33),
 290         .display.has_hotplug = 1,
 291         .display.has_overlay = 1,
 292         .dma_mask_size = 36,
 293 };
 294
 295 static const struct intel_device_info pnv_g_info = {
 296         GEN3_FEATURES,
 297         PLATFORM(INTEL_PINEVIEW),
 298         .display.has_hotplug = 1,
 299         .display.has_overlay = 1,
 300         .dma_mask_size = 36,
 301 };
 302
 303 static const struct intel_device_info pnv_m_info = {
 304         GEN3_FEATURES,
 305         PLATFORM(INTEL_PINEVIEW),
 306         .is_mobile = 1,
 307         .display.has_hotplug = 1,
 308         .display.has_overlay = 1,
 309         .dma_mask_size = 36,
 310 };
 311
 312 #define GEN4_FEATURES \
 313         GEN(4), \
 314         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 315         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 316         .display.has_hotplug = 1, \
 317         .display.has_gmch = 1, \
 318         .gpu_reset_clobbers_display = true, \
 319         .engine_mask = BIT(RCS0), \
 320         .has_snoop = true, \
 321         .has_coherent_ggtt = true, \
 322         .dma_mask_size = 36, \
 323         I9XX_PIPE_OFFSETS, \
 324         I9XX_CURSOR_OFFSETS, \
 325         I965_COLORS, \
 326         GEN_DEFAULT_PAGE_SIZES, \
 327         GEN_DEFAULT_REGIONS
 328
 329 static const struct intel_device_info i965g_info = {
 330         GEN4_FEATURES,
 331         PLATFORM(INTEL_I965G),
 332         .display.has_overlay = 1,
 333         .hws_needs_physical = 1,
 334         .has_snoop = false,
 335 };
 336
 337 static const struct intel_device_info i965gm_info = {
 338         GEN4_FEATURES,
 339         PLATFORM(INTEL_I965GM),
 340         .is_mobile = 1,
 341         .display.has_fbc = 1,
 342         .display.has_overlay = 1,
 343         .display.supports_tv = 1,
 344         .hws_needs_physical = 1,
 345         .has_snoop = false,
 346 };
 347
 348 static const struct intel_device_info g45_info = {
 349         GEN4_FEATURES,
 350         PLATFORM(INTEL_G45),
 351         .engine_mask = BIT(RCS0) | BIT(VCS0),
 352         .gpu_reset_clobbers_display = false,
 353 };
 354
 355 static const struct intel_device_info gm45_info = {
 356         GEN4_FEATURES,
 357         PLATFORM(INTEL_GM45),
 358         .is_mobile = 1,
 359         .display.has_fbc = 1,
 360         .display.supports_tv = 1,
 361         .engine_mask = BIT(RCS0) | BIT(VCS0),
 362         .gpu_reset_clobbers_display = false,
 363 };
 364
 365 #define GEN5_FEATURES \
 366         GEN(5), \
 367         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 368         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 369         .display.has_hotplug = 1, \
 370         .engine_mask = BIT(RCS0) | BIT(VCS0), \
 371         .has_snoop = true, \
 372         .has_coherent_ggtt = true, \
 373         /* ilk does support rc6, but we do not implement [power] contexts */ \
 374         .has_rc6 = 0, \
 375         .dma_mask_size = 36, \
 376         I9XX_PIPE_OFFSETS, \
 377         I9XX_CURSOR_OFFSETS, \
 378         ILK_COLORS, \
 379         GEN_DEFAULT_PAGE_SIZES, \
 380         GEN_DEFAULT_REGIONS
 381
 382 static const struct intel_device_info ilk_d_info = {
 383         GEN5_FEATURES,
 384         PLATFORM(INTEL_IRONLAKE),
 385 };
 386
 387 static const struct intel_device_info ilk_m_info = {
 388         GEN5_FEATURES,
 389         PLATFORM(INTEL_IRONLAKE),
 390         .is_mobile = 1,
 391         .display.has_fbc = 1,
 392 };
 393
 394 #define GEN6_FEATURES \
 395         GEN(6), \
 396         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 397         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 398         .display.has_hotplug = 1, \
 399         .display.has_fbc = 1, \
 400         .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
 401         .has_coherent_ggtt = true, \
 402         .has_llc = 1, \
 403         .has_rc6 = 1, \
 404         .has_rc6p = 1, \
 405         .has_rps = true, \
 406         .dma_mask_size = 40, \
 407         .ppgtt_type = INTEL_PPGTT_ALIASING, \
 408         .ppgtt_size = 31, \
 409         I9XX_PIPE_OFFSETS, \
 410         I9XX_CURSOR_OFFSETS, \
 411         ILK_COLORS, \
 412         GEN_DEFAULT_PAGE_SIZES, \
 413         GEN_DEFAULT_REGIONS
 414
 415 #define SNB_D_PLATFORM \
 416         GEN6_FEATURES, \
 417         PLATFORM(INTEL_SANDYBRIDGE)
 418
 419 static const struct intel_device_info snb_d_gt1_info = {
 420         SNB_D_PLATFORM,
 421         .gt = 1,
 422 };
 423
 424 static const struct intel_device_info snb_d_gt2_info = {
 425         SNB_D_PLATFORM,
 426         .gt = 2,
 427 };
 428
 429 #define SNB_M_PLATFORM \
 430         GEN6_FEATURES, \
 431         PLATFORM(INTEL_SANDYBRIDGE), \
 432         .is_mobile = 1
 433
 434
 435 static const struct intel_device_info snb_m_gt1_info = {
 436         SNB_M_PLATFORM,
 437         .gt = 1,
 438 };
 439
 440 static const struct intel_device_info snb_m_gt2_info = {
 441         SNB_M_PLATFORM,
 442         .gt = 2,
 443 };
 444
 445 #define GEN7_FEATURES  \
 446         GEN(7), \
 447         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
 448         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
 449         .display.has_hotplug = 1, \
 450         .display.has_fbc = 1, \
 451         .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
 452         .has_coherent_ggtt = true, \
 453         .has_llc = 1, \
 454         .has_rc6 = 1, \
 455         .has_rc6p = 1, \
 456         .has_rps = true, \
 457         .dma_mask_size = 40, \
 458         .ppgtt_type = INTEL_PPGTT_ALIASING, \
 459         .ppgtt_size = 31, \
 460         IVB_PIPE_OFFSETS, \
 461         IVB_CURSOR_OFFSETS, \
 462         IVB_COLORS, \
 463         GEN_DEFAULT_PAGE_SIZES, \
 464         GEN_DEFAULT_REGIONS
 465
 466 #define IVB_D_PLATFORM \
 467         GEN7_FEATURES, \
 468         PLATFORM(INTEL_IVYBRIDGE), \
 469         .has_l3_dpf = 1
 470
 471 static const struct intel_device_info ivb_d_gt1_info = {
 472         IVB_D_PLATFORM,
 473         .gt = 1,
 474 };
 475
 476 static const struct intel_device_info ivb_d_gt2_info = {
 477         IVB_D_PLATFORM,
 478         .gt = 2,
 479 };
 480
 481 #define IVB_M_PLATFORM \
 482         GEN7_FEATURES, \
 483         PLATFORM(INTEL_IVYBRIDGE), \
 484         .is_mobile = 1, \
 485         .has_l3_dpf = 1
 486
 487 static const struct intel_device_info ivb_m_gt1_info = {
 488         IVB_M_PLATFORM,
 489         .gt = 1,
 490 };
 491
 492 static const struct intel_device_info ivb_m_gt2_info = {
 493         IVB_M_PLATFORM,
 494         .gt = 2,
 495 };
 496
 497 static const struct intel_device_info ivb_q_info = {
 498         GEN7_FEATURES,
 499         PLATFORM(INTEL_IVYBRIDGE),
 500         .gt = 2,
 501         .pipe_mask = 0, /* legal, last one wins */
 502         .cpu_transcoder_mask = 0,
 503         .has_l3_dpf = 1,
 504 };
 505
 506 static const struct intel_device_info vlv_info = {
 507         PLATFORM(INTEL_VALLEYVIEW),
 508         GEN(7),
 509         .is_lp = 1,
 510         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
 511         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
 512         .has_runtime_pm = 1,
 513         .has_rc6 = 1,
 514         .has_rps = true,
 515         .display.has_gmch = 1,
 516         .display.has_hotplug = 1,
 517         .dma_mask_size = 40,
 518         .ppgtt_type = INTEL_PPGTT_ALIASING,
 519         .ppgtt_size = 31,
 520         .has_snoop = true,
 521         .has_coherent_ggtt = false,
 522         .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
 523         .display_mmio_offset = VLV_DISPLAY_BASE,
 524         I9XX_PIPE_OFFSETS,
 525         I9XX_CURSOR_OFFSETS,
 526         I965_COLORS,
 527         GEN_DEFAULT_PAGE_SIZES,
 528         GEN_DEFAULT_REGIONS,
 529 };
 530
 531 #define G75_FEATURES  \
 532         GEN7_FEATURES, \
 533         .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
 534         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 535                 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
 536         .display.has_ddi = 1, \
 537         .has_fpga_dbg = 1, \
 538         .display.has_psr = 1, \
 539         .display.has_dp_mst = 1, \
 540         .has_rc6p = 0 /* RC6p removed-by HSW */, \
 541         HSW_PIPE_OFFSETS, \
 542         .has_runtime_pm = 1
 543
 544 #define HSW_PLATFORM \
 545         G75_FEATURES, \
 546         PLATFORM(INTEL_HASWELL), \
 547         .has_l3_dpf = 1
 548
 549 static const struct intel_device_info hsw_gt1_info = {
 550         HSW_PLATFORM,
 551         .gt = 1,
 552 };
 553
 554 static const struct intel_device_info hsw_gt2_info = {
 555         HSW_PLATFORM,
 556         .gt = 2,
 557 };
 558
 559 static const struct intel_device_info hsw_gt3_info = {
 560         HSW_PLATFORM,
 561         .gt = 3,
 562 };
 563
 564 #define GEN8_FEATURES \
 565         G75_FEATURES, \
 566         GEN(8), \
 567         .has_logical_ring_contexts = 1, \
 568         .dma_mask_size = 39, \
 569         .ppgtt_type = INTEL_PPGTT_FULL, \
 570         .ppgtt_size = 48, \
 571         .has_64bit_reloc = 1, \
 572         .has_reset_engine = 1
 573
 574 #define BDW_PLATFORM \
 575         GEN8_FEATURES, \
 576         PLATFORM(INTEL_BROADWELL)
 577
 578 static const struct intel_device_info bdw_gt1_info = {
 579         BDW_PLATFORM,
 580         .gt = 1,
 581 };
 582
 583 static const struct intel_device_info bdw_gt2_info = {
 584         BDW_PLATFORM,
 585         .gt = 2,
 586 };
 587
 588 static const struct intel_device_info bdw_rsvd_info = {
 589         BDW_PLATFORM,
 590         .gt = 3,
 591         /* According to the device ID those devices are GT3, they were
 592          * previously treated as not GT3, keep it like that.
 593          */
 594 };
 595
 596 static const struct intel_device_info bdw_gt3_info = {
 597         BDW_PLATFORM,
 598         .gt = 3,
 599         .engine_mask =
 600                 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
 601 };
 602
 603 static const struct intel_device_info chv_info = {
 604         PLATFORM(INTEL_CHERRYVIEW),
 605         GEN(8),
 606         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
 607         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
 608         .display.has_hotplug = 1,
 609         .is_lp = 1,
 610         .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
 611         .has_64bit_reloc = 1,
 612         .has_runtime_pm = 1,
 613         .has_rc6 = 1,
 614         .has_rps = true,
 615         .has_logical_ring_contexts = 1,
 616         .display.has_gmch = 1,
 617         .dma_mask_size = 39,
 618         .ppgtt_type = INTEL_PPGTT_FULL,
 619         .ppgtt_size = 32,
 620         .has_reset_engine = 1,
 621         .has_snoop = true,
 622         .has_coherent_ggtt = false,
 623         .display_mmio_offset = VLV_DISPLAY_BASE,
 624         CHV_PIPE_OFFSETS,
 625         CHV_CURSOR_OFFSETS,
 626         CHV_COLORS,
 627         GEN_DEFAULT_PAGE_SIZES,
 628         GEN_DEFAULT_REGIONS,
 629 };
 630
 631 #define GEN9_DEFAULT_PAGE_SIZES \
 632         .page_sizes = I915_GTT_PAGE_SIZE_4K | \
 633                       I915_GTT_PAGE_SIZE_64K
 634
 635 #define GEN9_FEATURES \
 636         GEN8_FEATURES, \
 637         GEN(9), \
 638         GEN9_DEFAULT_PAGE_SIZES, \
 639         .has_logical_ring_preemption = 1, \
 640         .display.has_csr = 1, \
 641         .has_gt_uc = 1, \
 642         .display.has_hdcp = 1, \
 643         .display.has_ipc = 1, \
 644         .ddb_size = 896, \
 645         .num_supported_dbuf_slices = 1
 646
 647 #define SKL_PLATFORM \
 648         GEN9_FEATURES, \
 649         PLATFORM(INTEL_SKYLAKE)
 650
 651 static const struct intel_device_info skl_gt1_info = {
 652         SKL_PLATFORM,
 653         .gt = 1,
 654 };
 655
 656 static const struct intel_device_info skl_gt2_info = {
 657         SKL_PLATFORM,
 658         .gt = 2,
 659 };
 660
 661 #define SKL_GT3_PLUS_PLATFORM \
 662         SKL_PLATFORM, \
 663         .engine_mask = \
 664                 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
 665
 666
 667 static const struct intel_device_info skl_gt3_info = {
 668         SKL_GT3_PLUS_PLATFORM,
 669         .gt = 3,
 670 };
 671
 672 static const struct intel_device_info skl_gt4_info = {
 673         SKL_GT3_PLUS_PLATFORM,
 674         .gt = 4,
 675 };
 676
 677 #define GEN9_LP_FEATURES \
 678         GEN(9), \
 679         .is_lp = 1, \
 680         .num_supported_dbuf_slices = 1, \
 681         .display.has_hotplug = 1, \
 682         .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
 683         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
 684         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 685                 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
 686                 BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
 687         .has_64bit_reloc = 1, \
 688         .display.has_ddi = 1, \
 689         .has_fpga_dbg = 1, \
 690         .display.has_fbc = 1, \
 691         .display.has_hdcp = 1, \
 692         .display.has_psr = 1, \
 693         .has_runtime_pm = 1, \
 694         .display.has_csr = 1, \
 695         .has_rc6 = 1, \
 696         .has_rps = true, \
 697         .display.has_dp_mst = 1, \
 698         .has_logical_ring_contexts = 1, \
 699         .has_logical_ring_preemption = 1, \
 700         .has_gt_uc = 1, \
 701         .dma_mask_size = 39, \
 702         .ppgtt_type = INTEL_PPGTT_FULL, \
 703         .ppgtt_size = 48, \
 704         .has_reset_engine = 1, \
 705         .has_snoop = true, \
 706         .has_coherent_ggtt = false, \
 707         .display.has_ipc = 1, \
 708         HSW_PIPE_OFFSETS, \
 709         IVB_CURSOR_OFFSETS, \
 710         IVB_COLORS, \
 711         GEN9_DEFAULT_PAGE_SIZES, \
 712         GEN_DEFAULT_REGIONS
 713
 714 static const struct intel_device_info bxt_info = {
 715         GEN9_LP_FEATURES,
 716         PLATFORM(INTEL_BROXTON),
 717         .ddb_size = 512,
 718 };
 719
 720 static const struct intel_device_info glk_info = {
 721         GEN9_LP_FEATURES,
 722         PLATFORM(INTEL_GEMINILAKE),
 723         .ddb_size = 1024,
 724         GLK_COLORS,
 725 };
 726
 727 #define KBL_PLATFORM \
 728         GEN9_FEATURES, \
 729         PLATFORM(INTEL_KABYLAKE)
 730
 731 static const struct intel_device_info kbl_gt1_info = {
 732         KBL_PLATFORM,
 733         .gt = 1,
 734 };
 735
 736 static const struct intel_device_info kbl_gt2_info = {
 737         KBL_PLATFORM,
 738         .gt = 2,
 739 };
 740
 741 static const struct intel_device_info kbl_gt3_info = {
 742         KBL_PLATFORM,
 743         .gt = 3,
 744         .engine_mask =
 745                 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
 746 };
 747
 748 #define CFL_PLATFORM \
 749         GEN9_FEATURES, \
 750         PLATFORM(INTEL_COFFEELAKE)
 751
 752 static const struct intel_device_info cfl_gt1_info = {
 753         CFL_PLATFORM,
 754         .gt = 1,
 755 };
 756
 757 static const struct intel_device_info cfl_gt2_info = {
 758         CFL_PLATFORM,
 759         .gt = 2,
 760 };
 761
 762 static const struct intel_device_info cfl_gt3_info = {
 763         CFL_PLATFORM,
 764         .gt = 3,
 765         .engine_mask =
 766                 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
 767 };
 768
 769 #define CML_PLATFORM \
 770         GEN9_FEATURES, \
 771         PLATFORM(INTEL_COMETLAKE)
 772
 773 static const struct intel_device_info cml_gt1_info = {
 774         CML_PLATFORM,
 775         .gt = 1,
 776 };
 777
 778 static const struct intel_device_info cml_gt2_info = {
 779         CML_PLATFORM,
 780         .gt = 2,
 781 };
 782
 783 #define GEN10_FEATURES \
 784         GEN9_FEATURES, \
 785         GEN(10), \
 786         .ddb_size = 1024, \
 787         .display.has_dsc = 1, \
 788         .has_coherent_ggtt = false, \
 789         GLK_COLORS
 790
 791 static const struct intel_device_info cnl_info = {
 792         GEN10_FEATURES,
 793         PLATFORM(INTEL_CANNONLAKE),
 794         .gt = 2,
 795 };
 796
 797 #define GEN11_DEFAULT_PAGE_SIZES \
 798         .page_sizes = I915_GTT_PAGE_SIZE_4K | \
 799                       I915_GTT_PAGE_SIZE_64K | \
 800                       I915_GTT_PAGE_SIZE_2M
 801
 802 #define GEN11_FEATURES \
 803         GEN10_FEATURES, \
 804         GEN11_DEFAULT_PAGE_SIZES, \
 805         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 806                 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
 807                 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
 808         .pipe_offsets = { \
 809                 [TRANSCODER_A] = PIPE_A_OFFSET, \
 810                 [TRANSCODER_B] = PIPE_B_OFFSET, \
 811                 [TRANSCODER_C] = PIPE_C_OFFSET, \
 812                 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
 813                 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
 814                 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
 815         }, \
 816         .trans_offsets = { \
 817                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
 818                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
 819                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
 820                 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
 821                 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
 822                 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
 823         }, \
 824         GEN(11), \
 825         .ddb_size = 2048, \
 826         .num_supported_dbuf_slices = 2, \
 827         .has_logical_ring_elsq = 1, \
 828         .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }
 829
 830 static const struct intel_device_info icl_info = {
 831         GEN11_FEATURES,
 832         PLATFORM(INTEL_ICELAKE),
 833         .engine_mask =
 834                 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
 835 };
 836
 837 static const struct intel_device_info ehl_info = {
 838         GEN11_FEATURES,
 839         PLATFORM(INTEL_ELKHARTLAKE),
 840         .require_force_probe = 1,
 841         .engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
 842         .ppgtt_size = 36,
 843 };
 844
 845 #define GEN12_FEATURES \
 846         GEN11_FEATURES, \
 847         GEN(12), \
 848         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
 849         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 850                 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
 851                 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
 852         .pipe_offsets = { \
 853                 [TRANSCODER_A] = PIPE_A_OFFSET, \
 854                 [TRANSCODER_B] = PIPE_B_OFFSET, \
 855                 [TRANSCODER_C] = PIPE_C_OFFSET, \
 856                 [TRANSCODER_D] = PIPE_D_OFFSET, \
 857                 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
 858                 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
 859         }, \
 860         .trans_offsets = { \
 861                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
 862                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
 863                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
 864                 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
 865                 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
 866                 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
 867         }, \
 868         TGL_CURSOR_OFFSETS, \
 869         .has_global_mocs = 1, \
 870         .display.has_dsb = 1
 871
 872 static const struct intel_device_info tgl_info = {
 873         GEN12_FEATURES,
 874         PLATFORM(INTEL_TIGERLAKE),
 875         .display.has_modular_fia = 1,
 876         .engine_mask =
 877                 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
 878 };
 879
 880 static const struct intel_device_info rkl_info = {
 881         GEN12_FEATURES,
 882         PLATFORM(INTEL_ROCKETLAKE),
 883         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
 884         .require_force_probe = 1,
 885         .engine_mask =
 886                 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
 887 };
 888
 889 #define GEN12_DGFX_FEATURES \
 890         GEN12_FEATURES, \
 891         .is_dgfx = 1
 892
 893 #undef GEN
 894 #undef PLATFORM
 895
 896 /*
 897  * Make sure any device matches here are from most specific to most
 898  * general.  For example, since the Quanta match is based on the subsystem
 899  * and subvendor IDs, we need it to come before the more general IVB
 900  * PCI ID matches, otherwise we'll use the wrong info struct above.
 901  */
 902 static const struct pci_device_id pciidlist[] = {
 903         INTEL_I830_IDS(&i830_info),
 904         INTEL_I845G_IDS(&i845g_info),
 905         INTEL_I85X_IDS(&i85x_info),
 906         INTEL_I865G_IDS(&i865g_info),
 907         INTEL_I915G_IDS(&i915g_info),
 908         INTEL_I915GM_IDS(&i915gm_info),
 909         INTEL_I945G_IDS(&i945g_info),
 910         INTEL_I945GM_IDS(&i945gm_info),
 911         INTEL_I965G_IDS(&i965g_info),
 912         INTEL_G33_IDS(&g33_info),
 913         INTEL_I965GM_IDS(&i965gm_info),
 914         INTEL_GM45_IDS(&gm45_info),
 915         INTEL_G45_IDS(&g45_info),
 916         INTEL_PINEVIEW_G_IDS(&pnv_g_info),
 917         INTEL_PINEVIEW_M_IDS(&pnv_m_info),
 918         INTEL_IRONLAKE_D_IDS(&ilk_d_info),
 919         INTEL_IRONLAKE_M_IDS(&ilk_m_info),
 920         INTEL_SNB_D_GT1_IDS(&snb_d_gt1_info),
 921         INTEL_SNB_D_GT2_IDS(&snb_d_gt2_info),
 922         INTEL_SNB_M_GT1_IDS(&snb_m_gt1_info),
 923         INTEL_SNB_M_GT2_IDS(&snb_m_gt2_info),
 924         INTEL_IVB_Q_IDS(&ivb_q_info), /* must be first IVB */
 925         INTEL_IVB_M_GT1_IDS(&ivb_m_gt1_info),
 926         INTEL_IVB_M_GT2_IDS(&ivb_m_gt2_info),
 927         INTEL_IVB_D_GT1_IDS(&ivb_d_gt1_info),
 928         INTEL_IVB_D_GT2_IDS(&ivb_d_gt2_info),
 929         INTEL_HSW_GT1_IDS(&hsw_gt1_info),
 930         INTEL_HSW_GT2_IDS(&hsw_gt2_info),
 931         INTEL_HSW_GT3_IDS(&hsw_gt3_info),
 932         INTEL_VLV_IDS(&vlv_info),
 933         INTEL_BDW_GT1_IDS(&bdw_gt1_info),
 934         INTEL_BDW_GT2_IDS(&bdw_gt2_info),
 935         INTEL_BDW_GT3_IDS(&bdw_gt3_info),
 936         INTEL_BDW_RSVD_IDS(&bdw_rsvd_info),
 937         INTEL_CHV_IDS(&chv_info),
 938         INTEL_SKL_GT1_IDS(&skl_gt1_info),
 939         INTEL_SKL_GT2_IDS(&skl_gt2_info),
 940         INTEL_SKL_GT3_IDS(&skl_gt3_info),
 941         INTEL_SKL_GT4_IDS(&skl_gt4_info),
 942         INTEL_BXT_IDS(&bxt_info),
 943         INTEL_GLK_IDS(&glk_info),
 944         INTEL_KBL_GT1_IDS(&kbl_gt1_info),
 945         INTEL_KBL_GT2_IDS(&kbl_gt2_info),
 946         INTEL_KBL_GT3_IDS(&kbl_gt3_info),
 947         INTEL_KBL_GT4_IDS(&kbl_gt3_info),
 948         INTEL_AML_KBL_GT2_IDS(&kbl_gt2_info),
 949         INTEL_CFL_S_GT1_IDS(&cfl_gt1_info),
 950         INTEL_CFL_S_GT2_IDS(&cfl_gt2_info),
 951         INTEL_CFL_H_GT1_IDS(&cfl_gt1_info),
 952         INTEL_CFL_H_GT2_IDS(&cfl_gt2_info),
 953         INTEL_CFL_U_GT2_IDS(&cfl_gt2_info),
 954         INTEL_CFL_U_GT3_IDS(&cfl_gt3_info),
 955         INTEL_WHL_U_GT1_IDS(&cfl_gt1_info),
 956         INTEL_WHL_U_GT2_IDS(&cfl_gt2_info),
 957         INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info),
 958         INTEL_WHL_U_GT3_IDS(&cfl_gt3_info),
 959         INTEL_CML_GT1_IDS(&cml_gt1_info),
 960         INTEL_CML_GT2_IDS(&cml_gt2_info),
 961         INTEL_CML_U_GT1_IDS(&cml_gt1_info),
 962         INTEL_CML_U_GT2_IDS(&cml_gt2_info),
 963         INTEL_CNL_IDS(&cnl_info),
 964         INTEL_ICL_11_IDS(&icl_info),
 965         INTEL_EHL_IDS(&ehl_info),
 966         INTEL_TGL_12_IDS(&tgl_info),
 967         INTEL_RKL_IDS(&rkl_info),
 968         {0, 0, 0}
 969 };
 970 MODULE_DEVICE_TABLE(pci, pciidlist);
 971
 972 static void i915_pci_remove(struct pci_dev *pdev)
 973 {
 974         struct drm_i915_private *i915;
 975
 976         i915 = pci_get_drvdata(pdev);
 977         if (!i915) /* driver load aborted, nothing to cleanup */
 978                 return;
 979
 980         i915_driver_remove(i915);
 981         pci_set_drvdata(pdev, NULL);
 982
 983         drm_dev_put(&i915->drm);
 984 }
 985
 986 /* is device_id present in comma separated list of ids */
 987 static bool force_probe(u16 device_id, const char *devices)
 988 {
 989         char *s, *p, *tok;
 990         bool ret;
 991
 992         if (!devices || !*devices)
 993                 return false;
 994
 995         /* match everything */
 996         if (strcmp(devices, "*") == 0)
 997                 return true;
 998
 999         s = kstrdup(devices, GFP_KERNEL);
1000         if (!s)
1001                 return false;
1002
1003         for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) {
1004                 u16 val;
1005
1006                 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) {
1007                         ret = true;
1008                         break;
1009                 }
1010         }
1011
1012         kfree(s);
1013
1014         return ret;
1015 }
1016
1017 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1018 {
1019         struct intel_device_info *intel_info =
1020                 (struct intel_device_info *) ent->driver_data;
1021         int err;
1022
1023         if (intel_info->require_force_probe &&
1024             !force_probe(pdev->device, i915_modparams.force_probe)) {
1025                 dev_info(&pdev->dev,
1026                          "Your graphics device %04x is not properly supported by the driver in this\n"
1027                          "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n"
1028                          "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n"
1029                          "or (recommended) check for kernel updates.\n",
1030                          pdev->device, pdev->device, pdev->device);
1031                 return -ENODEV;
1032         }
1033
1034         /* Only bind to function 0 of the device. Early generations
1035          * used function 1 as a placeholder for multi-head. This causes
1036          * us confusion instead, especially on the systems where both
1037          * functions have the same PCI-ID!
1038          */
1039         if (PCI_FUNC(pdev->devfn))
1040                 return -ENODEV;
1041
1042         /*
1043          * apple-gmux is needed on dual GPU MacBook Pro
1044          * to probe the panel if we're the inactive GPU.
1045          */
1046         if (vga_switcheroo_client_probe_defer(pdev))
1047                 return -EPROBE_DEFER;
1048
1049         err = i915_driver_probe(pdev, ent);
1050         if (err)
1051                 return err;
1052
1053         if (i915_inject_probe_failure(pci_get_drvdata(pdev))) {
1054                 i915_pci_remove(pdev);
1055                 return -ENODEV;
1056         }
1057
1058         err = i915_live_selftests(pdev);
1059         if (err) {
1060                 i915_pci_remove(pdev);
1061                 return err > 0 ? -ENOTTY : err;
1062         }
1063
1064         err = i915_perf_selftests(pdev);
1065         if (err) {
1066                 i915_pci_remove(pdev);
1067                 return err > 0 ? -ENOTTY : err;
1068         }
1069
1070         return 0;
1071 }
1072
1073 static struct pci_driver i915_pci_driver = {
1074         .name = DRIVER_NAME,
1075         .id_table = pciidlist,
1076         .probe = i915_pci_probe,
1077         .remove = i915_pci_remove,
1078         .driver.pm = &i915_pm_ops,
1079 };
1080
1081 static int __init i915_init(void)
1082 {
1083         bool use_kms = true;
1084         int err;
1085
1086         err = i915_globals_init();
1087         if (err)
1088                 return err;
1089
1090         err = i915_mock_selftests();
1091         if (err)
1092                 return err > 0 ? 0 : err;
1093
1094         /*
1095          * Enable KMS by default, unless explicitly overriden by
1096          * either the i915.modeset prarameter or by the
1097          * vga_text_mode_force boot option.
1098          */
1099
1100         if (i915_modparams.modeset == 0)
1101                 use_kms = false;
1102
1103         if (vgacon_text_force() && i915_modparams.modeset == -1)
1104                 use_kms = false;
1105
1106         if (!use_kms) {
1107                 /* Silently fail loading to not upset userspace. */
1108                 DRM_DEBUG_DRIVER("KMS disabled.\n");
1109                 return 0;
1110         }
1111
1112         err = pci_register_driver(&i915_pci_driver);
1113         if (err)
1114                 return err;
1115
1116         i915_perf_sysctl_register();
1117         return 0;
1118 }
1119
1120 static void __exit i915_exit(void)
1121 {
1122         if (!i915_pci_driver.driver.owner)
1123                 return;
1124
1125         i915_perf_sysctl_unregister();
1126         pci_unregister_driver(&i915_pci_driver);
1127         i915_globals_exit();
1128 }
1129
1130 module_init(i915_init);
1131 module_exit(i915_exit);
1132
1133 MODULE_AUTHOR("Tungsten Graphics, Inc.");
1134 MODULE_AUTHOR("Intel Corporation");
1135
1136 MODULE_DESCRIPTION(DRIVER_DESC);
1137 MODULE_LICENSE("GPL and additional rights");