2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include <linux/vga_switcheroo.h>
27 #include <drm/drm_drv.h>
28 #include <drm/i915_pciids.h>
33 #define PLATFORM(x) .platform = (x)
35 .graphics_ver = (x), \
39 #define I845_PIPE_OFFSETS \
41 [TRANSCODER_A] = PIPE_A_OFFSET, \
44 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
47 #define I9XX_PIPE_OFFSETS \
49 [TRANSCODER_A] = PIPE_A_OFFSET, \
50 [TRANSCODER_B] = PIPE_B_OFFSET, \
53 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
54 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
57 #define IVB_PIPE_OFFSETS \
59 [TRANSCODER_A] = PIPE_A_OFFSET, \
60 [TRANSCODER_B] = PIPE_B_OFFSET, \
61 [TRANSCODER_C] = PIPE_C_OFFSET, \
64 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
65 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
66 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
69 #define HSW_PIPE_OFFSETS \
71 [TRANSCODER_A] = PIPE_A_OFFSET, \
72 [TRANSCODER_B] = PIPE_B_OFFSET, \
73 [TRANSCODER_C] = PIPE_C_OFFSET, \
74 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
77 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
78 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
79 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
80 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
83 #define CHV_PIPE_OFFSETS \
85 [TRANSCODER_A] = PIPE_A_OFFSET, \
86 [TRANSCODER_B] = PIPE_B_OFFSET, \
87 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
90 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
91 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
92 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
95 #define I845_CURSOR_OFFSETS \
97 [PIPE_A] = CURSOR_A_OFFSET, \
100 #define I9XX_CURSOR_OFFSETS \
101 .cursor_offsets = { \
102 [PIPE_A] = CURSOR_A_OFFSET, \
103 [PIPE_B] = CURSOR_B_OFFSET, \
106 #define CHV_CURSOR_OFFSETS \
107 .cursor_offsets = { \
108 [PIPE_A] = CURSOR_A_OFFSET, \
109 [PIPE_B] = CURSOR_B_OFFSET, \
110 [PIPE_C] = CHV_CURSOR_C_OFFSET, \
113 #define IVB_CURSOR_OFFSETS \
114 .cursor_offsets = { \
115 [PIPE_A] = CURSOR_A_OFFSET, \
116 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
117 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
120 #define TGL_CURSOR_OFFSETS \
121 .cursor_offsets = { \
122 [PIPE_A] = CURSOR_A_OFFSET, \
123 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
124 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
125 [PIPE_D] = TGL_CURSOR_D_OFFSET, \
128 #define I9XX_COLORS \
129 .color = { .gamma_lut_size = 256 }
130 #define I965_COLORS \
131 .color = { .gamma_lut_size = 129, \
132 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
135 .color = { .gamma_lut_size = 1024 }
137 .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
139 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \
140 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
141 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
144 .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024, \
145 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
146 DRM_COLOR_LUT_EQUAL_CHANNELS, \
149 /* Keep in gen based order, and chronological order within a gen */
151 #define GEN_DEFAULT_PAGE_SIZES \
152 .page_sizes = I915_GTT_PAGE_SIZE_4K
154 #define GEN_DEFAULT_REGIONS \
155 .memory_regions = REGION_SMEM | REGION_STOLEN_SMEM
157 #define I830_FEATURES \
160 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
161 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
162 .display.has_overlay = 1, \
163 .display.cursor_needs_physical = 1, \
164 .display.overlay_needs_physical = 1, \
165 .display.has_gmch = 1, \
166 .gpu_reset_clobbers_display = true, \
167 .hws_needs_physical = 1, \
168 .unfenced_needs_alignment = 1, \
169 .platform_engine_mask = BIT(RCS0), \
171 .has_coherent_ggtt = false, \
172 .dma_mask_size = 32, \
174 I9XX_CURSOR_OFFSETS, \
176 GEN_DEFAULT_PAGE_SIZES, \
179 #define I845_FEATURES \
181 .pipe_mask = BIT(PIPE_A), \
182 .cpu_transcoder_mask = BIT(TRANSCODER_A), \
183 .display.has_overlay = 1, \
184 .display.overlay_needs_physical = 1, \
185 .display.has_gmch = 1, \
186 .gpu_reset_clobbers_display = true, \
187 .hws_needs_physical = 1, \
188 .unfenced_needs_alignment = 1, \
189 .platform_engine_mask = BIT(RCS0), \
191 .has_coherent_ggtt = false, \
192 .dma_mask_size = 32, \
194 I845_CURSOR_OFFSETS, \
196 GEN_DEFAULT_PAGE_SIZES, \
199 static const struct intel_device_info i830_info = {
201 PLATFORM(INTEL_I830),
204 static const struct intel_device_info i845g_info = {
206 PLATFORM(INTEL_I845G),
209 static const struct intel_device_info i85x_info = {
211 PLATFORM(INTEL_I85X),
212 .display.has_fbc = 1,
215 static const struct intel_device_info i865g_info = {
217 PLATFORM(INTEL_I865G),
218 .display.has_fbc = 1,
221 #define GEN3_FEATURES \
223 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
224 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
225 .display.has_gmch = 1, \
226 .gpu_reset_clobbers_display = true, \
227 .platform_engine_mask = BIT(RCS0), \
229 .has_coherent_ggtt = true, \
230 .dma_mask_size = 32, \
232 I9XX_CURSOR_OFFSETS, \
234 GEN_DEFAULT_PAGE_SIZES, \
237 static const struct intel_device_info i915g_info = {
239 PLATFORM(INTEL_I915G),
240 .has_coherent_ggtt = false,
241 .display.cursor_needs_physical = 1,
242 .display.has_overlay = 1,
243 .display.overlay_needs_physical = 1,
244 .hws_needs_physical = 1,
245 .unfenced_needs_alignment = 1,
248 static const struct intel_device_info i915gm_info = {
250 PLATFORM(INTEL_I915GM),
252 .display.cursor_needs_physical = 1,
253 .display.has_overlay = 1,
254 .display.overlay_needs_physical = 1,
255 .display.supports_tv = 1,
256 .display.has_fbc = 1,
257 .hws_needs_physical = 1,
258 .unfenced_needs_alignment = 1,
261 static const struct intel_device_info i945g_info = {
263 PLATFORM(INTEL_I945G),
264 .display.has_hotplug = 1,
265 .display.cursor_needs_physical = 1,
266 .display.has_overlay = 1,
267 .display.overlay_needs_physical = 1,
268 .hws_needs_physical = 1,
269 .unfenced_needs_alignment = 1,
272 static const struct intel_device_info i945gm_info = {
274 PLATFORM(INTEL_I945GM),
276 .display.has_hotplug = 1,
277 .display.cursor_needs_physical = 1,
278 .display.has_overlay = 1,
279 .display.overlay_needs_physical = 1,
280 .display.supports_tv = 1,
281 .display.has_fbc = 1,
282 .hws_needs_physical = 1,
283 .unfenced_needs_alignment = 1,
286 static const struct intel_device_info g33_info = {
289 .display.has_hotplug = 1,
290 .display.has_overlay = 1,
294 static const struct intel_device_info pnv_g_info = {
296 PLATFORM(INTEL_PINEVIEW),
297 .display.has_hotplug = 1,
298 .display.has_overlay = 1,
302 static const struct intel_device_info pnv_m_info = {
304 PLATFORM(INTEL_PINEVIEW),
306 .display.has_hotplug = 1,
307 .display.has_overlay = 1,
311 #define GEN4_FEATURES \
313 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
314 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
315 .display.has_hotplug = 1, \
316 .display.has_gmch = 1, \
317 .gpu_reset_clobbers_display = true, \
318 .platform_engine_mask = BIT(RCS0), \
320 .has_coherent_ggtt = true, \
321 .dma_mask_size = 36, \
323 I9XX_CURSOR_OFFSETS, \
325 GEN_DEFAULT_PAGE_SIZES, \
328 static const struct intel_device_info i965g_info = {
330 PLATFORM(INTEL_I965G),
331 .display.has_overlay = 1,
332 .hws_needs_physical = 1,
336 static const struct intel_device_info i965gm_info = {
338 PLATFORM(INTEL_I965GM),
340 .display.has_fbc = 1,
341 .display.has_overlay = 1,
342 .display.supports_tv = 1,
343 .hws_needs_physical = 1,
347 static const struct intel_device_info g45_info = {
350 .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
351 .gpu_reset_clobbers_display = false,
354 static const struct intel_device_info gm45_info = {
356 PLATFORM(INTEL_GM45),
358 .display.has_fbc = 1,
359 .display.supports_tv = 1,
360 .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
361 .gpu_reset_clobbers_display = false,
364 #define GEN5_FEATURES \
366 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
367 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
368 .display.has_hotplug = 1, \
369 .platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
371 .has_coherent_ggtt = true, \
372 /* ilk does support rc6, but we do not implement [power] contexts */ \
374 .dma_mask_size = 36, \
376 I9XX_CURSOR_OFFSETS, \
378 GEN_DEFAULT_PAGE_SIZES, \
381 static const struct intel_device_info ilk_d_info = {
383 PLATFORM(INTEL_IRONLAKE),
386 static const struct intel_device_info ilk_m_info = {
388 PLATFORM(INTEL_IRONLAKE),
391 .display.has_fbc = 1,
394 #define GEN6_FEATURES \
396 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
397 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
398 .display.has_hotplug = 1, \
399 .display.has_fbc = 1, \
400 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
401 .has_coherent_ggtt = true, \
406 .dma_mask_size = 40, \
407 .ppgtt_type = INTEL_PPGTT_ALIASING, \
410 I9XX_CURSOR_OFFSETS, \
412 GEN_DEFAULT_PAGE_SIZES, \
415 #define SNB_D_PLATFORM \
417 PLATFORM(INTEL_SANDYBRIDGE)
419 static const struct intel_device_info snb_d_gt1_info = {
424 static const struct intel_device_info snb_d_gt2_info = {
429 #define SNB_M_PLATFORM \
431 PLATFORM(INTEL_SANDYBRIDGE), \
435 static const struct intel_device_info snb_m_gt1_info = {
440 static const struct intel_device_info snb_m_gt2_info = {
445 #define GEN7_FEATURES \
447 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
448 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
449 .display.has_hotplug = 1, \
450 .display.has_fbc = 1, \
451 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
452 .has_coherent_ggtt = true, \
456 .has_reset_engine = true, \
458 .dma_mask_size = 40, \
459 .ppgtt_type = INTEL_PPGTT_ALIASING, \
462 IVB_CURSOR_OFFSETS, \
464 GEN_DEFAULT_PAGE_SIZES, \
467 #define IVB_D_PLATFORM \
469 PLATFORM(INTEL_IVYBRIDGE), \
472 static const struct intel_device_info ivb_d_gt1_info = {
477 static const struct intel_device_info ivb_d_gt2_info = {
482 #define IVB_M_PLATFORM \
484 PLATFORM(INTEL_IVYBRIDGE), \
488 static const struct intel_device_info ivb_m_gt1_info = {
493 static const struct intel_device_info ivb_m_gt2_info = {
498 static const struct intel_device_info ivb_q_info = {
500 PLATFORM(INTEL_IVYBRIDGE),
502 .pipe_mask = 0, /* legal, last one wins */
503 .cpu_transcoder_mask = 0,
507 static const struct intel_device_info vlv_info = {
508 PLATFORM(INTEL_VALLEYVIEW),
511 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
512 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
515 .has_reset_engine = true,
517 .display.has_gmch = 1,
518 .display.has_hotplug = 1,
520 .ppgtt_type = INTEL_PPGTT_ALIASING,
523 .has_coherent_ggtt = false,
524 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
525 .display_mmio_offset = VLV_DISPLAY_BASE,
529 GEN_DEFAULT_PAGE_SIZES,
533 #define G75_FEATURES \
535 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
536 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
537 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
538 .display.has_ddi = 1, \
539 .display.has_fpga_dbg = 1, \
540 .display.has_psr = 1, \
541 .display.has_psr_hw_tracking = 1, \
542 .display.has_dp_mst = 1, \
543 .has_rc6p = 0 /* RC6p removed-by HSW */, \
547 #define HSW_PLATFORM \
549 PLATFORM(INTEL_HASWELL), \
552 static const struct intel_device_info hsw_gt1_info = {
557 static const struct intel_device_info hsw_gt2_info = {
562 static const struct intel_device_info hsw_gt3_info = {
567 #define GEN8_FEATURES \
570 .has_logical_ring_contexts = 1, \
571 .dma_mask_size = 39, \
572 .ppgtt_type = INTEL_PPGTT_FULL, \
576 #define BDW_PLATFORM \
578 PLATFORM(INTEL_BROADWELL)
580 static const struct intel_device_info bdw_gt1_info = {
585 static const struct intel_device_info bdw_gt2_info = {
590 static const struct intel_device_info bdw_rsvd_info = {
593 /* According to the device ID those devices are GT3, they were
594 * previously treated as not GT3, keep it like that.
598 static const struct intel_device_info bdw_gt3_info = {
601 .platform_engine_mask =
602 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
605 static const struct intel_device_info chv_info = {
606 PLATFORM(INTEL_CHERRYVIEW),
608 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
609 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
610 .display.has_hotplug = 1,
612 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
613 .has_64bit_reloc = 1,
617 .has_logical_ring_contexts = 1,
618 .display.has_gmch = 1,
620 .ppgtt_type = INTEL_PPGTT_FULL,
622 .has_reset_engine = 1,
624 .has_coherent_ggtt = false,
625 .display_mmio_offset = VLV_DISPLAY_BASE,
629 GEN_DEFAULT_PAGE_SIZES,
633 #define GEN9_DEFAULT_PAGE_SIZES \
634 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
635 I915_GTT_PAGE_SIZE_64K
637 #define GEN9_FEATURES \
640 GEN9_DEFAULT_PAGE_SIZES, \
641 .display.has_dmc = 1, \
643 .display.has_hdcp = 1, \
644 .display.has_ipc = 1, \
645 .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
646 .dbuf.slice_mask = BIT(DBUF_S1)
648 #define SKL_PLATFORM \
650 PLATFORM(INTEL_SKYLAKE)
652 static const struct intel_device_info skl_gt1_info = {
657 static const struct intel_device_info skl_gt2_info = {
662 #define SKL_GT3_PLUS_PLATFORM \
664 .platform_engine_mask = \
665 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
668 static const struct intel_device_info skl_gt3_info = {
669 SKL_GT3_PLUS_PLATFORM,
673 static const struct intel_device_info skl_gt4_info = {
674 SKL_GT3_PLUS_PLATFORM,
678 #define GEN9_LP_FEATURES \
681 .dbuf.slice_mask = BIT(DBUF_S1), \
682 .display.has_hotplug = 1, \
683 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
684 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
685 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
686 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
687 BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
688 .has_64bit_reloc = 1, \
689 .display.has_ddi = 1, \
690 .display.has_fpga_dbg = 1, \
691 .display.has_fbc = 1, \
692 .display.has_hdcp = 1, \
693 .display.has_psr = 1, \
694 .display.has_psr_hw_tracking = 1, \
695 .has_runtime_pm = 1, \
696 .display.has_dmc = 1, \
699 .display.has_dp_mst = 1, \
700 .has_logical_ring_contexts = 1, \
702 .dma_mask_size = 39, \
703 .ppgtt_type = INTEL_PPGTT_FULL, \
705 .has_reset_engine = 1, \
707 .has_coherent_ggtt = false, \
708 .display.has_ipc = 1, \
710 IVB_CURSOR_OFFSETS, \
712 GEN9_DEFAULT_PAGE_SIZES, \
715 static const struct intel_device_info bxt_info = {
717 PLATFORM(INTEL_BROXTON),
718 .dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
721 static const struct intel_device_info glk_info = {
723 PLATFORM(INTEL_GEMINILAKE),
725 .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
729 #define KBL_PLATFORM \
731 PLATFORM(INTEL_KABYLAKE)
733 static const struct intel_device_info kbl_gt1_info = {
738 static const struct intel_device_info kbl_gt2_info = {
743 static const struct intel_device_info kbl_gt3_info = {
746 .platform_engine_mask =
747 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
750 #define CFL_PLATFORM \
752 PLATFORM(INTEL_COFFEELAKE)
754 static const struct intel_device_info cfl_gt1_info = {
759 static const struct intel_device_info cfl_gt2_info = {
764 static const struct intel_device_info cfl_gt3_info = {
767 .platform_engine_mask =
768 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
771 #define CML_PLATFORM \
773 PLATFORM(INTEL_COMETLAKE)
775 static const struct intel_device_info cml_gt1_info = {
780 static const struct intel_device_info cml_gt2_info = {
785 #define GEN11_DEFAULT_PAGE_SIZES \
786 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
787 I915_GTT_PAGE_SIZE_64K | \
788 I915_GTT_PAGE_SIZE_2M
790 #define GEN11_FEATURES \
792 GEN11_DEFAULT_PAGE_SIZES, \
793 .abox_mask = BIT(0), \
794 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
795 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
796 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
798 [TRANSCODER_A] = PIPE_A_OFFSET, \
799 [TRANSCODER_B] = PIPE_B_OFFSET, \
800 [TRANSCODER_C] = PIPE_C_OFFSET, \
801 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
802 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
803 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
806 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
807 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
808 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
809 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
810 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
811 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
814 .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }, \
816 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
817 .display.has_dsc = 1, \
818 .has_coherent_ggtt = false, \
819 .has_logical_ring_elsq = 1
821 static const struct intel_device_info icl_info = {
823 PLATFORM(INTEL_ICELAKE),
824 .platform_engine_mask =
825 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
828 static const struct intel_device_info ehl_info = {
830 PLATFORM(INTEL_ELKHARTLAKE),
831 .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
835 static const struct intel_device_info jsl_info = {
837 PLATFORM(INTEL_JASPERLAKE),
838 .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
842 #define GEN12_FEATURES \
845 .abox_mask = GENMASK(2, 1), \
846 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
847 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
848 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
849 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
851 [TRANSCODER_A] = PIPE_A_OFFSET, \
852 [TRANSCODER_B] = PIPE_B_OFFSET, \
853 [TRANSCODER_C] = PIPE_C_OFFSET, \
854 [TRANSCODER_D] = PIPE_D_OFFSET, \
855 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
856 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
859 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
860 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
861 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
862 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
863 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
864 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
866 TGL_CURSOR_OFFSETS, \
867 .has_global_mocs = 1, \
870 static const struct intel_device_info tgl_info = {
872 PLATFORM(INTEL_TIGERLAKE),
873 .display.has_modular_fia = 1,
874 .platform_engine_mask =
875 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
878 static const struct intel_device_info rkl_info = {
880 PLATFORM(INTEL_ROCKETLAKE),
882 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
883 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
885 .display.has_hti = 1,
886 .display.has_psr_hw_tracking = 0,
887 .platform_engine_mask =
888 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
891 #define DGFX_FEATURES \
892 .memory_regions = REGION_SMEM | REGION_LMEM | REGION_STOLEN_LMEM, \
897 static const struct intel_device_info dg1_info __maybe_unused = {
902 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
903 .require_force_probe = 1,
904 .platform_engine_mask =
905 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
906 BIT(VCS0) | BIT(VCS2),
911 static const struct intel_device_info adl_s_info = {
913 PLATFORM(INTEL_ALDERLAKE_S),
914 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
915 .require_force_probe = 1,
916 .display.has_hti = 1,
917 .display.has_psr_hw_tracking = 0,
918 .platform_engine_mask =
919 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
923 #define XE_LPD_CURSOR_OFFSETS \
924 .cursor_offsets = { \
925 [PIPE_A] = CURSOR_A_OFFSET, \
926 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
927 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
928 [PIPE_D] = TGL_CURSOR_D_OFFSET, \
931 #define XE_LPD_FEATURES \
932 .abox_mask = GENMASK(1, 0), \
933 .color = { .degamma_lut_size = 0, .gamma_lut_size = 0 }, \
934 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
935 BIT(TRANSCODER_C) | BIT(TRANSCODER_D), \
937 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
939 .display.has_ddi = 1, \
940 .display.has_dmc = 1, \
941 .display.has_dp_mst = 1, \
942 .display.has_dsb = 1, \
943 .display.has_dsc = 1, \
944 .display.has_fbc = 1, \
945 .display.has_fpga_dbg = 1, \
946 .display.has_hdcp = 1, \
947 .display.has_hotplug = 1, \
948 .display.has_ipc = 1, \
949 .display.has_psr = 1, \
951 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
953 [TRANSCODER_A] = PIPE_A_OFFSET, \
954 [TRANSCODER_B] = PIPE_B_OFFSET, \
955 [TRANSCODER_C] = PIPE_C_OFFSET, \
956 [TRANSCODER_D] = PIPE_D_OFFSET, \
959 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
960 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
961 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
962 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
964 XE_LPD_CURSOR_OFFSETS
966 static const struct intel_device_info adl_p_info = {
969 PLATFORM(INTEL_ALDERLAKE_P),
970 .require_force_probe = 1,
971 .display.has_cdclk_crawl = 1,
972 .display.has_modular_fia = 1,
973 .display.has_psr_hw_tracking = 0,
974 .platform_engine_mask =
975 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
982 #define XE_HP_PAGE_SIZES \
983 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
984 I915_GTT_PAGE_SIZE_64K | \
985 I915_GTT_PAGE_SIZE_2M
987 #define XE_HP_FEATURES \
988 .graphics_ver = 12, \
989 .graphics_rel = 50, \
991 .dma_mask_size = 46, \
992 .has_64bit_reloc = 1, \
993 .has_global_mocs = 1, \
996 .has_logical_ring_contexts = 1, \
997 .has_logical_ring_elsq = 1, \
1000 .has_reset_engine = 1, \
1002 .has_runtime_pm = 1, \
1004 .ppgtt_type = INTEL_PPGTT_FULL
1006 #define XE_HPM_FEATURES \
1011 static const struct intel_device_info xehpsdv_info = {
1015 PLATFORM(INTEL_XEHPSDV),
1018 .platform_engine_mask =
1019 BIT(RCS0) | BIT(BCS0) |
1020 BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) |
1021 BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) |
1022 BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7),
1023 .require_force_probe = 1,
1027 static const struct intel_device_info dg2_info = {
1034 PLATFORM(INTEL_DG2),
1035 .platform_engine_mask =
1036 BIT(RCS0) | BIT(BCS0) |
1037 BIT(VECS0) | BIT(VECS1) |
1038 BIT(VCS0) | BIT(VCS2),
1039 .require_force_probe = 1,
1045 * Make sure any device matches here are from most specific to most
1046 * general. For example, since the Quanta match is based on the subsystem
1047 * and subvendor IDs, we need it to come before the more general IVB
1048 * PCI ID matches, otherwise we'll use the wrong info struct above.
1050 static const struct pci_device_id pciidlist[] = {
1051 INTEL_I830_IDS(&i830_info),
1052 INTEL_I845G_IDS(&i845g_info),
1053 INTEL_I85X_IDS(&i85x_info),
1054 INTEL_I865G_IDS(&i865g_info),
1055 INTEL_I915G_IDS(&i915g_info),
1056 INTEL_I915GM_IDS(&i915gm_info),
1057 INTEL_I945G_IDS(&i945g_info),
1058 INTEL_I945GM_IDS(&i945gm_info),
1059 INTEL_I965G_IDS(&i965g_info),
1060 INTEL_G33_IDS(&g33_info),
1061 INTEL_I965GM_IDS(&i965gm_info),
1062 INTEL_GM45_IDS(&gm45_info),
1063 INTEL_G45_IDS(&g45_info),
1064 INTEL_PINEVIEW_G_IDS(&pnv_g_info),
1065 INTEL_PINEVIEW_M_IDS(&pnv_m_info),
1066 INTEL_IRONLAKE_D_IDS(&ilk_d_info),
1067 INTEL_IRONLAKE_M_IDS(&ilk_m_info),
1068 INTEL_SNB_D_GT1_IDS(&snb_d_gt1_info),
1069 INTEL_SNB_D_GT2_IDS(&snb_d_gt2_info),
1070 INTEL_SNB_M_GT1_IDS(&snb_m_gt1_info),
1071 INTEL_SNB_M_GT2_IDS(&snb_m_gt2_info),
1072 INTEL_IVB_Q_IDS(&ivb_q_info), /* must be first IVB */
1073 INTEL_IVB_M_GT1_IDS(&ivb_m_gt1_info),
1074 INTEL_IVB_M_GT2_IDS(&ivb_m_gt2_info),
1075 INTEL_IVB_D_GT1_IDS(&ivb_d_gt1_info),
1076 INTEL_IVB_D_GT2_IDS(&ivb_d_gt2_info),
1077 INTEL_HSW_GT1_IDS(&hsw_gt1_info),
1078 INTEL_HSW_GT2_IDS(&hsw_gt2_info),
1079 INTEL_HSW_GT3_IDS(&hsw_gt3_info),
1080 INTEL_VLV_IDS(&vlv_info),
1081 INTEL_BDW_GT1_IDS(&bdw_gt1_info),
1082 INTEL_BDW_GT2_IDS(&bdw_gt2_info),
1083 INTEL_BDW_GT3_IDS(&bdw_gt3_info),
1084 INTEL_BDW_RSVD_IDS(&bdw_rsvd_info),
1085 INTEL_CHV_IDS(&chv_info),
1086 INTEL_SKL_GT1_IDS(&skl_gt1_info),
1087 INTEL_SKL_GT2_IDS(&skl_gt2_info),
1088 INTEL_SKL_GT3_IDS(&skl_gt3_info),
1089 INTEL_SKL_GT4_IDS(&skl_gt4_info),
1090 INTEL_BXT_IDS(&bxt_info),
1091 INTEL_GLK_IDS(&glk_info),
1092 INTEL_KBL_GT1_IDS(&kbl_gt1_info),
1093 INTEL_KBL_GT2_IDS(&kbl_gt2_info),
1094 INTEL_KBL_GT3_IDS(&kbl_gt3_info),
1095 INTEL_KBL_GT4_IDS(&kbl_gt3_info),
1096 INTEL_AML_KBL_GT2_IDS(&kbl_gt2_info),
1097 INTEL_CFL_S_GT1_IDS(&cfl_gt1_info),
1098 INTEL_CFL_S_GT2_IDS(&cfl_gt2_info),
1099 INTEL_CFL_H_GT1_IDS(&cfl_gt1_info),
1100 INTEL_CFL_H_GT2_IDS(&cfl_gt2_info),
1101 INTEL_CFL_U_GT2_IDS(&cfl_gt2_info),
1102 INTEL_CFL_U_GT3_IDS(&cfl_gt3_info),
1103 INTEL_WHL_U_GT1_IDS(&cfl_gt1_info),
1104 INTEL_WHL_U_GT2_IDS(&cfl_gt2_info),
1105 INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info),
1106 INTEL_WHL_U_GT3_IDS(&cfl_gt3_info),
1107 INTEL_CML_GT1_IDS(&cml_gt1_info),
1108 INTEL_CML_GT2_IDS(&cml_gt2_info),
1109 INTEL_CML_U_GT1_IDS(&cml_gt1_info),
1110 INTEL_CML_U_GT2_IDS(&cml_gt2_info),
1111 INTEL_ICL_11_IDS(&icl_info),
1112 INTEL_EHL_IDS(&ehl_info),
1113 INTEL_JSL_IDS(&jsl_info),
1114 INTEL_TGL_12_IDS(&tgl_info),
1115 INTEL_RKL_IDS(&rkl_info),
1116 INTEL_ADLS_IDS(&adl_s_info),
1117 INTEL_ADLP_IDS(&adl_p_info),
1120 MODULE_DEVICE_TABLE(pci, pciidlist);
1122 static void i915_pci_remove(struct pci_dev *pdev)
1124 struct drm_i915_private *i915;
1126 i915 = pci_get_drvdata(pdev);
1127 if (!i915) /* driver load aborted, nothing to cleanup */
1130 i915_driver_remove(i915);
1131 pci_set_drvdata(pdev, NULL);
1134 /* is device_id present in comma separated list of ids */
1135 static bool force_probe(u16 device_id, const char *devices)
1140 if (!devices || !*devices)
1143 /* match everything */
1144 if (strcmp(devices, "*") == 0)
1147 s = kstrdup(devices, GFP_KERNEL);
1151 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) {
1154 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) {
1165 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1167 struct intel_device_info *intel_info =
1168 (struct intel_device_info *) ent->driver_data;
1171 if (intel_info->require_force_probe &&
1172 !force_probe(pdev->device, i915_modparams.force_probe)) {
1173 dev_info(&pdev->dev,
1174 "Your graphics device %04x is not properly supported by the driver in this\n"
1175 "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n"
1176 "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n"
1177 "or (recommended) check for kernel updates.\n",
1178 pdev->device, pdev->device, pdev->device);
1182 /* Only bind to function 0 of the device. Early generations
1183 * used function 1 as a placeholder for multi-head. This causes
1184 * us confusion instead, especially on the systems where both
1185 * functions have the same PCI-ID!
1187 if (PCI_FUNC(pdev->devfn))
1191 * apple-gmux is needed on dual GPU MacBook Pro
1192 * to probe the panel if we're the inactive GPU.
1194 if (vga_switcheroo_client_probe_defer(pdev))
1195 return -EPROBE_DEFER;
1197 err = i915_driver_probe(pdev, ent);
1201 if (i915_inject_probe_failure(pci_get_drvdata(pdev))) {
1202 i915_pci_remove(pdev);
1206 err = i915_live_selftests(pdev);
1208 i915_pci_remove(pdev);
1209 return err > 0 ? -ENOTTY : err;
1212 err = i915_perf_selftests(pdev);
1214 i915_pci_remove(pdev);
1215 return err > 0 ? -ENOTTY : err;
1221 static void i915_pci_shutdown(struct pci_dev *pdev)
1223 struct drm_i915_private *i915 = pci_get_drvdata(pdev);
1225 i915_driver_shutdown(i915);
1228 static struct pci_driver i915_pci_driver = {
1229 .name = DRIVER_NAME,
1230 .id_table = pciidlist,
1231 .probe = i915_pci_probe,
1232 .remove = i915_pci_remove,
1233 .shutdown = i915_pci_shutdown,
1234 .driver.pm = &i915_pm_ops,
1237 int i915_register_pci_driver(void)
1239 return pci_register_driver(&i915_pci_driver);
1242 void i915_unregister_pci_driver(void)
1244 pci_unregister_driver(&i915_pci_driver);