drivers/gpu/drm/i915/i915_pci.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <drm/drm_color_mgmt.h>
  26 #include <drm/drm_drv.h>
  27 #include <drm/i915_pciids.h>
  28
  29 #include "i915_driver.h"
  30 #include "i915_drv.h"
  31 #include "i915_pci.h"
  32 #include "i915_reg.h"
  33
  34 #define PLATFORM(x) .platform = (x)
  35 #define GEN(x) \
  36         .graphics.ver = (x), \
  37         .media.ver = (x), \
  38         .display.ver = (x)
  39
  40 #define I845_PIPE_OFFSETS \
  41         .pipe_offsets = { \
  42                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  43         }, \
  44         .trans_offsets = { \
  45                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  46         }
  47
  48 #define I9XX_PIPE_OFFSETS \
  49         .pipe_offsets = { \
  50                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  51                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  52         }, \
  53         .trans_offsets = { \
  54                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  55                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  56         }
  57
  58 #define IVB_PIPE_OFFSETS \
  59         .pipe_offsets = { \
  60                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  61                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  62                 [TRANSCODER_C] = PIPE_C_OFFSET, \
  63         }, \
  64         .trans_offsets = { \
  65                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  66                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  67                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
  68         }
  69
  70 #define HSW_PIPE_OFFSETS \
  71         .pipe_offsets = { \
  72                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  73                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  74                 [TRANSCODER_C] = PIPE_C_OFFSET, \
  75                 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
  76         }, \
  77         .trans_offsets = { \
  78                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  79                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  80                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
  81                 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
  82         }
  83
  84 #define CHV_PIPE_OFFSETS \
  85         .pipe_offsets = { \
  86                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  87                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  88                 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
  89         }, \
  90         .trans_offsets = { \
  91                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  92                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  93                 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
  94         }
  95
  96 #define I845_CURSOR_OFFSETS \
  97         .cursor_offsets = { \
  98                 [PIPE_A] = CURSOR_A_OFFSET, \
  99         }
 100
 101 #define I9XX_CURSOR_OFFSETS \
 102         .cursor_offsets = { \
 103                 [PIPE_A] = CURSOR_A_OFFSET, \
 104                 [PIPE_B] = CURSOR_B_OFFSET, \
 105         }
 106
 107 #define CHV_CURSOR_OFFSETS \
 108         .cursor_offsets = { \
 109                 [PIPE_A] = CURSOR_A_OFFSET, \
 110                 [PIPE_B] = CURSOR_B_OFFSET, \
 111                 [PIPE_C] = CHV_CURSOR_C_OFFSET, \
 112         }
 113
 114 #define IVB_CURSOR_OFFSETS \
 115         .cursor_offsets = { \
 116                 [PIPE_A] = CURSOR_A_OFFSET, \
 117                 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
 118                 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
 119         }
 120
 121 #define TGL_CURSOR_OFFSETS \
 122         .cursor_offsets = { \
 123                 [PIPE_A] = CURSOR_A_OFFSET, \
 124                 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
 125                 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
 126                 [PIPE_D] = TGL_CURSOR_D_OFFSET, \
 127         }
 128
 129 #define I9XX_COLORS \
 130         .color = { .gamma_lut_size = 256 }
 131 #define I965_COLORS \
 132         .color = { .gamma_lut_size = 129, \
 133                    .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
 134         }
 135 #define ILK_COLORS \
 136         .color = { .gamma_lut_size = 1024 }
 137 #define IVB_COLORS \
 138         .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
 139 #define CHV_COLORS \
 140         .color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \
 141                    .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
 142                    .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
 143         }
 144 #define GLK_COLORS \
 145         .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024, \
 146                    .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
 147                                         DRM_COLOR_LUT_EQUAL_CHANNELS, \
 148         }
 149 #define ICL_COLORS \
 150         .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145, \
 151                    .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
 152                                         DRM_COLOR_LUT_EQUAL_CHANNELS, \
 153                    .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
 154         }
 155
 156 /* Keep in gen based order, and chronological order within a gen */
 157
 158 #define GEN_DEFAULT_PAGE_SIZES \
 159         .page_sizes = I915_GTT_PAGE_SIZE_4K
 160
 161 #define GEN_DEFAULT_REGIONS \
 162         .memory_regions = REGION_SMEM | REGION_STOLEN_SMEM
 163
 164 #define I830_FEATURES \
 165         GEN(2), \
 166         .is_mobile = 1, \
 167         .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 168         .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 169         .display.has_overlay = 1, \
 170         .display.cursor_needs_physical = 1, \
 171         .display.overlay_needs_physical = 1, \
 172         .display.has_gmch = 1, \
 173         .gpu_reset_clobbers_display = true, \
 174         .has_3d_pipeline = 1, \
 175         .hws_needs_physical = 1, \
 176         .unfenced_needs_alignment = 1, \
 177         .platform_engine_mask = BIT(RCS0), \
 178         .has_snoop = true, \
 179         .has_coherent_ggtt = false, \
 180         .dma_mask_size = 32, \
 181         I9XX_PIPE_OFFSETS, \
 182         I9XX_CURSOR_OFFSETS, \
 183         I9XX_COLORS, \
 184         GEN_DEFAULT_PAGE_SIZES, \
 185         GEN_DEFAULT_REGIONS
 186
 187 #define I845_FEATURES \
 188         GEN(2), \
 189         .display.pipe_mask = BIT(PIPE_A), \
 190         .display.cpu_transcoder_mask = BIT(TRANSCODER_A), \
 191         .display.has_overlay = 1, \
 192         .display.overlay_needs_physical = 1, \
 193         .display.has_gmch = 1, \
 194         .has_3d_pipeline = 1, \
 195         .gpu_reset_clobbers_display = true, \
 196         .hws_needs_physical = 1, \
 197         .unfenced_needs_alignment = 1, \
 198         .platform_engine_mask = BIT(RCS0), \
 199         .has_snoop = true, \
 200         .has_coherent_ggtt = false, \
 201         .dma_mask_size = 32, \
 202         I845_PIPE_OFFSETS, \
 203         I845_CURSOR_OFFSETS, \
 204         I9XX_COLORS, \
 205         GEN_DEFAULT_PAGE_SIZES, \
 206         GEN_DEFAULT_REGIONS
 207
 208 static const struct intel_device_info i830_info = {
 209         I830_FEATURES,
 210         PLATFORM(INTEL_I830),
 211 };
 212
 213 static const struct intel_device_info i845g_info = {
 214         I845_FEATURES,
 215         PLATFORM(INTEL_I845G),
 216 };
 217
 218 static const struct intel_device_info i85x_info = {
 219         I830_FEATURES,
 220         PLATFORM(INTEL_I85X),
 221         .display.fbc_mask = BIT(INTEL_FBC_A),
 222 };
 223
 224 static const struct intel_device_info i865g_info = {
 225         I845_FEATURES,
 226         PLATFORM(INTEL_I865G),
 227         .display.fbc_mask = BIT(INTEL_FBC_A),
 228 };
 229
 230 #define GEN3_FEATURES \
 231         GEN(3), \
 232         .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 233         .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 234         .display.has_gmch = 1, \
 235         .gpu_reset_clobbers_display = true, \
 236         .platform_engine_mask = BIT(RCS0), \
 237         .has_3d_pipeline = 1, \
 238         .has_snoop = true, \
 239         .has_coherent_ggtt = true, \
 240         .dma_mask_size = 32, \
 241         I9XX_PIPE_OFFSETS, \
 242         I9XX_CURSOR_OFFSETS, \
 243         I9XX_COLORS, \
 244         GEN_DEFAULT_PAGE_SIZES, \
 245         GEN_DEFAULT_REGIONS
 246
 247 static const struct intel_device_info i915g_info = {
 248         GEN3_FEATURES,
 249         PLATFORM(INTEL_I915G),
 250         .has_coherent_ggtt = false,
 251         .display.cursor_needs_physical = 1,
 252         .display.has_overlay = 1,
 253         .display.overlay_needs_physical = 1,
 254         .hws_needs_physical = 1,
 255         .unfenced_needs_alignment = 1,
 256 };
 257
 258 static const struct intel_device_info i915gm_info = {
 259         GEN3_FEATURES,
 260         PLATFORM(INTEL_I915GM),
 261         .is_mobile = 1,
 262         .display.cursor_needs_physical = 1,
 263         .display.has_overlay = 1,
 264         .display.overlay_needs_physical = 1,
 265         .display.supports_tv = 1,
 266         .display.fbc_mask = BIT(INTEL_FBC_A),
 267         .hws_needs_physical = 1,
 268         .unfenced_needs_alignment = 1,
 269 };
 270
 271 static const struct intel_device_info i945g_info = {
 272         GEN3_FEATURES,
 273         PLATFORM(INTEL_I945G),
 274         .display.has_hotplug = 1,
 275         .display.cursor_needs_physical = 1,
 276         .display.has_overlay = 1,
 277         .display.overlay_needs_physical = 1,
 278         .hws_needs_physical = 1,
 279         .unfenced_needs_alignment = 1,
 280 };
 281
 282 static const struct intel_device_info i945gm_info = {
 283         GEN3_FEATURES,
 284         PLATFORM(INTEL_I945GM),
 285         .is_mobile = 1,
 286         .display.has_hotplug = 1,
 287         .display.cursor_needs_physical = 1,
 288         .display.has_overlay = 1,
 289         .display.overlay_needs_physical = 1,
 290         .display.supports_tv = 1,
 291         .display.fbc_mask = BIT(INTEL_FBC_A),
 292         .hws_needs_physical = 1,
 293         .unfenced_needs_alignment = 1,
 294 };
 295
 296 static const struct intel_device_info g33_info = {
 297         GEN3_FEATURES,
 298         PLATFORM(INTEL_G33),
 299         .display.has_hotplug = 1,
 300         .display.has_overlay = 1,
 301         .dma_mask_size = 36,
 302 };
 303
 304 static const struct intel_device_info pnv_g_info = {
 305         GEN3_FEATURES,
 306         PLATFORM(INTEL_PINEVIEW),
 307         .display.has_hotplug = 1,
 308         .display.has_overlay = 1,
 309         .dma_mask_size = 36,
 310 };
 311
 312 static const struct intel_device_info pnv_m_info = {
 313         GEN3_FEATURES,
 314         PLATFORM(INTEL_PINEVIEW),
 315         .is_mobile = 1,
 316         .display.has_hotplug = 1,
 317         .display.has_overlay = 1,
 318         .dma_mask_size = 36,
 319 };
 320
 321 #define GEN4_FEATURES \
 322         GEN(4), \
 323         .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 324         .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 325         .display.has_hotplug = 1, \
 326         .display.has_gmch = 1, \
 327         .gpu_reset_clobbers_display = true, \
 328         .platform_engine_mask = BIT(RCS0), \
 329         .has_3d_pipeline = 1, \
 330         .has_snoop = true, \
 331         .has_coherent_ggtt = true, \
 332         .dma_mask_size = 36, \
 333         I9XX_PIPE_OFFSETS, \
 334         I9XX_CURSOR_OFFSETS, \
 335         I965_COLORS, \
 336         GEN_DEFAULT_PAGE_SIZES, \
 337         GEN_DEFAULT_REGIONS
 338
 339 static const struct intel_device_info i965g_info = {
 340         GEN4_FEATURES,
 341         PLATFORM(INTEL_I965G),
 342         .display.has_overlay = 1,
 343         .hws_needs_physical = 1,
 344         .has_snoop = false,
 345 };
 346
 347 static const struct intel_device_info i965gm_info = {
 348         GEN4_FEATURES,
 349         PLATFORM(INTEL_I965GM),
 350         .is_mobile = 1,
 351         .display.fbc_mask = BIT(INTEL_FBC_A),
 352         .display.has_overlay = 1,
 353         .display.supports_tv = 1,
 354         .hws_needs_physical = 1,
 355         .has_snoop = false,
 356 };
 357
 358 static const struct intel_device_info g45_info = {
 359         GEN4_FEATURES,
 360         PLATFORM(INTEL_G45),
 361         .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
 362         .gpu_reset_clobbers_display = false,
 363 };
 364
 365 static const struct intel_device_info gm45_info = {
 366         GEN4_FEATURES,
 367         PLATFORM(INTEL_GM45),
 368         .is_mobile = 1,
 369         .display.fbc_mask = BIT(INTEL_FBC_A),
 370         .display.supports_tv = 1,
 371         .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
 372         .gpu_reset_clobbers_display = false,
 373 };
 374
 375 #define GEN5_FEATURES \
 376         GEN(5), \
 377         .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 378         .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 379         .display.has_hotplug = 1, \
 380         .platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
 381         .has_3d_pipeline = 1, \
 382         .has_snoop = true, \
 383         .has_coherent_ggtt = true, \
 384         /* ilk does support rc6, but we do not implement [power] contexts */ \
 385         .has_rc6 = 0, \
 386         .dma_mask_size = 36, \
 387         I9XX_PIPE_OFFSETS, \
 388         I9XX_CURSOR_OFFSETS, \
 389         ILK_COLORS, \
 390         GEN_DEFAULT_PAGE_SIZES, \
 391         GEN_DEFAULT_REGIONS
 392
 393 static const struct intel_device_info ilk_d_info = {
 394         GEN5_FEATURES,
 395         PLATFORM(INTEL_IRONLAKE),
 396 };
 397
 398 static const struct intel_device_info ilk_m_info = {
 399         GEN5_FEATURES,
 400         PLATFORM(INTEL_IRONLAKE),
 401         .is_mobile = 1,
 402         .has_rps = true,
 403         .display.fbc_mask = BIT(INTEL_FBC_A),
 404 };
 405
 406 #define GEN6_FEATURES \
 407         GEN(6), \
 408         .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 409         .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 410         .display.has_hotplug = 1, \
 411         .display.fbc_mask = BIT(INTEL_FBC_A), \
 412         .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
 413         .has_3d_pipeline = 1, \
 414         .has_coherent_ggtt = true, \
 415         .has_llc = 1, \
 416         .has_rc6 = 1, \
 417         .has_rc6p = 1, \
 418         .has_rps = true, \
 419         .dma_mask_size = 40, \
 420         .ppgtt_type = INTEL_PPGTT_ALIASING, \
 421         .ppgtt_size = 31, \
 422         I9XX_PIPE_OFFSETS, \
 423         I9XX_CURSOR_OFFSETS, \
 424         ILK_COLORS, \
 425         GEN_DEFAULT_PAGE_SIZES, \
 426         GEN_DEFAULT_REGIONS
 427
 428 #define SNB_D_PLATFORM \
 429         GEN6_FEATURES, \
 430         PLATFORM(INTEL_SANDYBRIDGE)
 431
 432 static const struct intel_device_info snb_d_gt1_info = {
 433         SNB_D_PLATFORM,
 434         .gt = 1,
 435 };
 436
 437 static const struct intel_device_info snb_d_gt2_info = {
 438         SNB_D_PLATFORM,
 439         .gt = 2,
 440 };
 441
 442 #define SNB_M_PLATFORM \
 443         GEN6_FEATURES, \
 444         PLATFORM(INTEL_SANDYBRIDGE), \
 445         .is_mobile = 1
 446
 447
 448 static const struct intel_device_info snb_m_gt1_info = {
 449         SNB_M_PLATFORM,
 450         .gt = 1,
 451 };
 452
 453 static const struct intel_device_info snb_m_gt2_info = {
 454         SNB_M_PLATFORM,
 455         .gt = 2,
 456 };
 457
 458 #define GEN7_FEATURES  \
 459         GEN(7), \
 460         .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
 461         .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
 462         .display.has_hotplug = 1, \
 463         .display.fbc_mask = BIT(INTEL_FBC_A), \
 464         .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
 465         .has_3d_pipeline = 1, \
 466         .has_coherent_ggtt = true, \
 467         .has_llc = 1, \
 468         .has_rc6 = 1, \
 469         .has_rc6p = 1, \
 470         .has_reset_engine = true, \
 471         .has_rps = true, \
 472         .dma_mask_size = 40, \
 473         .ppgtt_type = INTEL_PPGTT_ALIASING, \
 474         .ppgtt_size = 31, \
 475         IVB_PIPE_OFFSETS, \
 476         IVB_CURSOR_OFFSETS, \
 477         IVB_COLORS, \
 478         GEN_DEFAULT_PAGE_SIZES, \
 479         GEN_DEFAULT_REGIONS
 480
 481 #define IVB_D_PLATFORM \
 482         GEN7_FEATURES, \
 483         PLATFORM(INTEL_IVYBRIDGE), \
 484         .has_l3_dpf = 1
 485
 486 static const struct intel_device_info ivb_d_gt1_info = {
 487         IVB_D_PLATFORM,
 488         .gt = 1,
 489 };
 490
 491 static const struct intel_device_info ivb_d_gt2_info = {
 492         IVB_D_PLATFORM,
 493         .gt = 2,
 494 };
 495
 496 #define IVB_M_PLATFORM \
 497         GEN7_FEATURES, \
 498         PLATFORM(INTEL_IVYBRIDGE), \
 499         .is_mobile = 1, \
 500         .has_l3_dpf = 1
 501
 502 static const struct intel_device_info ivb_m_gt1_info = {
 503         IVB_M_PLATFORM,
 504         .gt = 1,
 505 };
 506
 507 static const struct intel_device_info ivb_m_gt2_info = {
 508         IVB_M_PLATFORM,
 509         .gt = 2,
 510 };
 511
 512 static const struct intel_device_info ivb_q_info = {
 513         GEN7_FEATURES,
 514         PLATFORM(INTEL_IVYBRIDGE),
 515         .gt = 2,
 516         .display.pipe_mask = 0, /* legal, last one wins */
 517         .display.cpu_transcoder_mask = 0,
 518         .has_l3_dpf = 1,
 519 };
 520
 521 static const struct intel_device_info vlv_info = {
 522         PLATFORM(INTEL_VALLEYVIEW),
 523         GEN(7),
 524         .is_lp = 1,
 525         .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
 526         .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
 527         .has_runtime_pm = 1,
 528         .has_rc6 = 1,
 529         .has_reset_engine = true,
 530         .has_rps = true,
 531         .display.has_gmch = 1,
 532         .display.has_hotplug = 1,
 533         .dma_mask_size = 40,
 534         .ppgtt_type = INTEL_PPGTT_ALIASING,
 535         .ppgtt_size = 31,
 536         .has_snoop = true,
 537         .has_coherent_ggtt = false,
 538         .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
 539         .display_mmio_offset = VLV_DISPLAY_BASE,
 540         I9XX_PIPE_OFFSETS,
 541         I9XX_CURSOR_OFFSETS,
 542         I965_COLORS,
 543         GEN_DEFAULT_PAGE_SIZES,
 544         GEN_DEFAULT_REGIONS,
 545 };
 546
 547 #define G75_FEATURES  \
 548         GEN7_FEATURES, \
 549         .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
 550         .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 551                 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
 552         .display.has_ddi = 1, \
 553         .display.has_fpga_dbg = 1, \
 554         .display.has_dp_mst = 1, \
 555         .has_rc6p = 0 /* RC6p removed-by HSW */, \
 556         HSW_PIPE_OFFSETS, \
 557         .has_runtime_pm = 1
 558
 559 #define HSW_PLATFORM \
 560         G75_FEATURES, \
 561         PLATFORM(INTEL_HASWELL), \
 562         .has_l3_dpf = 1
 563
 564 static const struct intel_device_info hsw_gt1_info = {
 565         HSW_PLATFORM,
 566         .gt = 1,
 567 };
 568
 569 static const struct intel_device_info hsw_gt2_info = {
 570         HSW_PLATFORM,
 571         .gt = 2,
 572 };
 573
 574 static const struct intel_device_info hsw_gt3_info = {
 575         HSW_PLATFORM,
 576         .gt = 3,
 577 };
 578
 579 #define GEN8_FEATURES \
 580         G75_FEATURES, \
 581         GEN(8), \
 582         .has_logical_ring_contexts = 1, \
 583         .dma_mask_size = 39, \
 584         .ppgtt_type = INTEL_PPGTT_FULL, \
 585         .ppgtt_size = 48, \
 586         .has_64bit_reloc = 1
 587
 588 #define BDW_PLATFORM \
 589         GEN8_FEATURES, \
 590         PLATFORM(INTEL_BROADWELL)
 591
 592 static const struct intel_device_info bdw_gt1_info = {
 593         BDW_PLATFORM,
 594         .gt = 1,
 595 };
 596
 597 static const struct intel_device_info bdw_gt2_info = {
 598         BDW_PLATFORM,
 599         .gt = 2,
 600 };
 601
 602 static const struct intel_device_info bdw_rsvd_info = {
 603         BDW_PLATFORM,
 604         .gt = 3,
 605         /* According to the device ID those devices are GT3, they were
 606          * previously treated as not GT3, keep it like that.
 607          */
 608 };
 609
 610 static const struct intel_device_info bdw_gt3_info = {
 611         BDW_PLATFORM,
 612         .gt = 3,
 613         .platform_engine_mask =
 614                 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
 615 };
 616
 617 static const struct intel_device_info chv_info = {
 618         PLATFORM(INTEL_CHERRYVIEW),
 619         GEN(8),
 620         .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
 621         .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
 622         .display.has_hotplug = 1,
 623         .is_lp = 1,
 624         .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
 625         .has_64bit_reloc = 1,
 626         .has_runtime_pm = 1,
 627         .has_rc6 = 1,
 628         .has_rps = true,
 629         .has_logical_ring_contexts = 1,
 630         .display.has_gmch = 1,
 631         .dma_mask_size = 39,
 632         .ppgtt_type = INTEL_PPGTT_FULL,
 633         .ppgtt_size = 32,
 634         .has_reset_engine = 1,
 635         .has_snoop = true,
 636         .has_coherent_ggtt = false,
 637         .display_mmio_offset = VLV_DISPLAY_BASE,
 638         CHV_PIPE_OFFSETS,
 639         CHV_CURSOR_OFFSETS,
 640         CHV_COLORS,
 641         GEN_DEFAULT_PAGE_SIZES,
 642         GEN_DEFAULT_REGIONS,
 643 };
 644
 645 #define GEN9_DEFAULT_PAGE_SIZES \
 646         .page_sizes = I915_GTT_PAGE_SIZE_4K | \
 647                       I915_GTT_PAGE_SIZE_64K
 648
 649 #define GEN9_FEATURES \
 650         GEN8_FEATURES, \
 651         GEN(9), \
 652         GEN9_DEFAULT_PAGE_SIZES, \
 653         .display.has_dmc = 1, \
 654         .has_gt_uc = 1, \
 655         .display.has_hdcp = 1, \
 656         .display.has_ipc = 1, \
 657         .display.has_psr = 1, \
 658         .display.has_psr_hw_tracking = 1, \
 659         .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
 660         .dbuf.slice_mask = BIT(DBUF_S1)
 661
 662 #define SKL_PLATFORM \
 663         GEN9_FEATURES, \
 664         PLATFORM(INTEL_SKYLAKE)
 665
 666 static const struct intel_device_info skl_gt1_info = {
 667         SKL_PLATFORM,
 668         .gt = 1,
 669 };
 670
 671 static const struct intel_device_info skl_gt2_info = {
 672         SKL_PLATFORM,
 673         .gt = 2,
 674 };
 675
 676 #define SKL_GT3_PLUS_PLATFORM \
 677         SKL_PLATFORM, \
 678         .platform_engine_mask = \
 679                 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
 680
 681
 682 static const struct intel_device_info skl_gt3_info = {
 683         SKL_GT3_PLUS_PLATFORM,
 684         .gt = 3,
 685 };
 686
 687 static const struct intel_device_info skl_gt4_info = {
 688         SKL_GT3_PLUS_PLATFORM,
 689         .gt = 4,
 690 };
 691
 692 #define GEN9_LP_FEATURES \
 693         GEN(9), \
 694         .is_lp = 1, \
 695         .dbuf.slice_mask = BIT(DBUF_S1), \
 696         .display.has_hotplug = 1, \
 697         .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
 698         .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
 699         .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 700                 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
 701                 BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
 702         .has_3d_pipeline = 1, \
 703         .has_64bit_reloc = 1, \
 704         .display.has_ddi = 1, \
 705         .display.has_fpga_dbg = 1, \
 706         .display.fbc_mask = BIT(INTEL_FBC_A), \
 707         .display.has_hdcp = 1, \
 708         .display.has_psr = 1, \
 709         .display.has_psr_hw_tracking = 1, \
 710         .has_runtime_pm = 1, \
 711         .display.has_dmc = 1, \
 712         .has_rc6 = 1, \
 713         .has_rps = true, \
 714         .display.has_dp_mst = 1, \
 715         .has_logical_ring_contexts = 1, \
 716         .has_gt_uc = 1, \
 717         .dma_mask_size = 39, \
 718         .ppgtt_type = INTEL_PPGTT_FULL, \
 719         .ppgtt_size = 48, \
 720         .has_reset_engine = 1, \
 721         .has_snoop = true, \
 722         .has_coherent_ggtt = false, \
 723         .display.has_ipc = 1, \
 724         HSW_PIPE_OFFSETS, \
 725         IVB_CURSOR_OFFSETS, \
 726         IVB_COLORS, \
 727         GEN9_DEFAULT_PAGE_SIZES, \
 728         GEN_DEFAULT_REGIONS
 729
 730 static const struct intel_device_info bxt_info = {
 731         GEN9_LP_FEATURES,
 732         PLATFORM(INTEL_BROXTON),
 733         .dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
 734 };
 735
 736 static const struct intel_device_info glk_info = {
 737         GEN9_LP_FEATURES,
 738         PLATFORM(INTEL_GEMINILAKE),
 739         .display.ver = 10,
 740         .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
 741         GLK_COLORS,
 742 };
 743
 744 #define KBL_PLATFORM \
 745         GEN9_FEATURES, \
 746         PLATFORM(INTEL_KABYLAKE)
 747
 748 static const struct intel_device_info kbl_gt1_info = {
 749         KBL_PLATFORM,
 750         .gt = 1,
 751 };
 752
 753 static const struct intel_device_info kbl_gt2_info = {
 754         KBL_PLATFORM,
 755         .gt = 2,
 756 };
 757
 758 static const struct intel_device_info kbl_gt3_info = {
 759         KBL_PLATFORM,
 760         .gt = 3,
 761         .platform_engine_mask =
 762                 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
 763 };
 764
 765 #define CFL_PLATFORM \
 766         GEN9_FEATURES, \
 767         PLATFORM(INTEL_COFFEELAKE)
 768
 769 static const struct intel_device_info cfl_gt1_info = {
 770         CFL_PLATFORM,
 771         .gt = 1,
 772 };
 773
 774 static const struct intel_device_info cfl_gt2_info = {
 775         CFL_PLATFORM,
 776         .gt = 2,
 777 };
 778
 779 static const struct intel_device_info cfl_gt3_info = {
 780         CFL_PLATFORM,
 781         .gt = 3,
 782         .platform_engine_mask =
 783                 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
 784 };
 785
 786 #define CML_PLATFORM \
 787         GEN9_FEATURES, \
 788         PLATFORM(INTEL_COMETLAKE)
 789
 790 static const struct intel_device_info cml_gt1_info = {
 791         CML_PLATFORM,
 792         .gt = 1,
 793 };
 794
 795 static const struct intel_device_info cml_gt2_info = {
 796         CML_PLATFORM,
 797         .gt = 2,
 798 };
 799
 800 #define GEN11_DEFAULT_PAGE_SIZES \
 801         .page_sizes = I915_GTT_PAGE_SIZE_4K | \
 802                       I915_GTT_PAGE_SIZE_64K | \
 803                       I915_GTT_PAGE_SIZE_2M
 804
 805 #define GEN11_FEATURES \
 806         GEN9_FEATURES, \
 807         GEN11_DEFAULT_PAGE_SIZES, \
 808         .display.abox_mask = BIT(0), \
 809         .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 810                 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
 811                 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
 812         .pipe_offsets = { \
 813                 [TRANSCODER_A] = PIPE_A_OFFSET, \
 814                 [TRANSCODER_B] = PIPE_B_OFFSET, \
 815                 [TRANSCODER_C] = PIPE_C_OFFSET, \
 816                 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
 817                 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
 818                 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
 819         }, \
 820         .trans_offsets = { \
 821                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
 822                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
 823                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
 824                 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
 825                 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
 826                 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
 827         }, \
 828         GEN(11), \
 829         ICL_COLORS, \
 830         .dbuf.size = 2048, \
 831         .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
 832         .display.has_dsc = 1, \
 833         .has_coherent_ggtt = false, \
 834         .has_logical_ring_elsq = 1
 835
 836 static const struct intel_device_info icl_info = {
 837         GEN11_FEATURES,
 838         PLATFORM(INTEL_ICELAKE),
 839         .platform_engine_mask =
 840                 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
 841 };
 842
 843 static const struct intel_device_info ehl_info = {
 844         GEN11_FEATURES,
 845         PLATFORM(INTEL_ELKHARTLAKE),
 846         .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
 847         .ppgtt_size = 36,
 848 };
 849
 850 static const struct intel_device_info jsl_info = {
 851         GEN11_FEATURES,
 852         PLATFORM(INTEL_JASPERLAKE),
 853         .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
 854         .ppgtt_size = 36,
 855 };
 856
 857 #define GEN12_FEATURES \
 858         GEN11_FEATURES, \
 859         GEN(12), \
 860         .display.abox_mask = GENMASK(2, 1), \
 861         .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
 862         .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 863                 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
 864                 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
 865         .pipe_offsets = { \
 866                 [TRANSCODER_A] = PIPE_A_OFFSET, \
 867                 [TRANSCODER_B] = PIPE_B_OFFSET, \
 868                 [TRANSCODER_C] = PIPE_C_OFFSET, \
 869                 [TRANSCODER_D] = PIPE_D_OFFSET, \
 870                 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
 871                 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
 872         }, \
 873         .trans_offsets = { \
 874                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
 875                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
 876                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
 877                 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
 878                 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
 879                 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
 880         }, \
 881         TGL_CURSOR_OFFSETS, \
 882         .has_global_mocs = 1, \
 883         .has_pxp = 1, \
 884         .display.has_dsb = 0 /* FIXME: LUT load is broken with DSB */
 885
 886 static const struct intel_device_info tgl_info = {
 887         GEN12_FEATURES,
 888         PLATFORM(INTEL_TIGERLAKE),
 889         .display.has_modular_fia = 1,
 890         .platform_engine_mask =
 891                 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
 892 };
 893
 894 static const struct intel_device_info rkl_info = {
 895         GEN12_FEATURES,
 896         PLATFORM(INTEL_ROCKETLAKE),
 897         .display.abox_mask = BIT(0),
 898         .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
 899         .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
 900                 BIT(TRANSCODER_C),
 901         .display.has_hti = 1,
 902         .display.has_psr_hw_tracking = 0,
 903         .platform_engine_mask =
 904                 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
 905 };
 906
 907 #define DGFX_FEATURES \
 908         .memory_regions = REGION_SMEM | REGION_LMEM | REGION_STOLEN_LMEM, \
 909         .has_llc = 0, \
 910         .has_pxp = 0, \
 911         .has_snoop = 1, \
 912         .is_dgfx = 1, \
 913         .has_heci_gscfi = 1
 914
 915 static const struct intel_device_info dg1_info = {
 916         GEN12_FEATURES,
 917         DGFX_FEATURES,
 918         .graphics.rel = 10,
 919         PLATFORM(INTEL_DG1),
 920         .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
 921         .require_force_probe = 1,
 922         .platform_engine_mask =
 923                 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
 924                 BIT(VCS0) | BIT(VCS2),
 925         /* Wa_16011227922 */
 926         .ppgtt_size = 47,
 927 };
 928
 929 static const struct intel_device_info adl_s_info = {
 930         GEN12_FEATURES,
 931         PLATFORM(INTEL_ALDERLAKE_S),
 932         .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
 933         .display.has_hti = 1,
 934         .display.has_psr_hw_tracking = 0,
 935         .platform_engine_mask =
 936                 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
 937         .dma_mask_size = 39,
 938 };
 939
 940 #define XE_LPD_CURSOR_OFFSETS \
 941         .cursor_offsets = { \
 942                 [PIPE_A] = CURSOR_A_OFFSET, \
 943                 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
 944                 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
 945                 [PIPE_D] = TGL_CURSOR_D_OFFSET, \
 946         }
 947
 948 #define XE_LPD_FEATURES \
 949         .display.abox_mask = GENMASK(1, 0),                                     \
 950         .color = { .degamma_lut_size = 128, .gamma_lut_size = 1024,             \
 951                    .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING |          \
 952                                         DRM_COLOR_LUT_EQUAL_CHANNELS,           \
 953         },                                                                      \
 954         .dbuf.size = 4096,                                                      \
 955         .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |         \
 956                 BIT(DBUF_S4),                                                   \
 957         .display.has_ddi = 1,                                                   \
 958         .display.has_dmc = 1,                                                   \
 959         .display.has_dp_mst = 1,                                                \
 960         .display.has_dsb = 1,                                                   \
 961         .display.has_dsc = 1,                                                   \
 962         .display.fbc_mask = BIT(INTEL_FBC_A),                                   \
 963         .display.has_fpga_dbg = 1,                                              \
 964         .display.has_hdcp = 1,                                                  \
 965         .display.has_hotplug = 1,                                               \
 966         .display.has_ipc = 1,                                                   \
 967         .display.has_psr = 1,                                                   \
 968         .display.ver = 13,                                                      \
 969         .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),     \
 970         .pipe_offsets = {                                                       \
 971                 [TRANSCODER_A] = PIPE_A_OFFSET,                                 \
 972                 [TRANSCODER_B] = PIPE_B_OFFSET,                                 \
 973                 [TRANSCODER_C] = PIPE_C_OFFSET,                                 \
 974                 [TRANSCODER_D] = PIPE_D_OFFSET,                                 \
 975                 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET,                          \
 976                 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET,                          \
 977         },                                                                      \
 978         .trans_offsets = {                                                      \
 979                 [TRANSCODER_A] = TRANSCODER_A_OFFSET,                           \
 980                 [TRANSCODER_B] = TRANSCODER_B_OFFSET,                           \
 981                 [TRANSCODER_C] = TRANSCODER_C_OFFSET,                           \
 982                 [TRANSCODER_D] = TRANSCODER_D_OFFSET,                           \
 983                 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET,                    \
 984                 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET,                    \
 985         },                                                                      \
 986         XE_LPD_CURSOR_OFFSETS
 987
 988 static const struct intel_device_info adl_p_info = {
 989         GEN12_FEATURES,
 990         XE_LPD_FEATURES,
 991         PLATFORM(INTEL_ALDERLAKE_P),
 992         .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
 993                                BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
 994                                BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
 995         .display.has_cdclk_crawl = 1,
 996         .display.has_modular_fia = 1,
 997         .display.has_psr_hw_tracking = 0,
 998         .platform_engine_mask =
 999                 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
1000         .ppgtt_size = 48,
1001         .dma_mask_size = 39,
1002 };
1003
1004 #undef GEN
1005
1006 #define XE_HP_PAGE_SIZES \
1007         .page_sizes = I915_GTT_PAGE_SIZE_4K | \
1008                       I915_GTT_PAGE_SIZE_64K | \
1009                       I915_GTT_PAGE_SIZE_2M
1010
1011 #define XE_HP_FEATURES \
1012         .graphics.ver = 12, \
1013         .graphics.rel = 50, \
1014         XE_HP_PAGE_SIZES, \
1015         .dma_mask_size = 46, \
1016         .has_3d_pipeline = 1, \
1017         .has_64bit_reloc = 1, \
1018         .has_flat_ccs = 1, \
1019         .has_global_mocs = 1, \
1020         .has_gt_uc = 1, \
1021         .has_llc = 1, \
1022         .has_logical_ring_contexts = 1, \
1023         .has_logical_ring_elsq = 1, \
1024         .has_mslices = 1, \
1025         .has_rc6 = 1, \
1026         .has_reset_engine = 1, \
1027         .has_rps = 1, \
1028         .has_runtime_pm = 1, \
1029         .ppgtt_size = 48, \
1030         .ppgtt_type = INTEL_PPGTT_FULL
1031
1032 #define XE_HPM_FEATURES \
1033         .media.ver = 12, \
1034         .media.rel = 50
1035
1036 __maybe_unused
1037 static const struct intel_device_info xehpsdv_info = {
1038         XE_HP_FEATURES,
1039         XE_HPM_FEATURES,
1040         DGFX_FEATURES,
1041         PLATFORM(INTEL_XEHPSDV),
1042         .display = { },
1043         .has_64k_pages = 1,
1044         .needs_compact_pt = 1,
1045         .has_media_ratio_mode = 1,
1046         .platform_engine_mask =
1047                 BIT(RCS0) | BIT(BCS0) |
1048                 BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) |
1049                 BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) |
1050                 BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7) |
1051                 BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
1052         .require_force_probe = 1,
1053 };
1054
1055 #define DG2_FEATURES \
1056         XE_HP_FEATURES, \
1057         XE_HPM_FEATURES, \
1058         DGFX_FEATURES, \
1059         .graphics.rel = 55, \
1060         .media.rel = 55, \
1061         PLATFORM(INTEL_DG2), \
1062         .has_4tile = 1, \
1063         .has_64k_pages = 1, \
1064         .has_guc_deprivilege = 1, \
1065         .has_heci_pxp = 1, \
1066         .needs_compact_pt = 1, \
1067         .has_media_ratio_mode = 1, \
1068         .platform_engine_mask = \
1069                 BIT(RCS0) | BIT(BCS0) | \
1070                 BIT(VECS0) | BIT(VECS1) | \
1071                 BIT(VCS0) | BIT(VCS2) | \
1072                 BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3)
1073
1074 static const struct intel_device_info dg2_info = {
1075         DG2_FEATURES,
1076         XE_LPD_FEATURES,
1077         .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
1078                                BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
1079         .require_force_probe = 1,
1080 };
1081
1082 __maybe_unused
1083 static const struct intel_device_info ats_m_info = {
1084         DG2_FEATURES,
1085         .display = { 0 },
1086         .require_force_probe = 1,
1087 };
1088
1089 #define XE_HPC_FEATURES \
1090         XE_HP_FEATURES, \
1091         .dma_mask_size = 52, \
1092         .has_3d_pipeline = 0, \
1093         .has_l3_ccs_read = 1, \
1094         .has_one_eu_per_fuse_bit = 1
1095
1096 __maybe_unused
1097 static const struct intel_device_info pvc_info = {
1098         XE_HPC_FEATURES,
1099         XE_HPM_FEATURES,
1100         DGFX_FEATURES,
1101         .graphics.rel = 60,
1102         .media.rel = 60,
1103         PLATFORM(INTEL_PONTEVECCHIO),
1104         .display = { 0 },
1105         .has_flat_ccs = 0,
1106         .platform_engine_mask =
1107                 BIT(BCS0) |
1108                 BIT(VCS0) |
1109                 BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
1110         .require_force_probe = 1,
1111 };
1112
1113 #undef PLATFORM
1114
1115 /*
1116  * Make sure any device matches here are from most specific to most
1117  * general.  For example, since the Quanta match is based on the subsystem
1118  * and subvendor IDs, we need it to come before the more general IVB
1119  * PCI ID matches, otherwise we'll use the wrong info struct above.
1120  */
1121 static const struct pci_device_id pciidlist[] = {
1122         INTEL_I830_IDS(&i830_info),
1123         INTEL_I845G_IDS(&i845g_info),
1124         INTEL_I85X_IDS(&i85x_info),
1125         INTEL_I865G_IDS(&i865g_info),
1126         INTEL_I915G_IDS(&i915g_info),
1127         INTEL_I915GM_IDS(&i915gm_info),
1128         INTEL_I945G_IDS(&i945g_info),
1129         INTEL_I945GM_IDS(&i945gm_info),
1130         INTEL_I965G_IDS(&i965g_info),
1131         INTEL_G33_IDS(&g33_info),
1132         INTEL_I965GM_IDS(&i965gm_info),
1133         INTEL_GM45_IDS(&gm45_info),
1134         INTEL_G45_IDS(&g45_info),
1135         INTEL_PINEVIEW_G_IDS(&pnv_g_info),
1136         INTEL_PINEVIEW_M_IDS(&pnv_m_info),
1137         INTEL_IRONLAKE_D_IDS(&ilk_d_info),
1138         INTEL_IRONLAKE_M_IDS(&ilk_m_info),
1139         INTEL_SNB_D_GT1_IDS(&snb_d_gt1_info),
1140         INTEL_SNB_D_GT2_IDS(&snb_d_gt2_info),
1141         INTEL_SNB_M_GT1_IDS(&snb_m_gt1_info),
1142         INTEL_SNB_M_GT2_IDS(&snb_m_gt2_info),
1143         INTEL_IVB_Q_IDS(&ivb_q_info), /* must be first IVB */
1144         INTEL_IVB_M_GT1_IDS(&ivb_m_gt1_info),
1145         INTEL_IVB_M_GT2_IDS(&ivb_m_gt2_info),
1146         INTEL_IVB_D_GT1_IDS(&ivb_d_gt1_info),
1147         INTEL_IVB_D_GT2_IDS(&ivb_d_gt2_info),
1148         INTEL_HSW_GT1_IDS(&hsw_gt1_info),
1149         INTEL_HSW_GT2_IDS(&hsw_gt2_info),
1150         INTEL_HSW_GT3_IDS(&hsw_gt3_info),
1151         INTEL_VLV_IDS(&vlv_info),
1152         INTEL_BDW_GT1_IDS(&bdw_gt1_info),
1153         INTEL_BDW_GT2_IDS(&bdw_gt2_info),
1154         INTEL_BDW_GT3_IDS(&bdw_gt3_info),
1155         INTEL_BDW_RSVD_IDS(&bdw_rsvd_info),
1156         INTEL_CHV_IDS(&chv_info),
1157         INTEL_SKL_GT1_IDS(&skl_gt1_info),
1158         INTEL_SKL_GT2_IDS(&skl_gt2_info),
1159         INTEL_SKL_GT3_IDS(&skl_gt3_info),
1160         INTEL_SKL_GT4_IDS(&skl_gt4_info),
1161         INTEL_BXT_IDS(&bxt_info),
1162         INTEL_GLK_IDS(&glk_info),
1163         INTEL_KBL_GT1_IDS(&kbl_gt1_info),
1164         INTEL_KBL_GT2_IDS(&kbl_gt2_info),
1165         INTEL_KBL_GT3_IDS(&kbl_gt3_info),
1166         INTEL_KBL_GT4_IDS(&kbl_gt3_info),
1167         INTEL_AML_KBL_GT2_IDS(&kbl_gt2_info),
1168         INTEL_CFL_S_GT1_IDS(&cfl_gt1_info),
1169         INTEL_CFL_S_GT2_IDS(&cfl_gt2_info),
1170         INTEL_CFL_H_GT1_IDS(&cfl_gt1_info),
1171         INTEL_CFL_H_GT2_IDS(&cfl_gt2_info),
1172         INTEL_CFL_U_GT2_IDS(&cfl_gt2_info),
1173         INTEL_CFL_U_GT3_IDS(&cfl_gt3_info),
1174         INTEL_WHL_U_GT1_IDS(&cfl_gt1_info),
1175         INTEL_WHL_U_GT2_IDS(&cfl_gt2_info),
1176         INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info),
1177         INTEL_WHL_U_GT3_IDS(&cfl_gt3_info),
1178         INTEL_CML_GT1_IDS(&cml_gt1_info),
1179         INTEL_CML_GT2_IDS(&cml_gt2_info),
1180         INTEL_CML_U_GT1_IDS(&cml_gt1_info),
1181         INTEL_CML_U_GT2_IDS(&cml_gt2_info),
1182         INTEL_ICL_11_IDS(&icl_info),
1183         INTEL_EHL_IDS(&ehl_info),
1184         INTEL_JSL_IDS(&jsl_info),
1185         INTEL_TGL_12_IDS(&tgl_info),
1186         INTEL_RKL_IDS(&rkl_info),
1187         INTEL_ADLS_IDS(&adl_s_info),
1188         INTEL_ADLP_IDS(&adl_p_info),
1189         INTEL_ADLN_IDS(&adl_p_info),
1190         INTEL_DG1_IDS(&dg1_info),
1191         INTEL_RPLS_IDS(&adl_s_info),
1192         INTEL_RPLP_IDS(&adl_p_info),
1193         INTEL_DG2_IDS(&dg2_info),
1194         {0, 0, 0}
1195 };
1196 MODULE_DEVICE_TABLE(pci, pciidlist);
1197
1198 static void i915_pci_remove(struct pci_dev *pdev)
1199 {
1200         struct drm_i915_private *i915;
1201
1202         i915 = pci_get_drvdata(pdev);
1203         if (!i915) /* driver load aborted, nothing to cleanup */
1204                 return;
1205
1206         i915_driver_remove(i915);
1207         pci_set_drvdata(pdev, NULL);
1208 }
1209
1210 /* is device_id present in comma separated list of ids */
1211 static bool force_probe(u16 device_id, const char *devices)
1212 {
1213         char *s, *p, *tok;
1214         bool ret;
1215
1216         if (!devices || !*devices)
1217                 return false;
1218
1219         /* match everything */
1220         if (strcmp(devices, "*") == 0)
1221                 return true;
1222
1223         s = kstrdup(devices, GFP_KERNEL);
1224         if (!s)
1225                 return false;
1226
1227         for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) {
1228                 u16 val;
1229
1230                 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) {
1231                         ret = true;
1232                         break;
1233                 }
1234         }
1235
1236         kfree(s);
1237
1238         return ret;
1239 }
1240
1241 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1242 {
1243         struct intel_device_info *intel_info =
1244                 (struct intel_device_info *) ent->driver_data;
1245         int err;
1246
1247         if (intel_info->require_force_probe &&
1248             !force_probe(pdev->device, i915_modparams.force_probe)) {
1249                 dev_info(&pdev->dev,
1250                          "Your graphics device %04x is not properly supported by the driver in this\n"
1251                          "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n"
1252                          "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n"
1253                          "or (recommended) check for kernel updates.\n",
1254                          pdev->device, pdev->device, pdev->device);
1255                 return -ENODEV;
1256         }
1257
1258         /* Only bind to function 0 of the device. Early generations
1259          * used function 1 as a placeholder for multi-head. This causes
1260          * us confusion instead, especially on the systems where both
1261          * functions have the same PCI-ID!
1262          */
1263         if (PCI_FUNC(pdev->devfn))
1264                 return -ENODEV;
1265
1266         /* Detect if we need to wait for other drivers early on */
1267         if (intel_modeset_probe_defer(pdev))
1268                 return -EPROBE_DEFER;
1269
1270         err = i915_driver_probe(pdev, ent);
1271         if (err)
1272                 return err;
1273
1274         if (i915_inject_probe_failure(pci_get_drvdata(pdev))) {
1275                 i915_pci_remove(pdev);
1276                 return -ENODEV;
1277         }
1278
1279         err = i915_live_selftests(pdev);
1280         if (err) {
1281                 i915_pci_remove(pdev);
1282                 return err > 0 ? -ENOTTY : err;
1283         }
1284
1285         err = i915_perf_selftests(pdev);
1286         if (err) {
1287                 i915_pci_remove(pdev);
1288                 return err > 0 ? -ENOTTY : err;
1289         }
1290
1291         return 0;
1292 }
1293
1294 static void i915_pci_shutdown(struct pci_dev *pdev)
1295 {
1296         struct drm_i915_private *i915 = pci_get_drvdata(pdev);
1297
1298         i915_driver_shutdown(i915);
1299 }
1300
1301 static struct pci_driver i915_pci_driver = {
1302         .name = DRIVER_NAME,
1303         .id_table = pciidlist,
1304         .probe = i915_pci_probe,
1305         .remove = i915_pci_remove,
1306         .shutdown = i915_pci_shutdown,
1307         .driver.pm = &i915_pm_ops,
1308 };
1309
1310 int i915_pci_register_driver(void)
1311 {
1312         return pci_register_driver(&i915_pci_driver);
1313 }
1314
1315 void i915_pci_unregister_driver(void)
1316 {
1317         pci_unregister_driver(&i915_pci_driver);
1318 }