drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include <linux/circ_buf.h>
  34 #include <drm/drmP.h>
  35 #include <drm/i915_drm.h>
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "intel_drv.h"
  39
  40 /**
  41  * DOC: interrupt handling
  42  *
  43  * These functions provide the basic support for enabling and disabling the
  44  * interrupt handling support. There's a lot more functionality in i915_irq.c
  45  * and related files, but that will be described in separate chapters.
  46  */
  47
  48 static const u32 hpd_ilk[HPD_NUM_PINS] = {
  49         [HPD_PORT_A] = DE_DP_A_HOTPLUG,
  50 };
  51
  52 static const u32 hpd_ivb[HPD_NUM_PINS] = {
  53         [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
  54 };
  55
  56 static const u32 hpd_bdw[HPD_NUM_PINS] = {
  57         [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
  58 };
  59
  60 static const u32 hpd_ibx[HPD_NUM_PINS] = {
  61         [HPD_CRT] = SDE_CRT_HOTPLUG,
  62         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
  63         [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
  64         [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
  65         [HPD_PORT_D] = SDE_PORTD_HOTPLUG
  66 };
  67
  68 static const u32 hpd_cpt[HPD_NUM_PINS] = {
  69         [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
  70         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
  71         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  72         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  73         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
  74 };
  75
  76 static const u32 hpd_spt[HPD_NUM_PINS] = {
  77         [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
  78         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  79         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  80         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
  81         [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT
  82 };
  83
  84 static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
  85         [HPD_CRT] = CRT_HOTPLUG_INT_EN,
  86         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
  87         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
  88         [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
  89         [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
  90         [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
  91 };
  92
  93 static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
  94         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  95         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
  96         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
  97         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  98         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  99         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
 100 };
 101
 102 static const u32 hpd_status_i915[HPD_NUM_PINS] = {
 103         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
 104         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
 105         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
 106         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
 107         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
 108         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
 109 };
 110
 111 /* BXT hpd list */
 112 static const u32 hpd_bxt[HPD_NUM_PINS] = {
 113         [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
 114         [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
 115         [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
 116 };
 117
 118 /* IIR can theoretically queue up two events. Be paranoid. */
 119 #define GEN8_IRQ_RESET_NDX(type, which) do { \
 120         I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
 121         POSTING_READ(GEN8_##type##_IMR(which)); \
 122         I915_WRITE(GEN8_##type##_IER(which), 0); \
 123         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
 124         POSTING_READ(GEN8_##type##_IIR(which)); \
 125         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
 126         POSTING_READ(GEN8_##type##_IIR(which)); \
 127 } while (0)
 128
 129 #define GEN5_IRQ_RESET(type) do { \
 130         I915_WRITE(type##IMR, 0xffffffff); \
 131         POSTING_READ(type##IMR); \
 132         I915_WRITE(type##IER, 0); \
 133         I915_WRITE(type##IIR, 0xffffffff); \
 134         POSTING_READ(type##IIR); \
 135         I915_WRITE(type##IIR, 0xffffffff); \
 136         POSTING_READ(type##IIR); \
 137 } while (0)
 138
 139 /*
 140  * We should clear IMR at preinstall/uninstall, and just check at postinstall.
 141  */
 142 static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv,
 143                                     i915_reg_t reg)
 144 {
 145         u32 val = I915_READ(reg);
 146
 147         if (val == 0)
 148                 return;
 149
 150         WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
 151              i915_mmio_reg_offset(reg), val);
 152         I915_WRITE(reg, 0xffffffff);
 153         POSTING_READ(reg);
 154         I915_WRITE(reg, 0xffffffff);
 155         POSTING_READ(reg);
 156 }
 157
 158 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
 159         gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
 160         I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
 161         I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
 162         POSTING_READ(GEN8_##type##_IMR(which)); \
 163 } while (0)
 164
 165 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
 166         gen5_assert_iir_is_zero(dev_priv, type##IIR); \
 167         I915_WRITE(type##IER, (ier_val)); \
 168         I915_WRITE(type##IMR, (imr_val)); \
 169         POSTING_READ(type##IMR); \
 170 } while (0)
 171
 172 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
 173 static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
 174
 175 /* For display hotplug interrupt */
 176 static inline void
 177 i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
 178                                      uint32_t mask,
 179                                      uint32_t bits)
 180 {
 181         uint32_t val;
 182
 183         assert_spin_locked(&dev_priv->irq_lock);
 184         WARN_ON(bits & ~mask);
 185
 186         val = I915_READ(PORT_HOTPLUG_EN);
 187         val &= ~mask;
 188         val |= bits;
 189         I915_WRITE(PORT_HOTPLUG_EN, val);
 190 }
 191
 192 /**
 193  * i915_hotplug_interrupt_update - update hotplug interrupt enable
 194  * @dev_priv: driver private
 195  * @mask: bits to update
 196  * @bits: bits to enable
 197  * NOTE: the HPD enable bits are modified both inside and outside
 198  * of an interrupt context. To avoid that read-modify-write cycles
 199  * interfer, these bits are protected by a spinlock. Since this
 200  * function is usually not called from a context where the lock is
 201  * held already, this function acquires the lock itself. A non-locking
 202  * version is also available.
 203  */
 204 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
 205                                    uint32_t mask,
 206                                    uint32_t bits)
 207 {
 208         spin_lock_irq(&dev_priv->irq_lock);
 209         i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
 210         spin_unlock_irq(&dev_priv->irq_lock);
 211 }
 212
 213 /**
 214  * ilk_update_display_irq - update DEIMR
 215  * @dev_priv: driver private
 216  * @interrupt_mask: mask of interrupt bits to update
 217  * @enabled_irq_mask: mask of interrupt bits to enable
 218  */
 219 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
 220                             uint32_t interrupt_mask,
 221                             uint32_t enabled_irq_mask)
 222 {
 223         uint32_t new_val;
 224
 225         assert_spin_locked(&dev_priv->irq_lock);
 226
 227         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 228
 229         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 230                 return;
 231
 232         new_val = dev_priv->irq_mask;
 233         new_val &= ~interrupt_mask;
 234         new_val |= (~enabled_irq_mask & interrupt_mask);
 235
 236         if (new_val != dev_priv->irq_mask) {
 237                 dev_priv->irq_mask = new_val;
 238                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 239                 POSTING_READ(DEIMR);
 240         }
 241 }
 242
 243 /**
 244  * ilk_update_gt_irq - update GTIMR
 245  * @dev_priv: driver private
 246  * @interrupt_mask: mask of interrupt bits to update
 247  * @enabled_irq_mask: mask of interrupt bits to enable
 248  */
 249 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
 250                               uint32_t interrupt_mask,
 251                               uint32_t enabled_irq_mask)
 252 {
 253         assert_spin_locked(&dev_priv->irq_lock);
 254
 255         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 256
 257         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 258                 return;
 259
 260         dev_priv->gt_irq_mask &= ~interrupt_mask;
 261         dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
 262         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 263 }
 264
 265 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 266 {
 267         ilk_update_gt_irq(dev_priv, mask, mask);
 268         POSTING_READ_FW(GTIMR);
 269 }
 270
 271 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 272 {
 273         ilk_update_gt_irq(dev_priv, mask, 0);
 274 }
 275
 276 static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
 277 {
 278         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
 279 }
 280
 281 static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
 282 {
 283         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
 284 }
 285
 286 static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
 287 {
 288         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
 289 }
 290
 291 /**
 292  * snb_update_pm_irq - update GEN6_PMIMR
 293  * @dev_priv: driver private
 294  * @interrupt_mask: mask of interrupt bits to update
 295  * @enabled_irq_mask: mask of interrupt bits to enable
 296  */
 297 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
 298                               uint32_t interrupt_mask,
 299                               uint32_t enabled_irq_mask)
 300 {
 301         uint32_t new_val;
 302
 303         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 304
 305         assert_spin_locked(&dev_priv->irq_lock);
 306
 307         new_val = dev_priv->pm_imr;
 308         new_val &= ~interrupt_mask;
 309         new_val |= (~enabled_irq_mask & interrupt_mask);
 310
 311         if (new_val != dev_priv->pm_imr) {
 312                 dev_priv->pm_imr = new_val;
 313                 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_imr);
 314                 POSTING_READ(gen6_pm_imr(dev_priv));
 315         }
 316 }
 317
 318 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
 319 {
 320         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 321                 return;
 322
 323         snb_update_pm_irq(dev_priv, mask, mask);
 324 }
 325
 326 static void __gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
 327 {
 328         snb_update_pm_irq(dev_priv, mask, 0);
 329 }
 330
 331 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
 332 {
 333         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 334                 return;
 335
 336         __gen6_mask_pm_irq(dev_priv, mask);
 337 }
 338
 339 void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
 340 {
 341         i915_reg_t reg = gen6_pm_iir(dev_priv);
 342
 343         assert_spin_locked(&dev_priv->irq_lock);
 344
 345         I915_WRITE(reg, reset_mask);
 346         I915_WRITE(reg, reset_mask);
 347         POSTING_READ(reg);
 348 }
 349
 350 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask)
 351 {
 352         assert_spin_locked(&dev_priv->irq_lock);
 353
 354         dev_priv->pm_ier |= enable_mask;
 355         I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier);
 356         gen6_unmask_pm_irq(dev_priv, enable_mask);
 357         /* unmask_pm_irq provides an implicit barrier (POSTING_READ) */
 358 }
 359
 360 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask)
 361 {
 362         assert_spin_locked(&dev_priv->irq_lock);
 363
 364         dev_priv->pm_ier &= ~disable_mask;
 365         __gen6_mask_pm_irq(dev_priv, disable_mask);
 366         I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier);
 367         /* though a barrier is missing here, but don't really need a one */
 368 }
 369
 370 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
 371 {
 372         spin_lock_irq(&dev_priv->irq_lock);
 373         gen6_reset_pm_iir(dev_priv, dev_priv->pm_rps_events);
 374         dev_priv->rps.pm_iir = 0;
 375         spin_unlock_irq(&dev_priv->irq_lock);
 376 }
 377
 378 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
 379 {
 380         if (READ_ONCE(dev_priv->rps.interrupts_enabled))
 381                 return;
 382
 383         spin_lock_irq(&dev_priv->irq_lock);
 384         WARN_ON_ONCE(dev_priv->rps.pm_iir);
 385         WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
 386         dev_priv->rps.interrupts_enabled = true;
 387         gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
 388
 389         spin_unlock_irq(&dev_priv->irq_lock);
 390 }
 391
 392 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
 393 {
 394         return (mask & ~dev_priv->rps.pm_intr_keep);
 395 }
 396
 397 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
 398 {
 399         if (!READ_ONCE(dev_priv->rps.interrupts_enabled))
 400                 return;
 401
 402         spin_lock_irq(&dev_priv->irq_lock);
 403         dev_priv->rps.interrupts_enabled = false;
 404
 405         I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0u));
 406
 407         gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
 408
 409         spin_unlock_irq(&dev_priv->irq_lock);
 410         synchronize_irq(dev_priv->drm.irq);
 411
 412         /* Now that we will not be generating any more work, flush any
 413          * outsanding tasks. As we are called on the RPS idle path,
 414          * we will reset the GPU to minimum frequencies, so the current
 415          * state of the worker can be discarded.
 416          */
 417         cancel_work_sync(&dev_priv->rps.work);
 418         gen6_reset_rps_interrupts(dev_priv);
 419 }
 420
 421 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
 422 {
 423         spin_lock_irq(&dev_priv->irq_lock);
 424         gen6_reset_pm_iir(dev_priv, dev_priv->pm_guc_events);
 425         spin_unlock_irq(&dev_priv->irq_lock);
 426 }
 427
 428 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
 429 {
 430         spin_lock_irq(&dev_priv->irq_lock);
 431         if (!dev_priv->guc.interrupts_enabled) {
 432                 WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
 433                                        dev_priv->pm_guc_events);
 434                 dev_priv->guc.interrupts_enabled = true;
 435                 gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events);
 436         }
 437         spin_unlock_irq(&dev_priv->irq_lock);
 438 }
 439
 440 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
 441 {
 442         spin_lock_irq(&dev_priv->irq_lock);
 443         dev_priv->guc.interrupts_enabled = false;
 444
 445         gen6_disable_pm_irq(dev_priv, dev_priv->pm_guc_events);
 446
 447         spin_unlock_irq(&dev_priv->irq_lock);
 448         synchronize_irq(dev_priv->drm.irq);
 449
 450         gen9_reset_guc_interrupts(dev_priv);
 451 }
 452
 453 /**
 454  * bdw_update_port_irq - update DE port interrupt
 455  * @dev_priv: driver private
 456  * @interrupt_mask: mask of interrupt bits to update
 457  * @enabled_irq_mask: mask of interrupt bits to enable
 458  */
 459 static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
 460                                 uint32_t interrupt_mask,
 461                                 uint32_t enabled_irq_mask)
 462 {
 463         uint32_t new_val;
 464         uint32_t old_val;
 465
 466         assert_spin_locked(&dev_priv->irq_lock);
 467
 468         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 469
 470         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 471                 return;
 472
 473         old_val = I915_READ(GEN8_DE_PORT_IMR);
 474
 475         new_val = old_val;
 476         new_val &= ~interrupt_mask;
 477         new_val |= (~enabled_irq_mask & interrupt_mask);
 478
 479         if (new_val != old_val) {
 480                 I915_WRITE(GEN8_DE_PORT_IMR, new_val);
 481                 POSTING_READ(GEN8_DE_PORT_IMR);
 482         }
 483 }
 484
 485 /**
 486  * bdw_update_pipe_irq - update DE pipe interrupt
 487  * @dev_priv: driver private
 488  * @pipe: pipe whose interrupt to update
 489  * @interrupt_mask: mask of interrupt bits to update
 490  * @enabled_irq_mask: mask of interrupt bits to enable
 491  */
 492 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
 493                          enum pipe pipe,
 494                          uint32_t interrupt_mask,
 495                          uint32_t enabled_irq_mask)
 496 {
 497         uint32_t new_val;
 498
 499         assert_spin_locked(&dev_priv->irq_lock);
 500
 501         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 502
 503         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 504                 return;
 505
 506         new_val = dev_priv->de_irq_mask[pipe];
 507         new_val &= ~interrupt_mask;
 508         new_val |= (~enabled_irq_mask & interrupt_mask);
 509
 510         if (new_val != dev_priv->de_irq_mask[pipe]) {
 511                 dev_priv->de_irq_mask[pipe] = new_val;
 512                 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
 513                 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
 514         }
 515 }
 516
 517 /**
 518  * ibx_display_interrupt_update - update SDEIMR
 519  * @dev_priv: driver private
 520  * @interrupt_mask: mask of interrupt bits to update
 521  * @enabled_irq_mask: mask of interrupt bits to enable
 522  */
 523 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
 524                                   uint32_t interrupt_mask,
 525                                   uint32_t enabled_irq_mask)
 526 {
 527         uint32_t sdeimr = I915_READ(SDEIMR);
 528         sdeimr &= ~interrupt_mask;
 529         sdeimr |= (~enabled_irq_mask & interrupt_mask);
 530
 531         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 532
 533         assert_spin_locked(&dev_priv->irq_lock);
 534
 535         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 536                 return;
 537
 538         I915_WRITE(SDEIMR, sdeimr);
 539         POSTING_READ(SDEIMR);
 540 }
 541
 542 static void
 543 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 544                        u32 enable_mask, u32 status_mask)
 545 {
 546         i915_reg_t reg = PIPESTAT(pipe);
 547         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 548
 549         assert_spin_locked(&dev_priv->irq_lock);
 550         WARN_ON(!intel_irqs_enabled(dev_priv));
 551
 552         if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 553                       status_mask & ~PIPESTAT_INT_STATUS_MASK,
 554                       "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
 555                       pipe_name(pipe), enable_mask, status_mask))
 556                 return;
 557
 558         if ((pipestat & enable_mask) == enable_mask)
 559                 return;
 560
 561         dev_priv->pipestat_irq_mask[pipe] |= status_mask;
 562
 563         /* Enable the interrupt, clear any pending status */
 564         pipestat |= enable_mask | status_mask;
 565         I915_WRITE(reg, pipestat);
 566         POSTING_READ(reg);
 567 }
 568
 569 static void
 570 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 571                         u32 enable_mask, u32 status_mask)
 572 {
 573         i915_reg_t reg = PIPESTAT(pipe);
 574         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 575
 576         assert_spin_locked(&dev_priv->irq_lock);
 577         WARN_ON(!intel_irqs_enabled(dev_priv));
 578
 579         if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 580                       status_mask & ~PIPESTAT_INT_STATUS_MASK,
 581                       "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
 582                       pipe_name(pipe), enable_mask, status_mask))
 583                 return;
 584
 585         if ((pipestat & enable_mask) == 0)
 586                 return;
 587
 588         dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
 589
 590         pipestat &= ~enable_mask;
 591         I915_WRITE(reg, pipestat);
 592         POSTING_READ(reg);
 593 }
 594
 595 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
 596 {
 597         u32 enable_mask = status_mask << 16;
 598
 599         /*
 600          * On pipe A we don't support the PSR interrupt yet,
 601          * on pipe B and C the same bit MBZ.
 602          */
 603         if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
 604                 return 0;
 605         /*
 606          * On pipe B and C we don't support the PSR interrupt yet, on pipe
 607          * A the same bit is for perf counters which we don't use either.
 608          */
 609         if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
 610                 return 0;
 611
 612         enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
 613                          SPRITE0_FLIP_DONE_INT_EN_VLV |
 614                          SPRITE1_FLIP_DONE_INT_EN_VLV);
 615         if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
 616                 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
 617         if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
 618                 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
 619
 620         return enable_mask;
 621 }
 622
 623 void
 624 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 625                      u32 status_mask)
 626 {
 627         u32 enable_mask;
 628
 629         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 630                 enable_mask = vlv_get_pipestat_enable_mask(&dev_priv->drm,
 631                                                            status_mask);
 632         else
 633                 enable_mask = status_mask << 16;
 634         __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 635 }
 636
 637 void
 638 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 639                       u32 status_mask)
 640 {
 641         u32 enable_mask;
 642
 643         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 644                 enable_mask = vlv_get_pipestat_enable_mask(&dev_priv->drm,
 645                                                            status_mask);
 646         else
 647                 enable_mask = status_mask << 16;
 648         __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 649 }
 650
 651 /**
 652  * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
 653  * @dev_priv: i915 device private
 654  */
 655 static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
 656 {
 657         if (!dev_priv->opregion.asle || !IS_MOBILE(dev_priv))
 658                 return;
 659
 660         spin_lock_irq(&dev_priv->irq_lock);
 661
 662         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
 663         if (INTEL_GEN(dev_priv) >= 4)
 664                 i915_enable_pipestat(dev_priv, PIPE_A,
 665                                      PIPE_LEGACY_BLC_EVENT_STATUS);
 666
 667         spin_unlock_irq(&dev_priv->irq_lock);
 668 }
 669
 670 /*
 671  * This timing diagram depicts the video signal in and
 672  * around the vertical blanking period.
 673  *
 674  * Assumptions about the fictitious mode used in this example:
 675  *  vblank_start >= 3
 676  *  vsync_start = vblank_start + 1
 677  *  vsync_end = vblank_start + 2
 678  *  vtotal = vblank_start + 3
 679  *
 680  *           start of vblank:
 681  *           latch double buffered registers
 682  *           increment frame counter (ctg+)
 683  *           generate start of vblank interrupt (gen4+)
 684  *           |
 685  *           |          frame start:
 686  *           |          generate frame start interrupt (aka. vblank interrupt) (gmch)
 687  *           |          may be shifted forward 1-3 extra lines via PIPECONF
 688  *           |          |
 689  *           |          |  start of vsync:
 690  *           |          |  generate vsync interrupt
 691  *           |          |  |
 692  * ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx
 693  *       .   \hs/   .      \hs/          \hs/          \hs/   .      \hs/
 694  * ----va---> <-----------------vb--------------------> <--------va-------------
 695  *       |          |       <----vs----->                     |
 696  * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
 697  * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
 698  * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
 699  *       |          |                                         |
 700  *       last visible pixel                                   first visible pixel
 701  *                  |                                         increment frame counter (gen3/4)
 702  *                  pixel counter = vblank_start * htotal     pixel counter = 0 (gen3/4)
 703  *
 704  * x  = horizontal active
 705  * _  = horizontal blanking
 706  * hs = horizontal sync
 707  * va = vertical active
 708  * vb = vertical blanking
 709  * vs = vertical sync
 710  * vbs = vblank_start (number)
 711  *
 712  * Summary:
 713  * - most events happen at the start of horizontal sync
 714  * - frame start happens at the start of horizontal blank, 1-4 lines
 715  *   (depending on PIPECONF settings) after the start of vblank
 716  * - gen3/4 pixel and frame counter are synchronized with the start
 717  *   of horizontal active on the first line of vertical active
 718  */
 719
 720 /* Called from drm generic code, passed a 'crtc', which
 721  * we use as a pipe index
 722  */
 723 static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
 724 {
 725         struct drm_i915_private *dev_priv = to_i915(dev);
 726         i915_reg_t high_frame, low_frame;
 727         u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
 728         struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
 729                                                                 pipe);
 730         const struct drm_display_mode *mode = &intel_crtc->base.hwmode;
 731
 732         htotal = mode->crtc_htotal;
 733         hsync_start = mode->crtc_hsync_start;
 734         vbl_start = mode->crtc_vblank_start;
 735         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 736                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 737
 738         /* Convert to pixel count */
 739         vbl_start *= htotal;
 740
 741         /* Start of vblank event occurs at start of hsync */
 742         vbl_start -= htotal - hsync_start;
 743
 744         high_frame = PIPEFRAME(pipe);
 745         low_frame = PIPEFRAMEPIXEL(pipe);
 746
 747         /*
 748          * High & low register fields aren't synchronized, so make sure
 749          * we get a low value that's stable across two reads of the high
 750          * register.
 751          */
 752         do {
 753                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 754                 low   = I915_READ(low_frame);
 755                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 756         } while (high1 != high2);
 757
 758         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 759         pixel = low & PIPE_PIXEL_MASK;
 760         low >>= PIPE_FRAME_LOW_SHIFT;
 761
 762         /*
 763          * The frame counter increments at beginning of active.
 764          * Cook up a vblank counter by also checking the pixel
 765          * counter against vblank start.
 766          */
 767         return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
 768 }
 769
 770 static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
 771 {
 772         struct drm_i915_private *dev_priv = to_i915(dev);
 773
 774         return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
 775 }
 776
 777 /* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
 778 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
 779 {
 780         struct drm_device *dev = crtc->base.dev;
 781         struct drm_i915_private *dev_priv = to_i915(dev);
 782         const struct drm_display_mode *mode = &crtc->base.hwmode;
 783         enum pipe pipe = crtc->pipe;
 784         int position, vtotal;
 785
 786         vtotal = mode->crtc_vtotal;
 787         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 788                 vtotal /= 2;
 789
 790         if (IS_GEN2(dev_priv))
 791                 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
 792         else
 793                 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
 794
 795         /*
 796          * On HSW, the DSL reg (0x70000) appears to return 0 if we
 797          * read it just before the start of vblank.  So try it again
 798          * so we don't accidentally end up spanning a vblank frame
 799          * increment, causing the pipe_update_end() code to squak at us.
 800          *
 801          * The nature of this problem means we can't simply check the ISR
 802          * bit and return the vblank start value; nor can we use the scanline
 803          * debug register in the transcoder as it appears to have the same
 804          * problem.  We may need to extend this to include other platforms,
 805          * but so far testing only shows the problem on HSW.
 806          */
 807         if (HAS_DDI(dev_priv) && !position) {
 808                 int i, temp;
 809
 810                 for (i = 0; i < 100; i++) {
 811                         udelay(1);
 812                         temp = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) &
 813                                 DSL_LINEMASK_GEN3;
 814                         if (temp != position) {
 815                                 position = temp;
 816                                 break;
 817                         }
 818                 }
 819         }
 820
 821         /*
 822          * See update_scanline_offset() for the details on the
 823          * scanline_offset adjustment.
 824          */
 825         return (position + crtc->scanline_offset) % vtotal;
 826 }
 827
 828 static int i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
 829                                     unsigned int flags, int *vpos, int *hpos,
 830                                     ktime_t *stime, ktime_t *etime,
 831                                     const struct drm_display_mode *mode)
 832 {
 833         struct drm_i915_private *dev_priv = to_i915(dev);
 834         struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
 835                                                                 pipe);
 836         int position;
 837         int vbl_start, vbl_end, hsync_start, htotal, vtotal;
 838         bool in_vbl = true;
 839         int ret = 0;
 840         unsigned long irqflags;
 841
 842         if (WARN_ON(!mode->crtc_clock)) {
 843                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 844                                  "pipe %c\n", pipe_name(pipe));
 845                 return 0;
 846         }
 847
 848         htotal = mode->crtc_htotal;
 849         hsync_start = mode->crtc_hsync_start;
 850         vtotal = mode->crtc_vtotal;
 851         vbl_start = mode->crtc_vblank_start;
 852         vbl_end = mode->crtc_vblank_end;
 853
 854         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 855                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 856                 vbl_end /= 2;
 857                 vtotal /= 2;
 858         }
 859
 860         ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 861
 862         /*
 863          * Lock uncore.lock, as we will do multiple timing critical raw
 864          * register reads, potentially with preemption disabled, so the
 865          * following code must not block on uncore.lock.
 866          */
 867         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 868
 869         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 870
 871         /* Get optional system timestamp before query. */
 872         if (stime)
 873                 *stime = ktime_get();
 874
 875         if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
 876                 /* No obvious pixelcount register. Only query vertical
 877                  * scanout position from Display scan line register.
 878                  */
 879                 position = __intel_get_crtc_scanline(intel_crtc);
 880         } else {
 881                 /* Have access to pixelcount since start of frame.
 882                  * We can split this into vertical and horizontal
 883                  * scanout position.
 884                  */
 885                 position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 886
 887                 /* convert to pixel counts */
 888                 vbl_start *= htotal;
 889                 vbl_end *= htotal;
 890                 vtotal *= htotal;
 891
 892                 /*
 893                  * In interlaced modes, the pixel counter counts all pixels,
 894                  * so one field will have htotal more pixels. In order to avoid
 895                  * the reported position from jumping backwards when the pixel
 896                  * counter is beyond the length of the shorter field, just
 897                  * clamp the position the length of the shorter field. This
 898                  * matches how the scanline counter based position works since
 899                  * the scanline counter doesn't count the two half lines.
 900                  */
 901                 if (position >= vtotal)
 902                         position = vtotal - 1;
 903
 904                 /*
 905                  * Start of vblank interrupt is triggered at start of hsync,
 906                  * just prior to the first active line of vblank. However we
 907                  * consider lines to start at the leading edge of horizontal
 908                  * active. So, should we get here before we've crossed into
 909                  * the horizontal active of the first line in vblank, we would
 910                  * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
 911                  * always add htotal-hsync_start to the current pixel position.
 912                  */
 913                 position = (position + htotal - hsync_start) % vtotal;
 914         }
 915
 916         /* Get optional system timestamp after query. */
 917         if (etime)
 918                 *etime = ktime_get();
 919
 920         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 921
 922         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 923
 924         in_vbl = position >= vbl_start && position < vbl_end;
 925
 926         /*
 927          * While in vblank, position will be negative
 928          * counting up towards 0 at vbl_end. And outside
 929          * vblank, position will be positive counting
 930          * up since vbl_end.
 931          */
 932         if (position >= vbl_start)
 933                 position -= vbl_end;
 934         else
 935                 position += vtotal - vbl_end;
 936
 937         if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
 938                 *vpos = position;
 939                 *hpos = 0;
 940         } else {
 941                 *vpos = position / htotal;
 942                 *hpos = position - (*vpos * htotal);
 943         }
 944
 945         /* In vblank? */
 946         if (in_vbl)
 947                 ret |= DRM_SCANOUTPOS_IN_VBLANK;
 948
 949         return ret;
 950 }
 951
 952 int intel_get_crtc_scanline(struct intel_crtc *crtc)
 953 {
 954         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 955         unsigned long irqflags;
 956         int position;
 957
 958         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 959         position = __intel_get_crtc_scanline(crtc);
 960         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 961
 962         return position;
 963 }
 964
 965 static int i915_get_vblank_timestamp(struct drm_device *dev, unsigned int pipe,
 966                               int *max_error,
 967                               struct timeval *vblank_time,
 968                               unsigned flags)
 969 {
 970         struct drm_i915_private *dev_priv = to_i915(dev);
 971         struct intel_crtc *crtc;
 972
 973         if (pipe >= INTEL_INFO(dev_priv)->num_pipes) {
 974                 DRM_ERROR("Invalid crtc %u\n", pipe);
 975                 return -EINVAL;
 976         }
 977
 978         /* Get drm_crtc to timestamp: */
 979         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
 980         if (crtc == NULL) {
 981                 DRM_ERROR("Invalid crtc %u\n", pipe);
 982                 return -EINVAL;
 983         }
 984
 985         if (!crtc->base.hwmode.crtc_clock) {
 986                 DRM_DEBUG_KMS("crtc %u is disabled\n", pipe);
 987                 return -EBUSY;
 988         }
 989
 990         /* Helper routine in DRM core does all the work: */
 991         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 992                                                      vblank_time, flags,
 993                                                      &crtc->base.hwmode);
 994 }
 995
 996 static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv)
 997 {
 998         u32 busy_up, busy_down, max_avg, min_avg;
 999         u8 new_delay;
1000
1001         spin_lock(&mchdev_lock);
1002
1003         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
1004
1005         new_delay = dev_priv->ips.cur_delay;
1006
1007         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
1008         busy_up = I915_READ(RCPREVBSYTUPAVG);
1009         busy_down = I915_READ(RCPREVBSYTDNAVG);
1010         max_avg = I915_READ(RCBMAXAVG);
1011         min_avg = I915_READ(RCBMINAVG);
1012
1013         /* Handle RCS change request from hw */
1014         if (busy_up > max_avg) {
1015                 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
1016                         new_delay = dev_priv->ips.cur_delay - 1;
1017                 if (new_delay < dev_priv->ips.max_delay)
1018                         new_delay = dev_priv->ips.max_delay;
1019         } else if (busy_down < min_avg) {
1020                 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
1021                         new_delay = dev_priv->ips.cur_delay + 1;
1022                 if (new_delay > dev_priv->ips.min_delay)
1023                         new_delay = dev_priv->ips.min_delay;
1024         }
1025
1026         if (ironlake_set_drps(dev_priv, new_delay))
1027                 dev_priv->ips.cur_delay = new_delay;
1028
1029         spin_unlock(&mchdev_lock);
1030
1031         return;
1032 }
1033
1034 static void notify_ring(struct intel_engine_cs *engine)
1035 {
1036         smp_store_mb(engine->breadcrumbs.irq_posted, true);
1037         if (intel_engine_wakeup(engine))
1038                 trace_i915_gem_request_notify(engine);
1039 }
1040
1041 static void vlv_c0_read(struct drm_i915_private *dev_priv,
1042                         struct intel_rps_ei *ei)
1043 {
1044         ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
1045         ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
1046         ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
1047 }
1048
1049 static bool vlv_c0_above(struct drm_i915_private *dev_priv,
1050                          const struct intel_rps_ei *old,
1051                          const struct intel_rps_ei *now,
1052                          int threshold)
1053 {
1054         u64 time, c0;
1055         unsigned int mul = 100;
1056
1057         if (old->cz_clock == 0)
1058                 return false;
1059
1060         if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
1061                 mul <<= 8;
1062
1063         time = now->cz_clock - old->cz_clock;
1064         time *= threshold * dev_priv->czclk_freq;
1065
1066         /* Workload can be split between render + media, e.g. SwapBuffers
1067          * being blitted in X after being rendered in mesa. To account for
1068          * this we need to combine both engines into our activity counter.
1069          */
1070         c0 = now->render_c0 - old->render_c0;
1071         c0 += now->media_c0 - old->media_c0;
1072         c0 *= mul * VLV_CZ_CLOCK_TO_MILLI_SEC;
1073
1074         return c0 >= time;
1075 }
1076
1077 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
1078 {
1079         vlv_c0_read(dev_priv, &dev_priv->rps.down_ei);
1080         dev_priv->rps.up_ei = dev_priv->rps.down_ei;
1081 }
1082
1083 static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
1084 {
1085         struct intel_rps_ei now;
1086         u32 events = 0;
1087
1088         if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0)
1089                 return 0;
1090
1091         vlv_c0_read(dev_priv, &now);
1092         if (now.cz_clock == 0)
1093                 return 0;
1094
1095         if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) {
1096                 if (!vlv_c0_above(dev_priv,
1097                                   &dev_priv->rps.down_ei, &now,
1098                                   dev_priv->rps.down_threshold))
1099                         events |= GEN6_PM_RP_DOWN_THRESHOLD;
1100                 dev_priv->rps.down_ei = now;
1101         }
1102
1103         if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
1104                 if (vlv_c0_above(dev_priv,
1105                                  &dev_priv->rps.up_ei, &now,
1106                                  dev_priv->rps.up_threshold))
1107                         events |= GEN6_PM_RP_UP_THRESHOLD;
1108                 dev_priv->rps.up_ei = now;
1109         }
1110
1111         return events;
1112 }
1113
1114 static bool any_waiters(struct drm_i915_private *dev_priv)
1115 {
1116         struct intel_engine_cs *engine;
1117         enum intel_engine_id id;
1118
1119         for_each_engine(engine, dev_priv, id)
1120                 if (intel_engine_has_waiter(engine))
1121                         return true;
1122
1123         return false;
1124 }
1125
1126 static void gen6_pm_rps_work(struct work_struct *work)
1127 {
1128         struct drm_i915_private *dev_priv =
1129                 container_of(work, struct drm_i915_private, rps.work);
1130         bool client_boost;
1131         int new_delay, adj, min, max;
1132         u32 pm_iir;
1133
1134         spin_lock_irq(&dev_priv->irq_lock);
1135         /* Speed up work cancelation during disabling rps interrupts. */
1136         if (!dev_priv->rps.interrupts_enabled) {
1137                 spin_unlock_irq(&dev_priv->irq_lock);
1138                 return;
1139         }
1140
1141         pm_iir = dev_priv->rps.pm_iir;
1142         dev_priv->rps.pm_iir = 0;
1143         /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1144         gen6_unmask_pm_irq(dev_priv, dev_priv->pm_rps_events);
1145         client_boost = dev_priv->rps.client_boost;
1146         dev_priv->rps.client_boost = false;
1147         spin_unlock_irq(&dev_priv->irq_lock);
1148
1149         /* Make sure we didn't queue anything we're not going to process. */
1150         WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1151
1152         if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
1153                 return;
1154
1155         mutex_lock(&dev_priv->rps.hw_lock);
1156
1157         pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
1158
1159         adj = dev_priv->rps.last_adj;
1160         new_delay = dev_priv->rps.cur_freq;
1161         min = dev_priv->rps.min_freq_softlimit;
1162         max = dev_priv->rps.max_freq_softlimit;
1163         if (client_boost || any_waiters(dev_priv))
1164                 max = dev_priv->rps.max_freq;
1165         if (client_boost && new_delay < dev_priv->rps.boost_freq) {
1166                 new_delay = dev_priv->rps.boost_freq;
1167                 adj = 0;
1168         } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1169                 if (adj > 0)
1170                         adj *= 2;
1171                 else /* CHV needs even encode values */
1172                         adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
1173
1174                 if (new_delay >= dev_priv->rps.max_freq_softlimit)
1175                         adj = 0;
1176                 /*
1177                  * For better performance, jump directly
1178                  * to RPe if we're below it.
1179                  */
1180                 if (new_delay < dev_priv->rps.efficient_freq - adj) {
1181                         new_delay = dev_priv->rps.efficient_freq;
1182                         adj = 0;
1183                 }
1184         } else if (client_boost || any_waiters(dev_priv)) {
1185                 adj = 0;
1186         } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1187                 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1188                         new_delay = dev_priv->rps.efficient_freq;
1189                 else
1190                         new_delay = dev_priv->rps.min_freq_softlimit;
1191                 adj = 0;
1192         } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1193                 if (adj < 0)
1194                         adj *= 2;
1195                 else /* CHV needs even encode values */
1196                         adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
1197
1198                 if (new_delay <= dev_priv->rps.min_freq_softlimit)
1199                         adj = 0;
1200         } else { /* unknown event */
1201                 adj = 0;
1202         }
1203
1204         dev_priv->rps.last_adj = adj;
1205
1206         /* sysfs frequency interfaces may have snuck in while servicing the
1207          * interrupt
1208          */
1209         new_delay += adj;
1210         new_delay = clamp_t(int, new_delay, min, max);
1211
1212         intel_set_rps(dev_priv, new_delay);
1213
1214         mutex_unlock(&dev_priv->rps.hw_lock);
1215 }
1216
1217
1218 /**
1219  * ivybridge_parity_work - Workqueue called when a parity error interrupt
1220  * occurred.
1221  * @work: workqueue struct
1222  *
1223  * Doesn't actually do anything except notify userspace. As a consequence of
1224  * this event, userspace should try to remap the bad rows since statistically
1225  * it is likely the same row is more likely to go bad again.
1226  */
1227 static void ivybridge_parity_work(struct work_struct *work)
1228 {
1229         struct drm_i915_private *dev_priv =
1230                 container_of(work, struct drm_i915_private, l3_parity.error_work);
1231         u32 error_status, row, bank, subbank;
1232         char *parity_event[6];
1233         uint32_t misccpctl;
1234         uint8_t slice = 0;
1235
1236         /* We must turn off DOP level clock gating to access the L3 registers.
1237          * In order to prevent a get/put style interface, acquire struct mutex
1238          * any time we access those registers.
1239          */
1240         mutex_lock(&dev_priv->drm.struct_mutex);
1241
1242         /* If we've screwed up tracking, just let the interrupt fire again */
1243         if (WARN_ON(!dev_priv->l3_parity.which_slice))
1244                 goto out;
1245
1246         misccpctl = I915_READ(GEN7_MISCCPCTL);
1247         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1248         POSTING_READ(GEN7_MISCCPCTL);
1249
1250         while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1251                 i915_reg_t reg;
1252
1253                 slice--;
1254                 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv)))
1255                         break;
1256
1257                 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1258
1259                 reg = GEN7_L3CDERRST1(slice);
1260
1261                 error_status = I915_READ(reg);
1262                 row = GEN7_PARITY_ERROR_ROW(error_status);
1263                 bank = GEN7_PARITY_ERROR_BANK(error_status);
1264                 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1265
1266                 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1267                 POSTING_READ(reg);
1268
1269                 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1270                 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1271                 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1272                 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1273                 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1274                 parity_event[5] = NULL;
1275
1276                 kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj,
1277                                    KOBJ_CHANGE, parity_event);
1278
1279                 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1280                           slice, row, bank, subbank);
1281
1282                 kfree(parity_event[4]);
1283                 kfree(parity_event[3]);
1284                 kfree(parity_event[2]);
1285                 kfree(parity_event[1]);
1286         }
1287
1288         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1289
1290 out:
1291         WARN_ON(dev_priv->l3_parity.which_slice);
1292         spin_lock_irq(&dev_priv->irq_lock);
1293         gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1294         spin_unlock_irq(&dev_priv->irq_lock);
1295
1296         mutex_unlock(&dev_priv->drm.struct_mutex);
1297 }
1298
1299 static void ivybridge_parity_error_irq_handler(struct drm_i915_private *dev_priv,
1300                                                u32 iir)
1301 {
1302         if (!HAS_L3_DPF(dev_priv))
1303                 return;
1304
1305         spin_lock(&dev_priv->irq_lock);
1306         gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1307         spin_unlock(&dev_priv->irq_lock);
1308
1309         iir &= GT_PARITY_ERROR(dev_priv);
1310         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1311                 dev_priv->l3_parity.which_slice |= 1 << 1;
1312
1313         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1314                 dev_priv->l3_parity.which_slice |= 1 << 0;
1315
1316         queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1317 }
1318
1319 static void ilk_gt_irq_handler(struct drm_i915_private *dev_priv,
1320                                u32 gt_iir)
1321 {
1322         if (gt_iir & GT_RENDER_USER_INTERRUPT)
1323                 notify_ring(dev_priv->engine[RCS]);
1324         if (gt_iir & ILK_BSD_USER_INTERRUPT)
1325                 notify_ring(dev_priv->engine[VCS]);
1326 }
1327
1328 static void snb_gt_irq_handler(struct drm_i915_private *dev_priv,
1329                                u32 gt_iir)
1330 {
1331         if (gt_iir & GT_RENDER_USER_INTERRUPT)
1332                 notify_ring(dev_priv->engine[RCS]);
1333         if (gt_iir & GT_BSD_USER_INTERRUPT)
1334                 notify_ring(dev_priv->engine[VCS]);
1335         if (gt_iir & GT_BLT_USER_INTERRUPT)
1336                 notify_ring(dev_priv->engine[BCS]);
1337
1338         if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1339                       GT_BSD_CS_ERROR_INTERRUPT |
1340                       GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1341                 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1342
1343         if (gt_iir & GT_PARITY_ERROR(dev_priv))
1344                 ivybridge_parity_error_irq_handler(dev_priv, gt_iir);
1345 }
1346
1347 static __always_inline void
1348 gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift)
1349 {
1350         if (iir & (GT_RENDER_USER_INTERRUPT << test_shift))
1351                 notify_ring(engine);
1352         if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift))
1353                 tasklet_schedule(&engine->irq_tasklet);
1354 }
1355
1356 static irqreturn_t gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
1357                                    u32 master_ctl,
1358                                    u32 gt_iir[4])
1359 {
1360         irqreturn_t ret = IRQ_NONE;
1361
1362         if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1363                 gt_iir[0] = I915_READ_FW(GEN8_GT_IIR(0));
1364                 if (gt_iir[0]) {
1365                         I915_WRITE_FW(GEN8_GT_IIR(0), gt_iir[0]);
1366                         ret = IRQ_HANDLED;
1367                 } else
1368                         DRM_ERROR("The master control interrupt lied (GT0)!\n");
1369         }
1370
1371         if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1372                 gt_iir[1] = I915_READ_FW(GEN8_GT_IIR(1));
1373                 if (gt_iir[1]) {
1374                         I915_WRITE_FW(GEN8_GT_IIR(1), gt_iir[1]);
1375                         ret = IRQ_HANDLED;
1376                 } else
1377                         DRM_ERROR("The master control interrupt lied (GT1)!\n");
1378         }
1379
1380         if (master_ctl & GEN8_GT_VECS_IRQ) {
1381                 gt_iir[3] = I915_READ_FW(GEN8_GT_IIR(3));
1382                 if (gt_iir[3]) {
1383                         I915_WRITE_FW(GEN8_GT_IIR(3), gt_iir[3]);
1384                         ret = IRQ_HANDLED;
1385                 } else
1386                         DRM_ERROR("The master control interrupt lied (GT3)!\n");
1387         }
1388
1389         if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
1390                 gt_iir[2] = I915_READ_FW(GEN8_GT_IIR(2));
1391                 if (gt_iir[2] & (dev_priv->pm_rps_events |
1392                                  dev_priv->pm_guc_events)) {
1393                         I915_WRITE_FW(GEN8_GT_IIR(2),
1394                                       gt_iir[2] & (dev_priv->pm_rps_events |
1395                                                    dev_priv->pm_guc_events));
1396                         ret = IRQ_HANDLED;
1397                 } else
1398                         DRM_ERROR("The master control interrupt lied (PM)!\n");
1399         }
1400
1401         return ret;
1402 }
1403
1404 static void gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
1405                                 u32 gt_iir[4])
1406 {
1407         if (gt_iir[0]) {
1408                 gen8_cs_irq_handler(dev_priv->engine[RCS],
1409                                     gt_iir[0], GEN8_RCS_IRQ_SHIFT);
1410                 gen8_cs_irq_handler(dev_priv->engine[BCS],
1411                                     gt_iir[0], GEN8_BCS_IRQ_SHIFT);
1412         }
1413
1414         if (gt_iir[1]) {
1415                 gen8_cs_irq_handler(dev_priv->engine[VCS],
1416                                     gt_iir[1], GEN8_VCS1_IRQ_SHIFT);
1417                 gen8_cs_irq_handler(dev_priv->engine[VCS2],
1418                                     gt_iir[1], GEN8_VCS2_IRQ_SHIFT);
1419         }
1420
1421         if (gt_iir[3])
1422                 gen8_cs_irq_handler(dev_priv->engine[VECS],
1423                                     gt_iir[3], GEN8_VECS_IRQ_SHIFT);
1424
1425         if (gt_iir[2] & dev_priv->pm_rps_events)
1426                 gen6_rps_irq_handler(dev_priv, gt_iir[2]);
1427
1428         if (gt_iir[2] & dev_priv->pm_guc_events)
1429                 gen9_guc_irq_handler(dev_priv, gt_iir[2]);
1430 }
1431
1432 static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
1433 {
1434         switch (port) {
1435         case PORT_A:
1436                 return val & PORTA_HOTPLUG_LONG_DETECT;
1437         case PORT_B:
1438                 return val & PORTB_HOTPLUG_LONG_DETECT;
1439         case PORT_C:
1440                 return val & PORTC_HOTPLUG_LONG_DETECT;
1441         default:
1442                 return false;
1443         }
1444 }
1445
1446 static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
1447 {
1448         switch (port) {
1449         case PORT_E:
1450                 return val & PORTE_HOTPLUG_LONG_DETECT;
1451         default:
1452                 return false;
1453         }
1454 }
1455
1456 static bool spt_port_hotplug_long_detect(enum port port, u32 val)
1457 {
1458         switch (port) {
1459         case PORT_A:
1460                 return val & PORTA_HOTPLUG_LONG_DETECT;
1461         case PORT_B:
1462                 return val & PORTB_HOTPLUG_LONG_DETECT;
1463         case PORT_C:
1464                 return val & PORTC_HOTPLUG_LONG_DETECT;
1465         case PORT_D:
1466                 return val & PORTD_HOTPLUG_LONG_DETECT;
1467         default:
1468                 return false;
1469         }
1470 }
1471
1472 static bool ilk_port_hotplug_long_detect(enum port port, u32 val)
1473 {
1474         switch (port) {
1475         case PORT_A:
1476                 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
1477         default:
1478                 return false;
1479         }
1480 }
1481
1482 static bool pch_port_hotplug_long_detect(enum port port, u32 val)
1483 {
1484         switch (port) {
1485         case PORT_B:
1486                 return val & PORTB_HOTPLUG_LONG_DETECT;
1487         case PORT_C:
1488                 return val & PORTC_HOTPLUG_LONG_DETECT;
1489         case PORT_D:
1490                 return val & PORTD_HOTPLUG_LONG_DETECT;
1491         default:
1492                 return false;
1493         }
1494 }
1495
1496 static bool i9xx_port_hotplug_long_detect(enum port port, u32 val)
1497 {
1498         switch (port) {
1499         case PORT_B:
1500                 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1501         case PORT_C:
1502                 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1503         case PORT_D:
1504                 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1505         default:
1506                 return false;
1507         }
1508 }
1509
1510 /*
1511  * Get a bit mask of pins that have triggered, and which ones may be long.
1512  * This can be called multiple times with the same masks to accumulate
1513  * hotplug detection results from several registers.
1514  *
1515  * Note that the caller is expected to zero out the masks initially.
1516  */
1517 static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
1518                              u32 hotplug_trigger, u32 dig_hotplug_reg,
1519                              const u32 hpd[HPD_NUM_PINS],
1520                              bool long_pulse_detect(enum port port, u32 val))
1521 {
1522         enum port port;
1523         int i;
1524
1525         for_each_hpd_pin(i) {
1526                 if ((hpd[i] & hotplug_trigger) == 0)
1527                         continue;
1528
1529                 *pin_mask |= BIT(i);
1530
1531                 if (!intel_hpd_pin_to_port(i, &port))
1532                         continue;
1533
1534                 if (long_pulse_detect(port, dig_hotplug_reg))
1535                         *long_mask |= BIT(i);
1536         }
1537
1538         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
1539                          hotplug_trigger, dig_hotplug_reg, *pin_mask);
1540
1541 }
1542
1543 static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
1544 {
1545         wake_up_all(&dev_priv->gmbus_wait_queue);
1546 }
1547
1548 static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
1549 {
1550         wake_up_all(&dev_priv->gmbus_wait_queue);
1551 }
1552
1553 #if defined(CONFIG_DEBUG_FS)
1554 static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1555                                          enum pipe pipe,
1556                                          uint32_t crc0, uint32_t crc1,
1557                                          uint32_t crc2, uint32_t crc3,
1558                                          uint32_t crc4)
1559 {
1560         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1561         struct intel_pipe_crc_entry *entry;
1562         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1563         struct drm_driver *driver = dev_priv->drm.driver;
1564         uint32_t crcs[5];
1565         int head, tail;
1566
1567         spin_lock(&pipe_crc->lock);
1568         if (pipe_crc->source) {
1569                 if (!pipe_crc->entries) {
1570                         spin_unlock(&pipe_crc->lock);
1571                         DRM_DEBUG_KMS("spurious interrupt\n");
1572                         return;
1573                 }
1574
1575                 head = pipe_crc->head;
1576                 tail = pipe_crc->tail;
1577
1578                 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1579                         spin_unlock(&pipe_crc->lock);
1580                         DRM_ERROR("CRC buffer overflowing\n");
1581                         return;
1582                 }
1583
1584                 entry = &pipe_crc->entries[head];
1585
1586                 entry->frame = driver->get_vblank_counter(&dev_priv->drm, pipe);
1587                 entry->crc[0] = crc0;
1588                 entry->crc[1] = crc1;
1589                 entry->crc[2] = crc2;
1590                 entry->crc[3] = crc3;
1591                 entry->crc[4] = crc4;
1592
1593                 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1594                 pipe_crc->head = head;
1595
1596                 spin_unlock(&pipe_crc->lock);
1597
1598                 wake_up_interruptible(&pipe_crc->wq);
1599         } else {
1600                 /*
1601                  * For some not yet identified reason, the first CRC is
1602                  * bonkers. So let's just wait for the next vblank and read
1603                  * out the buggy result.
1604                  *
1605                  * On CHV sometimes the second CRC is bonkers as well, so
1606                  * don't trust that one either.
1607                  */
1608                 if (pipe_crc->skipped == 0 ||
1609                     (IS_CHERRYVIEW(dev_priv) && pipe_crc->skipped == 1)) {
1610                         pipe_crc->skipped++;
1611                         spin_unlock(&pipe_crc->lock);
1612                         return;
1613                 }
1614                 spin_unlock(&pipe_crc->lock);
1615                 crcs[0] = crc0;
1616                 crcs[1] = crc1;
1617                 crcs[2] = crc2;
1618                 crcs[3] = crc3;
1619                 crcs[4] = crc4;
1620                 drm_crtc_add_crc_entry(&crtc->base, true,
1621                                        drm_accurate_vblank_count(&crtc->base),
1622                                        crcs);
1623         }
1624 }
1625 #else
1626 static inline void
1627 display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1628                              enum pipe pipe,
1629                              uint32_t crc0, uint32_t crc1,
1630                              uint32_t crc2, uint32_t crc3,
1631                              uint32_t crc4) {}
1632 #endif
1633
1634
1635 static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1636                                      enum pipe pipe)
1637 {
1638         display_pipe_crc_irq_handler(dev_priv, pipe,
1639                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1640                                      0, 0, 0, 0);
1641 }
1642
1643 static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1644                                      enum pipe pipe)
1645 {
1646         display_pipe_crc_irq_handler(dev_priv, pipe,
1647                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1648                                      I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1649                                      I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1650                                      I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1651                                      I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1652 }
1653
1654 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1655                                       enum pipe pipe)
1656 {
1657         uint32_t res1, res2;
1658
1659         if (INTEL_GEN(dev_priv) >= 3)
1660                 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1661         else
1662                 res1 = 0;
1663
1664         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1665                 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1666         else
1667                 res2 = 0;
1668
1669         display_pipe_crc_irq_handler(dev_priv, pipe,
1670                                      I915_READ(PIPE_CRC_RES_RED(pipe)),
1671                                      I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1672                                      I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1673                                      res1, res2);
1674 }
1675
1676 /* The RPS events need forcewake, so we add them to a work queue and mask their
1677  * IMR bits until the work is done. Other interrupts can be processed without
1678  * the work queue. */
1679 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1680 {
1681         if (pm_iir & dev_priv->pm_rps_events) {
1682                 spin_lock(&dev_priv->irq_lock);
1683                 gen6_mask_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1684                 if (dev_priv->rps.interrupts_enabled) {
1685                         dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1686                         schedule_work(&dev_priv->rps.work);
1687                 }
1688                 spin_unlock(&dev_priv->irq_lock);
1689         }
1690
1691         if (INTEL_INFO(dev_priv)->gen >= 8)
1692                 return;
1693
1694         if (HAS_VEBOX(dev_priv)) {
1695                 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1696                         notify_ring(dev_priv->engine[VECS]);
1697
1698                 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1699                         DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
1700         }
1701 }
1702
1703 static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir)
1704 {
1705         if (gt_iir & GEN9_GUC_TO_HOST_INT_EVENT) {
1706                 /* Sample the log buffer flush related bits & clear them out now
1707                  * itself from the message identity register to minimize the
1708                  * probability of losing a flush interrupt, when there are back
1709                  * to back flush interrupts.
1710                  * There can be a new flush interrupt, for different log buffer
1711                  * type (like for ISR), whilst Host is handling one (for DPC).
1712                  * Since same bit is used in message register for ISR & DPC, it
1713                  * could happen that GuC sets the bit for 2nd interrupt but Host
1714                  * clears out the bit on handling the 1st interrupt.
1715                  */
1716                 u32 msg, flush;
1717
1718                 msg = I915_READ(SOFT_SCRATCH(15));
1719                 flush = msg & (INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED |
1720                                INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER);
1721                 if (flush) {
1722                         /* Clear the message bits that are handled */
1723                         I915_WRITE(SOFT_SCRATCH(15), msg & ~flush);
1724
1725                         /* Handle flush interrupt in bottom half */
1726                         queue_work(dev_priv->guc.log.flush_wq,
1727                                    &dev_priv->guc.log.flush_work);
1728
1729                         dev_priv->guc.log.flush_interrupt_count++;
1730                 } else {
1731                         /* Not clearing of unhandled event bits won't result in
1732                          * re-triggering of the interrupt.
1733                          */
1734                 }
1735         }
1736 }
1737
1738 static bool intel_pipe_handle_vblank(struct drm_i915_private *dev_priv,
1739                                      enum pipe pipe)
1740 {
1741         bool ret;
1742
1743         ret = drm_handle_vblank(&dev_priv->drm, pipe);
1744         if (ret)
1745                 intel_finish_page_flip_mmio(dev_priv, pipe);
1746
1747         return ret;
1748 }
1749
1750 static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv,
1751                                         u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1752 {
1753         int pipe;
1754
1755         spin_lock(&dev_priv->irq_lock);
1756
1757         if (!dev_priv->display_irqs_enabled) {
1758                 spin_unlock(&dev_priv->irq_lock);
1759                 return;
1760         }
1761
1762         for_each_pipe(dev_priv, pipe) {
1763                 i915_reg_t reg;
1764                 u32 mask, iir_bit = 0;
1765
1766                 /*
1767                  * PIPESTAT bits get signalled even when the interrupt is
1768                  * disabled with the mask bits, and some of the status bits do
1769                  * not generate interrupts at all (like the underrun bit). Hence
1770                  * we need to be careful that we only handle what we want to
1771                  * handle.
1772                  */
1773
1774                 /* fifo underruns are filterered in the underrun handler. */
1775                 mask = PIPE_FIFO_UNDERRUN_STATUS;
1776
1777                 switch (pipe) {
1778                 case PIPE_A:
1779                         iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1780                         break;
1781                 case PIPE_B:
1782                         iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1783                         break;
1784                 case PIPE_C:
1785                         iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1786                         break;
1787                 }
1788                 if (iir & iir_bit)
1789                         mask |= dev_priv->pipestat_irq_mask[pipe];
1790
1791                 if (!mask)
1792                         continue;
1793
1794                 reg = PIPESTAT(pipe);
1795                 mask |= PIPESTAT_INT_ENABLE_MASK;
1796                 pipe_stats[pipe] = I915_READ(reg) & mask;
1797
1798                 /*
1799                  * Clear the PIPE*STAT regs before the IIR
1800                  */
1801                 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1802                                         PIPESTAT_INT_STATUS_MASK))
1803                         I915_WRITE(reg, pipe_stats[pipe]);
1804         }
1805         spin_unlock(&dev_priv->irq_lock);
1806 }
1807
1808 static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1809                                             u32 pipe_stats[I915_MAX_PIPES])
1810 {
1811         enum pipe pipe;
1812
1813         for_each_pipe(dev_priv, pipe) {
1814                 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
1815                     intel_pipe_handle_vblank(dev_priv, pipe))
1816                         intel_check_page_flip(dev_priv, pipe);
1817
1818                 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV)
1819                         intel_finish_page_flip_cs(dev_priv, pipe);
1820
1821                 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1822                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1823
1824                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1825                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1826         }
1827
1828         if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1829                 gmbus_irq_handler(dev_priv);
1830 }
1831
1832 static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
1833 {
1834         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1835
1836         if (hotplug_status)
1837                 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1838
1839         return hotplug_status;
1840 }
1841
1842 static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1843                                  u32 hotplug_status)
1844 {
1845         u32 pin_mask = 0, long_mask = 0;
1846
1847         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
1848             IS_CHERRYVIEW(dev_priv)) {
1849                 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1850
1851                 if (hotplug_trigger) {
1852                         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1853                                            hotplug_trigger, hpd_status_g4x,
1854                                            i9xx_port_hotplug_long_detect);
1855
1856                         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1857                 }
1858
1859                 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1860                         dp_aux_irq_handler(dev_priv);
1861         } else {
1862                 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1863
1864                 if (hotplug_trigger) {
1865                         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1866                                            hotplug_trigger, hpd_status_i915,
1867                                            i9xx_port_hotplug_long_detect);
1868                         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1869                 }
1870         }
1871 }
1872
1873 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1874 {
1875         struct drm_device *dev = arg;
1876         struct drm_i915_private *dev_priv = to_i915(dev);
1877         irqreturn_t ret = IRQ_NONE;
1878
1879         if (!intel_irqs_enabled(dev_priv))
1880                 return IRQ_NONE;
1881
1882         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1883         disable_rpm_wakeref_asserts(dev_priv);
1884
1885         do {
1886                 u32 iir, gt_iir, pm_iir;
1887                 u32 pipe_stats[I915_MAX_PIPES] = {};
1888                 u32 hotplug_status = 0;
1889                 u32 ier = 0;
1890
1891                 gt_iir = I915_READ(GTIIR);
1892                 pm_iir = I915_READ(GEN6_PMIIR);
1893                 iir = I915_READ(VLV_IIR);
1894
1895                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1896                         break;
1897
1898                 ret = IRQ_HANDLED;
1899
1900                 /*
1901                  * Theory on interrupt generation, based on empirical evidence:
1902                  *
1903                  * x = ((VLV_IIR & VLV_IER) ||
1904                  *      (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
1905                  *       (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
1906                  *
1907                  * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1908                  * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
1909                  * guarantee the CPU interrupt will be raised again even if we
1910                  * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
1911                  * bits this time around.
1912                  */
1913                 I915_WRITE(VLV_MASTER_IER, 0);
1914                 ier = I915_READ(VLV_IER);
1915                 I915_WRITE(VLV_IER, 0);
1916
1917                 if (gt_iir)
1918                         I915_WRITE(GTIIR, gt_iir);
1919                 if (pm_iir)
1920                         I915_WRITE(GEN6_PMIIR, pm_iir);
1921
1922                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1923                         hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1924
1925                 /* Call regardless, as some status bits might not be
1926                  * signalled in iir */
1927                 valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1928
1929                 /*
1930                  * VLV_IIR is single buffered, and reflects the level
1931                  * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1932                  */
1933                 if (iir)
1934                         I915_WRITE(VLV_IIR, iir);
1935
1936                 I915_WRITE(VLV_IER, ier);
1937                 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1938                 POSTING_READ(VLV_MASTER_IER);
1939
1940                 if (gt_iir)
1941                         snb_gt_irq_handler(dev_priv, gt_iir);
1942                 if (pm_iir)
1943                         gen6_rps_irq_handler(dev_priv, pm_iir);
1944
1945                 if (hotplug_status)
1946                         i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1947
1948                 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1949         } while (0);
1950
1951         enable_rpm_wakeref_asserts(dev_priv);
1952
1953         return ret;
1954 }
1955
1956 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1957 {
1958         struct drm_device *dev = arg;
1959         struct drm_i915_private *dev_priv = to_i915(dev);
1960         irqreturn_t ret = IRQ_NONE;
1961
1962         if (!intel_irqs_enabled(dev_priv))
1963                 return IRQ_NONE;
1964
1965         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1966         disable_rpm_wakeref_asserts(dev_priv);
1967
1968         do {
1969                 u32 master_ctl, iir;
1970                 u32 gt_iir[4] = {};
1971                 u32 pipe_stats[I915_MAX_PIPES] = {};
1972                 u32 hotplug_status = 0;
1973                 u32 ier = 0;
1974
1975                 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1976                 iir = I915_READ(VLV_IIR);
1977
1978                 if (master_ctl == 0 && iir == 0)
1979                         break;
1980
1981                 ret = IRQ_HANDLED;
1982
1983                 /*
1984                  * Theory on interrupt generation, based on empirical evidence:
1985                  *
1986                  * x = ((VLV_IIR & VLV_IER) ||
1987                  *      ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
1988                  *       (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
1989                  *
1990                  * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1991                  * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
1992                  * guarantee the CPU interrupt will be raised again even if we
1993                  * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
1994                  * bits this time around.
1995                  */
1996                 I915_WRITE(GEN8_MASTER_IRQ, 0);
1997                 ier = I915_READ(VLV_IER);
1998                 I915_WRITE(VLV_IER, 0);
1999
2000                 gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
2001
2002                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
2003                         hotplug_status = i9xx_hpd_irq_ack(dev_priv);
2004
2005                 /* Call regardless, as some status bits might not be
2006                  * signalled in iir */
2007                 valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
2008
2009                 /*
2010                  * VLV_IIR is single buffered, and reflects the level
2011                  * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
2012                  */
2013                 if (iir)
2014                         I915_WRITE(VLV_IIR, iir);
2015
2016                 I915_WRITE(VLV_IER, ier);
2017                 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2018                 POSTING_READ(GEN8_MASTER_IRQ);
2019
2020                 gen8_gt_irq_handler(dev_priv, gt_iir);
2021
2022                 if (hotplug_status)
2023                         i9xx_hpd_irq_handler(dev_priv, hotplug_status);
2024
2025                 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
2026         } while (0);
2027
2028         enable_rpm_wakeref_asserts(dev_priv);
2029
2030         return ret;
2031 }
2032
2033 static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
2034                                 u32 hotplug_trigger,
2035                                 const u32 hpd[HPD_NUM_PINS])
2036 {
2037         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2038
2039         /*
2040          * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
2041          * unless we touch the hotplug register, even if hotplug_trigger is
2042          * zero. Not acking leads to "The master control interrupt lied (SDE)!"
2043          * errors.
2044          */
2045         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2046         if (!hotplug_trigger) {
2047                 u32 mask = PORTA_HOTPLUG_STATUS_MASK |
2048                         PORTD_HOTPLUG_STATUS_MASK |
2049                         PORTC_HOTPLUG_STATUS_MASK |
2050                         PORTB_HOTPLUG_STATUS_MASK;
2051                 dig_hotplug_reg &= ~mask;
2052         }
2053
2054         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2055         if (!hotplug_trigger)
2056                 return;
2057
2058         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2059                            dig_hotplug_reg, hpd,
2060                            pch_port_hotplug_long_detect);
2061
2062         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2063 }
2064
2065 static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2066 {
2067         int pipe;
2068         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
2069
2070         ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ibx);
2071
2072         if (pch_iir & SDE_AUDIO_POWER_MASK) {
2073                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
2074                                SDE_AUDIO_POWER_SHIFT);
2075                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
2076                                  port_name(port));
2077         }
2078
2079         if (pch_iir & SDE_AUX_MASK)
2080                 dp_aux_irq_handler(dev_priv);
2081
2082         if (pch_iir & SDE_GMBUS)
2083                 gmbus_irq_handler(dev_priv);
2084
2085         if (pch_iir & SDE_AUDIO_HDCP_MASK)
2086                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
2087
2088         if (pch_iir & SDE_AUDIO_TRANS_MASK)
2089                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
2090
2091         if (pch_iir & SDE_POISON)
2092                 DRM_ERROR("PCH poison interrupt\n");
2093
2094         if (pch_iir & SDE_FDI_MASK)
2095                 for_each_pipe(dev_priv, pipe)
2096                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
2097                                          pipe_name(pipe),
2098                                          I915_READ(FDI_RX_IIR(pipe)));
2099
2100         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
2101                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
2102
2103         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
2104                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
2105
2106         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
2107                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
2108
2109         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
2110                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2111 }
2112
2113 static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
2114 {
2115         u32 err_int = I915_READ(GEN7_ERR_INT);
2116         enum pipe pipe;
2117
2118         if (err_int & ERR_INT_POISON)
2119                 DRM_ERROR("Poison interrupt\n");
2120
2121         for_each_pipe(dev_priv, pipe) {
2122                 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
2123                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2124
2125                 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
2126                         if (IS_IVYBRIDGE(dev_priv))
2127                                 ivb_pipe_crc_irq_handler(dev_priv, pipe);
2128                         else
2129                                 hsw_pipe_crc_irq_handler(dev_priv, pipe);
2130                 }
2131         }
2132
2133         I915_WRITE(GEN7_ERR_INT, err_int);
2134 }
2135
2136 static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
2137 {
2138         u32 serr_int = I915_READ(SERR_INT);
2139
2140         if (serr_int & SERR_INT_POISON)
2141                 DRM_ERROR("PCH poison interrupt\n");
2142
2143         if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
2144                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
2145
2146         if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
2147                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2148
2149         if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
2150                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
2151
2152         I915_WRITE(SERR_INT, serr_int);
2153 }
2154
2155 static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2156 {
2157         int pipe;
2158         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2159
2160         ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_cpt);
2161
2162         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2163                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2164                                SDE_AUDIO_POWER_SHIFT_CPT);
2165                 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2166                                  port_name(port));
2167         }
2168
2169         if (pch_iir & SDE_AUX_MASK_CPT)
2170                 dp_aux_irq_handler(dev_priv);
2171
2172         if (pch_iir & SDE_GMBUS_CPT)
2173                 gmbus_irq_handler(dev_priv);
2174
2175         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2176                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2177
2178         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2179                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2180
2181         if (pch_iir & SDE_FDI_MASK_CPT)
2182                 for_each_pipe(dev_priv, pipe)
2183                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
2184                                          pipe_name(pipe),
2185                                          I915_READ(FDI_RX_IIR(pipe)));
2186
2187         if (pch_iir & SDE_ERROR_CPT)
2188                 cpt_serr_int_handler(dev_priv);
2189 }
2190
2191 static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2192 {
2193         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
2194                 ~SDE_PORTE_HOTPLUG_SPT;
2195         u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
2196         u32 pin_mask = 0, long_mask = 0;
2197
2198         if (hotplug_trigger) {
2199                 u32 dig_hotplug_reg;
2200
2201                 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2202                 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2203
2204                 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2205                                    dig_hotplug_reg, hpd_spt,
2206                                    spt_port_hotplug_long_detect);
2207         }
2208
2209         if (hotplug2_trigger) {
2210                 u32 dig_hotplug_reg;
2211
2212                 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
2213                 I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
2214
2215                 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger,
2216                                    dig_hotplug_reg, hpd_spt,
2217                                    spt_port_hotplug2_long_detect);
2218         }
2219
2220         if (pin_mask)
2221                 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2222
2223         if (pch_iir & SDE_GMBUS_CPT)
2224                 gmbus_irq_handler(dev_priv);
2225 }
2226
2227 static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
2228                                 u32 hotplug_trigger,
2229                                 const u32 hpd[HPD_NUM_PINS])
2230 {
2231         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2232
2233         dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
2234         I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
2235
2236         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2237                            dig_hotplug_reg, hpd,
2238                            ilk_port_hotplug_long_detect);
2239
2240         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2241 }
2242
2243 static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
2244                                     u32 de_iir)
2245 {
2246         enum pipe pipe;
2247         u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
2248
2249         if (hotplug_trigger)
2250                 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk);
2251
2252         if (de_iir & DE_AUX_CHANNEL_A)
2253                 dp_aux_irq_handler(dev_priv);
2254
2255         if (de_iir & DE_GSE)
2256                 intel_opregion_asle_intr(dev_priv);
2257
2258         if (de_iir & DE_POISON)
2259                 DRM_ERROR("Poison interrupt\n");
2260
2261         for_each_pipe(dev_priv, pipe) {
2262                 if (de_iir & DE_PIPE_VBLANK(pipe) &&
2263                     intel_pipe_handle_vblank(dev_priv, pipe))
2264                         intel_check_page_flip(dev_priv, pipe);
2265
2266                 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2267                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2268
2269                 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2270                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2271
2272                 /* plane/pipes map 1:1 on ilk+ */
2273                 if (de_iir & DE_PLANE_FLIP_DONE(pipe))
2274                         intel_finish_page_flip_cs(dev_priv, pipe);
2275         }
2276
2277         /* check event from PCH */
2278         if (de_iir & DE_PCH_EVENT) {
2279                 u32 pch_iir = I915_READ(SDEIIR);
2280
2281                 if (HAS_PCH_CPT(dev_priv))
2282                         cpt_irq_handler(dev_priv, pch_iir);
2283                 else
2284                         ibx_irq_handler(dev_priv, pch_iir);
2285
2286                 /* should clear PCH hotplug event before clear CPU irq */
2287                 I915_WRITE(SDEIIR, pch_iir);
2288         }
2289
2290         if (IS_GEN5(dev_priv) && de_iir & DE_PCU_EVENT)
2291                 ironlake_rps_change_irq_handler(dev_priv);
2292 }
2293
2294 static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
2295                                     u32 de_iir)
2296 {
2297         enum pipe pipe;
2298         u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2299
2300         if (hotplug_trigger)
2301                 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb);
2302
2303         if (de_iir & DE_ERR_INT_IVB)
2304                 ivb_err_int_handler(dev_priv);
2305
2306         if (de_iir & DE_AUX_CHANNEL_A_IVB)
2307                 dp_aux_irq_handler(dev_priv);
2308
2309         if (de_iir & DE_GSE_IVB)
2310                 intel_opregion_asle_intr(dev_priv);
2311
2312         for_each_pipe(dev_priv, pipe) {
2313                 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
2314                     intel_pipe_handle_vblank(dev_priv, pipe))
2315                         intel_check_page_flip(dev_priv, pipe);
2316
2317                 /* plane/pipes map 1:1 on ilk+ */
2318                 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe))
2319                         intel_finish_page_flip_cs(dev_priv, pipe);
2320         }
2321
2322         /* check event from PCH */
2323         if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
2324                 u32 pch_iir = I915_READ(SDEIIR);
2325
2326                 cpt_irq_handler(dev_priv, pch_iir);
2327
2328                 /* clear PCH hotplug event before clear CPU irq */
2329                 I915_WRITE(SDEIIR, pch_iir);
2330         }
2331 }
2332
2333 /*
2334  * To handle irqs with the minimum potential races with fresh interrupts, we:
2335  * 1 - Disable Master Interrupt Control.
2336  * 2 - Find the source(s) of the interrupt.
2337  * 3 - Clear the Interrupt Identity bits (IIR).
2338  * 4 - Process the interrupt(s) that had bits set in the IIRs.
2339  * 5 - Re-enable Master Interrupt Control.
2340  */
2341 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2342 {
2343         struct drm_device *dev = arg;
2344         struct drm_i915_private *dev_priv = to_i915(dev);
2345         u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2346         irqreturn_t ret = IRQ_NONE;
2347
2348         if (!intel_irqs_enabled(dev_priv))
2349                 return IRQ_NONE;
2350
2351         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2352         disable_rpm_wakeref_asserts(dev_priv);
2353
2354         /* disable master interrupt before clearing iir  */
2355         de_ier = I915_READ(DEIER);
2356         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2357         POSTING_READ(DEIER);
2358
2359         /* Disable south interrupts. We'll only write to SDEIIR once, so further
2360          * interrupts will will be stored on its back queue, and then we'll be
2361          * able to process them after we restore SDEIER (as soon as we restore
2362          * it, we'll get an interrupt if SDEIIR still has something to process
2363          * due to its back queue). */
2364         if (!HAS_PCH_NOP(dev_priv)) {
2365                 sde_ier = I915_READ(SDEIER);
2366                 I915_WRITE(SDEIER, 0);
2367                 POSTING_READ(SDEIER);
2368         }
2369
2370         /* Find, clear, then process each source of interrupt */
2371
2372         gt_iir = I915_READ(GTIIR);
2373         if (gt_iir) {
2374                 I915_WRITE(GTIIR, gt_iir);
2375                 ret = IRQ_HANDLED;
2376                 if (INTEL_GEN(dev_priv) >= 6)
2377                         snb_gt_irq_handler(dev_priv, gt_iir);
2378                 else
2379                         ilk_gt_irq_handler(dev_priv, gt_iir);
2380         }
2381
2382         de_iir = I915_READ(DEIIR);
2383         if (de_iir) {
2384                 I915_WRITE(DEIIR, de_iir);
2385                 ret = IRQ_HANDLED;
2386                 if (INTEL_GEN(dev_priv) >= 7)
2387                         ivb_display_irq_handler(dev_priv, de_iir);
2388                 else
2389                         ilk_display_irq_handler(dev_priv, de_iir);
2390         }
2391
2392         if (INTEL_GEN(dev_priv) >= 6) {
2393                 u32 pm_iir = I915_READ(GEN6_PMIIR);
2394                 if (pm_iir) {
2395                         I915_WRITE(GEN6_PMIIR, pm_iir);
2396                         ret = IRQ_HANDLED;
2397                         gen6_rps_irq_handler(dev_priv, pm_iir);
2398                 }
2399         }
2400
2401         I915_WRITE(DEIER, de_ier);
2402         POSTING_READ(DEIER);
2403         if (!HAS_PCH_NOP(dev_priv)) {
2404                 I915_WRITE(SDEIER, sde_ier);
2405                 POSTING_READ(SDEIER);
2406         }
2407
2408         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2409         enable_rpm_wakeref_asserts(dev_priv);
2410
2411         return ret;
2412 }
2413
2414 static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
2415                                 u32 hotplug_trigger,
2416                                 const u32 hpd[HPD_NUM_PINS])
2417 {
2418         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2419
2420         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2421         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2422
2423         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2424                            dig_hotplug_reg, hpd,
2425                            bxt_port_hotplug_long_detect);
2426
2427         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2428 }
2429
2430 static irqreturn_t
2431 gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2432 {
2433         irqreturn_t ret = IRQ_NONE;
2434         u32 iir;
2435         enum pipe pipe;
2436
2437         if (master_ctl & GEN8_DE_MISC_IRQ) {
2438                 iir = I915_READ(GEN8_DE_MISC_IIR);
2439                 if (iir) {
2440                         I915_WRITE(GEN8_DE_MISC_IIR, iir);
2441                         ret = IRQ_HANDLED;
2442                         if (iir & GEN8_DE_MISC_GSE)
2443                                 intel_opregion_asle_intr(dev_priv);
2444                         else
2445                                 DRM_ERROR("Unexpected DE Misc interrupt\n");
2446                 }
2447                 else
2448                         DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2449         }
2450
2451         if (master_ctl & GEN8_DE_PORT_IRQ) {
2452                 iir = I915_READ(GEN8_DE_PORT_IIR);
2453                 if (iir) {
2454                         u32 tmp_mask;
2455                         bool found = false;
2456
2457                         I915_WRITE(GEN8_DE_PORT_IIR, iir);
2458                         ret = IRQ_HANDLED;
2459
2460                         tmp_mask = GEN8_AUX_CHANNEL_A;
2461                         if (INTEL_INFO(dev_priv)->gen >= 9)
2462                                 tmp_mask |= GEN9_AUX_CHANNEL_B |
2463                                             GEN9_AUX_CHANNEL_C |
2464                                             GEN9_AUX_CHANNEL_D;
2465
2466                         if (iir & tmp_mask) {
2467                                 dp_aux_irq_handler(dev_priv);
2468                                 found = true;
2469                         }
2470
2471                         if (IS_GEN9_LP(dev_priv)) {
2472                                 tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
2473                                 if (tmp_mask) {
2474                                         bxt_hpd_irq_handler(dev_priv, tmp_mask,
2475                                                             hpd_bxt);
2476                                         found = true;
2477                                 }
2478                         } else if (IS_BROADWELL(dev_priv)) {
2479                                 tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
2480                                 if (tmp_mask) {
2481                                         ilk_hpd_irq_handler(dev_priv,
2482                                                             tmp_mask, hpd_bdw);
2483                                         found = true;
2484                                 }
2485                         }
2486
2487                         if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
2488                                 gmbus_irq_handler(dev_priv);
2489                                 found = true;
2490                         }
2491
2492                         if (!found)
2493                                 DRM_ERROR("Unexpected DE Port interrupt\n");
2494                 }
2495                 else
2496                         DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2497         }
2498
2499         for_each_pipe(dev_priv, pipe) {
2500                 u32 flip_done, fault_errors;
2501
2502                 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2503                         continue;
2504
2505                 iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2506                 if (!iir) {
2507                         DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2508                         continue;
2509                 }
2510
2511                 ret = IRQ_HANDLED;
2512                 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
2513
2514                 if (iir & GEN8_PIPE_VBLANK &&
2515                     intel_pipe_handle_vblank(dev_priv, pipe))
2516                         intel_check_page_flip(dev_priv, pipe);
2517
2518                 flip_done = iir;
2519                 if (INTEL_INFO(dev_priv)->gen >= 9)
2520                         flip_done &= GEN9_PIPE_PLANE1_FLIP_DONE;
2521                 else
2522                         flip_done &= GEN8_PIPE_PRIMARY_FLIP_DONE;
2523
2524                 if (flip_done)
2525                         intel_finish_page_flip_cs(dev_priv, pipe);
2526
2527                 if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
2528                         hsw_pipe_crc_irq_handler(dev_priv, pipe);
2529
2530                 if (iir & GEN8_PIPE_FIFO_UNDERRUN)
2531                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2532
2533                 fault_errors = iir;
2534                 if (INTEL_INFO(dev_priv)->gen >= 9)
2535                         fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2536                 else
2537                         fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2538
2539                 if (fault_errors)
2540                         DRM_ERROR("Fault errors on pipe %c: 0x%08x\n",
2541                                   pipe_name(pipe),
2542                                   fault_errors);
2543         }
2544
2545         if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
2546             master_ctl & GEN8_DE_PCH_IRQ) {
2547                 /*
2548                  * FIXME(BDW): Assume for now that the new interrupt handling
2549                  * scheme also closed the SDE interrupt handling race we've seen
2550                  * on older pch-split platforms. But this needs testing.
2551                  */
2552                 iir = I915_READ(SDEIIR);
2553                 if (iir) {
2554                         I915_WRITE(SDEIIR, iir);
2555                         ret = IRQ_HANDLED;
2556
2557                         if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
2558                                 spt_irq_handler(dev_priv, iir);
2559                         else
2560                                 cpt_irq_handler(dev_priv, iir);
2561                 } else {
2562                         /*
2563                          * Like on previous PCH there seems to be something
2564                          * fishy going on with forwarding PCH interrupts.
2565                          */
2566                         DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
2567                 }
2568         }
2569
2570         return ret;
2571 }
2572
2573 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2574 {
2575         struct drm_device *dev = arg;
2576         struct drm_i915_private *dev_priv = to_i915(dev);
2577         u32 master_ctl;
2578         u32 gt_iir[4] = {};
2579         irqreturn_t ret;
2580
2581         if (!intel_irqs_enabled(dev_priv))
2582                 return IRQ_NONE;
2583
2584         master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
2585         master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2586         if (!master_ctl)
2587                 return IRQ_NONE;
2588
2589         I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
2590
2591         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2592         disable_rpm_wakeref_asserts(dev_priv);
2593
2594         /* Find, clear, then process each source of interrupt */
2595         ret = gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
2596         gen8_gt_irq_handler(dev_priv, gt_iir);
2597         ret |= gen8_de_irq_handler(dev_priv, master_ctl);
2598
2599         I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2600         POSTING_READ_FW(GEN8_MASTER_IRQ);
2601
2602         enable_rpm_wakeref_asserts(dev_priv);
2603
2604         return ret;
2605 }
2606
2607 static void i915_error_wake_up(struct drm_i915_private *dev_priv)
2608 {
2609         /*
2610          * Notify all waiters for GPU completion events that reset state has
2611          * been changed, and that they need to restart their wait after
2612          * checking for potential errors (and bail out to drop locks if there is
2613          * a gpu reset pending so that i915_error_work_func can acquire them).
2614          */
2615
2616         /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2617         wake_up_all(&dev_priv->gpu_error.wait_queue);
2618
2619         /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2620         wake_up_all(&dev_priv->pending_flip_queue);
2621 }
2622
2623 /**
2624  * i915_reset_and_wakeup - do process context error handling work
2625  * @dev_priv: i915 device private
2626  *
2627  * Fire an error uevent so userspace can see that a hang or error
2628  * was detected.
2629  */
2630 static void i915_reset_and_wakeup(struct drm_i915_private *dev_priv)
2631 {
2632         struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj;
2633         char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2634         char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2635         char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2636
2637         kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
2638
2639         DRM_DEBUG_DRIVER("resetting chip\n");
2640         kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
2641
2642         /*
2643          * In most cases it's guaranteed that we get here with an RPM
2644          * reference held, for example because there is a pending GPU
2645          * request that won't finish until the reset is done. This
2646          * isn't the case at least when we get here by doing a
2647          * simulated reset via debugs, so get an RPM reference.
2648          */
2649         intel_runtime_pm_get(dev_priv);
2650         intel_prepare_reset(dev_priv);
2651
2652         do {
2653                 /*
2654                  * All state reset _must_ be completed before we update the
2655                  * reset counter, for otherwise waiters might miss the reset
2656                  * pending state and not properly drop locks, resulting in
2657                  * deadlocks with the reset work.
2658                  */
2659                 if (mutex_trylock(&dev_priv->drm.struct_mutex)) {
2660                         i915_reset(dev_priv);
2661                         mutex_unlock(&dev_priv->drm.struct_mutex);
2662                 }
2663
2664                 /* We need to wait for anyone holding the lock to wakeup */
2665         } while (wait_on_bit_timeout(&dev_priv->gpu_error.flags,
2666                                      I915_RESET_IN_PROGRESS,
2667                                      TASK_UNINTERRUPTIBLE,
2668                                      HZ));
2669
2670         intel_finish_reset(dev_priv);
2671         intel_runtime_pm_put(dev_priv);
2672
2673         if (!test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
2674                 kobject_uevent_env(kobj,
2675                                    KOBJ_CHANGE, reset_done_event);
2676
2677         /*
2678          * Note: The wake_up also serves as a memory barrier so that
2679          * waiters see the updated value of the dev_priv->gpu_error.
2680          */
2681         wake_up_all(&dev_priv->gpu_error.reset_queue);
2682 }
2683
2684 static inline void
2685 i915_err_print_instdone(struct drm_i915_private *dev_priv,
2686                         struct intel_instdone *instdone)
2687 {
2688         int slice;
2689         int subslice;
2690
2691         pr_err("  INSTDONE: 0x%08x\n", instdone->instdone);
2692
2693         if (INTEL_GEN(dev_priv) <= 3)
2694                 return;
2695
2696         pr_err("  SC_INSTDONE: 0x%08x\n", instdone->slice_common);
2697
2698         if (INTEL_GEN(dev_priv) <= 6)
2699                 return;
2700
2701         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
2702                 pr_err("  SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
2703                        slice, subslice, instdone->sampler[slice][subslice]);
2704
2705         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
2706                 pr_err("  ROW_INSTDONE[%d][%d]: 0x%08x\n",
2707                        slice, subslice, instdone->row[slice][subslice]);
2708 }
2709
2710 static void i915_clear_error_registers(struct drm_i915_private *dev_priv)
2711 {
2712         u32 eir;
2713
2714         if (!IS_GEN2(dev_priv))
2715                 I915_WRITE(PGTBL_ER, I915_READ(PGTBL_ER));
2716
2717         if (INTEL_GEN(dev_priv) < 4)
2718                 I915_WRITE(IPEIR, I915_READ(IPEIR));
2719         else
2720                 I915_WRITE(IPEIR_I965, I915_READ(IPEIR_I965));
2721
2722         I915_WRITE(EIR, I915_READ(EIR));
2723         eir = I915_READ(EIR);
2724         if (eir) {
2725                 /*
2726                  * some errors might have become stuck,
2727                  * mask them.
2728                  */
2729                 DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir);
2730                 I915_WRITE(EMR, I915_READ(EMR) | eir);
2731                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2732         }
2733 }
2734
2735 /**
2736  * i915_handle_error - handle a gpu error
2737  * @dev_priv: i915 device private
2738  * @engine_mask: mask representing engines that are hung
2739  * @fmt: Error message format string
2740  *
2741  * Do some basic checking of register state at error time and
2742  * dump it to the syslog.  Also call i915_capture_error_state() to make
2743  * sure we get a record and make it available in debugfs.  Fire a uevent
2744  * so userspace knows something bad happened (should trigger collection
2745  * of a ring dump etc.).
2746  */
2747 void i915_handle_error(struct drm_i915_private *dev_priv,
2748                        u32 engine_mask,
2749                        const char *fmt, ...)
2750 {
2751         va_list args;
2752         char error_msg[80];
2753
2754         va_start(args, fmt);
2755         vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2756         va_end(args);
2757
2758         i915_capture_error_state(dev_priv, engine_mask, error_msg);
2759         i915_clear_error_registers(dev_priv);
2760
2761         if (!engine_mask)
2762                 return;
2763
2764         if (test_and_set_bit(I915_RESET_IN_PROGRESS,
2765                              &dev_priv->gpu_error.flags))
2766                 return;
2767
2768         /*
2769          * Wakeup waiting processes so that the reset function
2770          * i915_reset_and_wakeup doesn't deadlock trying to grab
2771          * various locks. By bumping the reset counter first, the woken
2772          * processes will see a reset in progress and back off,
2773          * releasing their locks and then wait for the reset completion.
2774          * We must do this for _all_ gpu waiters that might hold locks
2775          * that the reset work needs to acquire.
2776          *
2777          * Note: The wake_up also provides a memory barrier to ensure that the
2778          * waiters see the updated value of the reset flags.
2779          */
2780         i915_error_wake_up(dev_priv);
2781
2782         i915_reset_and_wakeup(dev_priv);
2783 }
2784
2785 /* Called from drm generic code, passed 'crtc' which
2786  * we use as a pipe index
2787  */
2788 static int i8xx_enable_vblank(struct drm_device *dev, unsigned int pipe)
2789 {
2790         struct drm_i915_private *dev_priv = to_i915(dev);
2791         unsigned long irqflags;
2792
2793         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2794         i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
2795         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2796
2797         return 0;
2798 }
2799
2800 static int i965_enable_vblank(struct drm_device *dev, unsigned int pipe)
2801 {
2802         struct drm_i915_private *dev_priv = to_i915(dev);
2803         unsigned long irqflags;
2804
2805         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2806         i915_enable_pipestat(dev_priv, pipe,
2807                              PIPE_START_VBLANK_INTERRUPT_STATUS);
2808         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2809
2810         return 0;
2811 }
2812
2813 static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)
2814 {
2815         struct drm_i915_private *dev_priv = to_i915(dev);
2816         unsigned long irqflags;
2817         uint32_t bit = INTEL_GEN(dev_priv) >= 7 ?
2818                 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
2819
2820         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2821         ilk_enable_display_irq(dev_priv, bit);
2822         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2823
2824         return 0;
2825 }
2826
2827 static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe)
2828 {
2829         struct drm_i915_private *dev_priv = to_i915(dev);
2830         unsigned long irqflags;
2831
2832         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2833         bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2834         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2835
2836         return 0;
2837 }
2838
2839 /* Called from drm generic code, passed 'crtc' which
2840  * we use as a pipe index
2841  */
2842 static void i8xx_disable_vblank(struct drm_device *dev, unsigned int pipe)
2843 {
2844         struct drm_i915_private *dev_priv = to_i915(dev);
2845         unsigned long irqflags;
2846
2847         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2848         i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
2849         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2850 }
2851
2852 static void i965_disable_vblank(struct drm_device *dev, unsigned int pipe)
2853 {
2854         struct drm_i915_private *dev_priv = to_i915(dev);
2855         unsigned long irqflags;
2856
2857         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2858         i915_disable_pipestat(dev_priv, pipe,
2859                               PIPE_START_VBLANK_INTERRUPT_STATUS);
2860         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2861 }
2862
2863 static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)
2864 {
2865         struct drm_i915_private *dev_priv = to_i915(dev);
2866         unsigned long irqflags;
2867         uint32_t bit = INTEL_GEN(dev_priv) >= 7 ?
2868                 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
2869
2870         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2871         ilk_disable_display_irq(dev_priv, bit);
2872         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2873 }
2874
2875 static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe)
2876 {
2877         struct drm_i915_private *dev_priv = to_i915(dev);
2878         unsigned long irqflags;
2879
2880         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2881         bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2882         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2883 }
2884
2885 static void ibx_irq_reset(struct drm_i915_private *dev_priv)
2886 {
2887         if (HAS_PCH_NOP(dev_priv))
2888                 return;
2889
2890         GEN5_IRQ_RESET(SDE);
2891
2892         if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
2893                 I915_WRITE(SERR_INT, 0xffffffff);
2894 }
2895
2896 /*
2897  * SDEIER is also touched by the interrupt handler to work around missed PCH
2898  * interrupts. Hence we can't update it after the interrupt handler is enabled -
2899  * instead we unconditionally enable all PCH interrupt sources here, but then
2900  * only unmask them as needed with SDEIMR.
2901  *
2902  * This function needs to be called before interrupts are enabled.
2903  */
2904 static void ibx_irq_pre_postinstall(struct drm_device *dev)
2905 {
2906         struct drm_i915_private *dev_priv = to_i915(dev);
2907
2908         if (HAS_PCH_NOP(dev_priv))
2909                 return;
2910
2911         WARN_ON(I915_READ(SDEIER) != 0);
2912         I915_WRITE(SDEIER, 0xffffffff);
2913         POSTING_READ(SDEIER);
2914 }
2915
2916 static void gen5_gt_irq_reset(struct drm_i915_private *dev_priv)
2917 {
2918         GEN5_IRQ_RESET(GT);
2919         if (INTEL_GEN(dev_priv) >= 6)
2920                 GEN5_IRQ_RESET(GEN6_PM);
2921 }
2922
2923 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
2924 {
2925         enum pipe pipe;
2926
2927         if (IS_CHERRYVIEW(dev_priv))
2928                 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
2929         else
2930                 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2931
2932         i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
2933         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2934
2935         for_each_pipe(dev_priv, pipe) {
2936                 I915_WRITE(PIPESTAT(pipe),
2937                            PIPE_FIFO_UNDERRUN_STATUS |
2938                            PIPESTAT_INT_STATUS_MASK);
2939                 dev_priv->pipestat_irq_mask[pipe] = 0;
2940         }
2941
2942         GEN5_IRQ_RESET(VLV_);
2943         dev_priv->irq_mask = ~0;
2944 }
2945
2946 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
2947 {
2948         u32 pipestat_mask;
2949         u32 enable_mask;
2950         enum pipe pipe;
2951
2952         pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
2953                         PIPE_CRC_DONE_INTERRUPT_STATUS;
2954
2955         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
2956         for_each_pipe(dev_priv, pipe)
2957                 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
2958
2959         enable_mask = I915_DISPLAY_PORT_INTERRUPT |
2960                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2961                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
2962         if (IS_CHERRYVIEW(dev_priv))
2963                 enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
2964
2965         WARN_ON(dev_priv->irq_mask != ~0);
2966
2967         dev_priv->irq_mask = ~enable_mask;
2968
2969         GEN5_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask);
2970 }
2971
2972 /* drm_dma.h hooks
2973 */
2974 static void ironlake_irq_reset(struct drm_device *dev)
2975 {
2976         struct drm_i915_private *dev_priv = to_i915(dev);
2977
2978         I915_WRITE(HWSTAM, 0xffffffff);
2979
2980         GEN5_IRQ_RESET(DE);
2981         if (IS_GEN7(dev_priv))
2982                 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
2983
2984         gen5_gt_irq_reset(dev_priv);
2985
2986         ibx_irq_reset(dev_priv);
2987 }
2988
2989 static void valleyview_irq_preinstall(struct drm_device *dev)
2990 {
2991         struct drm_i915_private *dev_priv = to_i915(dev);
2992
2993         I915_WRITE(VLV_MASTER_IER, 0);
2994         POSTING_READ(VLV_MASTER_IER);
2995
2996         gen5_gt_irq_reset(dev_priv);
2997
2998         spin_lock_irq(&dev_priv->irq_lock);
2999         if (dev_priv->display_irqs_enabled)
3000                 vlv_display_irq_reset(dev_priv);
3001         spin_unlock_irq(&dev_priv->irq_lock);
3002 }
3003
3004 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3005 {
3006         GEN8_IRQ_RESET_NDX(GT, 0);
3007         GEN8_IRQ_RESET_NDX(GT, 1);
3008         GEN8_IRQ_RESET_NDX(GT, 2);
3009         GEN8_IRQ_RESET_NDX(GT, 3);
3010 }
3011
3012 static void gen8_irq_reset(struct drm_device *dev)
3013 {
3014         struct drm_i915_private *dev_priv = to_i915(dev);
3015         int pipe;
3016
3017         I915_WRITE(GEN8_MASTER_IRQ, 0);
3018         POSTING_READ(GEN8_MASTER_IRQ);
3019
3020         gen8_gt_irq_reset(dev_priv);
3021
3022         for_each_pipe(dev_priv, pipe)
3023                 if (intel_display_power_is_enabled(dev_priv,
3024                                                    POWER_DOMAIN_PIPE(pipe)))
3025                         GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3026
3027         GEN5_IRQ_RESET(GEN8_DE_PORT_);
3028         GEN5_IRQ_RESET(GEN8_DE_MISC_);
3029         GEN5_IRQ_RESET(GEN8_PCU_);
3030
3031         if (HAS_PCH_SPLIT(dev_priv))
3032                 ibx_irq_reset(dev_priv);
3033 }
3034
3035 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
3036                                      unsigned int pipe_mask)
3037 {
3038         uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3039         enum pipe pipe;
3040
3041         spin_lock_irq(&dev_priv->irq_lock);
3042         for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3043                 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3044                                   dev_priv->de_irq_mask[pipe],
3045                                   ~dev_priv->de_irq_mask[pipe] | extra_ier);
3046         spin_unlock_irq(&dev_priv->irq_lock);
3047 }
3048
3049 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
3050                                      unsigned int pipe_mask)
3051 {
3052         enum pipe pipe;
3053
3054         spin_lock_irq(&dev_priv->irq_lock);
3055         for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3056                 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3057         spin_unlock_irq(&dev_priv->irq_lock);
3058
3059         /* make sure we're done processing display irqs */
3060         synchronize_irq(dev_priv->drm.irq);
3061 }
3062
3063 static void cherryview_irq_preinstall(struct drm_device *dev)
3064 {
3065         struct drm_i915_private *dev_priv = to_i915(dev);
3066
3067         I915_WRITE(GEN8_MASTER_IRQ, 0);
3068         POSTING_READ(GEN8_MASTER_IRQ);
3069
3070         gen8_gt_irq_reset(dev_priv);
3071
3072         GEN5_IRQ_RESET(GEN8_PCU_);
3073
3074         spin_lock_irq(&dev_priv->irq_lock);
3075         if (dev_priv->display_irqs_enabled)
3076                 vlv_display_irq_reset(dev_priv);
3077         spin_unlock_irq(&dev_priv->irq_lock);
3078 }
3079
3080 static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
3081                                   const u32 hpd[HPD_NUM_PINS])
3082 {
3083         struct intel_encoder *encoder;
3084         u32 enabled_irqs = 0;
3085
3086         for_each_intel_encoder(&dev_priv->drm, encoder)
3087                 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
3088                         enabled_irqs |= hpd[encoder->hpd_pin];
3089
3090         return enabled_irqs;
3091 }
3092
3093 static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
3094 {
3095         u32 hotplug_irqs, hotplug, enabled_irqs;
3096
3097         if (HAS_PCH_IBX(dev_priv)) {
3098                 hotplug_irqs = SDE_HOTPLUG_MASK;
3099                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ibx);
3100         } else {
3101                 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3102                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_cpt);
3103         }
3104
3105         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3106
3107         /*
3108          * Enable digital hotplug on the PCH, and configure the DP short pulse
3109          * duration to 2ms (which is the minimum in the Display Port spec).
3110          * The pulse duration bits are reserved on LPT+.
3111          */
3112         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3113         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3114         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3115         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3116         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3117         /*
3118          * When CPU and PCH are on the same package, port A
3119          * HPD must be enabled in both north and south.
3120          */
3121         if (HAS_PCH_LPT_LP(dev_priv))
3122                 hotplug |= PORTA_HOTPLUG_ENABLE;
3123         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3124 }
3125
3126 static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3127 {
3128         u32 hotplug;
3129
3130         /* Enable digital hotplug on the PCH */
3131         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3132         hotplug |= PORTA_HOTPLUG_ENABLE |
3133                    PORTB_HOTPLUG_ENABLE |
3134                    PORTC_HOTPLUG_ENABLE |
3135                    PORTD_HOTPLUG_ENABLE;
3136         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3137
3138         hotplug = I915_READ(PCH_PORT_HOTPLUG2);
3139         hotplug |= PORTE_HOTPLUG_ENABLE;
3140         I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
3141 }
3142
3143 static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3144 {
3145         u32 hotplug_irqs, enabled_irqs;
3146
3147         hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
3148         enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt);
3149
3150         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3151
3152         spt_hpd_detection_setup(dev_priv);
3153 }
3154
3155 static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
3156 {
3157         u32 hotplug_irqs, hotplug, enabled_irqs;
3158
3159         if (INTEL_GEN(dev_priv) >= 8) {
3160                 hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
3161                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw);
3162
3163                 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3164         } else if (INTEL_GEN(dev_priv) >= 7) {
3165                 hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
3166                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ivb);
3167
3168                 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3169         } else {
3170                 hotplug_irqs = DE_DP_A_HOTPLUG;
3171                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ilk);
3172
3173                 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3174         }
3175
3176         /*
3177          * Enable digital hotplug on the CPU, and configure the DP short pulse
3178          * duration to 2ms (which is the minimum in the Display Port spec)
3179          * The pulse duration bits are reserved on HSW+.
3180          */
3181         hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
3182         hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
3183         hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE | DIGITAL_PORTA_PULSE_DURATION_2ms;
3184         I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
3185
3186         ibx_hpd_irq_setup(dev_priv);
3187 }
3188
3189 static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
3190                                       u32 enabled_irqs)
3191 {
3192         u32 hotplug;
3193
3194         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3195         hotplug |= PORTA_HOTPLUG_ENABLE |
3196                    PORTB_HOTPLUG_ENABLE |
3197                    PORTC_HOTPLUG_ENABLE;
3198
3199         DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x\n",
3200                       hotplug, enabled_irqs);
3201         hotplug &= ~BXT_DDI_HPD_INVERT_MASK;
3202
3203         /*
3204          * For BXT invert bit has to be set based on AOB design
3205          * for HPD detection logic, update it based on VBT fields.
3206          */
3207         if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) &&
3208             intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
3209                 hotplug |= BXT_DDIA_HPD_INVERT;
3210         if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) &&
3211             intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
3212                 hotplug |= BXT_DDIB_HPD_INVERT;
3213         if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) &&
3214             intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
3215                 hotplug |= BXT_DDIC_HPD_INVERT;
3216
3217         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3218 }
3219
3220 static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3221 {
3222         __bxt_hpd_detection_setup(dev_priv, BXT_DE_PORT_HOTPLUG_MASK);
3223 }
3224
3225 static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3226 {
3227         u32 hotplug_irqs, enabled_irqs;
3228
3229         enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bxt);
3230         hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK;
3231
3232         bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3233
3234         __bxt_hpd_detection_setup(dev_priv, enabled_irqs);
3235 }
3236
3237 static void ibx_irq_postinstall(struct drm_device *dev)
3238 {
3239         struct drm_i915_private *dev_priv = to_i915(dev);
3240         u32 mask;
3241
3242         if (HAS_PCH_NOP(dev_priv))
3243                 return;
3244
3245         if (HAS_PCH_IBX(dev_priv))
3246                 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3247         else
3248                 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3249
3250         gen5_assert_iir_is_zero(dev_priv, SDEIIR);
3251         I915_WRITE(SDEIMR, ~mask);
3252
3253         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
3254             HAS_PCH_LPT(dev_priv))
3255                 ; /* TODO: Enable HPD detection on older PCH platforms too */
3256         else
3257                 spt_hpd_detection_setup(dev_priv);
3258 }
3259
3260 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3261 {
3262         struct drm_i915_private *dev_priv = to_i915(dev);
3263         u32 pm_irqs, gt_irqs;
3264
3265         pm_irqs = gt_irqs = 0;
3266
3267         dev_priv->gt_irq_mask = ~0;
3268         if (HAS_L3_DPF(dev_priv)) {
3269                 /* L3 parity interrupt is always unmasked. */
3270                 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev_priv);
3271                 gt_irqs |= GT_PARITY_ERROR(dev_priv);
3272         }
3273
3274         gt_irqs |= GT_RENDER_USER_INTERRUPT;
3275         if (IS_GEN5(dev_priv)) {
3276                 gt_irqs |= ILK_BSD_USER_INTERRUPT;
3277         } else {
3278                 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3279         }
3280
3281         GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3282
3283         if (INTEL_GEN(dev_priv) >= 6) {
3284                 /*
3285                  * RPS interrupts will get enabled/disabled on demand when RPS
3286                  * itself is enabled/disabled.
3287                  */
3288                 if (HAS_VEBOX(dev_priv)) {
3289                         pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3290                         dev_priv->pm_ier |= PM_VEBOX_USER_INTERRUPT;
3291                 }
3292
3293                 dev_priv->pm_imr = 0xffffffff;
3294                 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_imr, pm_irqs);
3295         }
3296 }
3297
3298 static int ironlake_irq_postinstall(struct drm_device *dev)
3299 {
3300         struct drm_i915_private *dev_priv = to_i915(dev);
3301         u32 display_mask, extra_mask;
3302
3303         if (INTEL_GEN(dev_priv) >= 7) {
3304                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3305                                 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3306                                 DE_PLANEB_FLIP_DONE_IVB |
3307                                 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3308                 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3309                               DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
3310                               DE_DP_A_HOTPLUG_IVB);
3311         } else {
3312                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3313                                 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3314                                 DE_AUX_CHANNEL_A |
3315                                 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3316                                 DE_POISON);
3317                 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3318                               DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
3319                               DE_DP_A_HOTPLUG);
3320         }
3321
3322         dev_priv->irq_mask = ~display_mask;
3323
3324         I915_WRITE(HWSTAM, 0xeffe);
3325
3326         ibx_irq_pre_postinstall(dev);
3327
3328         GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3329
3330         gen5_gt_irq_postinstall(dev);
3331
3332         ibx_irq_postinstall(dev);
3333
3334         if (IS_IRONLAKE_M(dev_priv)) {
3335                 /* Enable PCU event interrupts
3336                  *
3337                  * spinlocking not required here for correctness since interrupt
3338                  * setup is guaranteed to run in single-threaded context. But we
3339                  * need it to make the assert_spin_locked happy. */
3340                 spin_lock_irq(&dev_priv->irq_lock);
3341                 ilk_enable_display_irq(dev_priv, DE_PCU_EVENT);
3342                 spin_unlock_irq(&dev_priv->irq_lock);
3343         }
3344
3345         return 0;
3346 }
3347
3348 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3349 {
3350         assert_spin_locked(&dev_priv->irq_lock);
3351
3352         if (dev_priv->display_irqs_enabled)
3353                 return;
3354
3355         dev_priv->display_irqs_enabled = true;
3356
3357         if (intel_irqs_enabled(dev_priv)) {
3358                 vlv_display_irq_reset(dev_priv);
3359                 vlv_display_irq_postinstall(dev_priv);
3360         }
3361 }
3362
3363 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3364 {
3365         assert_spin_locked(&dev_priv->irq_lock);
3366
3367         if (!dev_priv->display_irqs_enabled)
3368                 return;
3369
3370         dev_priv->display_irqs_enabled = false;
3371
3372         if (intel_irqs_enabled(dev_priv))
3373                 vlv_display_irq_reset(dev_priv);
3374 }
3375
3376
3377 static int valleyview_irq_postinstall(struct drm_device *dev)
3378 {
3379         struct drm_i915_private *dev_priv = to_i915(dev);
3380
3381         gen5_gt_irq_postinstall(dev);
3382
3383         spin_lock_irq(&dev_priv->irq_lock);
3384         if (dev_priv->display_irqs_enabled)
3385                 vlv_display_irq_postinstall(dev_priv);
3386         spin_unlock_irq(&dev_priv->irq_lock);
3387
3388         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3389         POSTING_READ(VLV_MASTER_IER);
3390
3391         return 0;
3392 }
3393
3394 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3395 {
3396         /* These are interrupts we'll toggle with the ring mask register */
3397         uint32_t gt_interrupts[] = {
3398                 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3399                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3400                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3401                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3402                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3403                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3404                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3405                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3406                 0,
3407                 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3408                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3409                 };
3410
3411         if (HAS_L3_DPF(dev_priv))
3412                 gt_interrupts[0] |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
3413
3414         dev_priv->pm_ier = 0x0;
3415         dev_priv->pm_imr = ~dev_priv->pm_ier;
3416         GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3417         GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
3418         /*
3419          * RPS interrupts will get enabled/disabled on demand when RPS itself
3420          * is enabled/disabled. Same wil be the case for GuC interrupts.
3421          */
3422         GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_imr, dev_priv->pm_ier);
3423         GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
3424 }
3425
3426 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3427 {
3428         uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3429         uint32_t de_pipe_enables;
3430         u32 de_port_masked = GEN8_AUX_CHANNEL_A;
3431         u32 de_port_enables;
3432         u32 de_misc_masked = GEN8_DE_MISC_GSE;
3433         enum pipe pipe;
3434
3435         if (INTEL_INFO(dev_priv)->gen >= 9) {
3436                 de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
3437                                   GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3438                 de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
3439                                   GEN9_AUX_CHANNEL_D;
3440                 if (IS_GEN9_LP(dev_priv))
3441                         de_port_masked |= BXT_DE_PORT_GMBUS;
3442         } else {
3443                 de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
3444                                   GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3445         }
3446
3447         de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3448                                            GEN8_PIPE_FIFO_UNDERRUN;
3449
3450         de_port_enables = de_port_masked;
3451         if (IS_GEN9_LP(dev_priv))
3452                 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
3453         else if (IS_BROADWELL(dev_priv))
3454                 de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
3455
3456         dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3457         dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3458         dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3459
3460         for_each_pipe(dev_priv, pipe)
3461                 if (intel_display_power_is_enabled(dev_priv,
3462                                 POWER_DOMAIN_PIPE(pipe)))
3463                         GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3464                                           dev_priv->de_irq_mask[pipe],
3465                                           de_pipe_enables);
3466
3467         GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
3468         GEN5_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
3469
3470         if (IS_GEN9_LP(dev_priv))
3471                 bxt_hpd_detection_setup(dev_priv);
3472 }
3473
3474 static int gen8_irq_postinstall(struct drm_device *dev)
3475 {
3476         struct drm_i915_private *dev_priv = to_i915(dev);
3477
3478         if (HAS_PCH_SPLIT(dev_priv))
3479                 ibx_irq_pre_postinstall(dev);
3480
3481         gen8_gt_irq_postinstall(dev_priv);
3482         gen8_de_irq_postinstall(dev_priv);
3483
3484         if (HAS_PCH_SPLIT(dev_priv))
3485                 ibx_irq_postinstall(dev);
3486
3487         I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3488         POSTING_READ(GEN8_MASTER_IRQ);
3489
3490         return 0;
3491 }
3492
3493 static int cherryview_irq_postinstall(struct drm_device *dev)
3494 {
3495         struct drm_i915_private *dev_priv = to_i915(dev);
3496
3497         gen8_gt_irq_postinstall(dev_priv);
3498
3499         spin_lock_irq(&dev_priv->irq_lock);
3500         if (dev_priv->display_irqs_enabled)
3501                 vlv_display_irq_postinstall(dev_priv);
3502         spin_unlock_irq(&dev_priv->irq_lock);
3503
3504         I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3505         POSTING_READ(GEN8_MASTER_IRQ);
3506
3507         return 0;
3508 }
3509
3510 static void gen8_irq_uninstall(struct drm_device *dev)
3511 {
3512         struct drm_i915_private *dev_priv = to_i915(dev);
3513
3514         if (!dev_priv)
3515                 return;
3516
3517         gen8_irq_reset(dev);
3518 }
3519
3520 static void valleyview_irq_uninstall(struct drm_device *dev)
3521 {
3522         struct drm_i915_private *dev_priv = to_i915(dev);
3523
3524         if (!dev_priv)
3525                 return;
3526
3527         I915_WRITE(VLV_MASTER_IER, 0);
3528         POSTING_READ(VLV_MASTER_IER);
3529
3530         gen5_gt_irq_reset(dev_priv);
3531
3532         I915_WRITE(HWSTAM, 0xffffffff);
3533
3534         spin_lock_irq(&dev_priv->irq_lock);
3535         if (dev_priv->display_irqs_enabled)
3536                 vlv_display_irq_reset(dev_priv);
3537         spin_unlock_irq(&dev_priv->irq_lock);
3538 }
3539
3540 static void cherryview_irq_uninstall(struct drm_device *dev)
3541 {
3542         struct drm_i915_private *dev_priv = to_i915(dev);
3543
3544         if (!dev_priv)
3545                 return;
3546
3547         I915_WRITE(GEN8_MASTER_IRQ, 0);
3548         POSTING_READ(GEN8_MASTER_IRQ);
3549
3550         gen8_gt_irq_reset(dev_priv);
3551
3552         GEN5_IRQ_RESET(GEN8_PCU_);
3553
3554         spin_lock_irq(&dev_priv->irq_lock);
3555         if (dev_priv->display_irqs_enabled)
3556                 vlv_display_irq_reset(dev_priv);
3557         spin_unlock_irq(&dev_priv->irq_lock);
3558 }
3559
3560 static void ironlake_irq_uninstall(struct drm_device *dev)
3561 {
3562         struct drm_i915_private *dev_priv = to_i915(dev);
3563
3564         if (!dev_priv)
3565                 return;
3566
3567         ironlake_irq_reset(dev);
3568 }
3569
3570 static void i8xx_irq_preinstall(struct drm_device * dev)
3571 {
3572         struct drm_i915_private *dev_priv = to_i915(dev);
3573         int pipe;
3574
3575         for_each_pipe(dev_priv, pipe)
3576                 I915_WRITE(PIPESTAT(pipe), 0);
3577         I915_WRITE16(IMR, 0xffff);
3578         I915_WRITE16(IER, 0x0);
3579         POSTING_READ16(IER);
3580 }
3581
3582 static int i8xx_irq_postinstall(struct drm_device *dev)
3583 {
3584         struct drm_i915_private *dev_priv = to_i915(dev);
3585
3586         I915_WRITE16(EMR,
3587                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3588
3589         /* Unmask the interrupts that we always want on. */
3590         dev_priv->irq_mask =
3591                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3592                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3593                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3594                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3595         I915_WRITE16(IMR, dev_priv->irq_mask);
3596
3597         I915_WRITE16(IER,
3598                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3599                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3600                      I915_USER_INTERRUPT);
3601         POSTING_READ16(IER);
3602
3603         /* Interrupt setup is already guaranteed to be single-threaded, this is
3604          * just to make the assert_spin_locked check happy. */
3605         spin_lock_irq(&dev_priv->irq_lock);
3606         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3607         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3608         spin_unlock_irq(&dev_priv->irq_lock);
3609
3610         return 0;
3611 }
3612
3613 /*
3614  * Returns true when a page flip has completed.
3615  */
3616 static bool i8xx_handle_vblank(struct drm_i915_private *dev_priv,
3617                                int plane, int pipe, u32 iir)
3618 {
3619         u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3620
3621         if (!intel_pipe_handle_vblank(dev_priv, pipe))
3622                 return false;
3623
3624         if ((iir & flip_pending) == 0)
3625                 goto check_page_flip;
3626
3627         /* We detect FlipDone by looking for the change in PendingFlip from '1'
3628          * to '0' on the following vblank, i.e. IIR has the Pendingflip
3629          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3630          * the flip is completed (no longer pending). Since this doesn't raise
3631          * an interrupt per se, we watch for the change at vblank.
3632          */
3633         if (I915_READ16(ISR) & flip_pending)
3634                 goto check_page_flip;
3635
3636         intel_finish_page_flip_cs(dev_priv, pipe);
3637         return true;
3638
3639 check_page_flip:
3640         intel_check_page_flip(dev_priv, pipe);
3641         return false;
3642 }
3643
3644 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3645 {
3646         struct drm_device *dev = arg;
3647         struct drm_i915_private *dev_priv = to_i915(dev);
3648         u16 iir, new_iir;
3649         u32 pipe_stats[2];
3650         int pipe;
3651         u16 flip_mask =
3652                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3653                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3654         irqreturn_t ret;
3655
3656         if (!intel_irqs_enabled(dev_priv))
3657                 return IRQ_NONE;
3658
3659         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3660         disable_rpm_wakeref_asserts(dev_priv);
3661
3662         ret = IRQ_NONE;
3663         iir = I915_READ16(IIR);
3664         if (iir == 0)
3665                 goto out;
3666
3667         while (iir & ~flip_mask) {
3668                 /* Can't rely on pipestat interrupt bit in iir as it might
3669                  * have been cleared after the pipestat interrupt was received.
3670                  * It doesn't set the bit in iir again, but it still produces
3671                  * interrupts (for non-MSI).
3672                  */
3673                 spin_lock(&dev_priv->irq_lock);
3674                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3675                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3676
3677                 for_each_pipe(dev_priv, pipe) {
3678                         i915_reg_t reg = PIPESTAT(pipe);
3679                         pipe_stats[pipe] = I915_READ(reg);
3680
3681                         /*
3682                          * Clear the PIPE*STAT regs before the IIR
3683                          */
3684                         if (pipe_stats[pipe] & 0x8000ffff)
3685                                 I915_WRITE(reg, pipe_stats[pipe]);
3686                 }
3687                 spin_unlock(&dev_priv->irq_lock);
3688
3689                 I915_WRITE16(IIR, iir & ~flip_mask);
3690                 new_iir = I915_READ16(IIR); /* Flush posted writes */
3691
3692                 if (iir & I915_USER_INTERRUPT)
3693                         notify_ring(dev_priv->engine[RCS]);
3694
3695                 for_each_pipe(dev_priv, pipe) {
3696                         int plane = pipe;
3697                         if (HAS_FBC(dev_priv))
3698                                 plane = !plane;
3699
3700                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3701                             i8xx_handle_vblank(dev_priv, plane, pipe, iir))
3702                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3703
3704                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3705                                 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
3706
3707                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3708                                 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3709                                                                     pipe);
3710                 }
3711
3712                 iir = new_iir;
3713         }
3714         ret = IRQ_HANDLED;
3715
3716 out:
3717         enable_rpm_wakeref_asserts(dev_priv);
3718
3719         return ret;
3720 }
3721
3722 static void i8xx_irq_uninstall(struct drm_device * dev)
3723 {
3724         struct drm_i915_private *dev_priv = to_i915(dev);
3725         int pipe;
3726
3727         for_each_pipe(dev_priv, pipe) {
3728                 /* Clear enable bits; then clear status bits */
3729                 I915_WRITE(PIPESTAT(pipe), 0);
3730                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3731         }
3732         I915_WRITE16(IMR, 0xffff);
3733         I915_WRITE16(IER, 0x0);
3734         I915_WRITE16(IIR, I915_READ16(IIR));
3735 }
3736
3737 static void i915_irq_preinstall(struct drm_device * dev)
3738 {
3739         struct drm_i915_private *dev_priv = to_i915(dev);
3740         int pipe;
3741
3742         if (I915_HAS_HOTPLUG(dev_priv)) {
3743                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3744                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3745         }
3746
3747         I915_WRITE16(HWSTAM, 0xeffe);
3748         for_each_pipe(dev_priv, pipe)
3749                 I915_WRITE(PIPESTAT(pipe), 0);
3750         I915_WRITE(IMR, 0xffffffff);
3751         I915_WRITE(IER, 0x0);
3752         POSTING_READ(IER);
3753 }
3754
3755 static int i915_irq_postinstall(struct drm_device *dev)
3756 {
3757         struct drm_i915_private *dev_priv = to_i915(dev);
3758         u32 enable_mask;
3759
3760         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3761
3762         /* Unmask the interrupts that we always want on. */
3763         dev_priv->irq_mask =
3764                 ~(I915_ASLE_INTERRUPT |
3765                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3766                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3767                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3768                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3769
3770         enable_mask =
3771                 I915_ASLE_INTERRUPT |
3772                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3773                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3774                 I915_USER_INTERRUPT;
3775
3776         if (I915_HAS_HOTPLUG(dev_priv)) {
3777                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3778                 POSTING_READ(PORT_HOTPLUG_EN);
3779
3780                 /* Enable in IER... */
3781                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3782                 /* and unmask in IMR */
3783                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3784         }
3785
3786         I915_WRITE(IMR, dev_priv->irq_mask);
3787         I915_WRITE(IER, enable_mask);
3788         POSTING_READ(IER);
3789
3790         i915_enable_asle_pipestat(dev_priv);
3791
3792         /* Interrupt setup is already guaranteed to be single-threaded, this is
3793          * just to make the assert_spin_locked check happy. */
3794         spin_lock_irq(&dev_priv->irq_lock);
3795         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3796         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3797         spin_unlock_irq(&dev_priv->irq_lock);
3798
3799         return 0;
3800 }
3801
3802 /*
3803  * Returns true when a page flip has completed.
3804  */
3805 static bool i915_handle_vblank(struct drm_i915_private *dev_priv,
3806                                int plane, int pipe, u32 iir)
3807 {
3808         u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3809
3810         if (!intel_pipe_handle_vblank(dev_priv, pipe))
3811                 return false;
3812
3813         if ((iir & flip_pending) == 0)
3814                 goto check_page_flip;
3815
3816         /* We detect FlipDone by looking for the change in PendingFlip from '1'
3817          * to '0' on the following vblank, i.e. IIR has the Pendingflip
3818          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3819          * the flip is completed (no longer pending). Since this doesn't raise
3820          * an interrupt per se, we watch for the change at vblank.
3821          */
3822         if (I915_READ(ISR) & flip_pending)
3823                 goto check_page_flip;
3824
3825         intel_finish_page_flip_cs(dev_priv, pipe);
3826         return true;
3827
3828 check_page_flip:
3829         intel_check_page_flip(dev_priv, pipe);
3830         return false;
3831 }
3832
3833 static irqreturn_t i915_irq_handler(int irq, void *arg)
3834 {
3835         struct drm_device *dev = arg;
3836         struct drm_i915_private *dev_priv = to_i915(dev);
3837         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3838         u32 flip_mask =
3839                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3840                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3841         int pipe, ret = IRQ_NONE;
3842
3843         if (!intel_irqs_enabled(dev_priv))
3844                 return IRQ_NONE;
3845
3846         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3847         disable_rpm_wakeref_asserts(dev_priv);
3848
3849         iir = I915_READ(IIR);
3850         do {
3851                 bool irq_received = (iir & ~flip_mask) != 0;
3852                 bool blc_event = false;
3853
3854                 /* Can't rely on pipestat interrupt bit in iir as it might
3855                  * have been cleared after the pipestat interrupt was received.
3856                  * It doesn't set the bit in iir again, but it still produces
3857                  * interrupts (for non-MSI).
3858                  */
3859                 spin_lock(&dev_priv->irq_lock);
3860                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3861                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3862
3863                 for_each_pipe(dev_priv, pipe) {
3864                         i915_reg_t reg = PIPESTAT(pipe);
3865                         pipe_stats[pipe] = I915_READ(reg);
3866
3867                         /* Clear the PIPE*STAT regs before the IIR */
3868                         if (pipe_stats[pipe] & 0x8000ffff) {
3869                                 I915_WRITE(reg, pipe_stats[pipe]);
3870                                 irq_received = true;
3871                         }
3872                 }
3873                 spin_unlock(&dev_priv->irq_lock);
3874
3875                 if (!irq_received)
3876                         break;
3877
3878                 /* Consume port.  Then clear IIR or we'll miss events */
3879                 if (I915_HAS_HOTPLUG(dev_priv) &&
3880                     iir & I915_DISPLAY_PORT_INTERRUPT) {
3881                         u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
3882                         if (hotplug_status)
3883                                 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
3884                 }
3885
3886                 I915_WRITE(IIR, iir & ~flip_mask);
3887                 new_iir = I915_READ(IIR); /* Flush posted writes */
3888
3889                 if (iir & I915_USER_INTERRUPT)
3890                         notify_ring(dev_priv->engine[RCS]);
3891
3892                 for_each_pipe(dev_priv, pipe) {
3893                         int plane = pipe;
3894                         if (HAS_FBC(dev_priv))
3895                                 plane = !plane;
3896
3897                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3898                             i915_handle_vblank(dev_priv, plane, pipe, iir))
3899                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3900
3901                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3902                                 blc_event = true;
3903
3904                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3905                                 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
3906
3907                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3908                                 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3909                                                                     pipe);
3910                 }
3911
3912                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3913                         intel_opregion_asle_intr(dev_priv);
3914
3915                 /* With MSI, interrupts are only generated when iir
3916                  * transitions from zero to nonzero.  If another bit got
3917                  * set while we were handling the existing iir bits, then
3918                  * we would never get another interrupt.
3919                  *
3920                  * This is fine on non-MSI as well, as if we hit this path
3921                  * we avoid exiting the interrupt handler only to generate
3922                  * another one.
3923                  *
3924                  * Note that for MSI this could cause a stray interrupt report
3925                  * if an interrupt landed in the time between writing IIR and
3926                  * the posting read.  This should be rare enough to never
3927                  * trigger the 99% of 100,000 interrupts test for disabling
3928                  * stray interrupts.
3929                  */
3930                 ret = IRQ_HANDLED;
3931                 iir = new_iir;
3932         } while (iir & ~flip_mask);
3933
3934         enable_rpm_wakeref_asserts(dev_priv);
3935
3936         return ret;
3937 }
3938
3939 static void i915_irq_uninstall(struct drm_device * dev)
3940 {
3941         struct drm_i915_private *dev_priv = to_i915(dev);
3942         int pipe;
3943
3944         if (I915_HAS_HOTPLUG(dev_priv)) {
3945                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3946                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3947         }
3948
3949         I915_WRITE16(HWSTAM, 0xffff);
3950         for_each_pipe(dev_priv, pipe) {
3951                 /* Clear enable bits; then clear status bits */
3952                 I915_WRITE(PIPESTAT(pipe), 0);
3953                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3954         }
3955         I915_WRITE(IMR, 0xffffffff);
3956         I915_WRITE(IER, 0x0);
3957
3958         I915_WRITE(IIR, I915_READ(IIR));
3959 }
3960
3961 static void i965_irq_preinstall(struct drm_device * dev)
3962 {
3963         struct drm_i915_private *dev_priv = to_i915(dev);
3964         int pipe;
3965
3966         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3967         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3968
3969         I915_WRITE(HWSTAM, 0xeffe);
3970         for_each_pipe(dev_priv, pipe)
3971                 I915_WRITE(PIPESTAT(pipe), 0);
3972         I915_WRITE(IMR, 0xffffffff);
3973         I915_WRITE(IER, 0x0);
3974         POSTING_READ(IER);
3975 }
3976
3977 static int i965_irq_postinstall(struct drm_device *dev)
3978 {
3979         struct drm_i915_private *dev_priv = to_i915(dev);
3980         u32 enable_mask;
3981         u32 error_mask;
3982
3983         /* Unmask the interrupts that we always want on. */
3984         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
3985                                I915_DISPLAY_PORT_INTERRUPT |
3986                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3987                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3988                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3989                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3990                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3991
3992         enable_mask = ~dev_priv->irq_mask;
3993         enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3994                          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3995         enable_mask |= I915_USER_INTERRUPT;
3996
3997         if (IS_G4X(dev_priv))
3998                 enable_mask |= I915_BSD_USER_INTERRUPT;
3999
4000         /* Interrupt setup is already guaranteed to be single-threaded, this is
4001          * just to make the assert_spin_locked check happy. */
4002         spin_lock_irq(&dev_priv->irq_lock);
4003         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4004         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4005         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4006         spin_unlock_irq(&dev_priv->irq_lock);
4007
4008         /*
4009          * Enable some error detection, note the instruction error mask
4010          * bit is reserved, so we leave it masked.
4011          */
4012         if (IS_G4X(dev_priv)) {
4013                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4014                                GM45_ERROR_MEM_PRIV |
4015                                GM45_ERROR_CP_PRIV |
4016                                I915_ERROR_MEMORY_REFRESH);
4017         } else {
4018                 error_mask = ~(I915_ERROR_PAGE_TABLE |
4019                                I915_ERROR_MEMORY_REFRESH);
4020         }
4021         I915_WRITE(EMR, error_mask);
4022
4023         I915_WRITE(IMR, dev_priv->irq_mask);
4024         I915_WRITE(IER, enable_mask);
4025         POSTING_READ(IER);
4026
4027         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4028         POSTING_READ(PORT_HOTPLUG_EN);
4029
4030         i915_enable_asle_pipestat(dev_priv);
4031
4032         return 0;
4033 }
4034
4035 static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
4036 {
4037         u32 hotplug_en;
4038
4039         assert_spin_locked(&dev_priv->irq_lock);
4040
4041         /* Note HDMI and DP share hotplug bits */
4042         /* enable bits are the same for all generations */
4043         hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);
4044         /* Programming the CRT detection parameters tends
4045            to generate a spurious hotplug event about three
4046            seconds later.  So just do it once.
4047         */
4048         if (IS_G4X(dev_priv))
4049                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4050         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4051
4052         /* Ignore TV since it's buggy */
4053         i915_hotplug_interrupt_update_locked(dev_priv,
4054                                              HOTPLUG_INT_EN_MASK |
4055                                              CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
4056                                              CRT_HOTPLUG_ACTIVATION_PERIOD_64,
4057                                              hotplug_en);
4058 }
4059
4060 static irqreturn_t i965_irq_handler(int irq, void *arg)
4061 {
4062         struct drm_device *dev = arg;
4063         struct drm_i915_private *dev_priv = to_i915(dev);
4064         u32 iir, new_iir;
4065         u32 pipe_stats[I915_MAX_PIPES];
4066         int ret = IRQ_NONE, pipe;
4067         u32 flip_mask =
4068                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4069                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4070
4071         if (!intel_irqs_enabled(dev_priv))
4072                 return IRQ_NONE;
4073
4074         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4075         disable_rpm_wakeref_asserts(dev_priv);
4076
4077         iir = I915_READ(IIR);
4078
4079         for (;;) {
4080                 bool irq_received = (iir & ~flip_mask) != 0;
4081                 bool blc_event = false;
4082
4083                 /* Can't rely on pipestat interrupt bit in iir as it might
4084                  * have been cleared after the pipestat interrupt was received.
4085                  * It doesn't set the bit in iir again, but it still produces
4086                  * interrupts (for non-MSI).
4087                  */
4088                 spin_lock(&dev_priv->irq_lock);
4089                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4090                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4091
4092                 for_each_pipe(dev_priv, pipe) {
4093                         i915_reg_t reg = PIPESTAT(pipe);
4094                         pipe_stats[pipe] = I915_READ(reg);
4095
4096                         /*
4097                          * Clear the PIPE*STAT regs before the IIR
4098                          */
4099                         if (pipe_stats[pipe] & 0x8000ffff) {
4100                                 I915_WRITE(reg, pipe_stats[pipe]);
4101                                 irq_received = true;
4102                         }
4103                 }
4104                 spin_unlock(&dev_priv->irq_lock);
4105
4106                 if (!irq_received)
4107                         break;
4108
4109                 ret = IRQ_HANDLED;
4110
4111                 /* Consume port.  Then clear IIR or we'll miss events */
4112                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
4113                         u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4114                         if (hotplug_status)
4115                                 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4116                 }
4117
4118                 I915_WRITE(IIR, iir & ~flip_mask);
4119                 new_iir = I915_READ(IIR); /* Flush posted writes */
4120
4121                 if (iir & I915_USER_INTERRUPT)
4122                         notify_ring(dev_priv->engine[RCS]);
4123                 if (iir & I915_BSD_USER_INTERRUPT)
4124                         notify_ring(dev_priv->engine[VCS]);
4125
4126                 for_each_pipe(dev_priv, pipe) {
4127                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4128                             i915_handle_vblank(dev_priv, pipe, pipe, iir))
4129                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4130
4131                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4132                                 blc_event = true;
4133
4134                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4135                                 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4136
4137                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4138                                 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
4139                 }
4140
4141                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4142                         intel_opregion_asle_intr(dev_priv);
4143
4144                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4145                         gmbus_irq_handler(dev_priv);
4146
4147                 /* With MSI, interrupts are only generated when iir
4148                  * transitions from zero to nonzero.  If another bit got
4149                  * set while we were handling the existing iir bits, then
4150                  * we would never get another interrupt.
4151                  *
4152                  * This is fine on non-MSI as well, as if we hit this path
4153                  * we avoid exiting the interrupt handler only to generate
4154                  * another one.
4155                  *
4156                  * Note that for MSI this could cause a stray interrupt report
4157                  * if an interrupt landed in the time between writing IIR and
4158                  * the posting read.  This should be rare enough to never
4159                  * trigger the 99% of 100,000 interrupts test for disabling
4160                  * stray interrupts.
4161                  */
4162                 iir = new_iir;
4163         }
4164
4165         enable_rpm_wakeref_asserts(dev_priv);
4166
4167         return ret;
4168 }
4169
4170 static void i965_irq_uninstall(struct drm_device * dev)
4171 {
4172         struct drm_i915_private *dev_priv = to_i915(dev);
4173         int pipe;
4174
4175         if (!dev_priv)
4176                 return;
4177
4178         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4179         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4180
4181         I915_WRITE(HWSTAM, 0xffffffff);
4182         for_each_pipe(dev_priv, pipe)
4183                 I915_WRITE(PIPESTAT(pipe), 0);
4184         I915_WRITE(IMR, 0xffffffff);
4185         I915_WRITE(IER, 0x0);
4186
4187         for_each_pipe(dev_priv, pipe)
4188                 I915_WRITE(PIPESTAT(pipe),
4189                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4190         I915_WRITE(IIR, I915_READ(IIR));
4191 }
4192
4193 /**
4194  * intel_irq_init - initializes irq support
4195  * @dev_priv: i915 device instance
4196  *
4197  * This function initializes all the irq support including work items, timers
4198  * and all the vtables. It does not setup the interrupt itself though.
4199  */
4200 void intel_irq_init(struct drm_i915_private *dev_priv)
4201 {
4202         struct drm_device *dev = &dev_priv->drm;
4203
4204         intel_hpd_init_work(dev_priv);
4205
4206         INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4207         INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4208
4209         if (HAS_GUC_SCHED(dev_priv))
4210                 dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT;
4211
4212         /* Let's track the enabled rps events */
4213         if (IS_VALLEYVIEW(dev_priv))
4214                 /* WaGsvRC0ResidencyMethod:vlv */
4215                 dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED;
4216         else
4217                 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4218
4219         dev_priv->rps.pm_intr_keep = 0;
4220
4221         /*
4222          * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
4223          * if GEN6_PM_UP_EI_EXPIRED is masked.
4224          *
4225          * TODO: verify if this can be reproduced on VLV,CHV.
4226          */
4227         if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
4228                 dev_priv->rps.pm_intr_keep |= GEN6_PM_RP_UP_EI_EXPIRED;
4229
4230         if (INTEL_INFO(dev_priv)->gen >= 8)
4231                 dev_priv->rps.pm_intr_keep |= GEN8_PMINTR_REDIRECT_TO_GUC;
4232
4233         if (IS_GEN2(dev_priv)) {
4234                 /* Gen2 doesn't have a hardware frame counter */
4235                 dev->max_vblank_count = 0;
4236         } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
4237                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4238                 dev->driver->get_vblank_counter = g4x_get_vblank_counter;
4239         } else {
4240                 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4241                 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4242         }
4243
4244         /*
4245          * Opt out of the vblank disable timer on everything except gen2.
4246          * Gen2 doesn't have a hardware frame counter and so depends on
4247          * vblank interrupts to produce sane vblank seuquence numbers.
4248          */
4249         if (!IS_GEN2(dev_priv))
4250                 dev->vblank_disable_immediate = true;
4251
4252         dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4253         dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4254
4255         if (IS_CHERRYVIEW(dev_priv)) {
4256                 dev->driver->irq_handler = cherryview_irq_handler;
4257                 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4258                 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4259                 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4260                 dev->driver->enable_vblank = i965_enable_vblank;
4261                 dev->driver->disable_vblank = i965_disable_vblank;
4262                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4263         } else if (IS_VALLEYVIEW(dev_priv)) {
4264                 dev->driver->irq_handler = valleyview_irq_handler;
4265                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4266                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4267                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4268                 dev->driver->enable_vblank = i965_enable_vblank;
4269                 dev->driver->disable_vblank = i965_disable_vblank;
4270                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4271         } else if (INTEL_INFO(dev_priv)->gen >= 8) {
4272                 dev->driver->irq_handler = gen8_irq_handler;
4273                 dev->driver->irq_preinstall = gen8_irq_reset;
4274                 dev->driver->irq_postinstall = gen8_irq_postinstall;
4275                 dev->driver->irq_uninstall = gen8_irq_uninstall;
4276                 dev->driver->enable_vblank = gen8_enable_vblank;
4277                 dev->driver->disable_vblank = gen8_disable_vblank;
4278                 if (IS_GEN9_LP(dev_priv))
4279                         dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4280                 else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
4281                         dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4282                 else
4283                         dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4284         } else if (HAS_PCH_SPLIT(dev_priv)) {
4285                 dev->driver->irq_handler = ironlake_irq_handler;
4286                 dev->driver->irq_preinstall = ironlake_irq_reset;
4287                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4288                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4289                 dev->driver->enable_vblank = ironlake_enable_vblank;
4290                 dev->driver->disable_vblank = ironlake_disable_vblank;
4291                 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4292         } else {
4293                 if (IS_GEN2(dev_priv)) {
4294                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
4295                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
4296                         dev->driver->irq_handler = i8xx_irq_handler;
4297                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
4298                         dev->driver->enable_vblank = i8xx_enable_vblank;
4299                         dev->driver->disable_vblank = i8xx_disable_vblank;
4300                 } else if (IS_GEN3(dev_priv)) {
4301                         dev->driver->irq_preinstall = i915_irq_preinstall;
4302                         dev->driver->irq_postinstall = i915_irq_postinstall;
4303                         dev->driver->irq_uninstall = i915_irq_uninstall;
4304                         dev->driver->irq_handler = i915_irq_handler;
4305                         dev->driver->enable_vblank = i8xx_enable_vblank;
4306                         dev->driver->disable_vblank = i8xx_disable_vblank;
4307                 } else {
4308                         dev->driver->irq_preinstall = i965_irq_preinstall;
4309                         dev->driver->irq_postinstall = i965_irq_postinstall;
4310                         dev->driver->irq_uninstall = i965_irq_uninstall;
4311                         dev->driver->irq_handler = i965_irq_handler;
4312                         dev->driver->enable_vblank = i965_enable_vblank;
4313                         dev->driver->disable_vblank = i965_disable_vblank;
4314                 }
4315                 if (I915_HAS_HOTPLUG(dev_priv))
4316                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4317         }
4318 }
4319
4320 /**
4321  * intel_irq_install - enables the hardware interrupt
4322  * @dev_priv: i915 device instance
4323  *
4324  * This function enables the hardware interrupt handling, but leaves the hotplug
4325  * handling still disabled. It is called after intel_irq_init().
4326  *
4327  * In the driver load and resume code we need working interrupts in a few places
4328  * but don't want to deal with the hassle of concurrent probe and hotplug
4329  * workers. Hence the split into this two-stage approach.
4330  */
4331 int intel_irq_install(struct drm_i915_private *dev_priv)
4332 {
4333         /*
4334          * We enable some interrupt sources in our postinstall hooks, so mark
4335          * interrupts as enabled _before_ actually enabling them to avoid
4336          * special cases in our ordering checks.
4337          */
4338         dev_priv->pm.irqs_enabled = true;
4339
4340         return drm_irq_install(&dev_priv->drm, dev_priv->drm.pdev->irq);
4341 }
4342
4343 /**
4344  * intel_irq_uninstall - finilizes all irq handling
4345  * @dev_priv: i915 device instance
4346  *
4347  * This stops interrupt and hotplug handling and unregisters and frees all
4348  * resources acquired in the init functions.
4349  */
4350 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4351 {
4352         drm_irq_uninstall(&dev_priv->drm);
4353         intel_hpd_cancel_work(dev_priv);
4354         dev_priv->pm.irqs_enabled = false;
4355 }
4356
4357 /**
4358  * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4359  * @dev_priv: i915 device instance
4360  *
4361  * This function is used to disable interrupts at runtime, both in the runtime
4362  * pm and the system suspend/resume code.
4363  */
4364 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4365 {
4366         dev_priv->drm.driver->irq_uninstall(&dev_priv->drm);
4367         dev_priv->pm.irqs_enabled = false;
4368         synchronize_irq(dev_priv->drm.irq);
4369 }
4370
4371 /**
4372  * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4373  * @dev_priv: i915 device instance
4374  *
4375  * This function is used to enable interrupts at runtime, both in the runtime
4376  * pm and the system suspend/resume code.
4377  */
4378 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4379 {
4380         dev_priv->pm.irqs_enabled = true;
4381         dev_priv->drm.driver->irq_preinstall(&dev_priv->drm);
4382         dev_priv->drm.driver->irq_postinstall(&dev_priv->drm);
4383 }