drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include <linux/circ_buf.h>
  34 #include <drm/drmP.h>
  35 #include <drm/i915_drm.h>
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "intel_drv.h"
  39
  40 /**
  41  * DOC: interrupt handling
  42  *
  43  * These functions provide the basic support for enabling and disabling the
  44  * interrupt handling support. There's a lot more functionality in i915_irq.c
  45  * and related files, but that will be described in separate chapters.
  46  */
  47
  48 static const u32 hpd_ilk[HPD_NUM_PINS] = {
  49         [HPD_PORT_A] = DE_DP_A_HOTPLUG,
  50 };
  51
  52 static const u32 hpd_ivb[HPD_NUM_PINS] = {
  53         [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
  54 };
  55
  56 static const u32 hpd_bdw[HPD_NUM_PINS] = {
  57         [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
  58 };
  59
  60 static const u32 hpd_ibx[HPD_NUM_PINS] = {
  61         [HPD_CRT] = SDE_CRT_HOTPLUG,
  62         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
  63         [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
  64         [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
  65         [HPD_PORT_D] = SDE_PORTD_HOTPLUG
  66 };
  67
  68 static const u32 hpd_cpt[HPD_NUM_PINS] = {
  69         [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
  70         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
  71         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  72         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  73         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
  74 };
  75
  76 static const u32 hpd_spt[HPD_NUM_PINS] = {
  77         [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
  78         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  79         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  80         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
  81         [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT
  82 };
  83
  84 static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
  85         [HPD_CRT] = CRT_HOTPLUG_INT_EN,
  86         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
  87         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
  88         [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
  89         [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
  90         [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
  91 };
  92
  93 static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
  94         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  95         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
  96         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
  97         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  98         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  99         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
 100 };
 101
 102 static const u32 hpd_status_i915[HPD_NUM_PINS] = {
 103         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
 104         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
 105         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
 106         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
 107         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
 108         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
 109 };
 110
 111 /* BXT hpd list */
 112 static const u32 hpd_bxt[HPD_NUM_PINS] = {
 113         [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
 114         [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
 115         [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
 116 };
 117
 118 /* IIR can theoretically queue up two events. Be paranoid. */
 119 #define GEN8_IRQ_RESET_NDX(type, which) do { \
 120         I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
 121         POSTING_READ(GEN8_##type##_IMR(which)); \
 122         I915_WRITE(GEN8_##type##_IER(which), 0); \
 123         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
 124         POSTING_READ(GEN8_##type##_IIR(which)); \
 125         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
 126         POSTING_READ(GEN8_##type##_IIR(which)); \
 127 } while (0)
 128
 129 #define GEN5_IRQ_RESET(type) do { \
 130         I915_WRITE(type##IMR, 0xffffffff); \
 131         POSTING_READ(type##IMR); \
 132         I915_WRITE(type##IER, 0); \
 133         I915_WRITE(type##IIR, 0xffffffff); \
 134         POSTING_READ(type##IIR); \
 135         I915_WRITE(type##IIR, 0xffffffff); \
 136         POSTING_READ(type##IIR); \
 137 } while (0)
 138
 139 /*
 140  * We should clear IMR at preinstall/uninstall, and just check at postinstall.
 141  */
 142 static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv,
 143                                     i915_reg_t reg)
 144 {
 145         u32 val = I915_READ(reg);
 146
 147         if (val == 0)
 148                 return;
 149
 150         WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
 151              i915_mmio_reg_offset(reg), val);
 152         I915_WRITE(reg, 0xffffffff);
 153         POSTING_READ(reg);
 154         I915_WRITE(reg, 0xffffffff);
 155         POSTING_READ(reg);
 156 }
 157
 158 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
 159         gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
 160         I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
 161         I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
 162         POSTING_READ(GEN8_##type##_IMR(which)); \
 163 } while (0)
 164
 165 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
 166         gen5_assert_iir_is_zero(dev_priv, type##IIR); \
 167         I915_WRITE(type##IER, (ier_val)); \
 168         I915_WRITE(type##IMR, (imr_val)); \
 169         POSTING_READ(type##IMR); \
 170 } while (0)
 171
 172 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
 173 static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
 174
 175 /* For display hotplug interrupt */
 176 static inline void
 177 i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
 178                                      uint32_t mask,
 179                                      uint32_t bits)
 180 {
 181         uint32_t val;
 182
 183         assert_spin_locked(&dev_priv->irq_lock);
 184         WARN_ON(bits & ~mask);
 185
 186         val = I915_READ(PORT_HOTPLUG_EN);
 187         val &= ~mask;
 188         val |= bits;
 189         I915_WRITE(PORT_HOTPLUG_EN, val);
 190 }
 191
 192 /**
 193  * i915_hotplug_interrupt_update - update hotplug interrupt enable
 194  * @dev_priv: driver private
 195  * @mask: bits to update
 196  * @bits: bits to enable
 197  * NOTE: the HPD enable bits are modified both inside and outside
 198  * of an interrupt context. To avoid that read-modify-write cycles
 199  * interfer, these bits are protected by a spinlock. Since this
 200  * function is usually not called from a context where the lock is
 201  * held already, this function acquires the lock itself. A non-locking
 202  * version is also available.
 203  */
 204 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
 205                                    uint32_t mask,
 206                                    uint32_t bits)
 207 {
 208         spin_lock_irq(&dev_priv->irq_lock);
 209         i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
 210         spin_unlock_irq(&dev_priv->irq_lock);
 211 }
 212
 213 /**
 214  * ilk_update_display_irq - update DEIMR
 215  * @dev_priv: driver private
 216  * @interrupt_mask: mask of interrupt bits to update
 217  * @enabled_irq_mask: mask of interrupt bits to enable
 218  */
 219 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
 220                             uint32_t interrupt_mask,
 221                             uint32_t enabled_irq_mask)
 222 {
 223         uint32_t new_val;
 224
 225         assert_spin_locked(&dev_priv->irq_lock);
 226
 227         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 228
 229         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 230                 return;
 231
 232         new_val = dev_priv->irq_mask;
 233         new_val &= ~interrupt_mask;
 234         new_val |= (~enabled_irq_mask & interrupt_mask);
 235
 236         if (new_val != dev_priv->irq_mask) {
 237                 dev_priv->irq_mask = new_val;
 238                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 239                 POSTING_READ(DEIMR);
 240         }
 241 }
 242
 243 /**
 244  * ilk_update_gt_irq - update GTIMR
 245  * @dev_priv: driver private
 246  * @interrupt_mask: mask of interrupt bits to update
 247  * @enabled_irq_mask: mask of interrupt bits to enable
 248  */
 249 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
 250                               uint32_t interrupt_mask,
 251                               uint32_t enabled_irq_mask)
 252 {
 253         assert_spin_locked(&dev_priv->irq_lock);
 254
 255         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 256
 257         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 258                 return;
 259
 260         dev_priv->gt_irq_mask &= ~interrupt_mask;
 261         dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
 262         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 263 }
 264
 265 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 266 {
 267         ilk_update_gt_irq(dev_priv, mask, mask);
 268         POSTING_READ_FW(GTIMR);
 269 }
 270
 271 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 272 {
 273         ilk_update_gt_irq(dev_priv, mask, 0);
 274 }
 275
 276 static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
 277 {
 278         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
 279 }
 280
 281 static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
 282 {
 283         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
 284 }
 285
 286 static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
 287 {
 288         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
 289 }
 290
 291 /**
 292  * snb_update_pm_irq - update GEN6_PMIMR
 293  * @dev_priv: driver private
 294  * @interrupt_mask: mask of interrupt bits to update
 295  * @enabled_irq_mask: mask of interrupt bits to enable
 296  */
 297 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
 298                               uint32_t interrupt_mask,
 299                               uint32_t enabled_irq_mask)
 300 {
 301         uint32_t new_val;
 302
 303         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 304
 305         assert_spin_locked(&dev_priv->irq_lock);
 306
 307         new_val = dev_priv->pm_imr;
 308         new_val &= ~interrupt_mask;
 309         new_val |= (~enabled_irq_mask & interrupt_mask);
 310
 311         if (new_val != dev_priv->pm_imr) {
 312                 dev_priv->pm_imr = new_val;
 313                 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_imr);
 314                 POSTING_READ(gen6_pm_imr(dev_priv));
 315         }
 316 }
 317
 318 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
 319 {
 320         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 321                 return;
 322
 323         snb_update_pm_irq(dev_priv, mask, mask);
 324 }
 325
 326 static void __gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
 327 {
 328         snb_update_pm_irq(dev_priv, mask, 0);
 329 }
 330
 331 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
 332 {
 333         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 334                 return;
 335
 336         __gen6_mask_pm_irq(dev_priv, mask);
 337 }
 338
 339 void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
 340 {
 341         i915_reg_t reg = gen6_pm_iir(dev_priv);
 342
 343         assert_spin_locked(&dev_priv->irq_lock);
 344
 345         I915_WRITE(reg, reset_mask);
 346         I915_WRITE(reg, reset_mask);
 347         POSTING_READ(reg);
 348 }
 349
 350 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask)
 351 {
 352         assert_spin_locked(&dev_priv->irq_lock);
 353
 354         dev_priv->pm_ier |= enable_mask;
 355         I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier);
 356         gen6_unmask_pm_irq(dev_priv, enable_mask);
 357         /* unmask_pm_irq provides an implicit barrier (POSTING_READ) */
 358 }
 359
 360 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask)
 361 {
 362         assert_spin_locked(&dev_priv->irq_lock);
 363
 364         dev_priv->pm_ier &= ~disable_mask;
 365         __gen6_mask_pm_irq(dev_priv, disable_mask);
 366         I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier);
 367         /* though a barrier is missing here, but don't really need a one */
 368 }
 369
 370 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
 371 {
 372         spin_lock_irq(&dev_priv->irq_lock);
 373         gen6_reset_pm_iir(dev_priv, dev_priv->pm_rps_events);
 374         dev_priv->rps.pm_iir = 0;
 375         spin_unlock_irq(&dev_priv->irq_lock);
 376 }
 377
 378 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
 379 {
 380         if (READ_ONCE(dev_priv->rps.interrupts_enabled))
 381                 return;
 382
 383         spin_lock_irq(&dev_priv->irq_lock);
 384         WARN_ON_ONCE(dev_priv->rps.pm_iir);
 385         WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
 386         dev_priv->rps.interrupts_enabled = true;
 387         gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
 388
 389         spin_unlock_irq(&dev_priv->irq_lock);
 390 }
 391
 392 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
 393 {
 394         return (mask & ~dev_priv->rps.pm_intr_keep);
 395 }
 396
 397 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
 398 {
 399         if (!READ_ONCE(dev_priv->rps.interrupts_enabled))
 400                 return;
 401
 402         spin_lock_irq(&dev_priv->irq_lock);
 403         dev_priv->rps.interrupts_enabled = false;
 404
 405         I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0u));
 406
 407         gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
 408
 409         spin_unlock_irq(&dev_priv->irq_lock);
 410         synchronize_irq(dev_priv->drm.irq);
 411
 412         /* Now that we will not be generating any more work, flush any
 413          * outsanding tasks. As we are called on the RPS idle path,
 414          * we will reset the GPU to minimum frequencies, so the current
 415          * state of the worker can be discarded.
 416          */
 417         cancel_work_sync(&dev_priv->rps.work);
 418         gen6_reset_rps_interrupts(dev_priv);
 419 }
 420
 421 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
 422 {
 423         spin_lock_irq(&dev_priv->irq_lock);
 424         gen6_reset_pm_iir(dev_priv, dev_priv->pm_guc_events);
 425         spin_unlock_irq(&dev_priv->irq_lock);
 426 }
 427
 428 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
 429 {
 430         spin_lock_irq(&dev_priv->irq_lock);
 431         if (!dev_priv->guc.interrupts_enabled) {
 432                 WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
 433                                        dev_priv->pm_guc_events);
 434                 dev_priv->guc.interrupts_enabled = true;
 435                 gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events);
 436         }
 437         spin_unlock_irq(&dev_priv->irq_lock);
 438 }
 439
 440 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
 441 {
 442         spin_lock_irq(&dev_priv->irq_lock);
 443         dev_priv->guc.interrupts_enabled = false;
 444
 445         gen6_disable_pm_irq(dev_priv, dev_priv->pm_guc_events);
 446
 447         spin_unlock_irq(&dev_priv->irq_lock);
 448         synchronize_irq(dev_priv->drm.irq);
 449
 450         gen9_reset_guc_interrupts(dev_priv);
 451 }
 452
 453 /**
 454  * bdw_update_port_irq - update DE port interrupt
 455  * @dev_priv: driver private
 456  * @interrupt_mask: mask of interrupt bits to update
 457  * @enabled_irq_mask: mask of interrupt bits to enable
 458  */
 459 static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
 460                                 uint32_t interrupt_mask,
 461                                 uint32_t enabled_irq_mask)
 462 {
 463         uint32_t new_val;
 464         uint32_t old_val;
 465
 466         assert_spin_locked(&dev_priv->irq_lock);
 467
 468         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 469
 470         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 471                 return;
 472
 473         old_val = I915_READ(GEN8_DE_PORT_IMR);
 474
 475         new_val = old_val;
 476         new_val &= ~interrupt_mask;
 477         new_val |= (~enabled_irq_mask & interrupt_mask);
 478
 479         if (new_val != old_val) {
 480                 I915_WRITE(GEN8_DE_PORT_IMR, new_val);
 481                 POSTING_READ(GEN8_DE_PORT_IMR);
 482         }
 483 }
 484
 485 /**
 486  * bdw_update_pipe_irq - update DE pipe interrupt
 487  * @dev_priv: driver private
 488  * @pipe: pipe whose interrupt to update
 489  * @interrupt_mask: mask of interrupt bits to update
 490  * @enabled_irq_mask: mask of interrupt bits to enable
 491  */
 492 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
 493                          enum pipe pipe,
 494                          uint32_t interrupt_mask,
 495                          uint32_t enabled_irq_mask)
 496 {
 497         uint32_t new_val;
 498
 499         assert_spin_locked(&dev_priv->irq_lock);
 500
 501         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 502
 503         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 504                 return;
 505
 506         new_val = dev_priv->de_irq_mask[pipe];
 507         new_val &= ~interrupt_mask;
 508         new_val |= (~enabled_irq_mask & interrupt_mask);
 509
 510         if (new_val != dev_priv->de_irq_mask[pipe]) {
 511                 dev_priv->de_irq_mask[pipe] = new_val;
 512                 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
 513                 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
 514         }
 515 }
 516
 517 /**
 518  * ibx_display_interrupt_update - update SDEIMR
 519  * @dev_priv: driver private
 520  * @interrupt_mask: mask of interrupt bits to update
 521  * @enabled_irq_mask: mask of interrupt bits to enable
 522  */
 523 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
 524                                   uint32_t interrupt_mask,
 525                                   uint32_t enabled_irq_mask)
 526 {
 527         uint32_t sdeimr = I915_READ(SDEIMR);
 528         sdeimr &= ~interrupt_mask;
 529         sdeimr |= (~enabled_irq_mask & interrupt_mask);
 530
 531         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 532
 533         assert_spin_locked(&dev_priv->irq_lock);
 534
 535         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 536                 return;
 537
 538         I915_WRITE(SDEIMR, sdeimr);
 539         POSTING_READ(SDEIMR);
 540 }
 541
 542 static void
 543 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 544                        u32 enable_mask, u32 status_mask)
 545 {
 546         i915_reg_t reg = PIPESTAT(pipe);
 547         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 548
 549         assert_spin_locked(&dev_priv->irq_lock);
 550         WARN_ON(!intel_irqs_enabled(dev_priv));
 551
 552         if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 553                       status_mask & ~PIPESTAT_INT_STATUS_MASK,
 554                       "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
 555                       pipe_name(pipe), enable_mask, status_mask))
 556                 return;
 557
 558         if ((pipestat & enable_mask) == enable_mask)
 559                 return;
 560
 561         dev_priv->pipestat_irq_mask[pipe] |= status_mask;
 562
 563         /* Enable the interrupt, clear any pending status */
 564         pipestat |= enable_mask | status_mask;
 565         I915_WRITE(reg, pipestat);
 566         POSTING_READ(reg);
 567 }
 568
 569 static void
 570 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 571                         u32 enable_mask, u32 status_mask)
 572 {
 573         i915_reg_t reg = PIPESTAT(pipe);
 574         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 575
 576         assert_spin_locked(&dev_priv->irq_lock);
 577         WARN_ON(!intel_irqs_enabled(dev_priv));
 578
 579         if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 580                       status_mask & ~PIPESTAT_INT_STATUS_MASK,
 581                       "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
 582                       pipe_name(pipe), enable_mask, status_mask))
 583                 return;
 584
 585         if ((pipestat & enable_mask) == 0)
 586                 return;
 587
 588         dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
 589
 590         pipestat &= ~enable_mask;
 591         I915_WRITE(reg, pipestat);
 592         POSTING_READ(reg);
 593 }
 594
 595 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
 596 {
 597         u32 enable_mask = status_mask << 16;
 598
 599         /*
 600          * On pipe A we don't support the PSR interrupt yet,
 601          * on pipe B and C the same bit MBZ.
 602          */
 603         if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
 604                 return 0;
 605         /*
 606          * On pipe B and C we don't support the PSR interrupt yet, on pipe
 607          * A the same bit is for perf counters which we don't use either.
 608          */
 609         if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
 610                 return 0;
 611
 612         enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
 613                          SPRITE0_FLIP_DONE_INT_EN_VLV |
 614                          SPRITE1_FLIP_DONE_INT_EN_VLV);
 615         if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
 616                 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
 617         if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
 618                 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
 619
 620         return enable_mask;
 621 }
 622
 623 void
 624 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 625                      u32 status_mask)
 626 {
 627         u32 enable_mask;
 628
 629         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 630                 enable_mask = vlv_get_pipestat_enable_mask(&dev_priv->drm,
 631                                                            status_mask);
 632         else
 633                 enable_mask = status_mask << 16;
 634         __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 635 }
 636
 637 void
 638 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 639                       u32 status_mask)
 640 {
 641         u32 enable_mask;
 642
 643         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 644                 enable_mask = vlv_get_pipestat_enable_mask(&dev_priv->drm,
 645                                                            status_mask);
 646         else
 647                 enable_mask = status_mask << 16;
 648         __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 649 }
 650
 651 /**
 652  * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
 653  * @dev_priv: i915 device private
 654  */
 655 static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
 656 {
 657         if (!dev_priv->opregion.asle || !IS_MOBILE(dev_priv))
 658                 return;
 659
 660         spin_lock_irq(&dev_priv->irq_lock);
 661
 662         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
 663         if (INTEL_GEN(dev_priv) >= 4)
 664                 i915_enable_pipestat(dev_priv, PIPE_A,
 665                                      PIPE_LEGACY_BLC_EVENT_STATUS);
 666
 667         spin_unlock_irq(&dev_priv->irq_lock);
 668 }
 669
 670 /*
 671  * This timing diagram depicts the video signal in and
 672  * around the vertical blanking period.
 673  *
 674  * Assumptions about the fictitious mode used in this example:
 675  *  vblank_start >= 3
 676  *  vsync_start = vblank_start + 1
 677  *  vsync_end = vblank_start + 2
 678  *  vtotal = vblank_start + 3
 679  *
 680  *           start of vblank:
 681  *           latch double buffered registers
 682  *           increment frame counter (ctg+)
 683  *           generate start of vblank interrupt (gen4+)
 684  *           |
 685  *           |          frame start:
 686  *           |          generate frame start interrupt (aka. vblank interrupt) (gmch)
 687  *           |          may be shifted forward 1-3 extra lines via PIPECONF
 688  *           |          |
 689  *           |          |  start of vsync:
 690  *           |          |  generate vsync interrupt
 691  *           |          |  |
 692  * ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx
 693  *       .   \hs/   .      \hs/          \hs/          \hs/   .      \hs/
 694  * ----va---> <-----------------vb--------------------> <--------va-------------
 695  *       |          |       <----vs----->                     |
 696  * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
 697  * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
 698  * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
 699  *       |          |                                         |
 700  *       last visible pixel                                   first visible pixel
 701  *                  |                                         increment frame counter (gen3/4)
 702  *                  pixel counter = vblank_start * htotal     pixel counter = 0 (gen3/4)
 703  *
 704  * x  = horizontal active
 705  * _  = horizontal blanking
 706  * hs = horizontal sync
 707  * va = vertical active
 708  * vb = vertical blanking
 709  * vs = vertical sync
 710  * vbs = vblank_start (number)
 711  *
 712  * Summary:
 713  * - most events happen at the start of horizontal sync
 714  * - frame start happens at the start of horizontal blank, 1-4 lines
 715  *   (depending on PIPECONF settings) after the start of vblank
 716  * - gen3/4 pixel and frame counter are synchronized with the start
 717  *   of horizontal active on the first line of vertical active
 718  */
 719
 720 /* Called from drm generic code, passed a 'crtc', which
 721  * we use as a pipe index
 722  */
 723 static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
 724 {
 725         struct drm_i915_private *dev_priv = to_i915(dev);
 726         i915_reg_t high_frame, low_frame;
 727         u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
 728         struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
 729                                                                 pipe);
 730         const struct drm_display_mode *mode = &intel_crtc->base.hwmode;
 731
 732         htotal = mode->crtc_htotal;
 733         hsync_start = mode->crtc_hsync_start;
 734         vbl_start = mode->crtc_vblank_start;
 735         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 736                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 737
 738         /* Convert to pixel count */
 739         vbl_start *= htotal;
 740
 741         /* Start of vblank event occurs at start of hsync */
 742         vbl_start -= htotal - hsync_start;
 743
 744         high_frame = PIPEFRAME(pipe);
 745         low_frame = PIPEFRAMEPIXEL(pipe);
 746
 747         /*
 748          * High & low register fields aren't synchronized, so make sure
 749          * we get a low value that's stable across two reads of the high
 750          * register.
 751          */
 752         do {
 753                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 754                 low   = I915_READ(low_frame);
 755                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 756         } while (high1 != high2);
 757
 758         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 759         pixel = low & PIPE_PIXEL_MASK;
 760         low >>= PIPE_FRAME_LOW_SHIFT;
 761
 762         /*
 763          * The frame counter increments at beginning of active.
 764          * Cook up a vblank counter by also checking the pixel
 765          * counter against vblank start.
 766          */
 767         return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
 768 }
 769
 770 static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
 771 {
 772         struct drm_i915_private *dev_priv = to_i915(dev);
 773
 774         return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
 775 }
 776
 777 /* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
 778 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
 779 {
 780         struct drm_device *dev = crtc->base.dev;
 781         struct drm_i915_private *dev_priv = to_i915(dev);
 782         const struct drm_display_mode *mode = &crtc->base.hwmode;
 783         enum pipe pipe = crtc->pipe;
 784         int position, vtotal;
 785
 786         vtotal = mode->crtc_vtotal;
 787         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 788                 vtotal /= 2;
 789
 790         if (IS_GEN2(dev_priv))
 791                 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
 792         else
 793                 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
 794
 795         /*
 796          * On HSW, the DSL reg (0x70000) appears to return 0 if we
 797          * read it just before the start of vblank.  So try it again
 798          * so we don't accidentally end up spanning a vblank frame
 799          * increment, causing the pipe_update_end() code to squak at us.
 800          *
 801          * The nature of this problem means we can't simply check the ISR
 802          * bit and return the vblank start value; nor can we use the scanline
 803          * debug register in the transcoder as it appears to have the same
 804          * problem.  We may need to extend this to include other platforms,
 805          * but so far testing only shows the problem on HSW.
 806          */
 807         if (HAS_DDI(dev_priv) && !position) {
 808                 int i, temp;
 809
 810                 for (i = 0; i < 100; i++) {
 811                         udelay(1);
 812                         temp = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) &
 813                                 DSL_LINEMASK_GEN3;
 814                         if (temp != position) {
 815                                 position = temp;
 816                                 break;
 817                         }
 818                 }
 819         }
 820
 821         /*
 822          * See update_scanline_offset() for the details on the
 823          * scanline_offset adjustment.
 824          */
 825         return (position + crtc->scanline_offset) % vtotal;
 826 }
 827
 828 static int i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
 829                                     unsigned int flags, int *vpos, int *hpos,
 830                                     ktime_t *stime, ktime_t *etime,
 831                                     const struct drm_display_mode *mode)
 832 {
 833         struct drm_i915_private *dev_priv = to_i915(dev);
 834         struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
 835                                                                 pipe);
 836         int position;
 837         int vbl_start, vbl_end, hsync_start, htotal, vtotal;
 838         bool in_vbl = true;
 839         int ret = 0;
 840         unsigned long irqflags;
 841
 842         if (WARN_ON(!mode->crtc_clock)) {
 843                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 844                                  "pipe %c\n", pipe_name(pipe));
 845                 return 0;
 846         }
 847
 848         htotal = mode->crtc_htotal;
 849         hsync_start = mode->crtc_hsync_start;
 850         vtotal = mode->crtc_vtotal;
 851         vbl_start = mode->crtc_vblank_start;
 852         vbl_end = mode->crtc_vblank_end;
 853
 854         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 855                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 856                 vbl_end /= 2;
 857                 vtotal /= 2;
 858         }
 859
 860         ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 861
 862         /*
 863          * Lock uncore.lock, as we will do multiple timing critical raw
 864          * register reads, potentially with preemption disabled, so the
 865          * following code must not block on uncore.lock.
 866          */
 867         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 868
 869         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 870
 871         /* Get optional system timestamp before query. */
 872         if (stime)
 873                 *stime = ktime_get();
 874
 875         if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
 876                 /* No obvious pixelcount register. Only query vertical
 877                  * scanout position from Display scan line register.
 878                  */
 879                 position = __intel_get_crtc_scanline(intel_crtc);
 880         } else {
 881                 /* Have access to pixelcount since start of frame.
 882                  * We can split this into vertical and horizontal
 883                  * scanout position.
 884                  */
 885                 position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 886
 887                 /* convert to pixel counts */
 888                 vbl_start *= htotal;
 889                 vbl_end *= htotal;
 890                 vtotal *= htotal;
 891
 892                 /*
 893                  * In interlaced modes, the pixel counter counts all pixels,
 894                  * so one field will have htotal more pixels. In order to avoid
 895                  * the reported position from jumping backwards when the pixel
 896                  * counter is beyond the length of the shorter field, just
 897                  * clamp the position the length of the shorter field. This
 898                  * matches how the scanline counter based position works since
 899                  * the scanline counter doesn't count the two half lines.
 900                  */
 901                 if (position >= vtotal)
 902                         position = vtotal - 1;
 903
 904                 /*
 905                  * Start of vblank interrupt is triggered at start of hsync,
 906                  * just prior to the first active line of vblank. However we
 907                  * consider lines to start at the leading edge of horizontal
 908                  * active. So, should we get here before we've crossed into
 909                  * the horizontal active of the first line in vblank, we would
 910                  * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
 911                  * always add htotal-hsync_start to the current pixel position.
 912                  */
 913                 position = (position + htotal - hsync_start) % vtotal;
 914         }
 915
 916         /* Get optional system timestamp after query. */
 917         if (etime)
 918                 *etime = ktime_get();
 919
 920         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 921
 922         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 923
 924         in_vbl = position >= vbl_start && position < vbl_end;
 925
 926         /*
 927          * While in vblank, position will be negative
 928          * counting up towards 0 at vbl_end. And outside
 929          * vblank, position will be positive counting
 930          * up since vbl_end.
 931          */
 932         if (position >= vbl_start)
 933                 position -= vbl_end;
 934         else
 935                 position += vtotal - vbl_end;
 936
 937         if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
 938                 *vpos = position;
 939                 *hpos = 0;
 940         } else {
 941                 *vpos = position / htotal;
 942                 *hpos = position - (*vpos * htotal);
 943         }
 944
 945         /* In vblank? */
 946         if (in_vbl)
 947                 ret |= DRM_SCANOUTPOS_IN_VBLANK;
 948
 949         return ret;
 950 }
 951
 952 int intel_get_crtc_scanline(struct intel_crtc *crtc)
 953 {
 954         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 955         unsigned long irqflags;
 956         int position;
 957
 958         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 959         position = __intel_get_crtc_scanline(crtc);
 960         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 961
 962         return position;
 963 }
 964
 965 static int i915_get_vblank_timestamp(struct drm_device *dev, unsigned int pipe,
 966                               int *max_error,
 967                               struct timeval *vblank_time,
 968                               unsigned flags)
 969 {
 970         struct drm_i915_private *dev_priv = to_i915(dev);
 971         struct intel_crtc *crtc;
 972
 973         if (pipe >= INTEL_INFO(dev_priv)->num_pipes) {
 974                 DRM_ERROR("Invalid crtc %u\n", pipe);
 975                 return -EINVAL;
 976         }
 977
 978         /* Get drm_crtc to timestamp: */
 979         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
 980         if (crtc == NULL) {
 981                 DRM_ERROR("Invalid crtc %u\n", pipe);
 982                 return -EINVAL;
 983         }
 984
 985         if (!crtc->base.hwmode.crtc_clock) {
 986                 DRM_DEBUG_KMS("crtc %u is disabled\n", pipe);
 987                 return -EBUSY;
 988         }
 989
 990         /* Helper routine in DRM core does all the work: */
 991         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 992                                                      vblank_time, flags,
 993                                                      &crtc->base.hwmode);
 994 }
 995
 996 static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv)
 997 {
 998         u32 busy_up, busy_down, max_avg, min_avg;
 999         u8 new_delay;
1000
1001         spin_lock(&mchdev_lock);
1002
1003         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
1004
1005         new_delay = dev_priv->ips.cur_delay;
1006
1007         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
1008         busy_up = I915_READ(RCPREVBSYTUPAVG);
1009         busy_down = I915_READ(RCPREVBSYTDNAVG);
1010         max_avg = I915_READ(RCBMAXAVG);
1011         min_avg = I915_READ(RCBMINAVG);
1012
1013         /* Handle RCS change request from hw */
1014         if (busy_up > max_avg) {
1015                 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
1016                         new_delay = dev_priv->ips.cur_delay - 1;
1017                 if (new_delay < dev_priv->ips.max_delay)
1018                         new_delay = dev_priv->ips.max_delay;
1019         } else if (busy_down < min_avg) {
1020                 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
1021                         new_delay = dev_priv->ips.cur_delay + 1;
1022                 if (new_delay > dev_priv->ips.min_delay)
1023                         new_delay = dev_priv->ips.min_delay;
1024         }
1025
1026         if (ironlake_set_drps(dev_priv, new_delay))
1027                 dev_priv->ips.cur_delay = new_delay;
1028
1029         spin_unlock(&mchdev_lock);
1030
1031         return;
1032 }
1033
1034 static void notify_ring(struct intel_engine_cs *engine)
1035 {
1036         smp_store_mb(engine->breadcrumbs.irq_posted, true);
1037         if (intel_engine_wakeup(engine))
1038                 trace_i915_gem_request_notify(engine);
1039 }
1040
1041 static void vlv_c0_read(struct drm_i915_private *dev_priv,
1042                         struct intel_rps_ei *ei)
1043 {
1044         ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
1045         ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
1046         ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
1047 }
1048
1049 static bool vlv_c0_above(struct drm_i915_private *dev_priv,
1050                          const struct intel_rps_ei *old,
1051                          const struct intel_rps_ei *now,
1052                          int threshold)
1053 {
1054         u64 time, c0;
1055         unsigned int mul = 100;
1056
1057         if (old->cz_clock == 0)
1058                 return false;
1059
1060         if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
1061                 mul <<= 8;
1062
1063         time = now->cz_clock - old->cz_clock;
1064         time *= threshold * dev_priv->czclk_freq;
1065
1066         /* Workload can be split between render + media, e.g. SwapBuffers
1067          * being blitted in X after being rendered in mesa. To account for
1068          * this we need to combine both engines into our activity counter.
1069          */
1070         c0 = now->render_c0 - old->render_c0;
1071         c0 += now->media_c0 - old->media_c0;
1072         c0 *= mul * VLV_CZ_CLOCK_TO_MILLI_SEC;
1073
1074         return c0 >= time;
1075 }
1076
1077 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
1078 {
1079         vlv_c0_read(dev_priv, &dev_priv->rps.down_ei);
1080         dev_priv->rps.up_ei = dev_priv->rps.down_ei;
1081 }
1082
1083 static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
1084 {
1085         struct intel_rps_ei now;
1086         u32 events = 0;
1087
1088         if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0)
1089                 return 0;
1090
1091         vlv_c0_read(dev_priv, &now);
1092         if (now.cz_clock == 0)
1093                 return 0;
1094
1095         if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) {
1096                 if (!vlv_c0_above(dev_priv,
1097                                   &dev_priv->rps.down_ei, &now,
1098                                   dev_priv->rps.down_threshold))
1099                         events |= GEN6_PM_RP_DOWN_THRESHOLD;
1100                 dev_priv->rps.down_ei = now;
1101         }
1102
1103         if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
1104                 if (vlv_c0_above(dev_priv,
1105                                  &dev_priv->rps.up_ei, &now,
1106                                  dev_priv->rps.up_threshold))
1107                         events |= GEN6_PM_RP_UP_THRESHOLD;
1108                 dev_priv->rps.up_ei = now;
1109         }
1110
1111         return events;
1112 }
1113
1114 static bool any_waiters(struct drm_i915_private *dev_priv)
1115 {
1116         struct intel_engine_cs *engine;
1117         enum intel_engine_id id;
1118
1119         for_each_engine(engine, dev_priv, id)
1120                 if (intel_engine_has_waiter(engine))
1121                         return true;
1122
1123         return false;
1124 }
1125
1126 static void gen6_pm_rps_work(struct work_struct *work)
1127 {
1128         struct drm_i915_private *dev_priv =
1129                 container_of(work, struct drm_i915_private, rps.work);
1130         bool client_boost;
1131         int new_delay, adj, min, max;
1132         u32 pm_iir;
1133
1134         spin_lock_irq(&dev_priv->irq_lock);
1135         /* Speed up work cancelation during disabling rps interrupts. */
1136         if (!dev_priv->rps.interrupts_enabled) {
1137                 spin_unlock_irq(&dev_priv->irq_lock);
1138                 return;
1139         }
1140
1141         pm_iir = dev_priv->rps.pm_iir;
1142         dev_priv->rps.pm_iir = 0;
1143         /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1144         gen6_unmask_pm_irq(dev_priv, dev_priv->pm_rps_events);
1145         client_boost = dev_priv->rps.client_boost;
1146         dev_priv->rps.client_boost = false;
1147         spin_unlock_irq(&dev_priv->irq_lock);
1148
1149         /* Make sure we didn't queue anything we're not going to process. */
1150         WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1151
1152         if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
1153                 return;
1154
1155         mutex_lock(&dev_priv->rps.hw_lock);
1156
1157         pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
1158
1159         adj = dev_priv->rps.last_adj;
1160         new_delay = dev_priv->rps.cur_freq;
1161         min = dev_priv->rps.min_freq_softlimit;
1162         max = dev_priv->rps.max_freq_softlimit;
1163         if (client_boost || any_waiters(dev_priv))
1164                 max = dev_priv->rps.max_freq;
1165         if (client_boost && new_delay < dev_priv->rps.boost_freq) {
1166                 new_delay = dev_priv->rps.boost_freq;
1167                 adj = 0;
1168         } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1169                 if (adj > 0)
1170                         adj *= 2;
1171                 else /* CHV needs even encode values */
1172                         adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
1173                 /*
1174                  * For better performance, jump directly
1175                  * to RPe if we're below it.
1176                  */
1177                 if (new_delay < dev_priv->rps.efficient_freq - adj) {
1178                         new_delay = dev_priv->rps.efficient_freq;
1179                         adj = 0;
1180                 }
1181         } else if (client_boost || any_waiters(dev_priv)) {
1182                 adj = 0;
1183         } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1184                 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1185                         new_delay = dev_priv->rps.efficient_freq;
1186                 else
1187                         new_delay = dev_priv->rps.min_freq_softlimit;
1188                 adj = 0;
1189         } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1190                 if (adj < 0)
1191                         adj *= 2;
1192                 else /* CHV needs even encode values */
1193                         adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
1194         } else { /* unknown event */
1195                 adj = 0;
1196         }
1197
1198         dev_priv->rps.last_adj = adj;
1199
1200         /* sysfs frequency interfaces may have snuck in while servicing the
1201          * interrupt
1202          */
1203         new_delay += adj;
1204         new_delay = clamp_t(int, new_delay, min, max);
1205
1206         intel_set_rps(dev_priv, new_delay);
1207
1208         mutex_unlock(&dev_priv->rps.hw_lock);
1209 }
1210
1211
1212 /**
1213  * ivybridge_parity_work - Workqueue called when a parity error interrupt
1214  * occurred.
1215  * @work: workqueue struct
1216  *
1217  * Doesn't actually do anything except notify userspace. As a consequence of
1218  * this event, userspace should try to remap the bad rows since statistically
1219  * it is likely the same row is more likely to go bad again.
1220  */
1221 static void ivybridge_parity_work(struct work_struct *work)
1222 {
1223         struct drm_i915_private *dev_priv =
1224                 container_of(work, struct drm_i915_private, l3_parity.error_work);
1225         u32 error_status, row, bank, subbank;
1226         char *parity_event[6];
1227         uint32_t misccpctl;
1228         uint8_t slice = 0;
1229
1230         /* We must turn off DOP level clock gating to access the L3 registers.
1231          * In order to prevent a get/put style interface, acquire struct mutex
1232          * any time we access those registers.
1233          */
1234         mutex_lock(&dev_priv->drm.struct_mutex);
1235
1236         /* If we've screwed up tracking, just let the interrupt fire again */
1237         if (WARN_ON(!dev_priv->l3_parity.which_slice))
1238                 goto out;
1239
1240         misccpctl = I915_READ(GEN7_MISCCPCTL);
1241         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1242         POSTING_READ(GEN7_MISCCPCTL);
1243
1244         while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1245                 i915_reg_t reg;
1246
1247                 slice--;
1248                 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv)))
1249                         break;
1250
1251                 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1252
1253                 reg = GEN7_L3CDERRST1(slice);
1254
1255                 error_status = I915_READ(reg);
1256                 row = GEN7_PARITY_ERROR_ROW(error_status);
1257                 bank = GEN7_PARITY_ERROR_BANK(error_status);
1258                 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1259
1260                 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1261                 POSTING_READ(reg);
1262
1263                 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1264                 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1265                 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1266                 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1267                 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1268                 parity_event[5] = NULL;
1269
1270                 kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj,
1271                                    KOBJ_CHANGE, parity_event);
1272
1273                 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1274                           slice, row, bank, subbank);
1275
1276                 kfree(parity_event[4]);
1277                 kfree(parity_event[3]);
1278                 kfree(parity_event[2]);
1279                 kfree(parity_event[1]);
1280         }
1281
1282         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1283
1284 out:
1285         WARN_ON(dev_priv->l3_parity.which_slice);
1286         spin_lock_irq(&dev_priv->irq_lock);
1287         gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1288         spin_unlock_irq(&dev_priv->irq_lock);
1289
1290         mutex_unlock(&dev_priv->drm.struct_mutex);
1291 }
1292
1293 static void ivybridge_parity_error_irq_handler(struct drm_i915_private *dev_priv,
1294                                                u32 iir)
1295 {
1296         if (!HAS_L3_DPF(dev_priv))
1297                 return;
1298
1299         spin_lock(&dev_priv->irq_lock);
1300         gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1301         spin_unlock(&dev_priv->irq_lock);
1302
1303         iir &= GT_PARITY_ERROR(dev_priv);
1304         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1305                 dev_priv->l3_parity.which_slice |= 1 << 1;
1306
1307         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1308                 dev_priv->l3_parity.which_slice |= 1 << 0;
1309
1310         queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1311 }
1312
1313 static void ilk_gt_irq_handler(struct drm_i915_private *dev_priv,
1314                                u32 gt_iir)
1315 {
1316         if (gt_iir & GT_RENDER_USER_INTERRUPT)
1317                 notify_ring(dev_priv->engine[RCS]);
1318         if (gt_iir & ILK_BSD_USER_INTERRUPT)
1319                 notify_ring(dev_priv->engine[VCS]);
1320 }
1321
1322 static void snb_gt_irq_handler(struct drm_i915_private *dev_priv,
1323                                u32 gt_iir)
1324 {
1325         if (gt_iir & GT_RENDER_USER_INTERRUPT)
1326                 notify_ring(dev_priv->engine[RCS]);
1327         if (gt_iir & GT_BSD_USER_INTERRUPT)
1328                 notify_ring(dev_priv->engine[VCS]);
1329         if (gt_iir & GT_BLT_USER_INTERRUPT)
1330                 notify_ring(dev_priv->engine[BCS]);
1331
1332         if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1333                       GT_BSD_CS_ERROR_INTERRUPT |
1334                       GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1335                 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1336
1337         if (gt_iir & GT_PARITY_ERROR(dev_priv))
1338                 ivybridge_parity_error_irq_handler(dev_priv, gt_iir);
1339 }
1340
1341 static __always_inline void
1342 gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift)
1343 {
1344         if (iir & (GT_RENDER_USER_INTERRUPT << test_shift))
1345                 notify_ring(engine);
1346         if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift))
1347                 tasklet_schedule(&engine->irq_tasklet);
1348 }
1349
1350 static irqreturn_t gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
1351                                    u32 master_ctl,
1352                                    u32 gt_iir[4])
1353 {
1354         irqreturn_t ret = IRQ_NONE;
1355
1356         if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1357                 gt_iir[0] = I915_READ_FW(GEN8_GT_IIR(0));
1358                 if (gt_iir[0]) {
1359                         I915_WRITE_FW(GEN8_GT_IIR(0), gt_iir[0]);
1360                         ret = IRQ_HANDLED;
1361                 } else
1362                         DRM_ERROR("The master control interrupt lied (GT0)!\n");
1363         }
1364
1365         if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1366                 gt_iir[1] = I915_READ_FW(GEN8_GT_IIR(1));
1367                 if (gt_iir[1]) {
1368                         I915_WRITE_FW(GEN8_GT_IIR(1), gt_iir[1]);
1369                         ret = IRQ_HANDLED;
1370                 } else
1371                         DRM_ERROR("The master control interrupt lied (GT1)!\n");
1372         }
1373
1374         if (master_ctl & GEN8_GT_VECS_IRQ) {
1375                 gt_iir[3] = I915_READ_FW(GEN8_GT_IIR(3));
1376                 if (gt_iir[3]) {
1377                         I915_WRITE_FW(GEN8_GT_IIR(3), gt_iir[3]);
1378                         ret = IRQ_HANDLED;
1379                 } else
1380                         DRM_ERROR("The master control interrupt lied (GT3)!\n");
1381         }
1382
1383         if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
1384                 gt_iir[2] = I915_READ_FW(GEN8_GT_IIR(2));
1385                 if (gt_iir[2] & (dev_priv->pm_rps_events |
1386                                  dev_priv->pm_guc_events)) {
1387                         I915_WRITE_FW(GEN8_GT_IIR(2),
1388                                       gt_iir[2] & (dev_priv->pm_rps_events |
1389                                                    dev_priv->pm_guc_events));
1390                         ret = IRQ_HANDLED;
1391                 } else
1392                         DRM_ERROR("The master control interrupt lied (PM)!\n");
1393         }
1394
1395         return ret;
1396 }
1397
1398 static void gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
1399                                 u32 gt_iir[4])
1400 {
1401         if (gt_iir[0]) {
1402                 gen8_cs_irq_handler(dev_priv->engine[RCS],
1403                                     gt_iir[0], GEN8_RCS_IRQ_SHIFT);
1404                 gen8_cs_irq_handler(dev_priv->engine[BCS],
1405                                     gt_iir[0], GEN8_BCS_IRQ_SHIFT);
1406         }
1407
1408         if (gt_iir[1]) {
1409                 gen8_cs_irq_handler(dev_priv->engine[VCS],
1410                                     gt_iir[1], GEN8_VCS1_IRQ_SHIFT);
1411                 gen8_cs_irq_handler(dev_priv->engine[VCS2],
1412                                     gt_iir[1], GEN8_VCS2_IRQ_SHIFT);
1413         }
1414
1415         if (gt_iir[3])
1416                 gen8_cs_irq_handler(dev_priv->engine[VECS],
1417                                     gt_iir[3], GEN8_VECS_IRQ_SHIFT);
1418
1419         if (gt_iir[2] & dev_priv->pm_rps_events)
1420                 gen6_rps_irq_handler(dev_priv, gt_iir[2]);
1421
1422         if (gt_iir[2] & dev_priv->pm_guc_events)
1423                 gen9_guc_irq_handler(dev_priv, gt_iir[2]);
1424 }
1425
1426 static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
1427 {
1428         switch (port) {
1429         case PORT_A:
1430                 return val & PORTA_HOTPLUG_LONG_DETECT;
1431         case PORT_B:
1432                 return val & PORTB_HOTPLUG_LONG_DETECT;
1433         case PORT_C:
1434                 return val & PORTC_HOTPLUG_LONG_DETECT;
1435         default:
1436                 return false;
1437         }
1438 }
1439
1440 static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
1441 {
1442         switch (port) {
1443         case PORT_E:
1444                 return val & PORTE_HOTPLUG_LONG_DETECT;
1445         default:
1446                 return false;
1447         }
1448 }
1449
1450 static bool spt_port_hotplug_long_detect(enum port port, u32 val)
1451 {
1452         switch (port) {
1453         case PORT_A:
1454                 return val & PORTA_HOTPLUG_LONG_DETECT;
1455         case PORT_B:
1456                 return val & PORTB_HOTPLUG_LONG_DETECT;
1457         case PORT_C:
1458                 return val & PORTC_HOTPLUG_LONG_DETECT;
1459         case PORT_D:
1460                 return val & PORTD_HOTPLUG_LONG_DETECT;
1461         default:
1462                 return false;
1463         }
1464 }
1465
1466 static bool ilk_port_hotplug_long_detect(enum port port, u32 val)
1467 {
1468         switch (port) {
1469         case PORT_A:
1470                 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
1471         default:
1472                 return false;
1473         }
1474 }
1475
1476 static bool pch_port_hotplug_long_detect(enum port port, u32 val)
1477 {
1478         switch (port) {
1479         case PORT_B:
1480                 return val & PORTB_HOTPLUG_LONG_DETECT;
1481         case PORT_C:
1482                 return val & PORTC_HOTPLUG_LONG_DETECT;
1483         case PORT_D:
1484                 return val & PORTD_HOTPLUG_LONG_DETECT;
1485         default:
1486                 return false;
1487         }
1488 }
1489
1490 static bool i9xx_port_hotplug_long_detect(enum port port, u32 val)
1491 {
1492         switch (port) {
1493         case PORT_B:
1494                 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1495         case PORT_C:
1496                 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1497         case PORT_D:
1498                 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1499         default:
1500                 return false;
1501         }
1502 }
1503
1504 /*
1505  * Get a bit mask of pins that have triggered, and which ones may be long.
1506  * This can be called multiple times with the same masks to accumulate
1507  * hotplug detection results from several registers.
1508  *
1509  * Note that the caller is expected to zero out the masks initially.
1510  */
1511 static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
1512                              u32 hotplug_trigger, u32 dig_hotplug_reg,
1513                              const u32 hpd[HPD_NUM_PINS],
1514                              bool long_pulse_detect(enum port port, u32 val))
1515 {
1516         enum port port;
1517         int i;
1518
1519         for_each_hpd_pin(i) {
1520                 if ((hpd[i] & hotplug_trigger) == 0)
1521                         continue;
1522
1523                 *pin_mask |= BIT(i);
1524
1525                 if (!intel_hpd_pin_to_port(i, &port))
1526                         continue;
1527
1528                 if (long_pulse_detect(port, dig_hotplug_reg))
1529                         *long_mask |= BIT(i);
1530         }
1531
1532         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
1533                          hotplug_trigger, dig_hotplug_reg, *pin_mask);
1534
1535 }
1536
1537 static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
1538 {
1539         wake_up_all(&dev_priv->gmbus_wait_queue);
1540 }
1541
1542 static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
1543 {
1544         wake_up_all(&dev_priv->gmbus_wait_queue);
1545 }
1546
1547 #if defined(CONFIG_DEBUG_FS)
1548 static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1549                                          enum pipe pipe,
1550                                          uint32_t crc0, uint32_t crc1,
1551                                          uint32_t crc2, uint32_t crc3,
1552                                          uint32_t crc4)
1553 {
1554         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1555         struct intel_pipe_crc_entry *entry;
1556         int head, tail;
1557
1558         spin_lock(&pipe_crc->lock);
1559
1560         if (!pipe_crc->entries) {
1561                 spin_unlock(&pipe_crc->lock);
1562                 DRM_DEBUG_KMS("spurious interrupt\n");
1563                 return;
1564         }
1565
1566         head = pipe_crc->head;
1567         tail = pipe_crc->tail;
1568
1569         if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1570                 spin_unlock(&pipe_crc->lock);
1571                 DRM_ERROR("CRC buffer overflowing\n");
1572                 return;
1573         }
1574
1575         entry = &pipe_crc->entries[head];
1576
1577         entry->frame = dev_priv->drm.driver->get_vblank_counter(&dev_priv->drm,
1578                                                                  pipe);
1579         entry->crc[0] = crc0;
1580         entry->crc[1] = crc1;
1581         entry->crc[2] = crc2;
1582         entry->crc[3] = crc3;
1583         entry->crc[4] = crc4;
1584
1585         head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1586         pipe_crc->head = head;
1587
1588         spin_unlock(&pipe_crc->lock);
1589
1590         wake_up_interruptible(&pipe_crc->wq);
1591 }
1592 #else
1593 static inline void
1594 display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1595                              enum pipe pipe,
1596                              uint32_t crc0, uint32_t crc1,
1597                              uint32_t crc2, uint32_t crc3,
1598                              uint32_t crc4) {}
1599 #endif
1600
1601
1602 static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1603                                      enum pipe pipe)
1604 {
1605         display_pipe_crc_irq_handler(dev_priv, pipe,
1606                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1607                                      0, 0, 0, 0);
1608 }
1609
1610 static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1611                                      enum pipe pipe)
1612 {
1613         display_pipe_crc_irq_handler(dev_priv, pipe,
1614                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1615                                      I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1616                                      I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1617                                      I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1618                                      I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1619 }
1620
1621 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1622                                       enum pipe pipe)
1623 {
1624         uint32_t res1, res2;
1625
1626         if (INTEL_GEN(dev_priv) >= 3)
1627                 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1628         else
1629                 res1 = 0;
1630
1631         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1632                 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1633         else
1634                 res2 = 0;
1635
1636         display_pipe_crc_irq_handler(dev_priv, pipe,
1637                                      I915_READ(PIPE_CRC_RES_RED(pipe)),
1638                                      I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1639                                      I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1640                                      res1, res2);
1641 }
1642
1643 /* The RPS events need forcewake, so we add them to a work queue and mask their
1644  * IMR bits until the work is done. Other interrupts can be processed without
1645  * the work queue. */
1646 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1647 {
1648         if (pm_iir & dev_priv->pm_rps_events) {
1649                 spin_lock(&dev_priv->irq_lock);
1650                 gen6_mask_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1651                 if (dev_priv->rps.interrupts_enabled) {
1652                         dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1653                         schedule_work(&dev_priv->rps.work);
1654                 }
1655                 spin_unlock(&dev_priv->irq_lock);
1656         }
1657
1658         if (INTEL_INFO(dev_priv)->gen >= 8)
1659                 return;
1660
1661         if (HAS_VEBOX(dev_priv)) {
1662                 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1663                         notify_ring(dev_priv->engine[VECS]);
1664
1665                 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1666                         DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
1667         }
1668 }
1669
1670 static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir)
1671 {
1672         if (gt_iir & GEN9_GUC_TO_HOST_INT_EVENT) {
1673                 /* Sample the log buffer flush related bits & clear them out now
1674                  * itself from the message identity register to minimize the
1675                  * probability of losing a flush interrupt, when there are back
1676                  * to back flush interrupts.
1677                  * There can be a new flush interrupt, for different log buffer
1678                  * type (like for ISR), whilst Host is handling one (for DPC).
1679                  * Since same bit is used in message register for ISR & DPC, it
1680                  * could happen that GuC sets the bit for 2nd interrupt but Host
1681                  * clears out the bit on handling the 1st interrupt.
1682                  */
1683                 u32 msg, flush;
1684
1685                 msg = I915_READ(SOFT_SCRATCH(15));
1686                 flush = msg & (GUC2HOST_MSG_CRASH_DUMP_POSTED |
1687                                GUC2HOST_MSG_FLUSH_LOG_BUFFER);
1688                 if (flush) {
1689                         /* Clear the message bits that are handled */
1690                         I915_WRITE(SOFT_SCRATCH(15), msg & ~flush);
1691
1692                         /* Handle flush interrupt in bottom half */
1693                         queue_work(dev_priv->guc.log.flush_wq,
1694                                    &dev_priv->guc.log.flush_work);
1695
1696                         dev_priv->guc.log.flush_interrupt_count++;
1697                 } else {
1698                         /* Not clearing of unhandled event bits won't result in
1699                          * re-triggering of the interrupt.
1700                          */
1701                 }
1702         }
1703 }
1704
1705 static bool intel_pipe_handle_vblank(struct drm_i915_private *dev_priv,
1706                                      enum pipe pipe)
1707 {
1708         bool ret;
1709
1710         ret = drm_handle_vblank(&dev_priv->drm, pipe);
1711         if (ret)
1712                 intel_finish_page_flip_mmio(dev_priv, pipe);
1713
1714         return ret;
1715 }
1716
1717 static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv,
1718                                         u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1719 {
1720         int pipe;
1721
1722         spin_lock(&dev_priv->irq_lock);
1723
1724         if (!dev_priv->display_irqs_enabled) {
1725                 spin_unlock(&dev_priv->irq_lock);
1726                 return;
1727         }
1728
1729         for_each_pipe(dev_priv, pipe) {
1730                 i915_reg_t reg;
1731                 u32 mask, iir_bit = 0;
1732
1733                 /*
1734                  * PIPESTAT bits get signalled even when the interrupt is
1735                  * disabled with the mask bits, and some of the status bits do
1736                  * not generate interrupts at all (like the underrun bit). Hence
1737                  * we need to be careful that we only handle what we want to
1738                  * handle.
1739                  */
1740
1741                 /* fifo underruns are filterered in the underrun handler. */
1742                 mask = PIPE_FIFO_UNDERRUN_STATUS;
1743
1744                 switch (pipe) {
1745                 case PIPE_A:
1746                         iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1747                         break;
1748                 case PIPE_B:
1749                         iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1750                         break;
1751                 case PIPE_C:
1752                         iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1753                         break;
1754                 }
1755                 if (iir & iir_bit)
1756                         mask |= dev_priv->pipestat_irq_mask[pipe];
1757
1758                 if (!mask)
1759                         continue;
1760
1761                 reg = PIPESTAT(pipe);
1762                 mask |= PIPESTAT_INT_ENABLE_MASK;
1763                 pipe_stats[pipe] = I915_READ(reg) & mask;
1764
1765                 /*
1766                  * Clear the PIPE*STAT regs before the IIR
1767                  */
1768                 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1769                                         PIPESTAT_INT_STATUS_MASK))
1770                         I915_WRITE(reg, pipe_stats[pipe]);
1771         }
1772         spin_unlock(&dev_priv->irq_lock);
1773 }
1774
1775 static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1776                                             u32 pipe_stats[I915_MAX_PIPES])
1777 {
1778         enum pipe pipe;
1779
1780         for_each_pipe(dev_priv, pipe) {
1781                 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
1782                     intel_pipe_handle_vblank(dev_priv, pipe))
1783                         intel_check_page_flip(dev_priv, pipe);
1784
1785                 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV)
1786                         intel_finish_page_flip_cs(dev_priv, pipe);
1787
1788                 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1789                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1790
1791                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1792                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1793         }
1794
1795         if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1796                 gmbus_irq_handler(dev_priv);
1797 }
1798
1799 static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
1800 {
1801         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1802
1803         if (hotplug_status)
1804                 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1805
1806         return hotplug_status;
1807 }
1808
1809 static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1810                                  u32 hotplug_status)
1811 {
1812         u32 pin_mask = 0, long_mask = 0;
1813
1814         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
1815             IS_CHERRYVIEW(dev_priv)) {
1816                 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1817
1818                 if (hotplug_trigger) {
1819                         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1820                                            hotplug_trigger, hpd_status_g4x,
1821                                            i9xx_port_hotplug_long_detect);
1822
1823                         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1824                 }
1825
1826                 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1827                         dp_aux_irq_handler(dev_priv);
1828         } else {
1829                 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1830
1831                 if (hotplug_trigger) {
1832                         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1833                                            hotplug_trigger, hpd_status_i915,
1834                                            i9xx_port_hotplug_long_detect);
1835                         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1836                 }
1837         }
1838 }
1839
1840 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1841 {
1842         struct drm_device *dev = arg;
1843         struct drm_i915_private *dev_priv = to_i915(dev);
1844         irqreturn_t ret = IRQ_NONE;
1845
1846         if (!intel_irqs_enabled(dev_priv))
1847                 return IRQ_NONE;
1848
1849         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1850         disable_rpm_wakeref_asserts(dev_priv);
1851
1852         do {
1853                 u32 iir, gt_iir, pm_iir;
1854                 u32 pipe_stats[I915_MAX_PIPES] = {};
1855                 u32 hotplug_status = 0;
1856                 u32 ier = 0;
1857
1858                 gt_iir = I915_READ(GTIIR);
1859                 pm_iir = I915_READ(GEN6_PMIIR);
1860                 iir = I915_READ(VLV_IIR);
1861
1862                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1863                         break;
1864
1865                 ret = IRQ_HANDLED;
1866
1867                 /*
1868                  * Theory on interrupt generation, based on empirical evidence:
1869                  *
1870                  * x = ((VLV_IIR & VLV_IER) ||
1871                  *      (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
1872                  *       (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
1873                  *
1874                  * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1875                  * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
1876                  * guarantee the CPU interrupt will be raised again even if we
1877                  * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
1878                  * bits this time around.
1879                  */
1880                 I915_WRITE(VLV_MASTER_IER, 0);
1881                 ier = I915_READ(VLV_IER);
1882                 I915_WRITE(VLV_IER, 0);
1883
1884                 if (gt_iir)
1885                         I915_WRITE(GTIIR, gt_iir);
1886                 if (pm_iir)
1887                         I915_WRITE(GEN6_PMIIR, pm_iir);
1888
1889                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1890                         hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1891
1892                 /* Call regardless, as some status bits might not be
1893                  * signalled in iir */
1894                 valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1895
1896                 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
1897                            I915_LPE_PIPE_B_INTERRUPT))
1898                         intel_lpe_audio_irq_handler(dev_priv);
1899
1900                 /*
1901                  * VLV_IIR is single buffered, and reflects the level
1902                  * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1903                  */
1904                 if (iir)
1905                         I915_WRITE(VLV_IIR, iir);
1906
1907                 I915_WRITE(VLV_IER, ier);
1908                 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1909                 POSTING_READ(VLV_MASTER_IER);
1910
1911                 if (gt_iir)
1912                         snb_gt_irq_handler(dev_priv, gt_iir);
1913                 if (pm_iir)
1914                         gen6_rps_irq_handler(dev_priv, pm_iir);
1915
1916                 if (hotplug_status)
1917                         i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1918
1919                 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1920         } while (0);
1921
1922         enable_rpm_wakeref_asserts(dev_priv);
1923
1924         return ret;
1925 }
1926
1927 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1928 {
1929         struct drm_device *dev = arg;
1930         struct drm_i915_private *dev_priv = to_i915(dev);
1931         irqreturn_t ret = IRQ_NONE;
1932
1933         if (!intel_irqs_enabled(dev_priv))
1934                 return IRQ_NONE;
1935
1936         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1937         disable_rpm_wakeref_asserts(dev_priv);
1938
1939         do {
1940                 u32 master_ctl, iir;
1941                 u32 gt_iir[4] = {};
1942                 u32 pipe_stats[I915_MAX_PIPES] = {};
1943                 u32 hotplug_status = 0;
1944                 u32 ier = 0;
1945
1946                 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1947                 iir = I915_READ(VLV_IIR);
1948
1949                 if (master_ctl == 0 && iir == 0)
1950                         break;
1951
1952                 ret = IRQ_HANDLED;
1953
1954                 /*
1955                  * Theory on interrupt generation, based on empirical evidence:
1956                  *
1957                  * x = ((VLV_IIR & VLV_IER) ||
1958                  *      ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
1959                  *       (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
1960                  *
1961                  * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1962                  * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
1963                  * guarantee the CPU interrupt will be raised again even if we
1964                  * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
1965                  * bits this time around.
1966                  */
1967                 I915_WRITE(GEN8_MASTER_IRQ, 0);
1968                 ier = I915_READ(VLV_IER);
1969                 I915_WRITE(VLV_IER, 0);
1970
1971                 gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
1972
1973                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1974                         hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1975
1976                 /* Call regardless, as some status bits might not be
1977                  * signalled in iir */
1978                 valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1979
1980                 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
1981                            I915_LPE_PIPE_B_INTERRUPT |
1982                            I915_LPE_PIPE_C_INTERRUPT))
1983                         intel_lpe_audio_irq_handler(dev_priv);
1984
1985                 /*
1986                  * VLV_IIR is single buffered, and reflects the level
1987                  * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1988                  */
1989                 if (iir)
1990                         I915_WRITE(VLV_IIR, iir);
1991
1992                 I915_WRITE(VLV_IER, ier);
1993                 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
1994                 POSTING_READ(GEN8_MASTER_IRQ);
1995
1996                 gen8_gt_irq_handler(dev_priv, gt_iir);
1997
1998                 if (hotplug_status)
1999                         i9xx_hpd_irq_handler(dev_priv, hotplug_status);
2000
2001                 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
2002         } while (0);
2003
2004         enable_rpm_wakeref_asserts(dev_priv);
2005
2006         return ret;
2007 }
2008
2009 static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
2010                                 u32 hotplug_trigger,
2011                                 const u32 hpd[HPD_NUM_PINS])
2012 {
2013         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2014
2015         /*
2016          * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
2017          * unless we touch the hotplug register, even if hotplug_trigger is
2018          * zero. Not acking leads to "The master control interrupt lied (SDE)!"
2019          * errors.
2020          */
2021         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2022         if (!hotplug_trigger) {
2023                 u32 mask = PORTA_HOTPLUG_STATUS_MASK |
2024                         PORTD_HOTPLUG_STATUS_MASK |
2025                         PORTC_HOTPLUG_STATUS_MASK |
2026                         PORTB_HOTPLUG_STATUS_MASK;
2027                 dig_hotplug_reg &= ~mask;
2028         }
2029
2030         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2031         if (!hotplug_trigger)
2032                 return;
2033
2034         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2035                            dig_hotplug_reg, hpd,
2036                            pch_port_hotplug_long_detect);
2037
2038         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2039 }
2040
2041 static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2042 {
2043         int pipe;
2044         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
2045
2046         ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ibx);
2047
2048         if (pch_iir & SDE_AUDIO_POWER_MASK) {
2049                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
2050                                SDE_AUDIO_POWER_SHIFT);
2051                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
2052                                  port_name(port));
2053         }
2054
2055         if (pch_iir & SDE_AUX_MASK)
2056                 dp_aux_irq_handler(dev_priv);
2057
2058         if (pch_iir & SDE_GMBUS)
2059                 gmbus_irq_handler(dev_priv);
2060
2061         if (pch_iir & SDE_AUDIO_HDCP_MASK)
2062                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
2063
2064         if (pch_iir & SDE_AUDIO_TRANS_MASK)
2065                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
2066
2067         if (pch_iir & SDE_POISON)
2068                 DRM_ERROR("PCH poison interrupt\n");
2069
2070         if (pch_iir & SDE_FDI_MASK)
2071                 for_each_pipe(dev_priv, pipe)
2072                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
2073                                          pipe_name(pipe),
2074                                          I915_READ(FDI_RX_IIR(pipe)));
2075
2076         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
2077                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
2078
2079         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
2080                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
2081
2082         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
2083                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
2084
2085         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
2086                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2087 }
2088
2089 static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
2090 {
2091         u32 err_int = I915_READ(GEN7_ERR_INT);
2092         enum pipe pipe;
2093
2094         if (err_int & ERR_INT_POISON)
2095                 DRM_ERROR("Poison interrupt\n");
2096
2097         for_each_pipe(dev_priv, pipe) {
2098                 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
2099                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2100
2101                 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
2102                         if (IS_IVYBRIDGE(dev_priv))
2103                                 ivb_pipe_crc_irq_handler(dev_priv, pipe);
2104                         else
2105                                 hsw_pipe_crc_irq_handler(dev_priv, pipe);
2106                 }
2107         }
2108
2109         I915_WRITE(GEN7_ERR_INT, err_int);
2110 }
2111
2112 static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
2113 {
2114         u32 serr_int = I915_READ(SERR_INT);
2115
2116         if (serr_int & SERR_INT_POISON)
2117                 DRM_ERROR("PCH poison interrupt\n");
2118
2119         if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
2120                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
2121
2122         if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
2123                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2124
2125         if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
2126                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
2127
2128         I915_WRITE(SERR_INT, serr_int);
2129 }
2130
2131 static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2132 {
2133         int pipe;
2134         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2135
2136         ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_cpt);
2137
2138         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2139                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2140                                SDE_AUDIO_POWER_SHIFT_CPT);
2141                 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2142                                  port_name(port));
2143         }
2144
2145         if (pch_iir & SDE_AUX_MASK_CPT)
2146                 dp_aux_irq_handler(dev_priv);
2147
2148         if (pch_iir & SDE_GMBUS_CPT)
2149                 gmbus_irq_handler(dev_priv);
2150
2151         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2152                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2153
2154         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2155                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2156
2157         if (pch_iir & SDE_FDI_MASK_CPT)
2158                 for_each_pipe(dev_priv, pipe)
2159                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
2160                                          pipe_name(pipe),
2161                                          I915_READ(FDI_RX_IIR(pipe)));
2162
2163         if (pch_iir & SDE_ERROR_CPT)
2164                 cpt_serr_int_handler(dev_priv);
2165 }
2166
2167 static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2168 {
2169         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
2170                 ~SDE_PORTE_HOTPLUG_SPT;
2171         u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
2172         u32 pin_mask = 0, long_mask = 0;
2173
2174         if (hotplug_trigger) {
2175                 u32 dig_hotplug_reg;
2176
2177                 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2178                 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2179
2180                 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2181                                    dig_hotplug_reg, hpd_spt,
2182                                    spt_port_hotplug_long_detect);
2183         }
2184
2185         if (hotplug2_trigger) {
2186                 u32 dig_hotplug_reg;
2187
2188                 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
2189                 I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
2190
2191                 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger,
2192                                    dig_hotplug_reg, hpd_spt,
2193                                    spt_port_hotplug2_long_detect);
2194         }
2195
2196         if (pin_mask)
2197                 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2198
2199         if (pch_iir & SDE_GMBUS_CPT)
2200                 gmbus_irq_handler(dev_priv);
2201 }
2202
2203 static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
2204                                 u32 hotplug_trigger,
2205                                 const u32 hpd[HPD_NUM_PINS])
2206 {
2207         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2208
2209         dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
2210         I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
2211
2212         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2213                            dig_hotplug_reg, hpd,
2214                            ilk_port_hotplug_long_detect);
2215
2216         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2217 }
2218
2219 static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
2220                                     u32 de_iir)
2221 {
2222         enum pipe pipe;
2223         u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
2224
2225         if (hotplug_trigger)
2226                 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk);
2227
2228         if (de_iir & DE_AUX_CHANNEL_A)
2229                 dp_aux_irq_handler(dev_priv);
2230
2231         if (de_iir & DE_GSE)
2232                 intel_opregion_asle_intr(dev_priv);
2233
2234         if (de_iir & DE_POISON)
2235                 DRM_ERROR("Poison interrupt\n");
2236
2237         for_each_pipe(dev_priv, pipe) {
2238                 if (de_iir & DE_PIPE_VBLANK(pipe) &&
2239                     intel_pipe_handle_vblank(dev_priv, pipe))
2240                         intel_check_page_flip(dev_priv, pipe);
2241
2242                 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2243                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2244
2245                 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2246                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2247
2248                 /* plane/pipes map 1:1 on ilk+ */
2249                 if (de_iir & DE_PLANE_FLIP_DONE(pipe))
2250                         intel_finish_page_flip_cs(dev_priv, pipe);
2251         }
2252
2253         /* check event from PCH */
2254         if (de_iir & DE_PCH_EVENT) {
2255                 u32 pch_iir = I915_READ(SDEIIR);
2256
2257                 if (HAS_PCH_CPT(dev_priv))
2258                         cpt_irq_handler(dev_priv, pch_iir);
2259                 else
2260                         ibx_irq_handler(dev_priv, pch_iir);
2261
2262                 /* should clear PCH hotplug event before clear CPU irq */
2263                 I915_WRITE(SDEIIR, pch_iir);
2264         }
2265
2266         if (IS_GEN5(dev_priv) && de_iir & DE_PCU_EVENT)
2267                 ironlake_rps_change_irq_handler(dev_priv);
2268 }
2269
2270 static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
2271                                     u32 de_iir)
2272 {
2273         enum pipe pipe;
2274         u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2275
2276         if (hotplug_trigger)
2277                 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb);
2278
2279         if (de_iir & DE_ERR_INT_IVB)
2280                 ivb_err_int_handler(dev_priv);
2281
2282         if (de_iir & DE_AUX_CHANNEL_A_IVB)
2283                 dp_aux_irq_handler(dev_priv);
2284
2285         if (de_iir & DE_GSE_IVB)
2286                 intel_opregion_asle_intr(dev_priv);
2287
2288         for_each_pipe(dev_priv, pipe) {
2289                 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
2290                     intel_pipe_handle_vblank(dev_priv, pipe))
2291                         intel_check_page_flip(dev_priv, pipe);
2292
2293                 /* plane/pipes map 1:1 on ilk+ */
2294                 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe))
2295                         intel_finish_page_flip_cs(dev_priv, pipe);
2296         }
2297
2298         /* check event from PCH */
2299         if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
2300                 u32 pch_iir = I915_READ(SDEIIR);
2301
2302                 cpt_irq_handler(dev_priv, pch_iir);
2303
2304                 /* clear PCH hotplug event before clear CPU irq */
2305                 I915_WRITE(SDEIIR, pch_iir);
2306         }
2307 }
2308
2309 /*
2310  * To handle irqs with the minimum potential races with fresh interrupts, we:
2311  * 1 - Disable Master Interrupt Control.
2312  * 2 - Find the source(s) of the interrupt.
2313  * 3 - Clear the Interrupt Identity bits (IIR).
2314  * 4 - Process the interrupt(s) that had bits set in the IIRs.
2315  * 5 - Re-enable Master Interrupt Control.
2316  */
2317 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2318 {
2319         struct drm_device *dev = arg;
2320         struct drm_i915_private *dev_priv = to_i915(dev);
2321         u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2322         irqreturn_t ret = IRQ_NONE;
2323
2324         if (!intel_irqs_enabled(dev_priv))
2325                 return IRQ_NONE;
2326
2327         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2328         disable_rpm_wakeref_asserts(dev_priv);
2329
2330         /* disable master interrupt before clearing iir  */
2331         de_ier = I915_READ(DEIER);
2332         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2333         POSTING_READ(DEIER);
2334
2335         /* Disable south interrupts. We'll only write to SDEIIR once, so further
2336          * interrupts will will be stored on its back queue, and then we'll be
2337          * able to process them after we restore SDEIER (as soon as we restore
2338          * it, we'll get an interrupt if SDEIIR still has something to process
2339          * due to its back queue). */
2340         if (!HAS_PCH_NOP(dev_priv)) {
2341                 sde_ier = I915_READ(SDEIER);
2342                 I915_WRITE(SDEIER, 0);
2343                 POSTING_READ(SDEIER);
2344         }
2345
2346         /* Find, clear, then process each source of interrupt */
2347
2348         gt_iir = I915_READ(GTIIR);
2349         if (gt_iir) {
2350                 I915_WRITE(GTIIR, gt_iir);
2351                 ret = IRQ_HANDLED;
2352                 if (INTEL_GEN(dev_priv) >= 6)
2353                         snb_gt_irq_handler(dev_priv, gt_iir);
2354                 else
2355                         ilk_gt_irq_handler(dev_priv, gt_iir);
2356         }
2357
2358         de_iir = I915_READ(DEIIR);
2359         if (de_iir) {
2360                 I915_WRITE(DEIIR, de_iir);
2361                 ret = IRQ_HANDLED;
2362                 if (INTEL_GEN(dev_priv) >= 7)
2363                         ivb_display_irq_handler(dev_priv, de_iir);
2364                 else
2365                         ilk_display_irq_handler(dev_priv, de_iir);
2366         }
2367
2368         if (INTEL_GEN(dev_priv) >= 6) {
2369                 u32 pm_iir = I915_READ(GEN6_PMIIR);
2370                 if (pm_iir) {
2371                         I915_WRITE(GEN6_PMIIR, pm_iir);
2372                         ret = IRQ_HANDLED;
2373                         gen6_rps_irq_handler(dev_priv, pm_iir);
2374                 }
2375         }
2376
2377         I915_WRITE(DEIER, de_ier);
2378         POSTING_READ(DEIER);
2379         if (!HAS_PCH_NOP(dev_priv)) {
2380                 I915_WRITE(SDEIER, sde_ier);
2381                 POSTING_READ(SDEIER);
2382         }
2383
2384         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2385         enable_rpm_wakeref_asserts(dev_priv);
2386
2387         return ret;
2388 }
2389
2390 static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
2391                                 u32 hotplug_trigger,
2392                                 const u32 hpd[HPD_NUM_PINS])
2393 {
2394         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2395
2396         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2397         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2398
2399         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2400                            dig_hotplug_reg, hpd,
2401                            bxt_port_hotplug_long_detect);
2402
2403         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2404 }
2405
2406 static irqreturn_t
2407 gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2408 {
2409         irqreturn_t ret = IRQ_NONE;
2410         u32 iir;
2411         enum pipe pipe;
2412
2413         if (master_ctl & GEN8_DE_MISC_IRQ) {
2414                 iir = I915_READ(GEN8_DE_MISC_IIR);
2415                 if (iir) {
2416                         I915_WRITE(GEN8_DE_MISC_IIR, iir);
2417                         ret = IRQ_HANDLED;
2418                         if (iir & GEN8_DE_MISC_GSE)
2419                                 intel_opregion_asle_intr(dev_priv);
2420                         else
2421                                 DRM_ERROR("Unexpected DE Misc interrupt\n");
2422                 }
2423                 else
2424                         DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2425         }
2426
2427         if (master_ctl & GEN8_DE_PORT_IRQ) {
2428                 iir = I915_READ(GEN8_DE_PORT_IIR);
2429                 if (iir) {
2430                         u32 tmp_mask;
2431                         bool found = false;
2432
2433                         I915_WRITE(GEN8_DE_PORT_IIR, iir);
2434                         ret = IRQ_HANDLED;
2435
2436                         tmp_mask = GEN8_AUX_CHANNEL_A;
2437                         if (INTEL_INFO(dev_priv)->gen >= 9)
2438                                 tmp_mask |= GEN9_AUX_CHANNEL_B |
2439                                             GEN9_AUX_CHANNEL_C |
2440                                             GEN9_AUX_CHANNEL_D;
2441
2442                         if (iir & tmp_mask) {
2443                                 dp_aux_irq_handler(dev_priv);
2444                                 found = true;
2445                         }
2446
2447                         if (IS_BROXTON(dev_priv)) {
2448                                 tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
2449                                 if (tmp_mask) {
2450                                         bxt_hpd_irq_handler(dev_priv, tmp_mask,
2451                                                             hpd_bxt);
2452                                         found = true;
2453                                 }
2454                         } else if (IS_BROADWELL(dev_priv)) {
2455                                 tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
2456                                 if (tmp_mask) {
2457                                         ilk_hpd_irq_handler(dev_priv,
2458                                                             tmp_mask, hpd_bdw);
2459                                         found = true;
2460                                 }
2461                         }
2462
2463                         if (IS_BROXTON(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
2464                                 gmbus_irq_handler(dev_priv);
2465                                 found = true;
2466                         }
2467
2468                         if (!found)
2469                                 DRM_ERROR("Unexpected DE Port interrupt\n");
2470                 }
2471                 else
2472                         DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2473         }
2474
2475         for_each_pipe(dev_priv, pipe) {
2476                 u32 flip_done, fault_errors;
2477
2478                 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2479                         continue;
2480
2481                 iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2482                 if (!iir) {
2483                         DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2484                         continue;
2485                 }
2486
2487                 ret = IRQ_HANDLED;
2488                 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
2489
2490                 if (iir & GEN8_PIPE_VBLANK &&
2491                     intel_pipe_handle_vblank(dev_priv, pipe))
2492                         intel_check_page_flip(dev_priv, pipe);
2493
2494                 flip_done = iir;
2495                 if (INTEL_INFO(dev_priv)->gen >= 9)
2496                         flip_done &= GEN9_PIPE_PLANE1_FLIP_DONE;
2497                 else
2498                         flip_done &= GEN8_PIPE_PRIMARY_FLIP_DONE;
2499
2500                 if (flip_done)
2501                         intel_finish_page_flip_cs(dev_priv, pipe);
2502
2503                 if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
2504                         hsw_pipe_crc_irq_handler(dev_priv, pipe);
2505
2506                 if (iir & GEN8_PIPE_FIFO_UNDERRUN)
2507                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2508
2509                 fault_errors = iir;
2510                 if (INTEL_INFO(dev_priv)->gen >= 9)
2511                         fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2512                 else
2513                         fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2514
2515                 if (fault_errors)
2516                         DRM_ERROR("Fault errors on pipe %c: 0x%08x\n",
2517                                   pipe_name(pipe),
2518                                   fault_errors);
2519         }
2520
2521         if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
2522             master_ctl & GEN8_DE_PCH_IRQ) {
2523                 /*
2524                  * FIXME(BDW): Assume for now that the new interrupt handling
2525                  * scheme also closed the SDE interrupt handling race we've seen
2526                  * on older pch-split platforms. But this needs testing.
2527                  */
2528                 iir = I915_READ(SDEIIR);
2529                 if (iir) {
2530                         I915_WRITE(SDEIIR, iir);
2531                         ret = IRQ_HANDLED;
2532
2533                         if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
2534                                 spt_irq_handler(dev_priv, iir);
2535                         else
2536                                 cpt_irq_handler(dev_priv, iir);
2537                 } else {
2538                         /*
2539                          * Like on previous PCH there seems to be something
2540                          * fishy going on with forwarding PCH interrupts.
2541                          */
2542                         DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
2543                 }
2544         }
2545
2546         return ret;
2547 }
2548
2549 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2550 {
2551         struct drm_device *dev = arg;
2552         struct drm_i915_private *dev_priv = to_i915(dev);
2553         u32 master_ctl;
2554         u32 gt_iir[4] = {};
2555         irqreturn_t ret;
2556
2557         if (!intel_irqs_enabled(dev_priv))
2558                 return IRQ_NONE;
2559
2560         master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
2561         master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2562         if (!master_ctl)
2563                 return IRQ_NONE;
2564
2565         I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
2566
2567         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2568         disable_rpm_wakeref_asserts(dev_priv);
2569
2570         /* Find, clear, then process each source of interrupt */
2571         ret = gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
2572         gen8_gt_irq_handler(dev_priv, gt_iir);
2573         ret |= gen8_de_irq_handler(dev_priv, master_ctl);
2574
2575         I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2576         POSTING_READ_FW(GEN8_MASTER_IRQ);
2577
2578         enable_rpm_wakeref_asserts(dev_priv);
2579
2580         return ret;
2581 }
2582
2583 static void i915_error_wake_up(struct drm_i915_private *dev_priv)
2584 {
2585         /*
2586          * Notify all waiters for GPU completion events that reset state has
2587          * been changed, and that they need to restart their wait after
2588          * checking for potential errors (and bail out to drop locks if there is
2589          * a gpu reset pending so that i915_error_work_func can acquire them).
2590          */
2591
2592         /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2593         wake_up_all(&dev_priv->gpu_error.wait_queue);
2594
2595         /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2596         wake_up_all(&dev_priv->pending_flip_queue);
2597 }
2598
2599 /**
2600  * i915_reset_and_wakeup - do process context error handling work
2601  * @dev_priv: i915 device private
2602  *
2603  * Fire an error uevent so userspace can see that a hang or error
2604  * was detected.
2605  */
2606 static void i915_reset_and_wakeup(struct drm_i915_private *dev_priv)
2607 {
2608         struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj;
2609         char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2610         char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2611         char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2612
2613         kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
2614
2615         DRM_DEBUG_DRIVER("resetting chip\n");
2616         kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
2617
2618         /*
2619          * In most cases it's guaranteed that we get here with an RPM
2620          * reference held, for example because there is a pending GPU
2621          * request that won't finish until the reset is done. This
2622          * isn't the case at least when we get here by doing a
2623          * simulated reset via debugs, so get an RPM reference.
2624          */
2625         intel_runtime_pm_get(dev_priv);
2626         intel_prepare_reset(dev_priv);
2627
2628         do {
2629                 /*
2630                  * All state reset _must_ be completed before we update the
2631                  * reset counter, for otherwise waiters might miss the reset
2632                  * pending state and not properly drop locks, resulting in
2633                  * deadlocks with the reset work.
2634                  */
2635                 if (mutex_trylock(&dev_priv->drm.struct_mutex)) {
2636                         i915_reset(dev_priv);
2637                         mutex_unlock(&dev_priv->drm.struct_mutex);
2638                 }
2639
2640                 /* We need to wait for anyone holding the lock to wakeup */
2641         } while (wait_on_bit_timeout(&dev_priv->gpu_error.flags,
2642                                      I915_RESET_IN_PROGRESS,
2643                                      TASK_UNINTERRUPTIBLE,
2644                                      HZ));
2645
2646         intel_finish_reset(dev_priv);
2647         intel_runtime_pm_put(dev_priv);
2648
2649         if (!test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
2650                 kobject_uevent_env(kobj,
2651                                    KOBJ_CHANGE, reset_done_event);
2652
2653         /*
2654          * Note: The wake_up also serves as a memory barrier so that
2655          * waiters see the updated value of the dev_priv->gpu_error.
2656          */
2657         wake_up_all(&dev_priv->gpu_error.reset_queue);
2658 }
2659
2660 static inline void
2661 i915_err_print_instdone(struct drm_i915_private *dev_priv,
2662                         struct intel_instdone *instdone)
2663 {
2664         int slice;
2665         int subslice;
2666
2667         pr_err("  INSTDONE: 0x%08x\n", instdone->instdone);
2668
2669         if (INTEL_GEN(dev_priv) <= 3)
2670                 return;
2671
2672         pr_err("  SC_INSTDONE: 0x%08x\n", instdone->slice_common);
2673
2674         if (INTEL_GEN(dev_priv) <= 6)
2675                 return;
2676
2677         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
2678                 pr_err("  SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
2679                        slice, subslice, instdone->sampler[slice][subslice]);
2680
2681         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
2682                 pr_err("  ROW_INSTDONE[%d][%d]: 0x%08x\n",
2683                        slice, subslice, instdone->row[slice][subslice]);
2684 }
2685
2686 static void i915_clear_error_registers(struct drm_i915_private *dev_priv)
2687 {
2688         u32 eir;
2689
2690         if (!IS_GEN2(dev_priv))
2691                 I915_WRITE(PGTBL_ER, I915_READ(PGTBL_ER));
2692
2693         if (INTEL_GEN(dev_priv) < 4)
2694                 I915_WRITE(IPEIR, I915_READ(IPEIR));
2695         else
2696                 I915_WRITE(IPEIR_I965, I915_READ(IPEIR_I965));
2697
2698         I915_WRITE(EIR, I915_READ(EIR));
2699         eir = I915_READ(EIR);
2700         if (eir) {
2701                 /*
2702                  * some errors might have become stuck,
2703                  * mask them.
2704                  */
2705                 DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir);
2706                 I915_WRITE(EMR, I915_READ(EMR) | eir);
2707                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2708         }
2709 }
2710
2711 /**
2712  * i915_handle_error - handle a gpu error
2713  * @dev_priv: i915 device private
2714  * @engine_mask: mask representing engines that are hung
2715  * Do some basic checking of register state at error time and
2716  * dump it to the syslog.  Also call i915_capture_error_state() to make
2717  * sure we get a record and make it available in debugfs.  Fire a uevent
2718  * so userspace knows something bad happened (should trigger collection
2719  * of a ring dump etc.).
2720  * @fmt: Error message format string
2721  */
2722 void i915_handle_error(struct drm_i915_private *dev_priv,
2723                        u32 engine_mask,
2724                        const char *fmt, ...)
2725 {
2726         va_list args;
2727         char error_msg[80];
2728
2729         va_start(args, fmt);
2730         vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2731         va_end(args);
2732
2733         i915_capture_error_state(dev_priv, engine_mask, error_msg);
2734         i915_clear_error_registers(dev_priv);
2735
2736         if (!engine_mask)
2737                 return;
2738
2739         if (test_and_set_bit(I915_RESET_IN_PROGRESS,
2740                              &dev_priv->gpu_error.flags))
2741                 return;
2742
2743         /*
2744          * Wakeup waiting processes so that the reset function
2745          * i915_reset_and_wakeup doesn't deadlock trying to grab
2746          * various locks. By bumping the reset counter first, the woken
2747          * processes will see a reset in progress and back off,
2748          * releasing their locks and then wait for the reset completion.
2749          * We must do this for _all_ gpu waiters that might hold locks
2750          * that the reset work needs to acquire.
2751          *
2752          * Note: The wake_up also provides a memory barrier to ensure that the
2753          * waiters see the updated value of the reset flags.
2754          */
2755         i915_error_wake_up(dev_priv);
2756
2757         i915_reset_and_wakeup(dev_priv);
2758 }
2759
2760 /* Called from drm generic code, passed 'crtc' which
2761  * we use as a pipe index
2762  */
2763 static int i8xx_enable_vblank(struct drm_device *dev, unsigned int pipe)
2764 {
2765         struct drm_i915_private *dev_priv = to_i915(dev);
2766         unsigned long irqflags;
2767
2768         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2769         i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
2770         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2771
2772         return 0;
2773 }
2774
2775 static int i965_enable_vblank(struct drm_device *dev, unsigned int pipe)
2776 {
2777         struct drm_i915_private *dev_priv = to_i915(dev);
2778         unsigned long irqflags;
2779
2780         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2781         i915_enable_pipestat(dev_priv, pipe,
2782                              PIPE_START_VBLANK_INTERRUPT_STATUS);
2783         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2784
2785         return 0;
2786 }
2787
2788 static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)
2789 {
2790         struct drm_i915_private *dev_priv = to_i915(dev);
2791         unsigned long irqflags;
2792         uint32_t bit = INTEL_GEN(dev_priv) >= 7 ?
2793                 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
2794
2795         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2796         ilk_enable_display_irq(dev_priv, bit);
2797         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2798
2799         return 0;
2800 }
2801
2802 static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe)
2803 {
2804         struct drm_i915_private *dev_priv = to_i915(dev);
2805         unsigned long irqflags;
2806
2807         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2808         bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2809         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2810
2811         return 0;
2812 }
2813
2814 /* Called from drm generic code, passed 'crtc' which
2815  * we use as a pipe index
2816  */
2817 static void i8xx_disable_vblank(struct drm_device *dev, unsigned int pipe)
2818 {
2819         struct drm_i915_private *dev_priv = to_i915(dev);
2820         unsigned long irqflags;
2821
2822         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2823         i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
2824         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2825 }
2826
2827 static void i965_disable_vblank(struct drm_device *dev, unsigned int pipe)
2828 {
2829         struct drm_i915_private *dev_priv = to_i915(dev);
2830         unsigned long irqflags;
2831
2832         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2833         i915_disable_pipestat(dev_priv, pipe,
2834                               PIPE_START_VBLANK_INTERRUPT_STATUS);
2835         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2836 }
2837
2838 static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)
2839 {
2840         struct drm_i915_private *dev_priv = to_i915(dev);
2841         unsigned long irqflags;
2842         uint32_t bit = INTEL_GEN(dev_priv) >= 7 ?
2843                 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
2844
2845         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2846         ilk_disable_display_irq(dev_priv, bit);
2847         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2848 }
2849
2850 static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe)
2851 {
2852         struct drm_i915_private *dev_priv = to_i915(dev);
2853         unsigned long irqflags;
2854
2855         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2856         bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2857         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2858 }
2859
2860 static void ibx_irq_reset(struct drm_i915_private *dev_priv)
2861 {
2862         if (HAS_PCH_NOP(dev_priv))
2863                 return;
2864
2865         GEN5_IRQ_RESET(SDE);
2866
2867         if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
2868                 I915_WRITE(SERR_INT, 0xffffffff);
2869 }
2870
2871 /*
2872  * SDEIER is also touched by the interrupt handler to work around missed PCH
2873  * interrupts. Hence we can't update it after the interrupt handler is enabled -
2874  * instead we unconditionally enable all PCH interrupt sources here, but then
2875  * only unmask them as needed with SDEIMR.
2876  *
2877  * This function needs to be called before interrupts are enabled.
2878  */
2879 static void ibx_irq_pre_postinstall(struct drm_device *dev)
2880 {
2881         struct drm_i915_private *dev_priv = to_i915(dev);
2882
2883         if (HAS_PCH_NOP(dev_priv))
2884                 return;
2885
2886         WARN_ON(I915_READ(SDEIER) != 0);
2887         I915_WRITE(SDEIER, 0xffffffff);
2888         POSTING_READ(SDEIER);
2889 }
2890
2891 static void gen5_gt_irq_reset(struct drm_i915_private *dev_priv)
2892 {
2893         GEN5_IRQ_RESET(GT);
2894         if (INTEL_GEN(dev_priv) >= 6)
2895                 GEN5_IRQ_RESET(GEN6_PM);
2896 }
2897
2898 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
2899 {
2900         enum pipe pipe;
2901
2902         if (IS_CHERRYVIEW(dev_priv))
2903                 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
2904         else
2905                 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2906
2907         i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
2908         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2909
2910         for_each_pipe(dev_priv, pipe) {
2911                 I915_WRITE(PIPESTAT(pipe),
2912                            PIPE_FIFO_UNDERRUN_STATUS |
2913                            PIPESTAT_INT_STATUS_MASK);
2914                 dev_priv->pipestat_irq_mask[pipe] = 0;
2915         }
2916
2917         GEN5_IRQ_RESET(VLV_);
2918         dev_priv->irq_mask = ~0;
2919 }
2920
2921 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
2922 {
2923         u32 pipestat_mask;
2924         u32 enable_mask;
2925         enum pipe pipe;
2926         u32 val;
2927
2928         pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
2929                         PIPE_CRC_DONE_INTERRUPT_STATUS;
2930
2931         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
2932         for_each_pipe(dev_priv, pipe)
2933                 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
2934
2935         enable_mask = I915_DISPLAY_PORT_INTERRUPT |
2936                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2937                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
2938         if (IS_CHERRYVIEW(dev_priv))
2939                 enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
2940
2941         WARN_ON(dev_priv->irq_mask != ~0);
2942
2943         val = (I915_LPE_PIPE_A_INTERRUPT |
2944                 I915_LPE_PIPE_B_INTERRUPT |
2945                 I915_LPE_PIPE_C_INTERRUPT);
2946
2947         enable_mask |= val;
2948
2949         dev_priv->irq_mask = ~enable_mask;
2950
2951         GEN5_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask);
2952 }
2953
2954 /* drm_dma.h hooks
2955 */
2956 static void ironlake_irq_reset(struct drm_device *dev)
2957 {
2958         struct drm_i915_private *dev_priv = to_i915(dev);
2959
2960         I915_WRITE(HWSTAM, 0xffffffff);
2961
2962         GEN5_IRQ_RESET(DE);
2963         if (IS_GEN7(dev_priv))
2964                 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
2965
2966         gen5_gt_irq_reset(dev_priv);
2967
2968         ibx_irq_reset(dev_priv);
2969 }
2970
2971 static void valleyview_irq_preinstall(struct drm_device *dev)
2972 {
2973         struct drm_i915_private *dev_priv = to_i915(dev);
2974
2975         I915_WRITE(VLV_MASTER_IER, 0);
2976         POSTING_READ(VLV_MASTER_IER);
2977
2978         gen5_gt_irq_reset(dev_priv);
2979
2980         spin_lock_irq(&dev_priv->irq_lock);
2981         if (dev_priv->display_irqs_enabled)
2982                 vlv_display_irq_reset(dev_priv);
2983         spin_unlock_irq(&dev_priv->irq_lock);
2984 }
2985
2986 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
2987 {
2988         GEN8_IRQ_RESET_NDX(GT, 0);
2989         GEN8_IRQ_RESET_NDX(GT, 1);
2990         GEN8_IRQ_RESET_NDX(GT, 2);
2991         GEN8_IRQ_RESET_NDX(GT, 3);
2992 }
2993
2994 static void gen8_irq_reset(struct drm_device *dev)
2995 {
2996         struct drm_i915_private *dev_priv = to_i915(dev);
2997         int pipe;
2998
2999         I915_WRITE(GEN8_MASTER_IRQ, 0);
3000         POSTING_READ(GEN8_MASTER_IRQ);
3001
3002         gen8_gt_irq_reset(dev_priv);
3003
3004         for_each_pipe(dev_priv, pipe)
3005                 if (intel_display_power_is_enabled(dev_priv,
3006                                                    POWER_DOMAIN_PIPE(pipe)))
3007                         GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3008
3009         GEN5_IRQ_RESET(GEN8_DE_PORT_);
3010         GEN5_IRQ_RESET(GEN8_DE_MISC_);
3011         GEN5_IRQ_RESET(GEN8_PCU_);
3012
3013         if (HAS_PCH_SPLIT(dev_priv))
3014                 ibx_irq_reset(dev_priv);
3015 }
3016
3017 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
3018                                      unsigned int pipe_mask)
3019 {
3020         uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3021         enum pipe pipe;
3022
3023         spin_lock_irq(&dev_priv->irq_lock);
3024         for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3025                 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3026                                   dev_priv->de_irq_mask[pipe],
3027                                   ~dev_priv->de_irq_mask[pipe] | extra_ier);
3028         spin_unlock_irq(&dev_priv->irq_lock);
3029 }
3030
3031 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
3032                                      unsigned int pipe_mask)
3033 {
3034         enum pipe pipe;
3035
3036         spin_lock_irq(&dev_priv->irq_lock);
3037         for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3038                 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3039         spin_unlock_irq(&dev_priv->irq_lock);
3040
3041         /* make sure we're done processing display irqs */
3042         synchronize_irq(dev_priv->drm.irq);
3043 }
3044
3045 static void cherryview_irq_preinstall(struct drm_device *dev)
3046 {
3047         struct drm_i915_private *dev_priv = to_i915(dev);
3048
3049         I915_WRITE(GEN8_MASTER_IRQ, 0);
3050         POSTING_READ(GEN8_MASTER_IRQ);
3051
3052         gen8_gt_irq_reset(dev_priv);
3053
3054         GEN5_IRQ_RESET(GEN8_PCU_);
3055
3056         spin_lock_irq(&dev_priv->irq_lock);
3057         if (dev_priv->display_irqs_enabled)
3058                 vlv_display_irq_reset(dev_priv);
3059         spin_unlock_irq(&dev_priv->irq_lock);
3060 }
3061
3062 static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
3063                                   const u32 hpd[HPD_NUM_PINS])
3064 {
3065         struct intel_encoder *encoder;
3066         u32 enabled_irqs = 0;
3067
3068         for_each_intel_encoder(&dev_priv->drm, encoder)
3069                 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
3070                         enabled_irqs |= hpd[encoder->hpd_pin];
3071
3072         return enabled_irqs;
3073 }
3074
3075 static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
3076 {
3077         u32 hotplug_irqs, hotplug, enabled_irqs;
3078
3079         if (HAS_PCH_IBX(dev_priv)) {
3080                 hotplug_irqs = SDE_HOTPLUG_MASK;
3081                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ibx);
3082         } else {
3083                 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3084                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_cpt);
3085         }
3086
3087         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3088
3089         /*
3090          * Enable digital hotplug on the PCH, and configure the DP short pulse
3091          * duration to 2ms (which is the minimum in the Display Port spec).
3092          * The pulse duration bits are reserved on LPT+.
3093          */
3094         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3095         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3096         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3097         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3098         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3099         /*
3100          * When CPU and PCH are on the same package, port A
3101          * HPD must be enabled in both north and south.
3102          */
3103         if (HAS_PCH_LPT_LP(dev_priv))
3104                 hotplug |= PORTA_HOTPLUG_ENABLE;
3105         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3106 }
3107
3108 static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3109 {
3110         u32 hotplug_irqs, hotplug, enabled_irqs;
3111
3112         hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
3113         enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt);
3114
3115         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3116
3117         /* Enable digital hotplug on the PCH */
3118         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3119         hotplug |= PORTD_HOTPLUG_ENABLE | PORTC_HOTPLUG_ENABLE |
3120                 PORTB_HOTPLUG_ENABLE | PORTA_HOTPLUG_ENABLE;
3121         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3122
3123         hotplug = I915_READ(PCH_PORT_HOTPLUG2);
3124         hotplug |= PORTE_HOTPLUG_ENABLE;
3125         I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
3126 }
3127
3128 static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
3129 {
3130         u32 hotplug_irqs, hotplug, enabled_irqs;
3131
3132         if (INTEL_GEN(dev_priv) >= 8) {
3133                 hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
3134                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw);
3135
3136                 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3137         } else if (INTEL_GEN(dev_priv) >= 7) {
3138                 hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
3139                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ivb);
3140
3141                 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3142         } else {
3143                 hotplug_irqs = DE_DP_A_HOTPLUG;
3144                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ilk);
3145
3146                 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3147         }
3148
3149         /*
3150          * Enable digital hotplug on the CPU, and configure the DP short pulse
3151          * duration to 2ms (which is the minimum in the Display Port spec)
3152          * The pulse duration bits are reserved on HSW+.
3153          */
3154         hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
3155         hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
3156         hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE | DIGITAL_PORTA_PULSE_DURATION_2ms;
3157         I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
3158
3159         ibx_hpd_irq_setup(dev_priv);
3160 }
3161
3162 static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3163 {
3164         u32 hotplug_irqs, hotplug, enabled_irqs;
3165
3166         enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bxt);
3167         hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK;
3168
3169         bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3170
3171         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3172         hotplug |= PORTC_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE |
3173                 PORTA_HOTPLUG_ENABLE;
3174
3175         DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x\n",
3176                       hotplug, enabled_irqs);
3177         hotplug &= ~BXT_DDI_HPD_INVERT_MASK;
3178
3179         /*
3180          * For BXT invert bit has to be set based on AOB design
3181          * for HPD detection logic, update it based on VBT fields.
3182          */
3183
3184         if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) &&
3185             intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
3186                 hotplug |= BXT_DDIA_HPD_INVERT;
3187         if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) &&
3188             intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
3189                 hotplug |= BXT_DDIB_HPD_INVERT;
3190         if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) &&
3191             intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
3192                 hotplug |= BXT_DDIC_HPD_INVERT;
3193
3194         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3195 }
3196
3197 static void ibx_irq_postinstall(struct drm_device *dev)
3198 {
3199         struct drm_i915_private *dev_priv = to_i915(dev);
3200         u32 mask;
3201
3202         if (HAS_PCH_NOP(dev_priv))
3203                 return;
3204
3205         if (HAS_PCH_IBX(dev_priv))
3206                 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3207         else
3208                 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3209
3210         gen5_assert_iir_is_zero(dev_priv, SDEIIR);
3211         I915_WRITE(SDEIMR, ~mask);
3212 }
3213
3214 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3215 {
3216         struct drm_i915_private *dev_priv = to_i915(dev);
3217         u32 pm_irqs, gt_irqs;
3218
3219         pm_irqs = gt_irqs = 0;
3220
3221         dev_priv->gt_irq_mask = ~0;
3222         if (HAS_L3_DPF(dev_priv)) {
3223                 /* L3 parity interrupt is always unmasked. */
3224                 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev_priv);
3225                 gt_irqs |= GT_PARITY_ERROR(dev_priv);
3226         }
3227
3228         gt_irqs |= GT_RENDER_USER_INTERRUPT;
3229         if (IS_GEN5(dev_priv)) {
3230                 gt_irqs |= ILK_BSD_USER_INTERRUPT;
3231         } else {
3232                 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3233         }
3234
3235         GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3236
3237         if (INTEL_GEN(dev_priv) >= 6) {
3238                 /*
3239                  * RPS interrupts will get enabled/disabled on demand when RPS
3240                  * itself is enabled/disabled.
3241                  */
3242                 if (HAS_VEBOX(dev_priv)) {
3243                         pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3244                         dev_priv->pm_ier |= PM_VEBOX_USER_INTERRUPT;
3245                 }
3246
3247                 dev_priv->pm_imr = 0xffffffff;
3248                 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_imr, pm_irqs);
3249         }
3250 }
3251
3252 static int ironlake_irq_postinstall(struct drm_device *dev)
3253 {
3254         struct drm_i915_private *dev_priv = to_i915(dev);
3255         u32 display_mask, extra_mask;
3256
3257         if (INTEL_GEN(dev_priv) >= 7) {
3258                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3259                                 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3260                                 DE_PLANEB_FLIP_DONE_IVB |
3261                                 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3262                 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3263                               DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
3264                               DE_DP_A_HOTPLUG_IVB);
3265         } else {
3266                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3267                                 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3268                                 DE_AUX_CHANNEL_A |
3269                                 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3270                                 DE_POISON);
3271                 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3272                               DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
3273                               DE_DP_A_HOTPLUG);
3274         }
3275
3276         dev_priv->irq_mask = ~display_mask;
3277
3278         I915_WRITE(HWSTAM, 0xeffe);
3279
3280         ibx_irq_pre_postinstall(dev);
3281
3282         GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3283
3284         gen5_gt_irq_postinstall(dev);
3285
3286         ibx_irq_postinstall(dev);
3287
3288         if (IS_IRONLAKE_M(dev_priv)) {
3289                 /* Enable PCU event interrupts
3290                  *
3291                  * spinlocking not required here for correctness since interrupt
3292                  * setup is guaranteed to run in single-threaded context. But we
3293                  * need it to make the assert_spin_locked happy. */
3294                 spin_lock_irq(&dev_priv->irq_lock);
3295                 ilk_enable_display_irq(dev_priv, DE_PCU_EVENT);
3296                 spin_unlock_irq(&dev_priv->irq_lock);
3297         }
3298
3299         return 0;
3300 }
3301
3302 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3303 {
3304         assert_spin_locked(&dev_priv->irq_lock);
3305
3306         if (dev_priv->display_irqs_enabled)
3307                 return;
3308
3309         dev_priv->display_irqs_enabled = true;
3310
3311         if (intel_irqs_enabled(dev_priv)) {
3312                 vlv_display_irq_reset(dev_priv);
3313                 vlv_display_irq_postinstall(dev_priv);
3314         }
3315 }
3316
3317 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3318 {
3319         assert_spin_locked(&dev_priv->irq_lock);
3320
3321         if (!dev_priv->display_irqs_enabled)
3322                 return;
3323
3324         dev_priv->display_irqs_enabled = false;
3325
3326         if (intel_irqs_enabled(dev_priv))
3327                 vlv_display_irq_reset(dev_priv);
3328 }
3329
3330
3331 static int valleyview_irq_postinstall(struct drm_device *dev)
3332 {
3333         struct drm_i915_private *dev_priv = to_i915(dev);
3334
3335         gen5_gt_irq_postinstall(dev);
3336
3337         spin_lock_irq(&dev_priv->irq_lock);
3338         if (dev_priv->display_irqs_enabled)
3339                 vlv_display_irq_postinstall(dev_priv);
3340         spin_unlock_irq(&dev_priv->irq_lock);
3341
3342         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3343         POSTING_READ(VLV_MASTER_IER);
3344
3345         return 0;
3346 }
3347
3348 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3349 {
3350         /* These are interrupts we'll toggle with the ring mask register */
3351         uint32_t gt_interrupts[] = {
3352                 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3353                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3354                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3355                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3356                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3357                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3358                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3359                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3360                 0,
3361                 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3362                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3363                 };
3364
3365         if (HAS_L3_DPF(dev_priv))
3366                 gt_interrupts[0] |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
3367
3368         dev_priv->pm_ier = 0x0;
3369         dev_priv->pm_imr = ~dev_priv->pm_ier;
3370         GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3371         GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
3372         /*
3373          * RPS interrupts will get enabled/disabled on demand when RPS itself
3374          * is enabled/disabled. Same wil be the case for GuC interrupts.
3375          */
3376         GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_imr, dev_priv->pm_ier);
3377         GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
3378 }
3379
3380 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3381 {
3382         uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3383         uint32_t de_pipe_enables;
3384         u32 de_port_masked = GEN8_AUX_CHANNEL_A;
3385         u32 de_port_enables;
3386         u32 de_misc_masked = GEN8_DE_MISC_GSE;
3387         enum pipe pipe;
3388
3389         if (INTEL_INFO(dev_priv)->gen >= 9) {
3390                 de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
3391                                   GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3392                 de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
3393                                   GEN9_AUX_CHANNEL_D;
3394                 if (IS_BROXTON(dev_priv))
3395                         de_port_masked |= BXT_DE_PORT_GMBUS;
3396         } else {
3397                 de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
3398                                   GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3399         }
3400
3401         de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3402                                            GEN8_PIPE_FIFO_UNDERRUN;
3403
3404         de_port_enables = de_port_masked;
3405         if (IS_BROXTON(dev_priv))
3406                 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
3407         else if (IS_BROADWELL(dev_priv))
3408                 de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
3409
3410         dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3411         dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3412         dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3413
3414         for_each_pipe(dev_priv, pipe)
3415                 if (intel_display_power_is_enabled(dev_priv,
3416                                 POWER_DOMAIN_PIPE(pipe)))
3417                         GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3418                                           dev_priv->de_irq_mask[pipe],
3419                                           de_pipe_enables);
3420
3421         GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
3422         GEN5_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
3423 }
3424
3425 static int gen8_irq_postinstall(struct drm_device *dev)
3426 {
3427         struct drm_i915_private *dev_priv = to_i915(dev);
3428
3429         if (HAS_PCH_SPLIT(dev_priv))
3430                 ibx_irq_pre_postinstall(dev);
3431
3432         gen8_gt_irq_postinstall(dev_priv);
3433         gen8_de_irq_postinstall(dev_priv);
3434
3435         if (HAS_PCH_SPLIT(dev_priv))
3436                 ibx_irq_postinstall(dev);
3437
3438         I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3439         POSTING_READ(GEN8_MASTER_IRQ);
3440
3441         return 0;
3442 }
3443
3444 static int cherryview_irq_postinstall(struct drm_device *dev)
3445 {
3446         struct drm_i915_private *dev_priv = to_i915(dev);
3447
3448         gen8_gt_irq_postinstall(dev_priv);
3449
3450         spin_lock_irq(&dev_priv->irq_lock);
3451         if (dev_priv->display_irqs_enabled)
3452                 vlv_display_irq_postinstall(dev_priv);
3453         spin_unlock_irq(&dev_priv->irq_lock);
3454
3455         I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3456         POSTING_READ(GEN8_MASTER_IRQ);
3457
3458         return 0;
3459 }
3460
3461 static void gen8_irq_uninstall(struct drm_device *dev)
3462 {
3463         struct drm_i915_private *dev_priv = to_i915(dev);
3464
3465         if (!dev_priv)
3466                 return;
3467
3468         gen8_irq_reset(dev);
3469 }
3470
3471 static void valleyview_irq_uninstall(struct drm_device *dev)
3472 {
3473         struct drm_i915_private *dev_priv = to_i915(dev);
3474
3475         if (!dev_priv)
3476                 return;
3477
3478         I915_WRITE(VLV_MASTER_IER, 0);
3479         POSTING_READ(VLV_MASTER_IER);
3480
3481         gen5_gt_irq_reset(dev_priv);
3482
3483         I915_WRITE(HWSTAM, 0xffffffff);
3484
3485         spin_lock_irq(&dev_priv->irq_lock);
3486         if (dev_priv->display_irqs_enabled)
3487                 vlv_display_irq_reset(dev_priv);
3488         spin_unlock_irq(&dev_priv->irq_lock);
3489 }
3490
3491 static void cherryview_irq_uninstall(struct drm_device *dev)
3492 {
3493         struct drm_i915_private *dev_priv = to_i915(dev);
3494
3495         if (!dev_priv)
3496                 return;
3497
3498         I915_WRITE(GEN8_MASTER_IRQ, 0);
3499         POSTING_READ(GEN8_MASTER_IRQ);
3500
3501         gen8_gt_irq_reset(dev_priv);
3502
3503         GEN5_IRQ_RESET(GEN8_PCU_);
3504
3505         spin_lock_irq(&dev_priv->irq_lock);
3506         if (dev_priv->display_irqs_enabled)
3507                 vlv_display_irq_reset(dev_priv);
3508         spin_unlock_irq(&dev_priv->irq_lock);
3509 }
3510
3511 static void ironlake_irq_uninstall(struct drm_device *dev)
3512 {
3513         struct drm_i915_private *dev_priv = to_i915(dev);
3514
3515         if (!dev_priv)
3516                 return;
3517
3518         ironlake_irq_reset(dev);
3519 }
3520
3521 static void i8xx_irq_preinstall(struct drm_device * dev)
3522 {
3523         struct drm_i915_private *dev_priv = to_i915(dev);
3524         int pipe;
3525
3526         for_each_pipe(dev_priv, pipe)
3527                 I915_WRITE(PIPESTAT(pipe), 0);
3528         I915_WRITE16(IMR, 0xffff);
3529         I915_WRITE16(IER, 0x0);
3530         POSTING_READ16(IER);
3531 }
3532
3533 static int i8xx_irq_postinstall(struct drm_device *dev)
3534 {
3535         struct drm_i915_private *dev_priv = to_i915(dev);
3536
3537         I915_WRITE16(EMR,
3538                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3539
3540         /* Unmask the interrupts that we always want on. */
3541         dev_priv->irq_mask =
3542                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3543                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3544                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3545                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3546         I915_WRITE16(IMR, dev_priv->irq_mask);
3547
3548         I915_WRITE16(IER,
3549                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3550                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3551                      I915_USER_INTERRUPT);
3552         POSTING_READ16(IER);
3553
3554         /* Interrupt setup is already guaranteed to be single-threaded, this is
3555          * just to make the assert_spin_locked check happy. */
3556         spin_lock_irq(&dev_priv->irq_lock);
3557         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3558         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3559         spin_unlock_irq(&dev_priv->irq_lock);
3560
3561         return 0;
3562 }
3563
3564 /*
3565  * Returns true when a page flip has completed.
3566  */
3567 static bool i8xx_handle_vblank(struct drm_i915_private *dev_priv,
3568                                int plane, int pipe, u32 iir)
3569 {
3570         u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3571
3572         if (!intel_pipe_handle_vblank(dev_priv, pipe))
3573                 return false;
3574
3575         if ((iir & flip_pending) == 0)
3576                 goto check_page_flip;
3577
3578         /* We detect FlipDone by looking for the change in PendingFlip from '1'
3579          * to '0' on the following vblank, i.e. IIR has the Pendingflip
3580          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3581          * the flip is completed (no longer pending). Since this doesn't raise
3582          * an interrupt per se, we watch for the change at vblank.
3583          */
3584         if (I915_READ16(ISR) & flip_pending)
3585                 goto check_page_flip;
3586
3587         intel_finish_page_flip_cs(dev_priv, pipe);
3588         return true;
3589
3590 check_page_flip:
3591         intel_check_page_flip(dev_priv, pipe);
3592         return false;
3593 }
3594
3595 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3596 {
3597         struct drm_device *dev = arg;
3598         struct drm_i915_private *dev_priv = to_i915(dev);
3599         u16 iir, new_iir;
3600         u32 pipe_stats[2];
3601         int pipe;
3602         u16 flip_mask =
3603                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3604                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3605         irqreturn_t ret;
3606
3607         if (!intel_irqs_enabled(dev_priv))
3608                 return IRQ_NONE;
3609
3610         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3611         disable_rpm_wakeref_asserts(dev_priv);
3612
3613         ret = IRQ_NONE;
3614         iir = I915_READ16(IIR);
3615         if (iir == 0)
3616                 goto out;
3617
3618         while (iir & ~flip_mask) {
3619                 /* Can't rely on pipestat interrupt bit in iir as it might
3620                  * have been cleared after the pipestat interrupt was received.
3621                  * It doesn't set the bit in iir again, but it still produces
3622                  * interrupts (for non-MSI).
3623                  */
3624                 spin_lock(&dev_priv->irq_lock);
3625                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3626                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3627
3628                 for_each_pipe(dev_priv, pipe) {
3629                         i915_reg_t reg = PIPESTAT(pipe);
3630                         pipe_stats[pipe] = I915_READ(reg);
3631
3632                         /*
3633                          * Clear the PIPE*STAT regs before the IIR
3634                          */
3635                         if (pipe_stats[pipe] & 0x8000ffff)
3636                                 I915_WRITE(reg, pipe_stats[pipe]);
3637                 }
3638                 spin_unlock(&dev_priv->irq_lock);
3639
3640                 I915_WRITE16(IIR, iir & ~flip_mask);
3641                 new_iir = I915_READ16(IIR); /* Flush posted writes */
3642
3643                 if (iir & I915_USER_INTERRUPT)
3644                         notify_ring(dev_priv->engine[RCS]);
3645
3646                 for_each_pipe(dev_priv, pipe) {
3647                         int plane = pipe;
3648                         if (HAS_FBC(dev_priv))
3649                                 plane = !plane;
3650
3651                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3652                             i8xx_handle_vblank(dev_priv, plane, pipe, iir))
3653                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3654
3655                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3656                                 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
3657
3658                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3659                                 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3660                                                                     pipe);
3661                 }
3662
3663                 iir = new_iir;
3664         }
3665         ret = IRQ_HANDLED;
3666
3667 out:
3668         enable_rpm_wakeref_asserts(dev_priv);
3669
3670         return ret;
3671 }
3672
3673 static void i8xx_irq_uninstall(struct drm_device * dev)
3674 {
3675         struct drm_i915_private *dev_priv = to_i915(dev);
3676         int pipe;
3677
3678         for_each_pipe(dev_priv, pipe) {
3679                 /* Clear enable bits; then clear status bits */
3680                 I915_WRITE(PIPESTAT(pipe), 0);
3681                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3682         }
3683         I915_WRITE16(IMR, 0xffff);
3684         I915_WRITE16(IER, 0x0);
3685         I915_WRITE16(IIR, I915_READ16(IIR));
3686 }
3687
3688 static void i915_irq_preinstall(struct drm_device * dev)
3689 {
3690         struct drm_i915_private *dev_priv = to_i915(dev);
3691         int pipe;
3692
3693         if (I915_HAS_HOTPLUG(dev_priv)) {
3694                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3695                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3696         }
3697
3698         I915_WRITE16(HWSTAM, 0xeffe);
3699         for_each_pipe(dev_priv, pipe)
3700                 I915_WRITE(PIPESTAT(pipe), 0);
3701         I915_WRITE(IMR, 0xffffffff);
3702         I915_WRITE(IER, 0x0);
3703         POSTING_READ(IER);
3704 }
3705
3706 static int i915_irq_postinstall(struct drm_device *dev)
3707 {
3708         struct drm_i915_private *dev_priv = to_i915(dev);
3709         u32 enable_mask;
3710
3711         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3712
3713         /* Unmask the interrupts that we always want on. */
3714         dev_priv->irq_mask =
3715                 ~(I915_ASLE_INTERRUPT |
3716                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3717                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3718                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3719                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3720
3721         enable_mask =
3722                 I915_ASLE_INTERRUPT |
3723                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3724                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3725                 I915_USER_INTERRUPT;
3726
3727         if (I915_HAS_HOTPLUG(dev_priv)) {
3728                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3729                 POSTING_READ(PORT_HOTPLUG_EN);
3730
3731                 /* Enable in IER... */
3732                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3733                 /* and unmask in IMR */
3734                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3735         }
3736
3737         I915_WRITE(IMR, dev_priv->irq_mask);
3738         I915_WRITE(IER, enable_mask);
3739         POSTING_READ(IER);
3740
3741         i915_enable_asle_pipestat(dev_priv);
3742
3743         /* Interrupt setup is already guaranteed to be single-threaded, this is
3744          * just to make the assert_spin_locked check happy. */
3745         spin_lock_irq(&dev_priv->irq_lock);
3746         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3747         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3748         spin_unlock_irq(&dev_priv->irq_lock);
3749
3750         return 0;
3751 }
3752
3753 /*
3754  * Returns true when a page flip has completed.
3755  */
3756 static bool i915_handle_vblank(struct drm_i915_private *dev_priv,
3757                                int plane, int pipe, u32 iir)
3758 {
3759         u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3760
3761         if (!intel_pipe_handle_vblank(dev_priv, pipe))
3762                 return false;
3763
3764         if ((iir & flip_pending) == 0)
3765                 goto check_page_flip;
3766
3767         /* We detect FlipDone by looking for the change in PendingFlip from '1'
3768          * to '0' on the following vblank, i.e. IIR has the Pendingflip
3769          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3770          * the flip is completed (no longer pending). Since this doesn't raise
3771          * an interrupt per se, we watch for the change at vblank.
3772          */
3773         if (I915_READ(ISR) & flip_pending)
3774                 goto check_page_flip;
3775
3776         intel_finish_page_flip_cs(dev_priv, pipe);
3777         return true;
3778
3779 check_page_flip:
3780         intel_check_page_flip(dev_priv, pipe);
3781         return false;
3782 }
3783
3784 static irqreturn_t i915_irq_handler(int irq, void *arg)
3785 {
3786         struct drm_device *dev = arg;
3787         struct drm_i915_private *dev_priv = to_i915(dev);
3788         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3789         u32 flip_mask =
3790                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3791                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3792         int pipe, ret = IRQ_NONE;
3793
3794         if (!intel_irqs_enabled(dev_priv))
3795                 return IRQ_NONE;
3796
3797         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3798         disable_rpm_wakeref_asserts(dev_priv);
3799
3800         iir = I915_READ(IIR);
3801         do {
3802                 bool irq_received = (iir & ~flip_mask) != 0;
3803                 bool blc_event = false;
3804
3805                 /* Can't rely on pipestat interrupt bit in iir as it might
3806                  * have been cleared after the pipestat interrupt was received.
3807                  * It doesn't set the bit in iir again, but it still produces
3808                  * interrupts (for non-MSI).
3809                  */
3810                 spin_lock(&dev_priv->irq_lock);
3811                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3812                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3813
3814                 for_each_pipe(dev_priv, pipe) {
3815                         i915_reg_t reg = PIPESTAT(pipe);
3816                         pipe_stats[pipe] = I915_READ(reg);
3817
3818                         /* Clear the PIPE*STAT regs before the IIR */
3819                         if (pipe_stats[pipe] & 0x8000ffff) {
3820                                 I915_WRITE(reg, pipe_stats[pipe]);
3821                                 irq_received = true;
3822                         }
3823                 }
3824                 spin_unlock(&dev_priv->irq_lock);
3825
3826                 if (!irq_received)
3827                         break;
3828
3829                 /* Consume port.  Then clear IIR or we'll miss events */
3830                 if (I915_HAS_HOTPLUG(dev_priv) &&
3831                     iir & I915_DISPLAY_PORT_INTERRUPT) {
3832                         u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
3833                         if (hotplug_status)
3834                                 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
3835                 }
3836
3837                 I915_WRITE(IIR, iir & ~flip_mask);
3838                 new_iir = I915_READ(IIR); /* Flush posted writes */
3839
3840                 if (iir & I915_USER_INTERRUPT)
3841                         notify_ring(dev_priv->engine[RCS]);
3842
3843                 for_each_pipe(dev_priv, pipe) {
3844                         int plane = pipe;
3845                         if (HAS_FBC(dev_priv))
3846                                 plane = !plane;
3847
3848                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3849                             i915_handle_vblank(dev_priv, plane, pipe, iir))
3850                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3851
3852                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3853                                 blc_event = true;
3854
3855                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3856                                 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
3857
3858                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3859                                 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3860                                                                     pipe);
3861                 }
3862
3863                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3864                         intel_opregion_asle_intr(dev_priv);
3865
3866                 /* With MSI, interrupts are only generated when iir
3867                  * transitions from zero to nonzero.  If another bit got
3868                  * set while we were handling the existing iir bits, then
3869                  * we would never get another interrupt.
3870                  *
3871                  * This is fine on non-MSI as well, as if we hit this path
3872                  * we avoid exiting the interrupt handler only to generate
3873                  * another one.
3874                  *
3875                  * Note that for MSI this could cause a stray interrupt report
3876                  * if an interrupt landed in the time between writing IIR and
3877                  * the posting read.  This should be rare enough to never
3878                  * trigger the 99% of 100,000 interrupts test for disabling
3879                  * stray interrupts.
3880                  */
3881                 ret = IRQ_HANDLED;
3882                 iir = new_iir;
3883         } while (iir & ~flip_mask);
3884
3885         enable_rpm_wakeref_asserts(dev_priv);
3886
3887         return ret;
3888 }
3889
3890 static void i915_irq_uninstall(struct drm_device * dev)
3891 {
3892         struct drm_i915_private *dev_priv = to_i915(dev);
3893         int pipe;
3894
3895         if (I915_HAS_HOTPLUG(dev_priv)) {
3896                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3897                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3898         }
3899
3900         I915_WRITE16(HWSTAM, 0xffff);
3901         for_each_pipe(dev_priv, pipe) {
3902                 /* Clear enable bits; then clear status bits */
3903                 I915_WRITE(PIPESTAT(pipe), 0);
3904                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3905         }
3906         I915_WRITE(IMR, 0xffffffff);
3907         I915_WRITE(IER, 0x0);
3908
3909         I915_WRITE(IIR, I915_READ(IIR));
3910 }
3911
3912 static void i965_irq_preinstall(struct drm_device * dev)
3913 {
3914         struct drm_i915_private *dev_priv = to_i915(dev);
3915         int pipe;
3916
3917         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3918         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3919
3920         I915_WRITE(HWSTAM, 0xeffe);
3921         for_each_pipe(dev_priv, pipe)
3922                 I915_WRITE(PIPESTAT(pipe), 0);
3923         I915_WRITE(IMR, 0xffffffff);
3924         I915_WRITE(IER, 0x0);
3925         POSTING_READ(IER);
3926 }
3927
3928 static int i965_irq_postinstall(struct drm_device *dev)
3929 {
3930         struct drm_i915_private *dev_priv = to_i915(dev);
3931         u32 enable_mask;
3932         u32 error_mask;
3933
3934         /* Unmask the interrupts that we always want on. */
3935         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
3936                                I915_DISPLAY_PORT_INTERRUPT |
3937                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3938                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3939                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3940                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3941                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3942
3943         enable_mask = ~dev_priv->irq_mask;
3944         enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3945                          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3946         enable_mask |= I915_USER_INTERRUPT;
3947
3948         if (IS_G4X(dev_priv))
3949                 enable_mask |= I915_BSD_USER_INTERRUPT;
3950
3951         /* Interrupt setup is already guaranteed to be single-threaded, this is
3952          * just to make the assert_spin_locked check happy. */
3953         spin_lock_irq(&dev_priv->irq_lock);
3954         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3955         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3956         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3957         spin_unlock_irq(&dev_priv->irq_lock);
3958
3959         /*
3960          * Enable some error detection, note the instruction error mask
3961          * bit is reserved, so we leave it masked.
3962          */
3963         if (IS_G4X(dev_priv)) {
3964                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3965                                GM45_ERROR_MEM_PRIV |
3966                                GM45_ERROR_CP_PRIV |
3967                                I915_ERROR_MEMORY_REFRESH);
3968         } else {
3969                 error_mask = ~(I915_ERROR_PAGE_TABLE |
3970                                I915_ERROR_MEMORY_REFRESH);
3971         }
3972         I915_WRITE(EMR, error_mask);
3973
3974         I915_WRITE(IMR, dev_priv->irq_mask);
3975         I915_WRITE(IER, enable_mask);
3976         POSTING_READ(IER);
3977
3978         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3979         POSTING_READ(PORT_HOTPLUG_EN);
3980
3981         i915_enable_asle_pipestat(dev_priv);
3982
3983         return 0;
3984 }
3985
3986 static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
3987 {
3988         u32 hotplug_en;
3989
3990         assert_spin_locked(&dev_priv->irq_lock);
3991
3992         /* Note HDMI and DP share hotplug bits */
3993         /* enable bits are the same for all generations */
3994         hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);
3995         /* Programming the CRT detection parameters tends
3996            to generate a spurious hotplug event about three
3997            seconds later.  So just do it once.
3998         */
3999         if (IS_G4X(dev_priv))
4000                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4001         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4002
4003         /* Ignore TV since it's buggy */
4004         i915_hotplug_interrupt_update_locked(dev_priv,
4005                                              HOTPLUG_INT_EN_MASK |
4006                                              CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
4007                                              CRT_HOTPLUG_ACTIVATION_PERIOD_64,
4008                                              hotplug_en);
4009 }
4010
4011 static irqreturn_t i965_irq_handler(int irq, void *arg)
4012 {
4013         struct drm_device *dev = arg;
4014         struct drm_i915_private *dev_priv = to_i915(dev);
4015         u32 iir, new_iir;
4016         u32 pipe_stats[I915_MAX_PIPES];
4017         int ret = IRQ_NONE, pipe;
4018         u32 flip_mask =
4019                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4020                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4021
4022         if (!intel_irqs_enabled(dev_priv))
4023                 return IRQ_NONE;
4024
4025         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4026         disable_rpm_wakeref_asserts(dev_priv);
4027
4028         iir = I915_READ(IIR);
4029
4030         for (;;) {
4031                 bool irq_received = (iir & ~flip_mask) != 0;
4032                 bool blc_event = false;
4033
4034                 /* Can't rely on pipestat interrupt bit in iir as it might
4035                  * have been cleared after the pipestat interrupt was received.
4036                  * It doesn't set the bit in iir again, but it still produces
4037                  * interrupts (for non-MSI).
4038                  */
4039                 spin_lock(&dev_priv->irq_lock);
4040                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4041                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4042
4043                 for_each_pipe(dev_priv, pipe) {
4044                         i915_reg_t reg = PIPESTAT(pipe);
4045                         pipe_stats[pipe] = I915_READ(reg);
4046
4047                         /*
4048                          * Clear the PIPE*STAT regs before the IIR
4049                          */
4050                         if (pipe_stats[pipe] & 0x8000ffff) {
4051                                 I915_WRITE(reg, pipe_stats[pipe]);
4052                                 irq_received = true;
4053                         }
4054                 }
4055                 spin_unlock(&dev_priv->irq_lock);
4056
4057                 if (!irq_received)
4058                         break;
4059
4060                 ret = IRQ_HANDLED;
4061
4062                 /* Consume port.  Then clear IIR or we'll miss events */
4063                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
4064                         u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4065                         if (hotplug_status)
4066                                 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4067                 }
4068
4069                 I915_WRITE(IIR, iir & ~flip_mask);
4070                 new_iir = I915_READ(IIR); /* Flush posted writes */
4071
4072                 if (iir & I915_USER_INTERRUPT)
4073                         notify_ring(dev_priv->engine[RCS]);
4074                 if (iir & I915_BSD_USER_INTERRUPT)
4075                         notify_ring(dev_priv->engine[VCS]);
4076
4077                 for_each_pipe(dev_priv, pipe) {
4078                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4079                             i915_handle_vblank(dev_priv, pipe, pipe, iir))
4080                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4081
4082                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4083                                 blc_event = true;
4084
4085                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4086                                 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4087
4088                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4089                                 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
4090                 }
4091
4092                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4093                         intel_opregion_asle_intr(dev_priv);
4094
4095                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4096                         gmbus_irq_handler(dev_priv);
4097
4098                 /* With MSI, interrupts are only generated when iir
4099                  * transitions from zero to nonzero.  If another bit got
4100                  * set while we were handling the existing iir bits, then
4101                  * we would never get another interrupt.
4102                  *
4103                  * This is fine on non-MSI as well, as if we hit this path
4104                  * we avoid exiting the interrupt handler only to generate
4105                  * another one.
4106                  *
4107                  * Note that for MSI this could cause a stray interrupt report
4108                  * if an interrupt landed in the time between writing IIR and
4109                  * the posting read.  This should be rare enough to never
4110                  * trigger the 99% of 100,000 interrupts test for disabling
4111                  * stray interrupts.
4112                  */
4113                 iir = new_iir;
4114         }
4115
4116         enable_rpm_wakeref_asserts(dev_priv);
4117
4118         return ret;
4119 }
4120
4121 static void i965_irq_uninstall(struct drm_device * dev)
4122 {
4123         struct drm_i915_private *dev_priv = to_i915(dev);
4124         int pipe;
4125
4126         if (!dev_priv)
4127                 return;
4128
4129         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4130         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4131
4132         I915_WRITE(HWSTAM, 0xffffffff);
4133         for_each_pipe(dev_priv, pipe)
4134                 I915_WRITE(PIPESTAT(pipe), 0);
4135         I915_WRITE(IMR, 0xffffffff);
4136         I915_WRITE(IER, 0x0);
4137
4138         for_each_pipe(dev_priv, pipe)
4139                 I915_WRITE(PIPESTAT(pipe),
4140                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4141         I915_WRITE(IIR, I915_READ(IIR));
4142 }
4143
4144 /**
4145  * intel_irq_init - initializes irq support
4146  * @dev_priv: i915 device instance
4147  *
4148  * This function initializes all the irq support including work items, timers
4149  * and all the vtables. It does not setup the interrupt itself though.
4150  */
4151 void intel_irq_init(struct drm_i915_private *dev_priv)
4152 {
4153         struct drm_device *dev = &dev_priv->drm;
4154
4155         intel_hpd_init_work(dev_priv);
4156
4157         INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4158         INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4159
4160         if (HAS_GUC_SCHED(dev_priv))
4161                 dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT;
4162
4163         /* Let's track the enabled rps events */
4164         if (IS_VALLEYVIEW(dev_priv))
4165                 /* WaGsvRC0ResidencyMethod:vlv */
4166                 dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED;
4167         else
4168                 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4169
4170         dev_priv->rps.pm_intr_keep = 0;
4171
4172         /*
4173          * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
4174          * if GEN6_PM_UP_EI_EXPIRED is masked.
4175          *
4176          * TODO: verify if this can be reproduced on VLV,CHV.
4177          */
4178         if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
4179                 dev_priv->rps.pm_intr_keep |= GEN6_PM_RP_UP_EI_EXPIRED;
4180
4181         if (INTEL_INFO(dev_priv)->gen >= 8)
4182                 dev_priv->rps.pm_intr_keep |= GEN8_PMINTR_REDIRECT_TO_GUC;
4183
4184         if (IS_GEN2(dev_priv)) {
4185                 /* Gen2 doesn't have a hardware frame counter */
4186                 dev->max_vblank_count = 0;
4187                 dev->driver->get_vblank_counter = drm_vblank_no_hw_counter;
4188         } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
4189                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4190                 dev->driver->get_vblank_counter = g4x_get_vblank_counter;
4191         } else {
4192                 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4193                 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4194         }
4195
4196         /*
4197          * Opt out of the vblank disable timer on everything except gen2.
4198          * Gen2 doesn't have a hardware frame counter and so depends on
4199          * vblank interrupts to produce sane vblank seuquence numbers.
4200          */
4201         if (!IS_GEN2(dev_priv))
4202                 dev->vblank_disable_immediate = true;
4203
4204         dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4205         dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4206
4207         if (IS_CHERRYVIEW(dev_priv)) {
4208                 dev->driver->irq_handler = cherryview_irq_handler;
4209                 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4210                 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4211                 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4212                 dev->driver->enable_vblank = i965_enable_vblank;
4213                 dev->driver->disable_vblank = i965_disable_vblank;
4214                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4215         } else if (IS_VALLEYVIEW(dev_priv)) {
4216                 dev->driver->irq_handler = valleyview_irq_handler;
4217                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4218                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4219                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4220                 dev->driver->enable_vblank = i965_enable_vblank;
4221                 dev->driver->disable_vblank = i965_disable_vblank;
4222                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4223         } else if (INTEL_INFO(dev_priv)->gen >= 8) {
4224                 dev->driver->irq_handler = gen8_irq_handler;
4225                 dev->driver->irq_preinstall = gen8_irq_reset;
4226                 dev->driver->irq_postinstall = gen8_irq_postinstall;
4227                 dev->driver->irq_uninstall = gen8_irq_uninstall;
4228                 dev->driver->enable_vblank = gen8_enable_vblank;
4229                 dev->driver->disable_vblank = gen8_disable_vblank;
4230                 if (IS_BROXTON(dev_priv))
4231                         dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4232                 else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
4233                         dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4234                 else
4235                         dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4236         } else if (HAS_PCH_SPLIT(dev_priv)) {
4237                 dev->driver->irq_handler = ironlake_irq_handler;
4238                 dev->driver->irq_preinstall = ironlake_irq_reset;
4239                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4240                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4241                 dev->driver->enable_vblank = ironlake_enable_vblank;
4242                 dev->driver->disable_vblank = ironlake_disable_vblank;
4243                 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4244         } else {
4245                 if (IS_GEN2(dev_priv)) {
4246                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
4247                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
4248                         dev->driver->irq_handler = i8xx_irq_handler;
4249                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
4250                         dev->driver->enable_vblank = i8xx_enable_vblank;
4251                         dev->driver->disable_vblank = i8xx_disable_vblank;
4252                 } else if (IS_GEN3(dev_priv)) {
4253                         dev->driver->irq_preinstall = i915_irq_preinstall;
4254                         dev->driver->irq_postinstall = i915_irq_postinstall;
4255                         dev->driver->irq_uninstall = i915_irq_uninstall;
4256                         dev->driver->irq_handler = i915_irq_handler;
4257                         dev->driver->enable_vblank = i8xx_enable_vblank;
4258                         dev->driver->disable_vblank = i8xx_disable_vblank;
4259                 } else {
4260                         dev->driver->irq_preinstall = i965_irq_preinstall;
4261                         dev->driver->irq_postinstall = i965_irq_postinstall;
4262                         dev->driver->irq_uninstall = i965_irq_uninstall;
4263                         dev->driver->irq_handler = i965_irq_handler;
4264                         dev->driver->enable_vblank = i965_enable_vblank;
4265                         dev->driver->disable_vblank = i965_disable_vblank;
4266                 }
4267                 if (I915_HAS_HOTPLUG(dev_priv))
4268                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4269         }
4270 }
4271
4272 /**
4273  * intel_irq_install - enables the hardware interrupt
4274  * @dev_priv: i915 device instance
4275  *
4276  * This function enables the hardware interrupt handling, but leaves the hotplug
4277  * handling still disabled. It is called after intel_irq_init().
4278  *
4279  * In the driver load and resume code we need working interrupts in a few places
4280  * but don't want to deal with the hassle of concurrent probe and hotplug
4281  * workers. Hence the split into this two-stage approach.
4282  */
4283 int intel_irq_install(struct drm_i915_private *dev_priv)
4284 {
4285         /*
4286          * We enable some interrupt sources in our postinstall hooks, so mark
4287          * interrupts as enabled _before_ actually enabling them to avoid
4288          * special cases in our ordering checks.
4289          */
4290         dev_priv->pm.irqs_enabled = true;
4291
4292         return drm_irq_install(&dev_priv->drm, dev_priv->drm.pdev->irq);
4293 }
4294
4295 /**
4296  * intel_irq_uninstall - finilizes all irq handling
4297  * @dev_priv: i915 device instance
4298  *
4299  * This stops interrupt and hotplug handling and unregisters and frees all
4300  * resources acquired in the init functions.
4301  */
4302 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4303 {
4304         drm_irq_uninstall(&dev_priv->drm);
4305         intel_hpd_cancel_work(dev_priv);
4306         dev_priv->pm.irqs_enabled = false;
4307 }
4308
4309 /**
4310  * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4311  * @dev_priv: i915 device instance
4312  *
4313  * This function is used to disable interrupts at runtime, both in the runtime
4314  * pm and the system suspend/resume code.
4315  */
4316 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4317 {
4318         dev_priv->drm.driver->irq_uninstall(&dev_priv->drm);
4319         dev_priv->pm.irqs_enabled = false;
4320         synchronize_irq(dev_priv->drm.irq);
4321 }
4322
4323 /**
4324  * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4325  * @dev_priv: i915 device instance
4326  *
4327  * This function is used to enable interrupts at runtime, both in the runtime
4328  * pm and the system suspend/resume code.
4329  */
4330 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4331 {
4332         dev_priv->pm.irqs_enabled = true;
4333         dev_priv->drm.driver->irq_preinstall(&dev_priv->drm);
4334         dev_priv->drm.driver->irq_postinstall(&dev_priv->drm);
4335 }