1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/circ_buf.h>
32 #include <linux/slab.h>
33 #include <linux/sysrq.h>
35 #include <drm/drm_drv.h>
36 #include <drm/drm_irq.h>
38 #include "display/intel_display_types.h"
39 #include "display/intel_fifo_underrun.h"
40 #include "display/intel_hotplug.h"
41 #include "display/intel_lpe_audio.h"
42 #include "display/intel_psr.h"
44 #include "gt/intel_gt.h"
45 #include "gt/intel_gt_irq.h"
46 #include "gt/intel_gt_pm_irq.h"
47 #include "gt/intel_rps.h"
51 #include "i915_trace.h"
55 * DOC: interrupt handling
57 * These functions provide the basic support for enabling and disabling the
58 * interrupt handling support. There's a lot more functionality in i915_irq.c
59 * and related files, but that will be described in separate chapters.
62 typedef bool (*long_pulse_detect_func)(enum hpd_pin pin, u32 val);
64 static const u32 hpd_ilk[HPD_NUM_PINS] = {
65 [HPD_PORT_A] = DE_DP_A_HOTPLUG,
68 static const u32 hpd_ivb[HPD_NUM_PINS] = {
69 [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
72 static const u32 hpd_bdw[HPD_NUM_PINS] = {
73 [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
76 static const u32 hpd_ibx[HPD_NUM_PINS] = {
77 [HPD_CRT] = SDE_CRT_HOTPLUG,
78 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
79 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
80 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
81 [HPD_PORT_D] = SDE_PORTD_HOTPLUG,
84 static const u32 hpd_cpt[HPD_NUM_PINS] = {
85 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
86 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
87 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
88 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
89 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
92 static const u32 hpd_spt[HPD_NUM_PINS] = {
93 [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
94 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
95 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
96 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
97 [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT,
100 static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
101 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
102 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
103 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
104 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
105 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
106 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN,
109 static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
110 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
111 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
112 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
113 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
114 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
115 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS,
118 static const u32 hpd_status_i915[HPD_NUM_PINS] = {
119 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
120 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
121 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
122 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
123 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
124 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS,
128 static const u32 hpd_bxt[HPD_NUM_PINS] = {
129 [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
130 [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
131 [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC,
134 static const u32 hpd_gen11[HPD_NUM_PINS] = {
135 [HPD_PORT_C] = GEN11_TC1_HOTPLUG | GEN11_TBT1_HOTPLUG,
136 [HPD_PORT_D] = GEN11_TC2_HOTPLUG | GEN11_TBT2_HOTPLUG,
137 [HPD_PORT_E] = GEN11_TC3_HOTPLUG | GEN11_TBT3_HOTPLUG,
138 [HPD_PORT_F] = GEN11_TC4_HOTPLUG | GEN11_TBT4_HOTPLUG,
141 static const u32 hpd_gen12[HPD_NUM_PINS] = {
142 [HPD_PORT_D] = GEN11_TC1_HOTPLUG | GEN11_TBT1_HOTPLUG,
143 [HPD_PORT_E] = GEN11_TC2_HOTPLUG | GEN11_TBT2_HOTPLUG,
144 [HPD_PORT_F] = GEN11_TC3_HOTPLUG | GEN11_TBT3_HOTPLUG,
145 [HPD_PORT_G] = GEN11_TC4_HOTPLUG | GEN11_TBT4_HOTPLUG,
146 [HPD_PORT_H] = GEN12_TC5_HOTPLUG | GEN12_TBT5_HOTPLUG,
147 [HPD_PORT_I] = GEN12_TC6_HOTPLUG | GEN12_TBT6_HOTPLUG,
150 static const u32 hpd_icp[HPD_NUM_PINS] = {
151 [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A),
152 [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B),
153 [HPD_PORT_C] = SDE_TC_HOTPLUG_ICP(PORT_TC1),
154 [HPD_PORT_D] = SDE_TC_HOTPLUG_ICP(PORT_TC2),
155 [HPD_PORT_E] = SDE_TC_HOTPLUG_ICP(PORT_TC3),
156 [HPD_PORT_F] = SDE_TC_HOTPLUG_ICP(PORT_TC4),
159 static const u32 hpd_tgp[HPD_NUM_PINS] = {
160 [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A),
161 [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B),
162 [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(PORT_C),
163 [HPD_PORT_D] = SDE_TC_HOTPLUG_ICP(PORT_TC1),
164 [HPD_PORT_E] = SDE_TC_HOTPLUG_ICP(PORT_TC2),
165 [HPD_PORT_F] = SDE_TC_HOTPLUG_ICP(PORT_TC3),
166 [HPD_PORT_G] = SDE_TC_HOTPLUG_ICP(PORT_TC4),
167 [HPD_PORT_H] = SDE_TC_HOTPLUG_ICP(PORT_TC5),
168 [HPD_PORT_I] = SDE_TC_HOTPLUG_ICP(PORT_TC6),
172 intel_handle_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
174 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
176 drm_crtc_handle_vblank(&crtc->base);
179 void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
180 i915_reg_t iir, i915_reg_t ier)
182 intel_uncore_write(uncore, imr, 0xffffffff);
183 intel_uncore_posting_read(uncore, imr);
185 intel_uncore_write(uncore, ier, 0);
187 /* IIR can theoretically queue up two events. Be paranoid. */
188 intel_uncore_write(uncore, iir, 0xffffffff);
189 intel_uncore_posting_read(uncore, iir);
190 intel_uncore_write(uncore, iir, 0xffffffff);
191 intel_uncore_posting_read(uncore, iir);
194 void gen2_irq_reset(struct intel_uncore *uncore)
196 intel_uncore_write16(uncore, GEN2_IMR, 0xffff);
197 intel_uncore_posting_read16(uncore, GEN2_IMR);
199 intel_uncore_write16(uncore, GEN2_IER, 0);
201 /* IIR can theoretically queue up two events. Be paranoid. */
202 intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
203 intel_uncore_posting_read16(uncore, GEN2_IIR);
204 intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
205 intel_uncore_posting_read16(uncore, GEN2_IIR);
209 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
211 static void gen3_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg)
213 u32 val = intel_uncore_read(uncore, reg);
218 drm_WARN(&uncore->i915->drm, 1,
219 "Interrupt register 0x%x is not zero: 0x%08x\n",
220 i915_mmio_reg_offset(reg), val);
221 intel_uncore_write(uncore, reg, 0xffffffff);
222 intel_uncore_posting_read(uncore, reg);
223 intel_uncore_write(uncore, reg, 0xffffffff);
224 intel_uncore_posting_read(uncore, reg);
227 static void gen2_assert_iir_is_zero(struct intel_uncore *uncore)
229 u16 val = intel_uncore_read16(uncore, GEN2_IIR);
234 drm_WARN(&uncore->i915->drm, 1,
235 "Interrupt register 0x%x is not zero: 0x%08x\n",
236 i915_mmio_reg_offset(GEN2_IIR), val);
237 intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
238 intel_uncore_posting_read16(uncore, GEN2_IIR);
239 intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
240 intel_uncore_posting_read16(uncore, GEN2_IIR);
243 void gen3_irq_init(struct intel_uncore *uncore,
244 i915_reg_t imr, u32 imr_val,
245 i915_reg_t ier, u32 ier_val,
248 gen3_assert_iir_is_zero(uncore, iir);
250 intel_uncore_write(uncore, ier, ier_val);
251 intel_uncore_write(uncore, imr, imr_val);
252 intel_uncore_posting_read(uncore, imr);
255 void gen2_irq_init(struct intel_uncore *uncore,
256 u32 imr_val, u32 ier_val)
258 gen2_assert_iir_is_zero(uncore);
260 intel_uncore_write16(uncore, GEN2_IER, ier_val);
261 intel_uncore_write16(uncore, GEN2_IMR, imr_val);
262 intel_uncore_posting_read16(uncore, GEN2_IMR);
265 /* For display hotplug interrupt */
267 i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
273 lockdep_assert_held(&dev_priv->irq_lock);
274 drm_WARN_ON(&dev_priv->drm, bits & ~mask);
276 val = I915_READ(PORT_HOTPLUG_EN);
279 I915_WRITE(PORT_HOTPLUG_EN, val);
283 * i915_hotplug_interrupt_update - update hotplug interrupt enable
284 * @dev_priv: driver private
285 * @mask: bits to update
286 * @bits: bits to enable
287 * NOTE: the HPD enable bits are modified both inside and outside
288 * of an interrupt context. To avoid that read-modify-write cycles
289 * interfer, these bits are protected by a spinlock. Since this
290 * function is usually not called from a context where the lock is
291 * held already, this function acquires the lock itself. A non-locking
292 * version is also available.
294 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
298 spin_lock_irq(&dev_priv->irq_lock);
299 i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
300 spin_unlock_irq(&dev_priv->irq_lock);
304 * ilk_update_display_irq - update DEIMR
305 * @dev_priv: driver private
306 * @interrupt_mask: mask of interrupt bits to update
307 * @enabled_irq_mask: mask of interrupt bits to enable
309 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
311 u32 enabled_irq_mask)
315 lockdep_assert_held(&dev_priv->irq_lock);
317 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
319 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
322 new_val = dev_priv->irq_mask;
323 new_val &= ~interrupt_mask;
324 new_val |= (~enabled_irq_mask & interrupt_mask);
326 if (new_val != dev_priv->irq_mask) {
327 dev_priv->irq_mask = new_val;
328 I915_WRITE(DEIMR, dev_priv->irq_mask);
334 * bdw_update_port_irq - update DE port interrupt
335 * @dev_priv: driver private
336 * @interrupt_mask: mask of interrupt bits to update
337 * @enabled_irq_mask: mask of interrupt bits to enable
339 static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
341 u32 enabled_irq_mask)
346 lockdep_assert_held(&dev_priv->irq_lock);
348 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
350 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
353 old_val = I915_READ(GEN8_DE_PORT_IMR);
356 new_val &= ~interrupt_mask;
357 new_val |= (~enabled_irq_mask & interrupt_mask);
359 if (new_val != old_val) {
360 I915_WRITE(GEN8_DE_PORT_IMR, new_val);
361 POSTING_READ(GEN8_DE_PORT_IMR);
366 * bdw_update_pipe_irq - update DE pipe interrupt
367 * @dev_priv: driver private
368 * @pipe: pipe whose interrupt to update
369 * @interrupt_mask: mask of interrupt bits to update
370 * @enabled_irq_mask: mask of interrupt bits to enable
372 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
375 u32 enabled_irq_mask)
379 lockdep_assert_held(&dev_priv->irq_lock);
381 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
383 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
386 new_val = dev_priv->de_irq_mask[pipe];
387 new_val &= ~interrupt_mask;
388 new_val |= (~enabled_irq_mask & interrupt_mask);
390 if (new_val != dev_priv->de_irq_mask[pipe]) {
391 dev_priv->de_irq_mask[pipe] = new_val;
392 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
393 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
398 * ibx_display_interrupt_update - update SDEIMR
399 * @dev_priv: driver private
400 * @interrupt_mask: mask of interrupt bits to update
401 * @enabled_irq_mask: mask of interrupt bits to enable
403 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
405 u32 enabled_irq_mask)
407 u32 sdeimr = I915_READ(SDEIMR);
408 sdeimr &= ~interrupt_mask;
409 sdeimr |= (~enabled_irq_mask & interrupt_mask);
411 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
413 lockdep_assert_held(&dev_priv->irq_lock);
415 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
418 I915_WRITE(SDEIMR, sdeimr);
419 POSTING_READ(SDEIMR);
422 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
425 u32 status_mask = dev_priv->pipestat_irq_mask[pipe];
426 u32 enable_mask = status_mask << 16;
428 lockdep_assert_held(&dev_priv->irq_lock);
430 if (INTEL_GEN(dev_priv) < 5)
434 * On pipe A we don't support the PSR interrupt yet,
435 * on pipe B and C the same bit MBZ.
437 if (drm_WARN_ON_ONCE(&dev_priv->drm,
438 status_mask & PIPE_A_PSR_STATUS_VLV))
441 * On pipe B and C we don't support the PSR interrupt yet, on pipe
442 * A the same bit is for perf counters which we don't use either.
444 if (drm_WARN_ON_ONCE(&dev_priv->drm,
445 status_mask & PIPE_B_PSR_STATUS_VLV))
448 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
449 SPRITE0_FLIP_DONE_INT_EN_VLV |
450 SPRITE1_FLIP_DONE_INT_EN_VLV);
451 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
452 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
453 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
454 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
457 drm_WARN_ONCE(&dev_priv->drm,
458 enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
459 status_mask & ~PIPESTAT_INT_STATUS_MASK,
460 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
461 pipe_name(pipe), enable_mask, status_mask);
466 void i915_enable_pipestat(struct drm_i915_private *dev_priv,
467 enum pipe pipe, u32 status_mask)
469 i915_reg_t reg = PIPESTAT(pipe);
472 drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,
473 "pipe %c: status_mask=0x%x\n",
474 pipe_name(pipe), status_mask);
476 lockdep_assert_held(&dev_priv->irq_lock);
477 drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv));
479 if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == status_mask)
482 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
483 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
485 I915_WRITE(reg, enable_mask | status_mask);
489 void i915_disable_pipestat(struct drm_i915_private *dev_priv,
490 enum pipe pipe, u32 status_mask)
492 i915_reg_t reg = PIPESTAT(pipe);
495 drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,
496 "pipe %c: status_mask=0x%x\n",
497 pipe_name(pipe), status_mask);
499 lockdep_assert_held(&dev_priv->irq_lock);
500 drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv));
502 if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == 0)
505 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
506 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
508 I915_WRITE(reg, enable_mask | status_mask);
512 static bool i915_has_asle(struct drm_i915_private *dev_priv)
514 if (!dev_priv->opregion.asle)
517 return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
521 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
522 * @dev_priv: i915 device private
524 static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
526 if (!i915_has_asle(dev_priv))
529 spin_lock_irq(&dev_priv->irq_lock);
531 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
532 if (INTEL_GEN(dev_priv) >= 4)
533 i915_enable_pipestat(dev_priv, PIPE_A,
534 PIPE_LEGACY_BLC_EVENT_STATUS);
536 spin_unlock_irq(&dev_priv->irq_lock);
540 * This timing diagram depicts the video signal in and
541 * around the vertical blanking period.
543 * Assumptions about the fictitious mode used in this example:
545 * vsync_start = vblank_start + 1
546 * vsync_end = vblank_start + 2
547 * vtotal = vblank_start + 3
550 * latch double buffered registers
551 * increment frame counter (ctg+)
552 * generate start of vblank interrupt (gen4+)
555 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
556 * | may be shifted forward 1-3 extra lines via PIPECONF
558 * | | start of vsync:
559 * | | generate vsync interrupt
561 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
562 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
563 * ----va---> <-----------------vb--------------------> <--------va-------------
564 * | | <----vs-----> |
565 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
566 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
567 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
569 * last visible pixel first visible pixel
570 * | increment frame counter (gen3/4)
571 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
573 * x = horizontal active
574 * _ = horizontal blanking
575 * hs = horizontal sync
576 * va = vertical active
577 * vb = vertical blanking
579 * vbs = vblank_start (number)
582 * - most events happen at the start of horizontal sync
583 * - frame start happens at the start of horizontal blank, 1-4 lines
584 * (depending on PIPECONF settings) after the start of vblank
585 * - gen3/4 pixel and frame counter are synchronized with the start
586 * of horizontal active on the first line of vertical active
589 /* Called from drm generic code, passed a 'crtc', which
590 * we use as a pipe index
592 u32 i915_get_vblank_counter(struct drm_crtc *crtc)
594 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
595 struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)];
596 const struct drm_display_mode *mode = &vblank->hwmode;
597 enum pipe pipe = to_intel_crtc(crtc)->pipe;
598 i915_reg_t high_frame, low_frame;
599 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
600 unsigned long irqflags;
603 * On i965gm TV output the frame counter only works up to
604 * the point when we enable the TV encoder. After that the
605 * frame counter ceases to work and reads zero. We need a
606 * vblank wait before enabling the TV encoder and so we
607 * have to enable vblank interrupts while the frame counter
608 * is still in a working state. However the core vblank code
609 * does not like us returning non-zero frame counter values
610 * when we've told it that we don't have a working frame
611 * counter. Thus we must stop non-zero values leaking out.
613 if (!vblank->max_vblank_count)
616 htotal = mode->crtc_htotal;
617 hsync_start = mode->crtc_hsync_start;
618 vbl_start = mode->crtc_vblank_start;
619 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
620 vbl_start = DIV_ROUND_UP(vbl_start, 2);
622 /* Convert to pixel count */
625 /* Start of vblank event occurs at start of hsync */
626 vbl_start -= htotal - hsync_start;
628 high_frame = PIPEFRAME(pipe);
629 low_frame = PIPEFRAMEPIXEL(pipe);
631 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
634 * High & low register fields aren't synchronized, so make sure
635 * we get a low value that's stable across two reads of the high
639 high1 = intel_de_read_fw(dev_priv, high_frame) & PIPE_FRAME_HIGH_MASK;
640 low = intel_de_read_fw(dev_priv, low_frame);
641 high2 = intel_de_read_fw(dev_priv, high_frame) & PIPE_FRAME_HIGH_MASK;
642 } while (high1 != high2);
644 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
646 high1 >>= PIPE_FRAME_HIGH_SHIFT;
647 pixel = low & PIPE_PIXEL_MASK;
648 low >>= PIPE_FRAME_LOW_SHIFT;
651 * The frame counter increments at beginning of active.
652 * Cook up a vblank counter by also checking the pixel
653 * counter against vblank start.
655 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
658 u32 g4x_get_vblank_counter(struct drm_crtc *crtc)
660 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
661 enum pipe pipe = to_intel_crtc(crtc)->pipe;
663 return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
667 * On certain encoders on certain platforms, pipe
668 * scanline register will not work to get the scanline,
669 * since the timings are driven from the PORT or issues
670 * with scanline register updates.
671 * This function will use Framestamp and current
672 * timestamp registers to calculate the scanline.
674 static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)
676 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
677 struct drm_vblank_crtc *vblank =
678 &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
679 const struct drm_display_mode *mode = &vblank->hwmode;
680 u32 vblank_start = mode->crtc_vblank_start;
681 u32 vtotal = mode->crtc_vtotal;
682 u32 htotal = mode->crtc_htotal;
683 u32 clock = mode->crtc_clock;
684 u32 scanline, scan_prev_time, scan_curr_time, scan_post_time;
687 * To avoid the race condition where we might cross into the
688 * next vblank just between the PIPE_FRMTMSTMP and TIMESTAMP_CTR
689 * reads. We make sure we read PIPE_FRMTMSTMP and TIMESTAMP_CTR
690 * during the same frame.
694 * This field provides read back of the display
695 * pipe frame time stamp. The time stamp value
696 * is sampled at every start of vertical blank.
698 scan_prev_time = intel_de_read_fw(dev_priv,
699 PIPE_FRMTMSTMP(crtc->pipe));
702 * The TIMESTAMP_CTR register has the current
705 scan_curr_time = intel_de_read_fw(dev_priv, IVB_TIMESTAMP_CTR);
707 scan_post_time = intel_de_read_fw(dev_priv,
708 PIPE_FRMTMSTMP(crtc->pipe));
709 } while (scan_post_time != scan_prev_time);
711 scanline = div_u64(mul_u32_u32(scan_curr_time - scan_prev_time,
712 clock), 1000 * htotal);
713 scanline = min(scanline, vtotal - 1);
714 scanline = (scanline + vblank_start) % vtotal;
720 * intel_de_read_fw(), only for fast reads of display block, no need for
723 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
725 struct drm_device *dev = crtc->base.dev;
726 struct drm_i915_private *dev_priv = to_i915(dev);
727 const struct drm_display_mode *mode;
728 struct drm_vblank_crtc *vblank;
729 enum pipe pipe = crtc->pipe;
730 int position, vtotal;
735 vblank = &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
736 mode = &vblank->hwmode;
738 if (mode->private_flags & I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP)
739 return __intel_get_crtc_scanline_from_timestamp(crtc);
741 vtotal = mode->crtc_vtotal;
742 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
745 if (IS_GEN(dev_priv, 2))
746 position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
748 position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
751 * On HSW, the DSL reg (0x70000) appears to return 0 if we
752 * read it just before the start of vblank. So try it again
753 * so we don't accidentally end up spanning a vblank frame
754 * increment, causing the pipe_update_end() code to squak at us.
756 * The nature of this problem means we can't simply check the ISR
757 * bit and return the vblank start value; nor can we use the scanline
758 * debug register in the transcoder as it appears to have the same
759 * problem. We may need to extend this to include other platforms,
760 * but so far testing only shows the problem on HSW.
762 if (HAS_DDI(dev_priv) && !position) {
765 for (i = 0; i < 100; i++) {
767 temp = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
768 if (temp != position) {
776 * See update_scanline_offset() for the details on the
777 * scanline_offset adjustment.
779 return (position + crtc->scanline_offset) % vtotal;
782 static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
784 int *vpos, int *hpos,
785 ktime_t *stime, ktime_t *etime,
786 const struct drm_display_mode *mode)
788 struct drm_device *dev = _crtc->dev;
789 struct drm_i915_private *dev_priv = to_i915(dev);
790 struct intel_crtc *crtc = to_intel_crtc(_crtc);
791 enum pipe pipe = crtc->pipe;
793 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
794 unsigned long irqflags;
795 bool use_scanline_counter = INTEL_GEN(dev_priv) >= 5 ||
796 IS_G4X(dev_priv) || IS_GEN(dev_priv, 2) ||
797 mode->private_flags & I915_MODE_FLAG_USE_SCANLINE_COUNTER;
799 if (drm_WARN_ON(&dev_priv->drm, !mode->crtc_clock)) {
800 drm_dbg(&dev_priv->drm,
801 "trying to get scanoutpos for disabled "
802 "pipe %c\n", pipe_name(pipe));
806 htotal = mode->crtc_htotal;
807 hsync_start = mode->crtc_hsync_start;
808 vtotal = mode->crtc_vtotal;
809 vbl_start = mode->crtc_vblank_start;
810 vbl_end = mode->crtc_vblank_end;
812 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
813 vbl_start = DIV_ROUND_UP(vbl_start, 2);
819 * Lock uncore.lock, as we will do multiple timing critical raw
820 * register reads, potentially with preemption disabled, so the
821 * following code must not block on uncore.lock.
823 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
825 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
827 /* Get optional system timestamp before query. */
829 *stime = ktime_get();
831 if (use_scanline_counter) {
832 /* No obvious pixelcount register. Only query vertical
833 * scanout position from Display scan line register.
835 position = __intel_get_crtc_scanline(crtc);
837 /* Have access to pixelcount since start of frame.
838 * We can split this into vertical and horizontal
841 position = (intel_de_read_fw(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
843 /* convert to pixel counts */
849 * In interlaced modes, the pixel counter counts all pixels,
850 * so one field will have htotal more pixels. In order to avoid
851 * the reported position from jumping backwards when the pixel
852 * counter is beyond the length of the shorter field, just
853 * clamp the position the length of the shorter field. This
854 * matches how the scanline counter based position works since
855 * the scanline counter doesn't count the two half lines.
857 if (position >= vtotal)
858 position = vtotal - 1;
861 * Start of vblank interrupt is triggered at start of hsync,
862 * just prior to the first active line of vblank. However we
863 * consider lines to start at the leading edge of horizontal
864 * active. So, should we get here before we've crossed into
865 * the horizontal active of the first line in vblank, we would
866 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
867 * always add htotal-hsync_start to the current pixel position.
869 position = (position + htotal - hsync_start) % vtotal;
872 /* Get optional system timestamp after query. */
874 *etime = ktime_get();
876 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
878 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
881 * While in vblank, position will be negative
882 * counting up towards 0 at vbl_end. And outside
883 * vblank, position will be positive counting
886 if (position >= vbl_start)
889 position += vtotal - vbl_end;
891 if (use_scanline_counter) {
895 *vpos = position / htotal;
896 *hpos = position - (*vpos * htotal);
902 bool intel_crtc_get_vblank_timestamp(struct drm_crtc *crtc, int *max_error,
903 ktime_t *vblank_time, bool in_vblank_irq)
905 return drm_crtc_vblank_helper_get_vblank_timestamp_internal(
906 crtc, max_error, vblank_time, in_vblank_irq,
907 i915_get_crtc_scanoutpos);
910 int intel_get_crtc_scanline(struct intel_crtc *crtc)
912 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
913 unsigned long irqflags;
916 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
917 position = __intel_get_crtc_scanline(crtc);
918 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
924 * ivb_parity_work - Workqueue called when a parity error interrupt
926 * @work: workqueue struct
928 * Doesn't actually do anything except notify userspace. As a consequence of
929 * this event, userspace should try to remap the bad rows since statistically
930 * it is likely the same row is more likely to go bad again.
932 static void ivb_parity_work(struct work_struct *work)
934 struct drm_i915_private *dev_priv =
935 container_of(work, typeof(*dev_priv), l3_parity.error_work);
936 struct intel_gt *gt = &dev_priv->gt;
937 u32 error_status, row, bank, subbank;
938 char *parity_event[6];
942 /* We must turn off DOP level clock gating to access the L3 registers.
943 * In order to prevent a get/put style interface, acquire struct mutex
944 * any time we access those registers.
946 mutex_lock(&dev_priv->drm.struct_mutex);
948 /* If we've screwed up tracking, just let the interrupt fire again */
949 if (drm_WARN_ON(&dev_priv->drm, !dev_priv->l3_parity.which_slice))
952 misccpctl = I915_READ(GEN7_MISCCPCTL);
953 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
954 POSTING_READ(GEN7_MISCCPCTL);
956 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
960 if (drm_WARN_ON_ONCE(&dev_priv->drm,
961 slice >= NUM_L3_SLICES(dev_priv)))
964 dev_priv->l3_parity.which_slice &= ~(1<<slice);
966 reg = GEN7_L3CDERRST1(slice);
968 error_status = I915_READ(reg);
969 row = GEN7_PARITY_ERROR_ROW(error_status);
970 bank = GEN7_PARITY_ERROR_BANK(error_status);
971 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
973 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
976 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
977 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
978 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
979 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
980 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
981 parity_event[5] = NULL;
983 kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj,
984 KOBJ_CHANGE, parity_event);
986 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
987 slice, row, bank, subbank);
989 kfree(parity_event[4]);
990 kfree(parity_event[3]);
991 kfree(parity_event[2]);
992 kfree(parity_event[1]);
995 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
998 drm_WARN_ON(&dev_priv->drm, dev_priv->l3_parity.which_slice);
999 spin_lock_irq(>->irq_lock);
1000 gen5_gt_enable_irq(gt, GT_PARITY_ERROR(dev_priv));
1001 spin_unlock_irq(>->irq_lock);
1003 mutex_unlock(&dev_priv->drm.struct_mutex);
1006 static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1010 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC1);
1012 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC2);
1014 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC3);
1016 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC4);
1022 static bool gen12_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1026 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC1);
1028 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC2);
1030 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC3);
1032 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC4);
1034 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC5);
1036 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC6);
1042 static bool bxt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1046 return val & PORTA_HOTPLUG_LONG_DETECT;
1048 return val & PORTB_HOTPLUG_LONG_DETECT;
1050 return val & PORTC_HOTPLUG_LONG_DETECT;
1056 static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1060 return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_A);
1062 return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_B);
1064 return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_C);
1070 static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1074 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
1076 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
1078 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
1080 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
1086 static bool tgp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1090 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
1092 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
1094 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
1096 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
1098 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC5);
1100 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC6);
1106 static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val)
1110 return val & PORTE_HOTPLUG_LONG_DETECT;
1116 static bool spt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1120 return val & PORTA_HOTPLUG_LONG_DETECT;
1122 return val & PORTB_HOTPLUG_LONG_DETECT;
1124 return val & PORTC_HOTPLUG_LONG_DETECT;
1126 return val & PORTD_HOTPLUG_LONG_DETECT;
1132 static bool ilk_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1136 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
1142 static bool pch_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1146 return val & PORTB_HOTPLUG_LONG_DETECT;
1148 return val & PORTC_HOTPLUG_LONG_DETECT;
1150 return val & PORTD_HOTPLUG_LONG_DETECT;
1156 static bool i9xx_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1160 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1162 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1164 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1171 * Get a bit mask of pins that have triggered, and which ones may be long.
1172 * This can be called multiple times with the same masks to accumulate
1173 * hotplug detection results from several registers.
1175 * Note that the caller is expected to zero out the masks initially.
1177 static void intel_get_hpd_pins(struct drm_i915_private *dev_priv,
1178 u32 *pin_mask, u32 *long_mask,
1179 u32 hotplug_trigger, u32 dig_hotplug_reg,
1180 const u32 hpd[HPD_NUM_PINS],
1181 bool long_pulse_detect(enum hpd_pin pin, u32 val))
1185 BUILD_BUG_ON(BITS_PER_TYPE(*pin_mask) < HPD_NUM_PINS);
1187 for_each_hpd_pin(pin) {
1188 if ((hpd[pin] & hotplug_trigger) == 0)
1191 *pin_mask |= BIT(pin);
1193 if (long_pulse_detect(pin, dig_hotplug_reg))
1194 *long_mask |= BIT(pin);
1197 drm_dbg(&dev_priv->drm,
1198 "hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x, long 0x%08x\n",
1199 hotplug_trigger, dig_hotplug_reg, *pin_mask, *long_mask);
1203 static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
1205 wake_up_all(&dev_priv->gmbus_wait_queue);
1208 static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
1210 wake_up_all(&dev_priv->gmbus_wait_queue);
1213 #if defined(CONFIG_DEBUG_FS)
1214 static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1220 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1221 struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
1222 u32 crcs[5] = { crc0, crc1, crc2, crc3, crc4 };
1224 trace_intel_pipe_crc(crtc, crcs);
1226 spin_lock(&pipe_crc->lock);
1228 * For some not yet identified reason, the first CRC is
1229 * bonkers. So let's just wait for the next vblank and read
1230 * out the buggy result.
1232 * On GEN8+ sometimes the second CRC is bonkers as well, so
1233 * don't trust that one either.
1235 if (pipe_crc->skipped <= 0 ||
1236 (INTEL_GEN(dev_priv) >= 8 && pipe_crc->skipped == 1)) {
1237 pipe_crc->skipped++;
1238 spin_unlock(&pipe_crc->lock);
1241 spin_unlock(&pipe_crc->lock);
1243 drm_crtc_add_crc_entry(&crtc->base, true,
1244 drm_crtc_accurate_vblank_count(&crtc->base),
1249 display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1257 static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1260 display_pipe_crc_irq_handler(dev_priv, pipe,
1261 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1265 static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1268 display_pipe_crc_irq_handler(dev_priv, pipe,
1269 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1270 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1271 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1272 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1273 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1276 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1281 if (INTEL_GEN(dev_priv) >= 3)
1282 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1286 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1287 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1291 display_pipe_crc_irq_handler(dev_priv, pipe,
1292 I915_READ(PIPE_CRC_RES_RED(pipe)),
1293 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1294 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1298 static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
1302 for_each_pipe(dev_priv, pipe) {
1303 I915_WRITE(PIPESTAT(pipe),
1304 PIPESTAT_INT_STATUS_MASK |
1305 PIPE_FIFO_UNDERRUN_STATUS);
1307 dev_priv->pipestat_irq_mask[pipe] = 0;
1311 static void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,
1312 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1316 spin_lock(&dev_priv->irq_lock);
1318 if (!dev_priv->display_irqs_enabled) {
1319 spin_unlock(&dev_priv->irq_lock);
1323 for_each_pipe(dev_priv, pipe) {
1325 u32 status_mask, enable_mask, iir_bit = 0;
1328 * PIPESTAT bits get signalled even when the interrupt is
1329 * disabled with the mask bits, and some of the status bits do
1330 * not generate interrupts at all (like the underrun bit). Hence
1331 * we need to be careful that we only handle what we want to
1335 /* fifo underruns are filterered in the underrun handler. */
1336 status_mask = PIPE_FIFO_UNDERRUN_STATUS;
1341 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1344 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1347 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1351 status_mask |= dev_priv->pipestat_irq_mask[pipe];
1356 reg = PIPESTAT(pipe);
1357 pipe_stats[pipe] = I915_READ(reg) & status_mask;
1358 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
1361 * Clear the PIPE*STAT regs before the IIR
1363 * Toggle the enable bits to make sure we get an
1364 * edge in the ISR pipe event bit if we don't clear
1365 * all the enabled status bits. Otherwise the edge
1366 * triggered IIR on i965/g4x wouldn't notice that
1367 * an interrupt is still pending.
1369 if (pipe_stats[pipe]) {
1370 I915_WRITE(reg, pipe_stats[pipe]);
1371 I915_WRITE(reg, enable_mask);
1374 spin_unlock(&dev_priv->irq_lock);
1377 static void i8xx_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1378 u16 iir, u32 pipe_stats[I915_MAX_PIPES])
1382 for_each_pipe(dev_priv, pipe) {
1383 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1384 intel_handle_vblank(dev_priv, pipe);
1386 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1387 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1389 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1390 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1394 static void i915_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1395 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1397 bool blc_event = false;
1400 for_each_pipe(dev_priv, pipe) {
1401 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1402 intel_handle_vblank(dev_priv, pipe);
1404 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1407 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1408 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1410 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1411 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1414 if (blc_event || (iir & I915_ASLE_INTERRUPT))
1415 intel_opregion_asle_intr(dev_priv);
1418 static void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1419 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1421 bool blc_event = false;
1424 for_each_pipe(dev_priv, pipe) {
1425 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1426 intel_handle_vblank(dev_priv, pipe);
1428 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1431 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1432 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1434 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1435 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1438 if (blc_event || (iir & I915_ASLE_INTERRUPT))
1439 intel_opregion_asle_intr(dev_priv);
1441 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1442 gmbus_irq_handler(dev_priv);
1445 static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1446 u32 pipe_stats[I915_MAX_PIPES])
1450 for_each_pipe(dev_priv, pipe) {
1451 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1452 intel_handle_vblank(dev_priv, pipe);
1454 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1455 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1457 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1458 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1461 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1462 gmbus_irq_handler(dev_priv);
1465 static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
1467 u32 hotplug_status = 0, hotplug_status_mask;
1470 if (IS_G4X(dev_priv) ||
1471 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1472 hotplug_status_mask = HOTPLUG_INT_STATUS_G4X |
1473 DP_AUX_CHANNEL_MASK_INT_STATUS_G4X;
1475 hotplug_status_mask = HOTPLUG_INT_STATUS_I915;
1478 * We absolutely have to clear all the pending interrupt
1479 * bits in PORT_HOTPLUG_STAT. Otherwise the ISR port
1480 * interrupt bit won't have an edge, and the i965/g4x
1481 * edge triggered IIR will not notice that an interrupt
1482 * is still pending. We can't use PORT_HOTPLUG_EN to
1483 * guarantee the edge as the act of toggling the enable
1484 * bits can itself generate a new hotplug interrupt :(
1486 for (i = 0; i < 10; i++) {
1487 u32 tmp = I915_READ(PORT_HOTPLUG_STAT) & hotplug_status_mask;
1490 return hotplug_status;
1492 hotplug_status |= tmp;
1493 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1496 drm_WARN_ONCE(&dev_priv->drm, 1,
1497 "PORT_HOTPLUG_STAT did not clear (0x%08x)\n",
1498 I915_READ(PORT_HOTPLUG_STAT));
1500 return hotplug_status;
1503 static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1506 u32 pin_mask = 0, long_mask = 0;
1508 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
1509 IS_CHERRYVIEW(dev_priv)) {
1510 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1512 if (hotplug_trigger) {
1513 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1514 hotplug_trigger, hotplug_trigger,
1516 i9xx_port_hotplug_long_detect);
1518 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1521 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1522 dp_aux_irq_handler(dev_priv);
1524 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1526 if (hotplug_trigger) {
1527 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1528 hotplug_trigger, hotplug_trigger,
1530 i9xx_port_hotplug_long_detect);
1531 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1536 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1538 struct drm_i915_private *dev_priv = arg;
1539 irqreturn_t ret = IRQ_NONE;
1541 if (!intel_irqs_enabled(dev_priv))
1544 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1545 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1548 u32 iir, gt_iir, pm_iir;
1549 u32 pipe_stats[I915_MAX_PIPES] = {};
1550 u32 hotplug_status = 0;
1553 gt_iir = I915_READ(GTIIR);
1554 pm_iir = I915_READ(GEN6_PMIIR);
1555 iir = I915_READ(VLV_IIR);
1557 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1563 * Theory on interrupt generation, based on empirical evidence:
1565 * x = ((VLV_IIR & VLV_IER) ||
1566 * (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
1567 * (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
1569 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1570 * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
1571 * guarantee the CPU interrupt will be raised again even if we
1572 * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
1573 * bits this time around.
1575 I915_WRITE(VLV_MASTER_IER, 0);
1576 ier = I915_READ(VLV_IER);
1577 I915_WRITE(VLV_IER, 0);
1580 I915_WRITE(GTIIR, gt_iir);
1582 I915_WRITE(GEN6_PMIIR, pm_iir);
1584 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1585 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1587 /* Call regardless, as some status bits might not be
1588 * signalled in iir */
1589 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1591 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
1592 I915_LPE_PIPE_B_INTERRUPT))
1593 intel_lpe_audio_irq_handler(dev_priv);
1596 * VLV_IIR is single buffered, and reflects the level
1597 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1600 I915_WRITE(VLV_IIR, iir);
1602 I915_WRITE(VLV_IER, ier);
1603 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1606 gen6_gt_irq_handler(&dev_priv->gt, gt_iir);
1608 gen6_rps_irq_handler(&dev_priv->gt.rps, pm_iir);
1611 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1613 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1616 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1621 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1623 struct drm_i915_private *dev_priv = arg;
1624 irqreturn_t ret = IRQ_NONE;
1626 if (!intel_irqs_enabled(dev_priv))
1629 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1630 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1633 u32 master_ctl, iir;
1634 u32 pipe_stats[I915_MAX_PIPES] = {};
1635 u32 hotplug_status = 0;
1638 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1639 iir = I915_READ(VLV_IIR);
1641 if (master_ctl == 0 && iir == 0)
1647 * Theory on interrupt generation, based on empirical evidence:
1649 * x = ((VLV_IIR & VLV_IER) ||
1650 * ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
1651 * (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
1653 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1654 * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
1655 * guarantee the CPU interrupt will be raised again even if we
1656 * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
1657 * bits this time around.
1659 I915_WRITE(GEN8_MASTER_IRQ, 0);
1660 ier = I915_READ(VLV_IER);
1661 I915_WRITE(VLV_IER, 0);
1663 gen8_gt_irq_handler(&dev_priv->gt, master_ctl);
1665 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1666 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1668 /* Call regardless, as some status bits might not be
1669 * signalled in iir */
1670 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1672 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
1673 I915_LPE_PIPE_B_INTERRUPT |
1674 I915_LPE_PIPE_C_INTERRUPT))
1675 intel_lpe_audio_irq_handler(dev_priv);
1678 * VLV_IIR is single buffered, and reflects the level
1679 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1682 I915_WRITE(VLV_IIR, iir);
1684 I915_WRITE(VLV_IER, ier);
1685 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
1688 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1690 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1693 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1698 static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1699 u32 hotplug_trigger,
1700 const u32 hpd[HPD_NUM_PINS])
1702 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
1705 * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
1706 * unless we touch the hotplug register, even if hotplug_trigger is
1707 * zero. Not acking leads to "The master control interrupt lied (SDE)!"
1710 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1711 if (!hotplug_trigger) {
1712 u32 mask = PORTA_HOTPLUG_STATUS_MASK |
1713 PORTD_HOTPLUG_STATUS_MASK |
1714 PORTC_HOTPLUG_STATUS_MASK |
1715 PORTB_HOTPLUG_STATUS_MASK;
1716 dig_hotplug_reg &= ~mask;
1719 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1720 if (!hotplug_trigger)
1723 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
1724 dig_hotplug_reg, hpd,
1725 pch_port_hotplug_long_detect);
1727 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1730 static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1733 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1735 ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ibx);
1737 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1738 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1739 SDE_AUDIO_POWER_SHIFT);
1740 drm_dbg(&dev_priv->drm, "PCH audio power change on port %d\n",
1744 if (pch_iir & SDE_AUX_MASK)
1745 dp_aux_irq_handler(dev_priv);
1747 if (pch_iir & SDE_GMBUS)
1748 gmbus_irq_handler(dev_priv);
1750 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1751 drm_dbg(&dev_priv->drm, "PCH HDCP audio interrupt\n");
1753 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1754 drm_dbg(&dev_priv->drm, "PCH transcoder audio interrupt\n");
1756 if (pch_iir & SDE_POISON)
1757 drm_err(&dev_priv->drm, "PCH poison interrupt\n");
1759 if (pch_iir & SDE_FDI_MASK) {
1760 for_each_pipe(dev_priv, pipe)
1761 drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n",
1763 I915_READ(FDI_RX_IIR(pipe)));
1766 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1767 drm_dbg(&dev_priv->drm, "PCH transcoder CRC done interrupt\n");
1769 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1770 drm_dbg(&dev_priv->drm,
1771 "PCH transcoder CRC error interrupt\n");
1773 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1774 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A);
1776 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1777 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B);
1780 static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
1782 u32 err_int = I915_READ(GEN7_ERR_INT);
1785 if (err_int & ERR_INT_POISON)
1786 drm_err(&dev_priv->drm, "Poison interrupt\n");
1788 for_each_pipe(dev_priv, pipe) {
1789 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
1790 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1792 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1793 if (IS_IVYBRIDGE(dev_priv))
1794 ivb_pipe_crc_irq_handler(dev_priv, pipe);
1796 hsw_pipe_crc_irq_handler(dev_priv, pipe);
1800 I915_WRITE(GEN7_ERR_INT, err_int);
1803 static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
1805 u32 serr_int = I915_READ(SERR_INT);
1808 if (serr_int & SERR_INT_POISON)
1809 drm_err(&dev_priv->drm, "PCH poison interrupt\n");
1811 for_each_pipe(dev_priv, pipe)
1812 if (serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pipe))
1813 intel_pch_fifo_underrun_irq_handler(dev_priv, pipe);
1815 I915_WRITE(SERR_INT, serr_int);
1818 static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1821 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1823 ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_cpt);
1825 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1826 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1827 SDE_AUDIO_POWER_SHIFT_CPT);
1828 drm_dbg(&dev_priv->drm, "PCH audio power change on port %c\n",
1832 if (pch_iir & SDE_AUX_MASK_CPT)
1833 dp_aux_irq_handler(dev_priv);
1835 if (pch_iir & SDE_GMBUS_CPT)
1836 gmbus_irq_handler(dev_priv);
1838 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1839 drm_dbg(&dev_priv->drm, "Audio CP request interrupt\n");
1841 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1842 drm_dbg(&dev_priv->drm, "Audio CP change interrupt\n");
1844 if (pch_iir & SDE_FDI_MASK_CPT) {
1845 for_each_pipe(dev_priv, pipe)
1846 drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n",
1848 I915_READ(FDI_RX_IIR(pipe)));
1851 if (pch_iir & SDE_ERROR_CPT)
1852 cpt_serr_int_handler(dev_priv);
1855 static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1857 u32 ddi_hotplug_trigger, tc_hotplug_trigger;
1858 u32 pin_mask = 0, long_mask = 0;
1859 bool (*tc_port_hotplug_long_detect)(enum hpd_pin pin, u32 val);
1862 if (HAS_PCH_TGP(dev_priv)) {
1863 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
1864 tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
1865 tc_port_hotplug_long_detect = tgp_tc_port_hotplug_long_detect;
1867 } else if (HAS_PCH_JSP(dev_priv)) {
1868 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
1869 tc_hotplug_trigger = 0;
1871 } else if (HAS_PCH_MCC(dev_priv)) {
1872 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
1873 tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(PORT_TC1);
1874 tc_port_hotplug_long_detect = icp_tc_port_hotplug_long_detect;
1877 drm_WARN(&dev_priv->drm, !HAS_PCH_ICP(dev_priv),
1878 "Unrecognized PCH type 0x%x\n",
1879 INTEL_PCH_TYPE(dev_priv));
1881 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
1882 tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
1883 tc_port_hotplug_long_detect = icp_tc_port_hotplug_long_detect;
1887 if (ddi_hotplug_trigger) {
1888 u32 dig_hotplug_reg;
1890 dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI);
1891 I915_WRITE(SHOTPLUG_CTL_DDI, dig_hotplug_reg);
1893 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1894 ddi_hotplug_trigger,
1895 dig_hotplug_reg, pins,
1896 icp_ddi_port_hotplug_long_detect);
1899 if (tc_hotplug_trigger) {
1900 u32 dig_hotplug_reg;
1902 dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC);
1903 I915_WRITE(SHOTPLUG_CTL_TC, dig_hotplug_reg);
1905 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1907 dig_hotplug_reg, pins,
1908 tc_port_hotplug_long_detect);
1912 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1914 if (pch_iir & SDE_GMBUS_ICP)
1915 gmbus_irq_handler(dev_priv);
1918 static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1920 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
1921 ~SDE_PORTE_HOTPLUG_SPT;
1922 u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
1923 u32 pin_mask = 0, long_mask = 0;
1925 if (hotplug_trigger) {
1926 u32 dig_hotplug_reg;
1928 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1929 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1931 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1932 hotplug_trigger, dig_hotplug_reg, hpd_spt,
1933 spt_port_hotplug_long_detect);
1936 if (hotplug2_trigger) {
1937 u32 dig_hotplug_reg;
1939 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
1940 I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
1942 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1943 hotplug2_trigger, dig_hotplug_reg, hpd_spt,
1944 spt_port_hotplug2_long_detect);
1948 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1950 if (pch_iir & SDE_GMBUS_CPT)
1951 gmbus_irq_handler(dev_priv);
1954 static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
1955 u32 hotplug_trigger,
1956 const u32 hpd[HPD_NUM_PINS])
1958 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
1960 dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
1961 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
1963 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
1964 dig_hotplug_reg, hpd,
1965 ilk_port_hotplug_long_detect);
1967 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1970 static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
1974 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
1976 if (hotplug_trigger)
1977 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk);
1979 if (de_iir & DE_AUX_CHANNEL_A)
1980 dp_aux_irq_handler(dev_priv);
1982 if (de_iir & DE_GSE)
1983 intel_opregion_asle_intr(dev_priv);
1985 if (de_iir & DE_POISON)
1986 drm_err(&dev_priv->drm, "Poison interrupt\n");
1988 for_each_pipe(dev_priv, pipe) {
1989 if (de_iir & DE_PIPE_VBLANK(pipe))
1990 intel_handle_vblank(dev_priv, pipe);
1992 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
1993 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1995 if (de_iir & DE_PIPE_CRC_DONE(pipe))
1996 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1999 /* check event from PCH */
2000 if (de_iir & DE_PCH_EVENT) {
2001 u32 pch_iir = I915_READ(SDEIIR);
2003 if (HAS_PCH_CPT(dev_priv))
2004 cpt_irq_handler(dev_priv, pch_iir);
2006 ibx_irq_handler(dev_priv, pch_iir);
2008 /* should clear PCH hotplug event before clear CPU irq */
2009 I915_WRITE(SDEIIR, pch_iir);
2012 if (IS_GEN(dev_priv, 5) && de_iir & DE_PCU_EVENT)
2013 gen5_rps_irq_handler(&dev_priv->gt.rps);
2016 static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
2020 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2022 if (hotplug_trigger)
2023 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb);
2025 if (de_iir & DE_ERR_INT_IVB)
2026 ivb_err_int_handler(dev_priv);
2028 if (de_iir & DE_EDP_PSR_INT_HSW) {
2029 u32 psr_iir = I915_READ(EDP_PSR_IIR);
2031 intel_psr_irq_handler(dev_priv, psr_iir);
2032 I915_WRITE(EDP_PSR_IIR, psr_iir);
2035 if (de_iir & DE_AUX_CHANNEL_A_IVB)
2036 dp_aux_irq_handler(dev_priv);
2038 if (de_iir & DE_GSE_IVB)
2039 intel_opregion_asle_intr(dev_priv);
2041 for_each_pipe(dev_priv, pipe) {
2042 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
2043 intel_handle_vblank(dev_priv, pipe);
2046 /* check event from PCH */
2047 if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
2048 u32 pch_iir = I915_READ(SDEIIR);
2050 cpt_irq_handler(dev_priv, pch_iir);
2052 /* clear PCH hotplug event before clear CPU irq */
2053 I915_WRITE(SDEIIR, pch_iir);
2058 * To handle irqs with the minimum potential races with fresh interrupts, we:
2059 * 1 - Disable Master Interrupt Control.
2060 * 2 - Find the source(s) of the interrupt.
2061 * 3 - Clear the Interrupt Identity bits (IIR).
2062 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2063 * 5 - Re-enable Master Interrupt Control.
2065 static irqreturn_t ilk_irq_handler(int irq, void *arg)
2067 struct drm_i915_private *dev_priv = arg;
2068 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2069 irqreturn_t ret = IRQ_NONE;
2071 if (!intel_irqs_enabled(dev_priv))
2074 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2075 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2077 /* disable master interrupt before clearing iir */
2078 de_ier = I915_READ(DEIER);
2079 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2081 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2082 * interrupts will will be stored on its back queue, and then we'll be
2083 * able to process them after we restore SDEIER (as soon as we restore
2084 * it, we'll get an interrupt if SDEIIR still has something to process
2085 * due to its back queue). */
2086 if (!HAS_PCH_NOP(dev_priv)) {
2087 sde_ier = I915_READ(SDEIER);
2088 I915_WRITE(SDEIER, 0);
2091 /* Find, clear, then process each source of interrupt */
2093 gt_iir = I915_READ(GTIIR);
2095 I915_WRITE(GTIIR, gt_iir);
2097 if (INTEL_GEN(dev_priv) >= 6)
2098 gen6_gt_irq_handler(&dev_priv->gt, gt_iir);
2100 gen5_gt_irq_handler(&dev_priv->gt, gt_iir);
2103 de_iir = I915_READ(DEIIR);
2105 I915_WRITE(DEIIR, de_iir);
2107 if (INTEL_GEN(dev_priv) >= 7)
2108 ivb_display_irq_handler(dev_priv, de_iir);
2110 ilk_display_irq_handler(dev_priv, de_iir);
2113 if (INTEL_GEN(dev_priv) >= 6) {
2114 u32 pm_iir = I915_READ(GEN6_PMIIR);
2116 I915_WRITE(GEN6_PMIIR, pm_iir);
2118 gen6_rps_irq_handler(&dev_priv->gt.rps, pm_iir);
2122 I915_WRITE(DEIER, de_ier);
2123 if (!HAS_PCH_NOP(dev_priv))
2124 I915_WRITE(SDEIER, sde_ier);
2126 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2127 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2132 static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
2133 u32 hotplug_trigger,
2134 const u32 hpd[HPD_NUM_PINS])
2136 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2138 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2139 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2141 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
2142 dig_hotplug_reg, hpd,
2143 bxt_port_hotplug_long_detect);
2145 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2148 static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
2150 u32 pin_mask = 0, long_mask = 0;
2151 u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK;
2152 u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK;
2153 long_pulse_detect_func long_pulse_detect;
2156 if (INTEL_GEN(dev_priv) >= 12) {
2157 long_pulse_detect = gen12_port_hotplug_long_detect;
2160 long_pulse_detect = gen11_port_hotplug_long_detect;
2165 u32 dig_hotplug_reg;
2167 dig_hotplug_reg = I915_READ(GEN11_TC_HOTPLUG_CTL);
2168 I915_WRITE(GEN11_TC_HOTPLUG_CTL, dig_hotplug_reg);
2170 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, trigger_tc,
2171 dig_hotplug_reg, hpd, long_pulse_detect);
2175 u32 dig_hotplug_reg;
2177 dig_hotplug_reg = I915_READ(GEN11_TBT_HOTPLUG_CTL);
2178 I915_WRITE(GEN11_TBT_HOTPLUG_CTL, dig_hotplug_reg);
2180 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, trigger_tbt,
2181 dig_hotplug_reg, hpd, long_pulse_detect);
2185 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2187 drm_err(&dev_priv->drm,
2188 "Unexpected DE HPD interrupt 0x%08x\n", iir);
2191 static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
2195 if (INTEL_GEN(dev_priv) >= 12)
2196 return TGL_DE_PORT_AUX_DDIA |
2197 TGL_DE_PORT_AUX_DDIB |
2198 TGL_DE_PORT_AUX_DDIC |
2199 TGL_DE_PORT_AUX_USBC1 |
2200 TGL_DE_PORT_AUX_USBC2 |
2201 TGL_DE_PORT_AUX_USBC3 |
2202 TGL_DE_PORT_AUX_USBC4 |
2203 TGL_DE_PORT_AUX_USBC5 |
2204 TGL_DE_PORT_AUX_USBC6;
2207 mask = GEN8_AUX_CHANNEL_A;
2208 if (INTEL_GEN(dev_priv) >= 9)
2209 mask |= GEN9_AUX_CHANNEL_B |
2210 GEN9_AUX_CHANNEL_C |
2213 if (IS_CNL_WITH_PORT_F(dev_priv) || IS_GEN(dev_priv, 11))
2214 mask |= CNL_AUX_CHANNEL_F;
2216 if (IS_GEN(dev_priv, 11))
2217 mask |= ICL_AUX_CHANNEL_E;
2222 static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
2224 if (INTEL_GEN(dev_priv) >= 11)
2225 return GEN11_DE_PIPE_IRQ_FAULT_ERRORS;
2226 else if (INTEL_GEN(dev_priv) >= 9)
2227 return GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2229 return GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2233 gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
2237 if (iir & GEN8_DE_MISC_GSE) {
2238 intel_opregion_asle_intr(dev_priv);
2242 if (iir & GEN8_DE_EDP_PSR) {
2246 if (INTEL_GEN(dev_priv) >= 12)
2247 iir_reg = TRANS_PSR_IIR(dev_priv->psr.transcoder);
2249 iir_reg = EDP_PSR_IIR;
2251 psr_iir = I915_READ(iir_reg);
2252 I915_WRITE(iir_reg, psr_iir);
2257 intel_psr_irq_handler(dev_priv, psr_iir);
2261 drm_err(&dev_priv->drm, "Unexpected DE Misc interrupt\n");
2265 gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2267 irqreturn_t ret = IRQ_NONE;
2271 if (master_ctl & GEN8_DE_MISC_IRQ) {
2272 iir = I915_READ(GEN8_DE_MISC_IIR);
2274 I915_WRITE(GEN8_DE_MISC_IIR, iir);
2276 gen8_de_misc_irq_handler(dev_priv, iir);
2278 drm_err(&dev_priv->drm,
2279 "The master control interrupt lied (DE MISC)!\n");
2283 if (INTEL_GEN(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) {
2284 iir = I915_READ(GEN11_DE_HPD_IIR);
2286 I915_WRITE(GEN11_DE_HPD_IIR, iir);
2288 gen11_hpd_irq_handler(dev_priv, iir);
2290 drm_err(&dev_priv->drm,
2291 "The master control interrupt lied, (DE HPD)!\n");
2295 if (master_ctl & GEN8_DE_PORT_IRQ) {
2296 iir = I915_READ(GEN8_DE_PORT_IIR);
2301 I915_WRITE(GEN8_DE_PORT_IIR, iir);
2304 if (iir & gen8_de_port_aux_mask(dev_priv)) {
2305 dp_aux_irq_handler(dev_priv);
2309 if (IS_GEN9_LP(dev_priv)) {
2310 tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
2312 bxt_hpd_irq_handler(dev_priv, tmp_mask,
2316 } else if (IS_BROADWELL(dev_priv)) {
2317 tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
2319 ilk_hpd_irq_handler(dev_priv,
2325 if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
2326 gmbus_irq_handler(dev_priv);
2331 drm_err(&dev_priv->drm,
2332 "Unexpected DE Port interrupt\n");
2335 drm_err(&dev_priv->drm,
2336 "The master control interrupt lied (DE PORT)!\n");
2339 for_each_pipe(dev_priv, pipe) {
2342 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2345 iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2347 drm_err(&dev_priv->drm,
2348 "The master control interrupt lied (DE PIPE)!\n");
2353 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
2355 if (iir & GEN8_PIPE_VBLANK)
2356 intel_handle_vblank(dev_priv, pipe);
2358 if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
2359 hsw_pipe_crc_irq_handler(dev_priv, pipe);
2361 if (iir & GEN8_PIPE_FIFO_UNDERRUN)
2362 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2364 fault_errors = iir & gen8_de_pipe_fault_mask(dev_priv);
2366 drm_err(&dev_priv->drm,
2367 "Fault errors on pipe %c: 0x%08x\n",
2372 if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
2373 master_ctl & GEN8_DE_PCH_IRQ) {
2375 * FIXME(BDW): Assume for now that the new interrupt handling
2376 * scheme also closed the SDE interrupt handling race we've seen
2377 * on older pch-split platforms. But this needs testing.
2379 iir = I915_READ(SDEIIR);
2381 I915_WRITE(SDEIIR, iir);
2384 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2385 icp_irq_handler(dev_priv, iir);
2386 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
2387 spt_irq_handler(dev_priv, iir);
2389 cpt_irq_handler(dev_priv, iir);
2392 * Like on previous PCH there seems to be something
2393 * fishy going on with forwarding PCH interrupts.
2395 drm_dbg(&dev_priv->drm,
2396 "The master control interrupt lied (SDE)!\n");
2403 static inline u32 gen8_master_intr_disable(void __iomem * const regs)
2405 raw_reg_write(regs, GEN8_MASTER_IRQ, 0);
2408 * Now with master disabled, get a sample of level indications
2409 * for this interrupt. Indications will be cleared on related acks.
2410 * New indications can and will light up during processing,
2411 * and will generate new interrupt after enabling master.
2413 return raw_reg_read(regs, GEN8_MASTER_IRQ);
2416 static inline void gen8_master_intr_enable(void __iomem * const regs)
2418 raw_reg_write(regs, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2421 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2423 struct drm_i915_private *dev_priv = arg;
2424 void __iomem * const regs = dev_priv->uncore.regs;
2427 if (!intel_irqs_enabled(dev_priv))
2430 master_ctl = gen8_master_intr_disable(regs);
2432 gen8_master_intr_enable(regs);
2436 /* Find, queue (onto bottom-halves), then clear each source */
2437 gen8_gt_irq_handler(&dev_priv->gt, master_ctl);
2439 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2440 if (master_ctl & ~GEN8_GT_IRQS) {
2441 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2442 gen8_de_irq_handler(dev_priv, master_ctl);
2443 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2446 gen8_master_intr_enable(regs);
2452 gen11_gu_misc_irq_ack(struct intel_gt *gt, const u32 master_ctl)
2454 void __iomem * const regs = gt->uncore->regs;
2457 if (!(master_ctl & GEN11_GU_MISC_IRQ))
2460 iir = raw_reg_read(regs, GEN11_GU_MISC_IIR);
2462 raw_reg_write(regs, GEN11_GU_MISC_IIR, iir);
2468 gen11_gu_misc_irq_handler(struct intel_gt *gt, const u32 iir)
2470 if (iir & GEN11_GU_MISC_GSE)
2471 intel_opregion_asle_intr(gt->i915);
2474 static inline u32 gen11_master_intr_disable(void __iomem * const regs)
2476 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, 0);
2479 * Now with master disabled, get a sample of level indications
2480 * for this interrupt. Indications will be cleared on related acks.
2481 * New indications can and will light up during processing,
2482 * and will generate new interrupt after enabling master.
2484 return raw_reg_read(regs, GEN11_GFX_MSTR_IRQ);
2487 static inline void gen11_master_intr_enable(void __iomem * const regs)
2489 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
2493 gen11_display_irq_handler(struct drm_i915_private *i915)
2495 void __iomem * const regs = i915->uncore.regs;
2496 const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL);
2498 disable_rpm_wakeref_asserts(&i915->runtime_pm);
2500 * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ
2501 * for the display related bits.
2503 raw_reg_write(regs, GEN11_DISPLAY_INT_CTL, 0x0);
2504 gen8_de_irq_handler(i915, disp_ctl);
2505 raw_reg_write(regs, GEN11_DISPLAY_INT_CTL,
2506 GEN11_DISPLAY_IRQ_ENABLE);
2508 enable_rpm_wakeref_asserts(&i915->runtime_pm);
2511 static __always_inline irqreturn_t
2512 __gen11_irq_handler(struct drm_i915_private * const i915,
2513 u32 (*intr_disable)(void __iomem * const regs),
2514 void (*intr_enable)(void __iomem * const regs))
2516 void __iomem * const regs = i915->uncore.regs;
2517 struct intel_gt *gt = &i915->gt;
2521 if (!intel_irqs_enabled(i915))
2524 master_ctl = intr_disable(regs);
2530 /* Find, queue (onto bottom-halves), then clear each source */
2531 gen11_gt_irq_handler(gt, master_ctl);
2533 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2534 if (master_ctl & GEN11_DISPLAY_IRQ)
2535 gen11_display_irq_handler(i915);
2537 gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
2541 gen11_gu_misc_irq_handler(gt, gu_misc_iir);
2546 static irqreturn_t gen11_irq_handler(int irq, void *arg)
2548 return __gen11_irq_handler(arg,
2549 gen11_master_intr_disable,
2550 gen11_master_intr_enable);
2553 /* Called from drm generic code, passed 'crtc' which
2554 * we use as a pipe index
2556 int i8xx_enable_vblank(struct drm_crtc *crtc)
2558 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2559 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2560 unsigned long irqflags;
2562 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2563 i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
2564 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2569 int i915gm_enable_vblank(struct drm_crtc *crtc)
2571 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2574 * Vblank interrupts fail to wake the device up from C2+.
2575 * Disabling render clock gating during C-states avoids
2576 * the problem. There is a small power cost so we do this
2577 * only when vblank interrupts are actually enabled.
2579 if (dev_priv->vblank_enabled++ == 0)
2580 I915_WRITE(SCPD0, _MASKED_BIT_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));
2582 return i8xx_enable_vblank(crtc);
2585 int i965_enable_vblank(struct drm_crtc *crtc)
2587 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2588 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2589 unsigned long irqflags;
2591 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2592 i915_enable_pipestat(dev_priv, pipe,
2593 PIPE_START_VBLANK_INTERRUPT_STATUS);
2594 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2599 int ilk_enable_vblank(struct drm_crtc *crtc)
2601 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2602 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2603 unsigned long irqflags;
2604 u32 bit = INTEL_GEN(dev_priv) >= 7 ?
2605 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
2607 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2608 ilk_enable_display_irq(dev_priv, bit);
2609 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2611 /* Even though there is no DMC, frame counter can get stuck when
2612 * PSR is active as no frames are generated.
2614 if (HAS_PSR(dev_priv))
2615 drm_crtc_vblank_restore(crtc);
2620 int bdw_enable_vblank(struct drm_crtc *crtc)
2622 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2623 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2624 unsigned long irqflags;
2626 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2627 bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2628 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2630 /* Even if there is no DMC, frame counter can get stuck when
2631 * PSR is active as no frames are generated, so check only for PSR.
2633 if (HAS_PSR(dev_priv))
2634 drm_crtc_vblank_restore(crtc);
2639 /* Called from drm generic code, passed 'crtc' which
2640 * we use as a pipe index
2642 void i8xx_disable_vblank(struct drm_crtc *crtc)
2644 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2645 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2646 unsigned long irqflags;
2648 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2649 i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
2650 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2653 void i915gm_disable_vblank(struct drm_crtc *crtc)
2655 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2657 i8xx_disable_vblank(crtc);
2659 if (--dev_priv->vblank_enabled == 0)
2660 I915_WRITE(SCPD0, _MASKED_BIT_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));
2663 void i965_disable_vblank(struct drm_crtc *crtc)
2665 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2666 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2667 unsigned long irqflags;
2669 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2670 i915_disable_pipestat(dev_priv, pipe,
2671 PIPE_START_VBLANK_INTERRUPT_STATUS);
2672 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2675 void ilk_disable_vblank(struct drm_crtc *crtc)
2677 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2678 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2679 unsigned long irqflags;
2680 u32 bit = INTEL_GEN(dev_priv) >= 7 ?
2681 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
2683 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2684 ilk_disable_display_irq(dev_priv, bit);
2685 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2688 void bdw_disable_vblank(struct drm_crtc *crtc)
2690 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2691 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2692 unsigned long irqflags;
2694 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2695 bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2696 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2699 static void ibx_irq_reset(struct drm_i915_private *dev_priv)
2701 struct intel_uncore *uncore = &dev_priv->uncore;
2703 if (HAS_PCH_NOP(dev_priv))
2706 GEN3_IRQ_RESET(uncore, SDE);
2708 if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
2709 I915_WRITE(SERR_INT, 0xffffffff);
2713 * SDEIER is also touched by the interrupt handler to work around missed PCH
2714 * interrupts. Hence we can't update it after the interrupt handler is enabled -
2715 * instead we unconditionally enable all PCH interrupt sources here, but then
2716 * only unmask them as needed with SDEIMR.
2718 * This function needs to be called before interrupts are enabled.
2720 static void ibx_irq_pre_postinstall(struct drm_i915_private *dev_priv)
2722 if (HAS_PCH_NOP(dev_priv))
2725 drm_WARN_ON(&dev_priv->drm, I915_READ(SDEIER) != 0);
2726 I915_WRITE(SDEIER, 0xffffffff);
2727 POSTING_READ(SDEIER);
2730 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
2732 struct intel_uncore *uncore = &dev_priv->uncore;
2734 if (IS_CHERRYVIEW(dev_priv))
2735 intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
2737 intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK);
2739 i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
2740 intel_uncore_write(uncore, PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2742 i9xx_pipestat_irq_reset(dev_priv);
2744 GEN3_IRQ_RESET(uncore, VLV_);
2745 dev_priv->irq_mask = ~0u;
2748 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
2750 struct intel_uncore *uncore = &dev_priv->uncore;
2756 pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS;
2758 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
2759 for_each_pipe(dev_priv, pipe)
2760 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
2762 enable_mask = I915_DISPLAY_PORT_INTERRUPT |
2763 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2764 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2765 I915_LPE_PIPE_A_INTERRUPT |
2766 I915_LPE_PIPE_B_INTERRUPT;
2768 if (IS_CHERRYVIEW(dev_priv))
2769 enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT |
2770 I915_LPE_PIPE_C_INTERRUPT;
2772 drm_WARN_ON(&dev_priv->drm, dev_priv->irq_mask != ~0u);
2774 dev_priv->irq_mask = ~enable_mask;
2776 GEN3_IRQ_INIT(uncore, VLV_, dev_priv->irq_mask, enable_mask);
2781 static void ilk_irq_reset(struct drm_i915_private *dev_priv)
2783 struct intel_uncore *uncore = &dev_priv->uncore;
2785 GEN3_IRQ_RESET(uncore, DE);
2786 if (IS_GEN(dev_priv, 7))
2787 intel_uncore_write(uncore, GEN7_ERR_INT, 0xffffffff);
2789 if (IS_HASWELL(dev_priv)) {
2790 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
2791 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
2794 gen5_gt_irq_reset(&dev_priv->gt);
2796 ibx_irq_reset(dev_priv);
2799 static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
2801 I915_WRITE(VLV_MASTER_IER, 0);
2802 POSTING_READ(VLV_MASTER_IER);
2804 gen5_gt_irq_reset(&dev_priv->gt);
2806 spin_lock_irq(&dev_priv->irq_lock);
2807 if (dev_priv->display_irqs_enabled)
2808 vlv_display_irq_reset(dev_priv);
2809 spin_unlock_irq(&dev_priv->irq_lock);
2812 static void gen8_irq_reset(struct drm_i915_private *dev_priv)
2814 struct intel_uncore *uncore = &dev_priv->uncore;
2817 gen8_master_intr_disable(dev_priv->uncore.regs);
2819 gen8_gt_irq_reset(&dev_priv->gt);
2821 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
2822 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
2824 for_each_pipe(dev_priv, pipe)
2825 if (intel_display_power_is_enabled(dev_priv,
2826 POWER_DOMAIN_PIPE(pipe)))
2827 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
2829 GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);
2830 GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
2831 GEN3_IRQ_RESET(uncore, GEN8_PCU_);
2833 if (HAS_PCH_SPLIT(dev_priv))
2834 ibx_irq_reset(dev_priv);
2837 static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
2839 struct intel_uncore *uncore = &dev_priv->uncore;
2842 intel_uncore_write(uncore, GEN11_DISPLAY_INT_CTL, 0);
2844 if (INTEL_GEN(dev_priv) >= 12) {
2845 enum transcoder trans;
2847 for (trans = TRANSCODER_A; trans <= TRANSCODER_D; trans++) {
2848 enum intel_display_power_domain domain;
2850 domain = POWER_DOMAIN_TRANSCODER(trans);
2851 if (!intel_display_power_is_enabled(dev_priv, domain))
2854 intel_uncore_write(uncore, TRANS_PSR_IMR(trans), 0xffffffff);
2855 intel_uncore_write(uncore, TRANS_PSR_IIR(trans), 0xffffffff);
2858 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
2859 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
2862 for_each_pipe(dev_priv, pipe)
2863 if (intel_display_power_is_enabled(dev_priv,
2864 POWER_DOMAIN_PIPE(pipe)))
2865 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
2867 GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);
2868 GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
2869 GEN3_IRQ_RESET(uncore, GEN11_DE_HPD_);
2871 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2872 GEN3_IRQ_RESET(uncore, SDE);
2874 /* Wa_14010685332:icl */
2875 if (INTEL_PCH_TYPE(dev_priv) == PCH_ICP) {
2876 intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
2877 SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
2878 intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
2879 SBCLK_RUN_REFCLK_DIS, 0);
2883 static void gen11_irq_reset(struct drm_i915_private *dev_priv)
2885 struct intel_uncore *uncore = &dev_priv->uncore;
2887 gen11_master_intr_disable(dev_priv->uncore.regs);
2889 gen11_gt_irq_reset(&dev_priv->gt);
2890 gen11_display_irq_reset(dev_priv);
2892 GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
2893 GEN3_IRQ_RESET(uncore, GEN8_PCU_);
2896 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
2899 struct intel_uncore *uncore = &dev_priv->uncore;
2901 u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
2904 spin_lock_irq(&dev_priv->irq_lock);
2906 if (!intel_irqs_enabled(dev_priv)) {
2907 spin_unlock_irq(&dev_priv->irq_lock);
2911 for_each_pipe_masked(dev_priv, pipe, pipe_mask)
2912 GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,
2913 dev_priv->de_irq_mask[pipe],
2914 ~dev_priv->de_irq_mask[pipe] | extra_ier);
2916 spin_unlock_irq(&dev_priv->irq_lock);
2919 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
2922 struct intel_uncore *uncore = &dev_priv->uncore;
2925 spin_lock_irq(&dev_priv->irq_lock);
2927 if (!intel_irqs_enabled(dev_priv)) {
2928 spin_unlock_irq(&dev_priv->irq_lock);
2932 for_each_pipe_masked(dev_priv, pipe, pipe_mask)
2933 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
2935 spin_unlock_irq(&dev_priv->irq_lock);
2937 /* make sure we're done processing display irqs */
2938 intel_synchronize_irq(dev_priv);
2941 static void cherryview_irq_reset(struct drm_i915_private *dev_priv)
2943 struct intel_uncore *uncore = &dev_priv->uncore;
2945 I915_WRITE(GEN8_MASTER_IRQ, 0);
2946 POSTING_READ(GEN8_MASTER_IRQ);
2948 gen8_gt_irq_reset(&dev_priv->gt);
2950 GEN3_IRQ_RESET(uncore, GEN8_PCU_);
2952 spin_lock_irq(&dev_priv->irq_lock);
2953 if (dev_priv->display_irqs_enabled)
2954 vlv_display_irq_reset(dev_priv);
2955 spin_unlock_irq(&dev_priv->irq_lock);
2958 static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
2959 const u32 hpd[HPD_NUM_PINS])
2961 struct intel_encoder *encoder;
2962 u32 enabled_irqs = 0;
2964 for_each_intel_encoder(&dev_priv->drm, encoder)
2965 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
2966 enabled_irqs |= hpd[encoder->hpd_pin];
2968 return enabled_irqs;
2971 static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
2976 * Enable digital hotplug on the PCH, and configure the DP short pulse
2977 * duration to 2ms (which is the minimum in the Display Port spec).
2978 * The pulse duration bits are reserved on LPT+.
2980 hotplug = I915_READ(PCH_PORT_HOTPLUG);
2981 hotplug &= ~(PORTB_PULSE_DURATION_MASK |
2982 PORTC_PULSE_DURATION_MASK |
2983 PORTD_PULSE_DURATION_MASK);
2984 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2985 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2986 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2988 * When CPU and PCH are on the same package, port A
2989 * HPD must be enabled in both north and south.
2991 if (HAS_PCH_LPT_LP(dev_priv))
2992 hotplug |= PORTA_HOTPLUG_ENABLE;
2993 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2996 static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
2998 u32 hotplug_irqs, enabled_irqs;
3000 if (HAS_PCH_IBX(dev_priv)) {
3001 hotplug_irqs = SDE_HOTPLUG_MASK;
3002 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ibx);
3004 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3005 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_cpt);
3008 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3010 ibx_hpd_detection_setup(dev_priv);
3013 static void icp_hpd_detection_setup(struct drm_i915_private *dev_priv,
3014 u32 ddi_hotplug_enable_mask,
3015 u32 tc_hotplug_enable_mask)
3019 hotplug = I915_READ(SHOTPLUG_CTL_DDI);
3020 hotplug |= ddi_hotplug_enable_mask;
3021 I915_WRITE(SHOTPLUG_CTL_DDI, hotplug);
3023 if (tc_hotplug_enable_mask) {
3024 hotplug = I915_READ(SHOTPLUG_CTL_TC);
3025 hotplug |= tc_hotplug_enable_mask;
3026 I915_WRITE(SHOTPLUG_CTL_TC, hotplug);
3030 static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv,
3031 u32 sde_ddi_mask, u32 sde_tc_mask,
3032 u32 ddi_enable_mask, u32 tc_enable_mask,
3035 u32 hotplug_irqs, enabled_irqs;
3037 hotplug_irqs = sde_ddi_mask | sde_tc_mask;
3038 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, pins);
3040 I915_WRITE(SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
3042 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3044 icp_hpd_detection_setup(dev_priv, ddi_enable_mask, tc_enable_mask);
3048 * EHL doesn't need most of gen11_hpd_irq_setup, it's handling only the
3049 * equivalent of SDE.
3051 static void mcc_hpd_irq_setup(struct drm_i915_private *dev_priv)
3053 icp_hpd_irq_setup(dev_priv,
3054 SDE_DDI_MASK_ICP, SDE_TC_HOTPLUG_ICP(PORT_TC1),
3055 ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE(PORT_TC1),
3060 * JSP behaves exactly the same as MCC above except that port C is mapped to
3061 * the DDI-C pins instead of the TC1 pins. This means we should follow TGP's
3062 * masks & tables rather than ICP's masks & tables.
3064 static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv)
3066 icp_hpd_irq_setup(dev_priv,
3067 SDE_DDI_MASK_TGP, 0,
3068 TGP_DDI_HPD_ENABLE_MASK, 0,
3072 static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
3076 hotplug = I915_READ(GEN11_TC_HOTPLUG_CTL);
3077 hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) |
3078 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) |
3079 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) |
3080 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4);
3081 I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug);
3083 hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL);
3084 hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) |
3085 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) |
3086 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) |
3087 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4);
3088 I915_WRITE(GEN11_TBT_HOTPLUG_CTL, hotplug);
3091 static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
3093 u32 hotplug_irqs, enabled_irqs;
3097 hpd = INTEL_GEN(dev_priv) >= 12 ? hpd_gen12 : hpd_gen11;
3098 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd);
3099 hotplug_irqs = GEN11_DE_TC_HOTPLUG_MASK | GEN11_DE_TBT_HOTPLUG_MASK;
3101 val = I915_READ(GEN11_DE_HPD_IMR);
3102 val &= ~hotplug_irqs;
3103 I915_WRITE(GEN11_DE_HPD_IMR, val);
3104 POSTING_READ(GEN11_DE_HPD_IMR);
3106 gen11_hpd_detection_setup(dev_priv);
3108 if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP)
3109 icp_hpd_irq_setup(dev_priv, SDE_DDI_MASK_TGP, SDE_TC_MASK_TGP,
3110 TGP_DDI_HPD_ENABLE_MASK,
3111 TGP_TC_HPD_ENABLE_MASK, hpd_tgp);
3112 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3113 icp_hpd_irq_setup(dev_priv, SDE_DDI_MASK_ICP, SDE_TC_MASK_ICP,
3114 ICP_DDI_HPD_ENABLE_MASK,
3115 ICP_TC_HPD_ENABLE_MASK, hpd_icp);
3118 static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3122 /* Display WA #1179 WaHardHangonHotPlug: cnp */
3123 if (HAS_PCH_CNP(dev_priv)) {
3124 val = I915_READ(SOUTH_CHICKEN1);
3125 val &= ~CHASSIS_CLK_REQ_DURATION_MASK;
3126 val |= CHASSIS_CLK_REQ_DURATION(0xf);
3127 I915_WRITE(SOUTH_CHICKEN1, val);
3130 /* Enable digital hotplug on the PCH */
3131 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3132 hotplug |= PORTA_HOTPLUG_ENABLE |
3133 PORTB_HOTPLUG_ENABLE |
3134 PORTC_HOTPLUG_ENABLE |
3135 PORTD_HOTPLUG_ENABLE;
3136 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3138 hotplug = I915_READ(PCH_PORT_HOTPLUG2);
3139 hotplug |= PORTE_HOTPLUG_ENABLE;
3140 I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
3143 static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3145 u32 hotplug_irqs, enabled_irqs;
3147 if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
3148 I915_WRITE(SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
3150 hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
3151 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt);
3153 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3155 spt_hpd_detection_setup(dev_priv);
3158 static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv)
3163 * Enable digital hotplug on the CPU, and configure the DP short pulse
3164 * duration to 2ms (which is the minimum in the Display Port spec)
3165 * The pulse duration bits are reserved on HSW+.
3167 hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
3168 hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
3169 hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE |
3170 DIGITAL_PORTA_PULSE_DURATION_2ms;
3171 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
3174 static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
3176 u32 hotplug_irqs, enabled_irqs;
3178 if (INTEL_GEN(dev_priv) >= 8) {
3179 hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
3180 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw);
3182 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3183 } else if (INTEL_GEN(dev_priv) >= 7) {
3184 hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
3185 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ivb);
3187 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3189 hotplug_irqs = DE_DP_A_HOTPLUG;
3190 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ilk);
3192 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3195 ilk_hpd_detection_setup(dev_priv);
3197 ibx_hpd_irq_setup(dev_priv);
3200 static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
3205 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3206 hotplug |= PORTA_HOTPLUG_ENABLE |
3207 PORTB_HOTPLUG_ENABLE |
3208 PORTC_HOTPLUG_ENABLE;
3210 drm_dbg_kms(&dev_priv->drm,
3211 "Invert bit setting: hp_ctl:%x hp_port:%x\n",
3212 hotplug, enabled_irqs);
3213 hotplug &= ~BXT_DDI_HPD_INVERT_MASK;
3216 * For BXT invert bit has to be set based on AOB design
3217 * for HPD detection logic, update it based on VBT fields.
3219 if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) &&
3220 intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
3221 hotplug |= BXT_DDIA_HPD_INVERT;
3222 if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) &&
3223 intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
3224 hotplug |= BXT_DDIB_HPD_INVERT;
3225 if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) &&
3226 intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
3227 hotplug |= BXT_DDIC_HPD_INVERT;
3229 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3232 static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3234 __bxt_hpd_detection_setup(dev_priv, BXT_DE_PORT_HOTPLUG_MASK);
3237 static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3239 u32 hotplug_irqs, enabled_irqs;
3241 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bxt);
3242 hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK;
3244 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3246 __bxt_hpd_detection_setup(dev_priv, enabled_irqs);
3249 static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
3253 if (HAS_PCH_NOP(dev_priv))
3256 if (HAS_PCH_IBX(dev_priv))
3257 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3258 else if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
3259 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3261 mask = SDE_GMBUS_CPT;
3263 gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
3264 I915_WRITE(SDEIMR, ~mask);
3266 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
3267 HAS_PCH_LPT(dev_priv))
3268 ibx_hpd_detection_setup(dev_priv);
3270 spt_hpd_detection_setup(dev_priv);
3273 static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
3275 struct intel_uncore *uncore = &dev_priv->uncore;
3276 u32 display_mask, extra_mask;
3278 if (INTEL_GEN(dev_priv) >= 7) {
3279 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3280 DE_PCH_EVENT_IVB | DE_AUX_CHANNEL_A_IVB);
3281 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3282 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
3283 DE_DP_A_HOTPLUG_IVB);
3285 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3286 DE_AUX_CHANNEL_A | DE_PIPEB_CRC_DONE |
3287 DE_PIPEA_CRC_DONE | DE_POISON);
3288 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3289 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
3293 if (IS_HASWELL(dev_priv)) {
3294 gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
3295 display_mask |= DE_EDP_PSR_INT_HSW;
3298 dev_priv->irq_mask = ~display_mask;
3300 ibx_irq_pre_postinstall(dev_priv);
3302 GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask,
3303 display_mask | extra_mask);
3305 gen5_gt_irq_postinstall(&dev_priv->gt);
3307 ilk_hpd_detection_setup(dev_priv);
3309 ibx_irq_postinstall(dev_priv);
3311 if (IS_IRONLAKE_M(dev_priv)) {
3312 /* Enable PCU event interrupts
3314 * spinlocking not required here for correctness since interrupt
3315 * setup is guaranteed to run in single-threaded context. But we
3316 * need it to make the assert_spin_locked happy. */
3317 spin_lock_irq(&dev_priv->irq_lock);
3318 ilk_enable_display_irq(dev_priv, DE_PCU_EVENT);
3319 spin_unlock_irq(&dev_priv->irq_lock);
3323 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3325 lockdep_assert_held(&dev_priv->irq_lock);
3327 if (dev_priv->display_irqs_enabled)
3330 dev_priv->display_irqs_enabled = true;
3332 if (intel_irqs_enabled(dev_priv)) {
3333 vlv_display_irq_reset(dev_priv);
3334 vlv_display_irq_postinstall(dev_priv);
3338 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3340 lockdep_assert_held(&dev_priv->irq_lock);
3342 if (!dev_priv->display_irqs_enabled)
3345 dev_priv->display_irqs_enabled = false;
3347 if (intel_irqs_enabled(dev_priv))
3348 vlv_display_irq_reset(dev_priv);
3352 static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv)
3354 gen5_gt_irq_postinstall(&dev_priv->gt);
3356 spin_lock_irq(&dev_priv->irq_lock);
3357 if (dev_priv->display_irqs_enabled)
3358 vlv_display_irq_postinstall(dev_priv);
3359 spin_unlock_irq(&dev_priv->irq_lock);
3361 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3362 POSTING_READ(VLV_MASTER_IER);
3365 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3367 struct intel_uncore *uncore = &dev_priv->uncore;
3369 u32 de_pipe_masked = gen8_de_pipe_fault_mask(dev_priv) |
3370 GEN8_PIPE_CDCLK_CRC_DONE;
3371 u32 de_pipe_enables;
3372 u32 de_port_masked = gen8_de_port_aux_mask(dev_priv);
3373 u32 de_port_enables;
3374 u32 de_misc_masked = GEN8_DE_EDP_PSR;
3377 if (INTEL_GEN(dev_priv) <= 10)
3378 de_misc_masked |= GEN8_DE_MISC_GSE;
3380 if (IS_GEN9_LP(dev_priv))
3381 de_port_masked |= BXT_DE_PORT_GMBUS;
3383 de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3384 GEN8_PIPE_FIFO_UNDERRUN;
3386 de_port_enables = de_port_masked;
3387 if (IS_GEN9_LP(dev_priv))
3388 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
3389 else if (IS_BROADWELL(dev_priv))
3390 de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
3392 if (INTEL_GEN(dev_priv) >= 12) {
3393 enum transcoder trans;
3395 for (trans = TRANSCODER_A; trans <= TRANSCODER_D; trans++) {
3396 enum intel_display_power_domain domain;
3398 domain = POWER_DOMAIN_TRANSCODER(trans);
3399 if (!intel_display_power_is_enabled(dev_priv, domain))
3402 gen3_assert_iir_is_zero(uncore, TRANS_PSR_IIR(trans));
3405 gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
3408 for_each_pipe(dev_priv, pipe) {
3409 dev_priv->de_irq_mask[pipe] = ~de_pipe_masked;
3411 if (intel_display_power_is_enabled(dev_priv,
3412 POWER_DOMAIN_PIPE(pipe)))
3413 GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,
3414 dev_priv->de_irq_mask[pipe],
3418 GEN3_IRQ_INIT(uncore, GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
3419 GEN3_IRQ_INIT(uncore, GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
3421 if (INTEL_GEN(dev_priv) >= 11) {
3422 u32 de_hpd_masked = 0;
3423 u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK |
3424 GEN11_DE_TBT_HOTPLUG_MASK;
3426 GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked,
3428 gen11_hpd_detection_setup(dev_priv);
3429 } else if (IS_GEN9_LP(dev_priv)) {
3430 bxt_hpd_detection_setup(dev_priv);
3431 } else if (IS_BROADWELL(dev_priv)) {
3432 ilk_hpd_detection_setup(dev_priv);
3436 static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
3438 if (HAS_PCH_SPLIT(dev_priv))
3439 ibx_irq_pre_postinstall(dev_priv);
3441 gen8_gt_irq_postinstall(&dev_priv->gt);
3442 gen8_de_irq_postinstall(dev_priv);
3444 if (HAS_PCH_SPLIT(dev_priv))
3445 ibx_irq_postinstall(dev_priv);
3447 gen8_master_intr_enable(dev_priv->uncore.regs);
3450 static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
3452 u32 mask = SDE_GMBUS_ICP;
3454 drm_WARN_ON(&dev_priv->drm, I915_READ(SDEIER) != 0);
3455 I915_WRITE(SDEIER, 0xffffffff);
3456 POSTING_READ(SDEIER);
3458 gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
3459 I915_WRITE(SDEIMR, ~mask);
3461 if (HAS_PCH_TGP(dev_priv))
3462 icp_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK,
3463 TGP_TC_HPD_ENABLE_MASK);
3464 else if (HAS_PCH_JSP(dev_priv))
3465 icp_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK, 0);
3466 else if (HAS_PCH_MCC(dev_priv))
3467 icp_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK,
3468 ICP_TC_HPD_ENABLE(PORT_TC1));
3470 icp_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK,
3471 ICP_TC_HPD_ENABLE_MASK);
3474 static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
3476 struct intel_uncore *uncore = &dev_priv->uncore;
3477 u32 gu_misc_masked = GEN11_GU_MISC_GSE;
3479 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3480 icp_irq_postinstall(dev_priv);
3482 gen11_gt_irq_postinstall(&dev_priv->gt);
3483 gen8_de_irq_postinstall(dev_priv);
3485 GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
3487 I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
3489 gen11_master_intr_enable(uncore->regs);
3490 POSTING_READ(GEN11_GFX_MSTR_IRQ);
3493 static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
3495 gen8_gt_irq_postinstall(&dev_priv->gt);
3497 spin_lock_irq(&dev_priv->irq_lock);
3498 if (dev_priv->display_irqs_enabled)
3499 vlv_display_irq_postinstall(dev_priv);
3500 spin_unlock_irq(&dev_priv->irq_lock);
3502 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3503 POSTING_READ(GEN8_MASTER_IRQ);
3506 static void i8xx_irq_reset(struct drm_i915_private *dev_priv)
3508 struct intel_uncore *uncore = &dev_priv->uncore;
3510 i9xx_pipestat_irq_reset(dev_priv);
3512 GEN2_IRQ_RESET(uncore);
3515 static void i8xx_irq_postinstall(struct drm_i915_private *dev_priv)
3517 struct intel_uncore *uncore = &dev_priv->uncore;
3520 intel_uncore_write16(uncore,
3522 ~(I915_ERROR_PAGE_TABLE |
3523 I915_ERROR_MEMORY_REFRESH));
3525 /* Unmask the interrupts that we always want on. */
3526 dev_priv->irq_mask =
3527 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3528 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3529 I915_MASTER_ERROR_INTERRUPT);
3532 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3533 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3534 I915_MASTER_ERROR_INTERRUPT |
3535 I915_USER_INTERRUPT;
3537 GEN2_IRQ_INIT(uncore, dev_priv->irq_mask, enable_mask);
3539 /* Interrupt setup is already guaranteed to be single-threaded, this is
3540 * just to make the assert_spin_locked check happy. */
3541 spin_lock_irq(&dev_priv->irq_lock);
3542 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3543 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3544 spin_unlock_irq(&dev_priv->irq_lock);
3547 static void i8xx_error_irq_ack(struct drm_i915_private *i915,
3548 u16 *eir, u16 *eir_stuck)
3550 struct intel_uncore *uncore = &i915->uncore;
3553 *eir = intel_uncore_read16(uncore, EIR);
3556 intel_uncore_write16(uncore, EIR, *eir);
3558 *eir_stuck = intel_uncore_read16(uncore, EIR);
3559 if (*eir_stuck == 0)
3563 * Toggle all EMR bits to make sure we get an edge
3564 * in the ISR master error bit if we don't clear
3565 * all the EIR bits. Otherwise the edge triggered
3566 * IIR on i965/g4x wouldn't notice that an interrupt
3567 * is still pending. Also some EIR bits can't be
3568 * cleared except by handling the underlying error
3569 * (or by a GPU reset) so we mask any bit that
3572 emr = intel_uncore_read16(uncore, EMR);
3573 intel_uncore_write16(uncore, EMR, 0xffff);
3574 intel_uncore_write16(uncore, EMR, emr | *eir_stuck);
3577 static void i8xx_error_irq_handler(struct drm_i915_private *dev_priv,
3578 u16 eir, u16 eir_stuck)
3580 DRM_DEBUG("Master Error: EIR 0x%04x\n", eir);
3583 drm_dbg(&dev_priv->drm, "EIR stuck: 0x%04x, masked\n",
3587 static void i9xx_error_irq_ack(struct drm_i915_private *dev_priv,
3588 u32 *eir, u32 *eir_stuck)
3592 *eir = I915_READ(EIR);
3594 I915_WRITE(EIR, *eir);
3596 *eir_stuck = I915_READ(EIR);
3597 if (*eir_stuck == 0)
3601 * Toggle all EMR bits to make sure we get an edge
3602 * in the ISR master error bit if we don't clear
3603 * all the EIR bits. Otherwise the edge triggered
3604 * IIR on i965/g4x wouldn't notice that an interrupt
3605 * is still pending. Also some EIR bits can't be
3606 * cleared except by handling the underlying error
3607 * (or by a GPU reset) so we mask any bit that
3610 emr = I915_READ(EMR);
3611 I915_WRITE(EMR, 0xffffffff);
3612 I915_WRITE(EMR, emr | *eir_stuck);
3615 static void i9xx_error_irq_handler(struct drm_i915_private *dev_priv,
3616 u32 eir, u32 eir_stuck)
3618 DRM_DEBUG("Master Error, EIR 0x%08x\n", eir);
3621 drm_dbg(&dev_priv->drm, "EIR stuck: 0x%08x, masked\n",
3625 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3627 struct drm_i915_private *dev_priv = arg;
3628 irqreturn_t ret = IRQ_NONE;
3630 if (!intel_irqs_enabled(dev_priv))
3633 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3634 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
3637 u32 pipe_stats[I915_MAX_PIPES] = {};
3638 u16 eir = 0, eir_stuck = 0;
3641 iir = intel_uncore_read16(&dev_priv->uncore, GEN2_IIR);
3647 /* Call regardless, as some status bits might not be
3648 * signalled in iir */
3649 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
3651 if (iir & I915_MASTER_ERROR_INTERRUPT)
3652 i8xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
3654 intel_uncore_write16(&dev_priv->uncore, GEN2_IIR, iir);
3656 if (iir & I915_USER_INTERRUPT)
3657 intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]);
3659 if (iir & I915_MASTER_ERROR_INTERRUPT)
3660 i8xx_error_irq_handler(dev_priv, eir, eir_stuck);
3662 i8xx_pipestat_irq_handler(dev_priv, iir, pipe_stats);
3665 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
3670 static void i915_irq_reset(struct drm_i915_private *dev_priv)
3672 struct intel_uncore *uncore = &dev_priv->uncore;
3674 if (I915_HAS_HOTPLUG(dev_priv)) {
3675 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3676 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3679 i9xx_pipestat_irq_reset(dev_priv);
3681 GEN3_IRQ_RESET(uncore, GEN2_);
3684 static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
3686 struct intel_uncore *uncore = &dev_priv->uncore;
3689 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE |
3690 I915_ERROR_MEMORY_REFRESH));
3692 /* Unmask the interrupts that we always want on. */
3693 dev_priv->irq_mask =
3694 ~(I915_ASLE_INTERRUPT |
3695 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3696 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3697 I915_MASTER_ERROR_INTERRUPT);
3700 I915_ASLE_INTERRUPT |
3701 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3702 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3703 I915_MASTER_ERROR_INTERRUPT |
3704 I915_USER_INTERRUPT;
3706 if (I915_HAS_HOTPLUG(dev_priv)) {
3707 /* Enable in IER... */
3708 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3709 /* and unmask in IMR */
3710 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3713 GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);
3715 /* Interrupt setup is already guaranteed to be single-threaded, this is
3716 * just to make the assert_spin_locked check happy. */
3717 spin_lock_irq(&dev_priv->irq_lock);
3718 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3719 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3720 spin_unlock_irq(&dev_priv->irq_lock);
3722 i915_enable_asle_pipestat(dev_priv);
3725 static irqreturn_t i915_irq_handler(int irq, void *arg)
3727 struct drm_i915_private *dev_priv = arg;
3728 irqreturn_t ret = IRQ_NONE;
3730 if (!intel_irqs_enabled(dev_priv))
3733 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3734 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
3737 u32 pipe_stats[I915_MAX_PIPES] = {};
3738 u32 eir = 0, eir_stuck = 0;
3739 u32 hotplug_status = 0;
3742 iir = I915_READ(GEN2_IIR);
3748 if (I915_HAS_HOTPLUG(dev_priv) &&
3749 iir & I915_DISPLAY_PORT_INTERRUPT)
3750 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
3752 /* Call regardless, as some status bits might not be
3753 * signalled in iir */
3754 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
3756 if (iir & I915_MASTER_ERROR_INTERRUPT)
3757 i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
3759 I915_WRITE(GEN2_IIR, iir);
3761 if (iir & I915_USER_INTERRUPT)
3762 intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]);
3764 if (iir & I915_MASTER_ERROR_INTERRUPT)
3765 i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
3768 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
3770 i915_pipestat_irq_handler(dev_priv, iir, pipe_stats);
3773 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
3778 static void i965_irq_reset(struct drm_i915_private *dev_priv)
3780 struct intel_uncore *uncore = &dev_priv->uncore;
3782 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3783 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3785 i9xx_pipestat_irq_reset(dev_priv);
3787 GEN3_IRQ_RESET(uncore, GEN2_);
3790 static void i965_irq_postinstall(struct drm_i915_private *dev_priv)
3792 struct intel_uncore *uncore = &dev_priv->uncore;
3797 * Enable some error detection, note the instruction error mask
3798 * bit is reserved, so we leave it masked.
3800 if (IS_G4X(dev_priv)) {
3801 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3802 GM45_ERROR_MEM_PRIV |
3803 GM45_ERROR_CP_PRIV |
3804 I915_ERROR_MEMORY_REFRESH);
3806 error_mask = ~(I915_ERROR_PAGE_TABLE |
3807 I915_ERROR_MEMORY_REFRESH);
3809 I915_WRITE(EMR, error_mask);
3811 /* Unmask the interrupts that we always want on. */
3812 dev_priv->irq_mask =
3813 ~(I915_ASLE_INTERRUPT |
3814 I915_DISPLAY_PORT_INTERRUPT |
3815 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3816 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3817 I915_MASTER_ERROR_INTERRUPT);
3820 I915_ASLE_INTERRUPT |
3821 I915_DISPLAY_PORT_INTERRUPT |
3822 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3823 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3824 I915_MASTER_ERROR_INTERRUPT |
3825 I915_USER_INTERRUPT;
3827 if (IS_G4X(dev_priv))
3828 enable_mask |= I915_BSD_USER_INTERRUPT;
3830 GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);
3832 /* Interrupt setup is already guaranteed to be single-threaded, this is
3833 * just to make the assert_spin_locked check happy. */
3834 spin_lock_irq(&dev_priv->irq_lock);
3835 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3836 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3837 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3838 spin_unlock_irq(&dev_priv->irq_lock);
3840 i915_enable_asle_pipestat(dev_priv);
3843 static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
3847 lockdep_assert_held(&dev_priv->irq_lock);
3849 /* Note HDMI and DP share hotplug bits */
3850 /* enable bits are the same for all generations */
3851 hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);
3852 /* Programming the CRT detection parameters tends
3853 to generate a spurious hotplug event about three
3854 seconds later. So just do it once.
3856 if (IS_G4X(dev_priv))
3857 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
3858 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
3860 /* Ignore TV since it's buggy */
3861 i915_hotplug_interrupt_update_locked(dev_priv,
3862 HOTPLUG_INT_EN_MASK |
3863 CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
3864 CRT_HOTPLUG_ACTIVATION_PERIOD_64,
3868 static irqreturn_t i965_irq_handler(int irq, void *arg)
3870 struct drm_i915_private *dev_priv = arg;
3871 irqreturn_t ret = IRQ_NONE;
3873 if (!intel_irqs_enabled(dev_priv))
3876 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3877 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
3880 u32 pipe_stats[I915_MAX_PIPES] = {};
3881 u32 eir = 0, eir_stuck = 0;
3882 u32 hotplug_status = 0;
3885 iir = I915_READ(GEN2_IIR);
3891 if (iir & I915_DISPLAY_PORT_INTERRUPT)
3892 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
3894 /* Call regardless, as some status bits might not be
3895 * signalled in iir */
3896 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
3898 if (iir & I915_MASTER_ERROR_INTERRUPT)
3899 i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
3901 I915_WRITE(GEN2_IIR, iir);
3903 if (iir & I915_USER_INTERRUPT)
3904 intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]);
3906 if (iir & I915_BSD_USER_INTERRUPT)
3907 intel_engine_signal_breadcrumbs(dev_priv->gt.engine[VCS0]);
3909 if (iir & I915_MASTER_ERROR_INTERRUPT)
3910 i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
3913 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
3915 i965_pipestat_irq_handler(dev_priv, iir, pipe_stats);
3918 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
3924 * intel_irq_init - initializes irq support
3925 * @dev_priv: i915 device instance
3927 * This function initializes all the irq support including work items, timers
3928 * and all the vtables. It does not setup the interrupt itself though.
3930 void intel_irq_init(struct drm_i915_private *dev_priv)
3932 struct drm_device *dev = &dev_priv->drm;
3935 intel_hpd_init_work(dev_priv);
3937 INIT_WORK(&dev_priv->l3_parity.error_work, ivb_parity_work);
3938 for (i = 0; i < MAX_L3_SLICES; ++i)
3939 dev_priv->l3_parity.remap_info[i] = NULL;
3941 /* pre-gen11 the guc irqs bits are in the upper 16 bits of the pm reg */
3942 if (HAS_GT_UC(dev_priv) && INTEL_GEN(dev_priv) < 11)
3943 dev_priv->gt.pm_guc_events = GUC_INTR_GUC2HOST << 16;
3945 dev->vblank_disable_immediate = true;
3947 /* Most platforms treat the display irq block as an always-on
3948 * power domain. vlv/chv can disable it at runtime and need
3949 * special care to avoid writing any of the display block registers
3950 * outside of the power domain. We defer setting up the display irqs
3951 * in this case to the runtime pm.
3953 dev_priv->display_irqs_enabled = true;
3954 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3955 dev_priv->display_irqs_enabled = false;
3957 dev_priv->hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD;
3958 /* If we have MST support, we want to avoid doing short HPD IRQ storm
3959 * detection, as short HPD storms will occur as a natural part of
3960 * sideband messaging with MST.
3961 * On older platforms however, IRQ storms can occur with both long and
3962 * short pulses, as seen on some G4x systems.
3964 dev_priv->hotplug.hpd_short_storm_enabled = !HAS_DP_MST(dev_priv);
3966 if (HAS_GMCH(dev_priv)) {
3967 if (I915_HAS_HOTPLUG(dev_priv))
3968 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3970 if (HAS_PCH_JSP(dev_priv))
3971 dev_priv->display.hpd_irq_setup = jsp_hpd_irq_setup;
3972 else if (HAS_PCH_MCC(dev_priv))
3973 dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup;
3974 else if (INTEL_GEN(dev_priv) >= 11)
3975 dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
3976 else if (IS_GEN9_LP(dev_priv))
3977 dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
3978 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
3979 dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
3981 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
3986 * intel_irq_fini - deinitializes IRQ support
3987 * @i915: i915 device instance
3989 * This function deinitializes all the IRQ support.
3991 void intel_irq_fini(struct drm_i915_private *i915)
3995 for (i = 0; i < MAX_L3_SLICES; ++i)
3996 kfree(i915->l3_parity.remap_info[i]);
3999 static irq_handler_t intel_irq_handler(struct drm_i915_private *dev_priv)
4001 if (HAS_GMCH(dev_priv)) {
4002 if (IS_CHERRYVIEW(dev_priv))
4003 return cherryview_irq_handler;
4004 else if (IS_VALLEYVIEW(dev_priv))
4005 return valleyview_irq_handler;
4006 else if (IS_GEN(dev_priv, 4))
4007 return i965_irq_handler;
4008 else if (IS_GEN(dev_priv, 3))
4009 return i915_irq_handler;
4011 return i8xx_irq_handler;
4013 if (INTEL_GEN(dev_priv) >= 11)
4014 return gen11_irq_handler;
4015 else if (INTEL_GEN(dev_priv) >= 8)
4016 return gen8_irq_handler;
4018 return ilk_irq_handler;
4022 static void intel_irq_reset(struct drm_i915_private *dev_priv)
4024 if (HAS_GMCH(dev_priv)) {
4025 if (IS_CHERRYVIEW(dev_priv))
4026 cherryview_irq_reset(dev_priv);
4027 else if (IS_VALLEYVIEW(dev_priv))
4028 valleyview_irq_reset(dev_priv);
4029 else if (IS_GEN(dev_priv, 4))
4030 i965_irq_reset(dev_priv);
4031 else if (IS_GEN(dev_priv, 3))
4032 i915_irq_reset(dev_priv);
4034 i8xx_irq_reset(dev_priv);
4036 if (INTEL_GEN(dev_priv) >= 11)
4037 gen11_irq_reset(dev_priv);
4038 else if (INTEL_GEN(dev_priv) >= 8)
4039 gen8_irq_reset(dev_priv);
4041 ilk_irq_reset(dev_priv);
4045 static void intel_irq_postinstall(struct drm_i915_private *dev_priv)
4047 if (HAS_GMCH(dev_priv)) {
4048 if (IS_CHERRYVIEW(dev_priv))
4049 cherryview_irq_postinstall(dev_priv);
4050 else if (IS_VALLEYVIEW(dev_priv))
4051 valleyview_irq_postinstall(dev_priv);
4052 else if (IS_GEN(dev_priv, 4))
4053 i965_irq_postinstall(dev_priv);
4054 else if (IS_GEN(dev_priv, 3))
4055 i915_irq_postinstall(dev_priv);
4057 i8xx_irq_postinstall(dev_priv);
4059 if (INTEL_GEN(dev_priv) >= 11)
4060 gen11_irq_postinstall(dev_priv);
4061 else if (INTEL_GEN(dev_priv) >= 8)
4062 gen8_irq_postinstall(dev_priv);
4064 ilk_irq_postinstall(dev_priv);
4069 * intel_irq_install - enables the hardware interrupt
4070 * @dev_priv: i915 device instance
4072 * This function enables the hardware interrupt handling, but leaves the hotplug
4073 * handling still disabled. It is called after intel_irq_init().
4075 * In the driver load and resume code we need working interrupts in a few places
4076 * but don't want to deal with the hassle of concurrent probe and hotplug
4077 * workers. Hence the split into this two-stage approach.
4079 int intel_irq_install(struct drm_i915_private *dev_priv)
4081 int irq = dev_priv->drm.pdev->irq;
4085 * We enable some interrupt sources in our postinstall hooks, so mark
4086 * interrupts as enabled _before_ actually enabling them to avoid
4087 * special cases in our ordering checks.
4089 dev_priv->runtime_pm.irqs_enabled = true;
4091 dev_priv->drm.irq_enabled = true;
4093 intel_irq_reset(dev_priv);
4095 ret = request_irq(irq, intel_irq_handler(dev_priv),
4096 IRQF_SHARED, DRIVER_NAME, dev_priv);
4098 dev_priv->drm.irq_enabled = false;
4102 intel_irq_postinstall(dev_priv);
4108 * intel_irq_uninstall - finilizes all irq handling
4109 * @dev_priv: i915 device instance
4111 * This stops interrupt and hotplug handling and unregisters and frees all
4112 * resources acquired in the init functions.
4114 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4116 int irq = dev_priv->drm.pdev->irq;
4119 * FIXME we can get called twice during driver probe
4120 * error handling as well as during driver remove due to
4121 * intel_modeset_driver_remove() calling us out of sequence.
4122 * Would be nice if it didn't do that...
4124 if (!dev_priv->drm.irq_enabled)
4127 dev_priv->drm.irq_enabled = false;
4129 intel_irq_reset(dev_priv);
4131 free_irq(irq, dev_priv);
4133 intel_hpd_cancel_work(dev_priv);
4134 dev_priv->runtime_pm.irqs_enabled = false;
4138 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4139 * @dev_priv: i915 device instance
4141 * This function is used to disable interrupts at runtime, both in the runtime
4142 * pm and the system suspend/resume code.
4144 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4146 intel_irq_reset(dev_priv);
4147 dev_priv->runtime_pm.irqs_enabled = false;
4148 intel_synchronize_irq(dev_priv);
4152 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4153 * @dev_priv: i915 device instance
4155 * This function is used to enable interrupts at runtime, both in the runtime
4156 * pm and the system suspend/resume code.
4158 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4160 dev_priv->runtime_pm.irqs_enabled = true;
4161 intel_irq_reset(dev_priv);
4162 intel_irq_postinstall(dev_priv);
4165 bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
4168 * We only use drm_irq_uninstall() at unload and VT switch, so
4169 * this is the only thing we need to check.
4171 return dev_priv->runtime_pm.irqs_enabled;
4174 void intel_synchronize_irq(struct drm_i915_private *i915)
4176 synchronize_irq(i915->drm.pdev->irq);