1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/circ_buf.h>
32 #include <linux/cpuidle.h>
33 #include <linux/slab.h>
34 #include <linux/sysrq.h>
36 #include <drm/drm_drv.h>
37 #include <drm/drm_irq.h>
38 #include <drm/i915_drm.h>
40 #include "display/intel_fifo_underrun.h"
41 #include "display/intel_hotplug.h"
42 #include "display/intel_lpe_audio.h"
43 #include "display/intel_psr.h"
47 #include "i915_trace.h"
48 #include "intel_drv.h"
52 * DOC: interrupt handling
54 * These functions provide the basic support for enabling and disabling the
55 * interrupt handling support. There's a lot more functionality in i915_irq.c
56 * and related files, but that will be described in separate chapters.
59 static const u32 hpd_ilk[HPD_NUM_PINS] = {
60 [HPD_PORT_A] = DE_DP_A_HOTPLUG,
63 static const u32 hpd_ivb[HPD_NUM_PINS] = {
64 [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
67 static const u32 hpd_bdw[HPD_NUM_PINS] = {
68 [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
71 static const u32 hpd_ibx[HPD_NUM_PINS] = {
72 [HPD_CRT] = SDE_CRT_HOTPLUG,
73 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
74 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
75 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
76 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
79 static const u32 hpd_cpt[HPD_NUM_PINS] = {
80 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
81 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
82 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
83 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
84 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
87 static const u32 hpd_spt[HPD_NUM_PINS] = {
88 [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
89 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
90 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
91 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
92 [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT
95 static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
96 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
97 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
98 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
99 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
100 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
101 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
104 static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
105 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
106 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
107 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
108 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
109 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
110 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
113 static const u32 hpd_status_i915[HPD_NUM_PINS] = {
114 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
115 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
116 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
117 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
118 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
119 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
123 static const u32 hpd_bxt[HPD_NUM_PINS] = {
124 [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
125 [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
126 [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
129 static const u32 hpd_gen11[HPD_NUM_PINS] = {
130 [HPD_PORT_C] = GEN11_TC1_HOTPLUG | GEN11_TBT1_HOTPLUG,
131 [HPD_PORT_D] = GEN11_TC2_HOTPLUG | GEN11_TBT2_HOTPLUG,
132 [HPD_PORT_E] = GEN11_TC3_HOTPLUG | GEN11_TBT3_HOTPLUG,
133 [HPD_PORT_F] = GEN11_TC4_HOTPLUG | GEN11_TBT4_HOTPLUG
136 static const u32 hpd_icp[HPD_NUM_PINS] = {
137 [HPD_PORT_A] = SDE_DDIA_HOTPLUG_ICP,
138 [HPD_PORT_B] = SDE_DDIB_HOTPLUG_ICP,
139 [HPD_PORT_C] = SDE_TC1_HOTPLUG_ICP,
140 [HPD_PORT_D] = SDE_TC2_HOTPLUG_ICP,
141 [HPD_PORT_E] = SDE_TC3_HOTPLUG_ICP,
142 [HPD_PORT_F] = SDE_TC4_HOTPLUG_ICP
145 static const u32 hpd_mcc[HPD_NUM_PINS] = {
146 [HPD_PORT_A] = SDE_DDIA_HOTPLUG_ICP,
147 [HPD_PORT_B] = SDE_DDIB_HOTPLUG_ICP,
148 [HPD_PORT_C] = SDE_TC1_HOTPLUG_ICP
151 static void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
152 i915_reg_t iir, i915_reg_t ier)
154 intel_uncore_write(uncore, imr, 0xffffffff);
155 intel_uncore_posting_read(uncore, imr);
157 intel_uncore_write(uncore, ier, 0);
159 /* IIR can theoretically queue up two events. Be paranoid. */
160 intel_uncore_write(uncore, iir, 0xffffffff);
161 intel_uncore_posting_read(uncore, iir);
162 intel_uncore_write(uncore, iir, 0xffffffff);
163 intel_uncore_posting_read(uncore, iir);
166 static void gen2_irq_reset(struct intel_uncore *uncore)
168 intel_uncore_write16(uncore, GEN2_IMR, 0xffff);
169 intel_uncore_posting_read16(uncore, GEN2_IMR);
171 intel_uncore_write16(uncore, GEN2_IER, 0);
173 /* IIR can theoretically queue up two events. Be paranoid. */
174 intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
175 intel_uncore_posting_read16(uncore, GEN2_IIR);
176 intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
177 intel_uncore_posting_read16(uncore, GEN2_IIR);
180 #define GEN8_IRQ_RESET_NDX(uncore, type, which) \
182 unsigned int which_ = which; \
183 gen3_irq_reset((uncore), GEN8_##type##_IMR(which_), \
184 GEN8_##type##_IIR(which_), GEN8_##type##_IER(which_)); \
187 #define GEN3_IRQ_RESET(uncore, type) \
188 gen3_irq_reset((uncore), type##IMR, type##IIR, type##IER)
190 #define GEN2_IRQ_RESET(uncore) \
191 gen2_irq_reset(uncore)
194 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
196 static void gen3_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg)
198 u32 val = intel_uncore_read(uncore, reg);
203 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
204 i915_mmio_reg_offset(reg), val);
205 intel_uncore_write(uncore, reg, 0xffffffff);
206 intel_uncore_posting_read(uncore, reg);
207 intel_uncore_write(uncore, reg, 0xffffffff);
208 intel_uncore_posting_read(uncore, reg);
211 static void gen2_assert_iir_is_zero(struct intel_uncore *uncore)
213 u16 val = intel_uncore_read16(uncore, GEN2_IIR);
218 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
219 i915_mmio_reg_offset(GEN2_IIR), val);
220 intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
221 intel_uncore_posting_read16(uncore, GEN2_IIR);
222 intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
223 intel_uncore_posting_read16(uncore, GEN2_IIR);
226 static void gen3_irq_init(struct intel_uncore *uncore,
227 i915_reg_t imr, u32 imr_val,
228 i915_reg_t ier, u32 ier_val,
231 gen3_assert_iir_is_zero(uncore, iir);
233 intel_uncore_write(uncore, ier, ier_val);
234 intel_uncore_write(uncore, imr, imr_val);
235 intel_uncore_posting_read(uncore, imr);
238 static void gen2_irq_init(struct intel_uncore *uncore,
239 u32 imr_val, u32 ier_val)
241 gen2_assert_iir_is_zero(uncore);
243 intel_uncore_write16(uncore, GEN2_IER, ier_val);
244 intel_uncore_write16(uncore, GEN2_IMR, imr_val);
245 intel_uncore_posting_read16(uncore, GEN2_IMR);
248 #define GEN8_IRQ_INIT_NDX(uncore, type, which, imr_val, ier_val) \
250 unsigned int which_ = which; \
251 gen3_irq_init((uncore), \
252 GEN8_##type##_IMR(which_), imr_val, \
253 GEN8_##type##_IER(which_), ier_val, \
254 GEN8_##type##_IIR(which_)); \
257 #define GEN3_IRQ_INIT(uncore, type, imr_val, ier_val) \
258 gen3_irq_init((uncore), \
259 type##IMR, imr_val, \
260 type##IER, ier_val, \
263 #define GEN2_IRQ_INIT(uncore, imr_val, ier_val) \
264 gen2_irq_init((uncore), imr_val, ier_val)
266 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
267 static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
269 /* For display hotplug interrupt */
271 i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
277 lockdep_assert_held(&dev_priv->irq_lock);
278 WARN_ON(bits & ~mask);
280 val = I915_READ(PORT_HOTPLUG_EN);
283 I915_WRITE(PORT_HOTPLUG_EN, val);
287 * i915_hotplug_interrupt_update - update hotplug interrupt enable
288 * @dev_priv: driver private
289 * @mask: bits to update
290 * @bits: bits to enable
291 * NOTE: the HPD enable bits are modified both inside and outside
292 * of an interrupt context. To avoid that read-modify-write cycles
293 * interfer, these bits are protected by a spinlock. Since this
294 * function is usually not called from a context where the lock is
295 * held already, this function acquires the lock itself. A non-locking
296 * version is also available.
298 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
302 spin_lock_irq(&dev_priv->irq_lock);
303 i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
304 spin_unlock_irq(&dev_priv->irq_lock);
308 gen11_gt_engine_identity(struct drm_i915_private * const i915,
309 const unsigned int bank, const unsigned int bit);
311 static bool gen11_reset_one_iir(struct drm_i915_private * const i915,
312 const unsigned int bank,
313 const unsigned int bit)
315 void __iomem * const regs = i915->uncore.regs;
318 lockdep_assert_held(&i915->irq_lock);
320 dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));
323 * According to the BSpec, DW_IIR bits cannot be cleared without
324 * first servicing the Selector & Shared IIR registers.
326 gen11_gt_engine_identity(i915, bank, bit);
329 * We locked GT INT DW by reading it. If we want to (try
330 * to) recover from this succesfully, we need to clear
331 * our bit, otherwise we are locking the register for
334 raw_reg_write(regs, GEN11_GT_INTR_DW(bank), BIT(bit));
343 * ilk_update_display_irq - update DEIMR
344 * @dev_priv: driver private
345 * @interrupt_mask: mask of interrupt bits to update
346 * @enabled_irq_mask: mask of interrupt bits to enable
348 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
350 u32 enabled_irq_mask)
354 lockdep_assert_held(&dev_priv->irq_lock);
356 WARN_ON(enabled_irq_mask & ~interrupt_mask);
358 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
361 new_val = dev_priv->irq_mask;
362 new_val &= ~interrupt_mask;
363 new_val |= (~enabled_irq_mask & interrupt_mask);
365 if (new_val != dev_priv->irq_mask) {
366 dev_priv->irq_mask = new_val;
367 I915_WRITE(DEIMR, dev_priv->irq_mask);
373 * ilk_update_gt_irq - update GTIMR
374 * @dev_priv: driver private
375 * @interrupt_mask: mask of interrupt bits to update
376 * @enabled_irq_mask: mask of interrupt bits to enable
378 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
380 u32 enabled_irq_mask)
382 lockdep_assert_held(&dev_priv->irq_lock);
384 WARN_ON(enabled_irq_mask & ~interrupt_mask);
386 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
389 dev_priv->gt_irq_mask &= ~interrupt_mask;
390 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
391 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
394 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, u32 mask)
396 ilk_update_gt_irq(dev_priv, mask, mask);
397 intel_uncore_posting_read_fw(&dev_priv->uncore, GTIMR);
400 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, u32 mask)
402 ilk_update_gt_irq(dev_priv, mask, 0);
405 static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
407 WARN_ON_ONCE(INTEL_GEN(dev_priv) >= 11);
409 return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
412 static void write_pm_imr(struct drm_i915_private *dev_priv)
415 u32 mask = dev_priv->pm_imr;
417 if (INTEL_GEN(dev_priv) >= 11) {
418 reg = GEN11_GPM_WGBOXPERF_INTR_MASK;
419 /* pm is in upper half */
421 } else if (INTEL_GEN(dev_priv) >= 8) {
422 reg = GEN8_GT_IMR(2);
427 I915_WRITE(reg, mask);
431 static void write_pm_ier(struct drm_i915_private *dev_priv)
434 u32 mask = dev_priv->pm_ier;
436 if (INTEL_GEN(dev_priv) >= 11) {
437 reg = GEN11_GPM_WGBOXPERF_INTR_ENABLE;
438 /* pm is in upper half */
440 } else if (INTEL_GEN(dev_priv) >= 8) {
441 reg = GEN8_GT_IER(2);
446 I915_WRITE(reg, mask);
450 * snb_update_pm_irq - update GEN6_PMIMR
451 * @dev_priv: driver private
452 * @interrupt_mask: mask of interrupt bits to update
453 * @enabled_irq_mask: mask of interrupt bits to enable
455 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
457 u32 enabled_irq_mask)
461 WARN_ON(enabled_irq_mask & ~interrupt_mask);
463 lockdep_assert_held(&dev_priv->irq_lock);
465 new_val = dev_priv->pm_imr;
466 new_val &= ~interrupt_mask;
467 new_val |= (~enabled_irq_mask & interrupt_mask);
469 if (new_val != dev_priv->pm_imr) {
470 dev_priv->pm_imr = new_val;
471 write_pm_imr(dev_priv);
475 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
477 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
480 snb_update_pm_irq(dev_priv, mask, mask);
483 static void __gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
485 snb_update_pm_irq(dev_priv, mask, 0);
488 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
490 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
493 __gen6_mask_pm_irq(dev_priv, mask);
496 static void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
498 i915_reg_t reg = gen6_pm_iir(dev_priv);
500 lockdep_assert_held(&dev_priv->irq_lock);
502 I915_WRITE(reg, reset_mask);
503 I915_WRITE(reg, reset_mask);
507 static void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask)
509 lockdep_assert_held(&dev_priv->irq_lock);
511 dev_priv->pm_ier |= enable_mask;
512 write_pm_ier(dev_priv);
513 gen6_unmask_pm_irq(dev_priv, enable_mask);
514 /* unmask_pm_irq provides an implicit barrier (POSTING_READ) */
517 static void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask)
519 lockdep_assert_held(&dev_priv->irq_lock);
521 dev_priv->pm_ier &= ~disable_mask;
522 __gen6_mask_pm_irq(dev_priv, disable_mask);
523 write_pm_ier(dev_priv);
524 /* though a barrier is missing here, but don't really need a one */
527 void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv)
529 spin_lock_irq(&dev_priv->irq_lock);
531 while (gen11_reset_one_iir(dev_priv, 0, GEN11_GTPM))
534 dev_priv->gt_pm.rps.pm_iir = 0;
536 spin_unlock_irq(&dev_priv->irq_lock);
539 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
541 spin_lock_irq(&dev_priv->irq_lock);
542 gen6_reset_pm_iir(dev_priv, GEN6_PM_RPS_EVENTS);
543 dev_priv->gt_pm.rps.pm_iir = 0;
544 spin_unlock_irq(&dev_priv->irq_lock);
547 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
549 struct intel_rps *rps = &dev_priv->gt_pm.rps;
551 if (READ_ONCE(rps->interrupts_enabled))
554 spin_lock_irq(&dev_priv->irq_lock);
555 WARN_ON_ONCE(rps->pm_iir);
557 if (INTEL_GEN(dev_priv) >= 11)
558 WARN_ON_ONCE(gen11_reset_one_iir(dev_priv, 0, GEN11_GTPM));
560 WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
562 rps->interrupts_enabled = true;
563 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
565 spin_unlock_irq(&dev_priv->irq_lock);
568 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
570 struct intel_rps *rps = &dev_priv->gt_pm.rps;
572 if (!READ_ONCE(rps->interrupts_enabled))
575 spin_lock_irq(&dev_priv->irq_lock);
576 rps->interrupts_enabled = false;
578 I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0u));
580 gen6_disable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
582 spin_unlock_irq(&dev_priv->irq_lock);
583 synchronize_irq(dev_priv->drm.irq);
585 /* Now that we will not be generating any more work, flush any
586 * outstanding tasks. As we are called on the RPS idle path,
587 * we will reset the GPU to minimum frequencies, so the current
588 * state of the worker can be discarded.
590 cancel_work_sync(&rps->work);
591 if (INTEL_GEN(dev_priv) >= 11)
592 gen11_reset_rps_interrupts(dev_priv);
594 gen6_reset_rps_interrupts(dev_priv);
597 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
599 assert_rpm_wakelock_held(&dev_priv->runtime_pm);
601 spin_lock_irq(&dev_priv->irq_lock);
602 gen6_reset_pm_iir(dev_priv, dev_priv->pm_guc_events);
603 spin_unlock_irq(&dev_priv->irq_lock);
606 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
608 assert_rpm_wakelock_held(&dev_priv->runtime_pm);
610 spin_lock_irq(&dev_priv->irq_lock);
611 if (!dev_priv->guc.interrupts.enabled) {
612 WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
613 dev_priv->pm_guc_events);
614 dev_priv->guc.interrupts.enabled = true;
615 gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events);
617 spin_unlock_irq(&dev_priv->irq_lock);
620 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
622 assert_rpm_wakelock_held(&dev_priv->runtime_pm);
624 spin_lock_irq(&dev_priv->irq_lock);
625 dev_priv->guc.interrupts.enabled = false;
627 gen6_disable_pm_irq(dev_priv, dev_priv->pm_guc_events);
629 spin_unlock_irq(&dev_priv->irq_lock);
630 synchronize_irq(dev_priv->drm.irq);
632 gen9_reset_guc_interrupts(dev_priv);
635 void gen11_reset_guc_interrupts(struct drm_i915_private *i915)
637 spin_lock_irq(&i915->irq_lock);
638 gen11_reset_one_iir(i915, 0, GEN11_GUC);
639 spin_unlock_irq(&i915->irq_lock);
642 void gen11_enable_guc_interrupts(struct drm_i915_private *dev_priv)
644 spin_lock_irq(&dev_priv->irq_lock);
645 if (!dev_priv->guc.interrupts.enabled) {
646 u32 events = REG_FIELD_PREP(ENGINE1_MASK,
647 GEN11_GUC_INTR_GUC2HOST);
649 WARN_ON_ONCE(gen11_reset_one_iir(dev_priv, 0, GEN11_GUC));
650 I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, events);
651 I915_WRITE(GEN11_GUC_SG_INTR_MASK, ~events);
652 dev_priv->guc.interrupts.enabled = true;
654 spin_unlock_irq(&dev_priv->irq_lock);
657 void gen11_disable_guc_interrupts(struct drm_i915_private *dev_priv)
659 spin_lock_irq(&dev_priv->irq_lock);
660 dev_priv->guc.interrupts.enabled = false;
662 I915_WRITE(GEN11_GUC_SG_INTR_MASK, ~0);
663 I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, 0);
665 spin_unlock_irq(&dev_priv->irq_lock);
666 synchronize_irq(dev_priv->drm.irq);
668 gen11_reset_guc_interrupts(dev_priv);
672 * bdw_update_port_irq - update DE port interrupt
673 * @dev_priv: driver private
674 * @interrupt_mask: mask of interrupt bits to update
675 * @enabled_irq_mask: mask of interrupt bits to enable
677 static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
679 u32 enabled_irq_mask)
684 lockdep_assert_held(&dev_priv->irq_lock);
686 WARN_ON(enabled_irq_mask & ~interrupt_mask);
688 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
691 old_val = I915_READ(GEN8_DE_PORT_IMR);
694 new_val &= ~interrupt_mask;
695 new_val |= (~enabled_irq_mask & interrupt_mask);
697 if (new_val != old_val) {
698 I915_WRITE(GEN8_DE_PORT_IMR, new_val);
699 POSTING_READ(GEN8_DE_PORT_IMR);
704 * bdw_update_pipe_irq - update DE pipe interrupt
705 * @dev_priv: driver private
706 * @pipe: pipe whose interrupt to update
707 * @interrupt_mask: mask of interrupt bits to update
708 * @enabled_irq_mask: mask of interrupt bits to enable
710 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
713 u32 enabled_irq_mask)
717 lockdep_assert_held(&dev_priv->irq_lock);
719 WARN_ON(enabled_irq_mask & ~interrupt_mask);
721 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
724 new_val = dev_priv->de_irq_mask[pipe];
725 new_val &= ~interrupt_mask;
726 new_val |= (~enabled_irq_mask & interrupt_mask);
728 if (new_val != dev_priv->de_irq_mask[pipe]) {
729 dev_priv->de_irq_mask[pipe] = new_val;
730 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
731 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
736 * ibx_display_interrupt_update - update SDEIMR
737 * @dev_priv: driver private
738 * @interrupt_mask: mask of interrupt bits to update
739 * @enabled_irq_mask: mask of interrupt bits to enable
741 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
743 u32 enabled_irq_mask)
745 u32 sdeimr = I915_READ(SDEIMR);
746 sdeimr &= ~interrupt_mask;
747 sdeimr |= (~enabled_irq_mask & interrupt_mask);
749 WARN_ON(enabled_irq_mask & ~interrupt_mask);
751 lockdep_assert_held(&dev_priv->irq_lock);
753 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
756 I915_WRITE(SDEIMR, sdeimr);
757 POSTING_READ(SDEIMR);
760 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
763 u32 status_mask = dev_priv->pipestat_irq_mask[pipe];
764 u32 enable_mask = status_mask << 16;
766 lockdep_assert_held(&dev_priv->irq_lock);
768 if (INTEL_GEN(dev_priv) < 5)
772 * On pipe A we don't support the PSR interrupt yet,
773 * on pipe B and C the same bit MBZ.
775 if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
778 * On pipe B and C we don't support the PSR interrupt yet, on pipe
779 * A the same bit is for perf counters which we don't use either.
781 if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
784 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
785 SPRITE0_FLIP_DONE_INT_EN_VLV |
786 SPRITE1_FLIP_DONE_INT_EN_VLV);
787 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
788 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
789 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
790 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
793 WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
794 status_mask & ~PIPESTAT_INT_STATUS_MASK,
795 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
796 pipe_name(pipe), enable_mask, status_mask);
801 void i915_enable_pipestat(struct drm_i915_private *dev_priv,
802 enum pipe pipe, u32 status_mask)
804 i915_reg_t reg = PIPESTAT(pipe);
807 WARN_ONCE(status_mask & ~PIPESTAT_INT_STATUS_MASK,
808 "pipe %c: status_mask=0x%x\n",
809 pipe_name(pipe), status_mask);
811 lockdep_assert_held(&dev_priv->irq_lock);
812 WARN_ON(!intel_irqs_enabled(dev_priv));
814 if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == status_mask)
817 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
818 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
820 I915_WRITE(reg, enable_mask | status_mask);
824 void i915_disable_pipestat(struct drm_i915_private *dev_priv,
825 enum pipe pipe, u32 status_mask)
827 i915_reg_t reg = PIPESTAT(pipe);
830 WARN_ONCE(status_mask & ~PIPESTAT_INT_STATUS_MASK,
831 "pipe %c: status_mask=0x%x\n",
832 pipe_name(pipe), status_mask);
834 lockdep_assert_held(&dev_priv->irq_lock);
835 WARN_ON(!intel_irqs_enabled(dev_priv));
837 if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == 0)
840 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
841 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
843 I915_WRITE(reg, enable_mask | status_mask);
847 static bool i915_has_asle(struct drm_i915_private *dev_priv)
849 if (!dev_priv->opregion.asle)
852 return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
856 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
857 * @dev_priv: i915 device private
859 static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
861 if (!i915_has_asle(dev_priv))
864 spin_lock_irq(&dev_priv->irq_lock);
866 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
867 if (INTEL_GEN(dev_priv) >= 4)
868 i915_enable_pipestat(dev_priv, PIPE_A,
869 PIPE_LEGACY_BLC_EVENT_STATUS);
871 spin_unlock_irq(&dev_priv->irq_lock);
875 * This timing diagram depicts the video signal in and
876 * around the vertical blanking period.
878 * Assumptions about the fictitious mode used in this example:
880 * vsync_start = vblank_start + 1
881 * vsync_end = vblank_start + 2
882 * vtotal = vblank_start + 3
885 * latch double buffered registers
886 * increment frame counter (ctg+)
887 * generate start of vblank interrupt (gen4+)
890 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
891 * | may be shifted forward 1-3 extra lines via PIPECONF
893 * | | start of vsync:
894 * | | generate vsync interrupt
896 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
897 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
898 * ----va---> <-----------------vb--------------------> <--------va-------------
899 * | | <----vs-----> |
900 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
901 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
902 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
904 * last visible pixel first visible pixel
905 * | increment frame counter (gen3/4)
906 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
908 * x = horizontal active
909 * _ = horizontal blanking
910 * hs = horizontal sync
911 * va = vertical active
912 * vb = vertical blanking
914 * vbs = vblank_start (number)
917 * - most events happen at the start of horizontal sync
918 * - frame start happens at the start of horizontal blank, 1-4 lines
919 * (depending on PIPECONF settings) after the start of vblank
920 * - gen3/4 pixel and frame counter are synchronized with the start
921 * of horizontal active on the first line of vertical active
924 /* Called from drm generic code, passed a 'crtc', which
925 * we use as a pipe index
927 static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
929 struct drm_i915_private *dev_priv = to_i915(dev);
930 struct drm_vblank_crtc *vblank = &dev->vblank[pipe];
931 const struct drm_display_mode *mode = &vblank->hwmode;
932 i915_reg_t high_frame, low_frame;
933 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
934 unsigned long irqflags;
937 * On i965gm TV output the frame counter only works up to
938 * the point when we enable the TV encoder. After that the
939 * frame counter ceases to work and reads zero. We need a
940 * vblank wait before enabling the TV encoder and so we
941 * have to enable vblank interrupts while the frame counter
942 * is still in a working state. However the core vblank code
943 * does not like us returning non-zero frame counter values
944 * when we've told it that we don't have a working frame
945 * counter. Thus we must stop non-zero values leaking out.
947 if (!vblank->max_vblank_count)
950 htotal = mode->crtc_htotal;
951 hsync_start = mode->crtc_hsync_start;
952 vbl_start = mode->crtc_vblank_start;
953 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
954 vbl_start = DIV_ROUND_UP(vbl_start, 2);
956 /* Convert to pixel count */
959 /* Start of vblank event occurs at start of hsync */
960 vbl_start -= htotal - hsync_start;
962 high_frame = PIPEFRAME(pipe);
963 low_frame = PIPEFRAMEPIXEL(pipe);
965 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
968 * High & low register fields aren't synchronized, so make sure
969 * we get a low value that's stable across two reads of the high
973 high1 = I915_READ_FW(high_frame) & PIPE_FRAME_HIGH_MASK;
974 low = I915_READ_FW(low_frame);
975 high2 = I915_READ_FW(high_frame) & PIPE_FRAME_HIGH_MASK;
976 } while (high1 != high2);
978 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
980 high1 >>= PIPE_FRAME_HIGH_SHIFT;
981 pixel = low & PIPE_PIXEL_MASK;
982 low >>= PIPE_FRAME_LOW_SHIFT;
985 * The frame counter increments at beginning of active.
986 * Cook up a vblank counter by also checking the pixel
987 * counter against vblank start.
989 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
992 static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
994 struct drm_i915_private *dev_priv = to_i915(dev);
996 return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
1000 * On certain encoders on certain platforms, pipe
1001 * scanline register will not work to get the scanline,
1002 * since the timings are driven from the PORT or issues
1003 * with scanline register updates.
1004 * This function will use Framestamp and current
1005 * timestamp registers to calculate the scanline.
1007 static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)
1009 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1010 struct drm_vblank_crtc *vblank =
1011 &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
1012 const struct drm_display_mode *mode = &vblank->hwmode;
1013 u32 vblank_start = mode->crtc_vblank_start;
1014 u32 vtotal = mode->crtc_vtotal;
1015 u32 htotal = mode->crtc_htotal;
1016 u32 clock = mode->crtc_clock;
1017 u32 scanline, scan_prev_time, scan_curr_time, scan_post_time;
1020 * To avoid the race condition where we might cross into the
1021 * next vblank just between the PIPE_FRMTMSTMP and TIMESTAMP_CTR
1022 * reads. We make sure we read PIPE_FRMTMSTMP and TIMESTAMP_CTR
1023 * during the same frame.
1027 * This field provides read back of the display
1028 * pipe frame time stamp. The time stamp value
1029 * is sampled at every start of vertical blank.
1031 scan_prev_time = I915_READ_FW(PIPE_FRMTMSTMP(crtc->pipe));
1034 * The TIMESTAMP_CTR register has the current
1037 scan_curr_time = I915_READ_FW(IVB_TIMESTAMP_CTR);
1039 scan_post_time = I915_READ_FW(PIPE_FRMTMSTMP(crtc->pipe));
1040 } while (scan_post_time != scan_prev_time);
1042 scanline = div_u64(mul_u32_u32(scan_curr_time - scan_prev_time,
1043 clock), 1000 * htotal);
1044 scanline = min(scanline, vtotal - 1);
1045 scanline = (scanline + vblank_start) % vtotal;
1050 /* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
1051 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
1053 struct drm_device *dev = crtc->base.dev;
1054 struct drm_i915_private *dev_priv = to_i915(dev);
1055 const struct drm_display_mode *mode;
1056 struct drm_vblank_crtc *vblank;
1057 enum pipe pipe = crtc->pipe;
1058 int position, vtotal;
1063 vblank = &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
1064 mode = &vblank->hwmode;
1066 if (mode->private_flags & I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP)
1067 return __intel_get_crtc_scanline_from_timestamp(crtc);
1069 vtotal = mode->crtc_vtotal;
1070 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1073 if (IS_GEN(dev_priv, 2))
1074 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
1076 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
1079 * On HSW, the DSL reg (0x70000) appears to return 0 if we
1080 * read it just before the start of vblank. So try it again
1081 * so we don't accidentally end up spanning a vblank frame
1082 * increment, causing the pipe_update_end() code to squak at us.
1084 * The nature of this problem means we can't simply check the ISR
1085 * bit and return the vblank start value; nor can we use the scanline
1086 * debug register in the transcoder as it appears to have the same
1087 * problem. We may need to extend this to include other platforms,
1088 * but so far testing only shows the problem on HSW.
1090 if (HAS_DDI(dev_priv) && !position) {
1093 for (i = 0; i < 100; i++) {
1095 temp = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
1096 if (temp != position) {
1104 * See update_scanline_offset() for the details on the
1105 * scanline_offset adjustment.
1107 return (position + crtc->scanline_offset) % vtotal;
1110 static bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
1111 bool in_vblank_irq, int *vpos, int *hpos,
1112 ktime_t *stime, ktime_t *etime,
1113 const struct drm_display_mode *mode)
1115 struct drm_i915_private *dev_priv = to_i915(dev);
1116 struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1119 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
1120 unsigned long irqflags;
1121 bool use_scanline_counter = INTEL_GEN(dev_priv) >= 5 ||
1122 IS_G4X(dev_priv) || IS_GEN(dev_priv, 2) ||
1123 mode->private_flags & I915_MODE_FLAG_USE_SCANLINE_COUNTER;
1125 if (WARN_ON(!mode->crtc_clock)) {
1126 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
1127 "pipe %c\n", pipe_name(pipe));
1131 htotal = mode->crtc_htotal;
1132 hsync_start = mode->crtc_hsync_start;
1133 vtotal = mode->crtc_vtotal;
1134 vbl_start = mode->crtc_vblank_start;
1135 vbl_end = mode->crtc_vblank_end;
1137 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1138 vbl_start = DIV_ROUND_UP(vbl_start, 2);
1144 * Lock uncore.lock, as we will do multiple timing critical raw
1145 * register reads, potentially with preemption disabled, so the
1146 * following code must not block on uncore.lock.
1148 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1150 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1152 /* Get optional system timestamp before query. */
1154 *stime = ktime_get();
1156 if (use_scanline_counter) {
1157 /* No obvious pixelcount register. Only query vertical
1158 * scanout position from Display scan line register.
1160 position = __intel_get_crtc_scanline(intel_crtc);
1162 /* Have access to pixelcount since start of frame.
1163 * We can split this into vertical and horizontal
1166 position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
1168 /* convert to pixel counts */
1169 vbl_start *= htotal;
1174 * In interlaced modes, the pixel counter counts all pixels,
1175 * so one field will have htotal more pixels. In order to avoid
1176 * the reported position from jumping backwards when the pixel
1177 * counter is beyond the length of the shorter field, just
1178 * clamp the position the length of the shorter field. This
1179 * matches how the scanline counter based position works since
1180 * the scanline counter doesn't count the two half lines.
1182 if (position >= vtotal)
1183 position = vtotal - 1;
1186 * Start of vblank interrupt is triggered at start of hsync,
1187 * just prior to the first active line of vblank. However we
1188 * consider lines to start at the leading edge of horizontal
1189 * active. So, should we get here before we've crossed into
1190 * the horizontal active of the first line in vblank, we would
1191 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
1192 * always add htotal-hsync_start to the current pixel position.
1194 position = (position + htotal - hsync_start) % vtotal;
1197 /* Get optional system timestamp after query. */
1199 *etime = ktime_get();
1201 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1203 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1206 * While in vblank, position will be negative
1207 * counting up towards 0 at vbl_end. And outside
1208 * vblank, position will be positive counting
1211 if (position >= vbl_start)
1212 position -= vbl_end;
1214 position += vtotal - vbl_end;
1216 if (use_scanline_counter) {
1220 *vpos = position / htotal;
1221 *hpos = position - (*vpos * htotal);
1227 int intel_get_crtc_scanline(struct intel_crtc *crtc)
1229 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1230 unsigned long irqflags;
1233 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1234 position = __intel_get_crtc_scanline(crtc);
1235 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1240 static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv)
1242 struct intel_uncore *uncore = &dev_priv->uncore;
1243 u32 busy_up, busy_down, max_avg, min_avg;
1246 spin_lock(&mchdev_lock);
1248 intel_uncore_write16(uncore,
1250 intel_uncore_read(uncore, MEMINTRSTS));
1252 new_delay = dev_priv->ips.cur_delay;
1254 intel_uncore_write16(uncore, MEMINTRSTS, MEMINT_EVAL_CHG);
1255 busy_up = intel_uncore_read(uncore, RCPREVBSYTUPAVG);
1256 busy_down = intel_uncore_read(uncore, RCPREVBSYTDNAVG);
1257 max_avg = intel_uncore_read(uncore, RCBMAXAVG);
1258 min_avg = intel_uncore_read(uncore, RCBMINAVG);
1260 /* Handle RCS change request from hw */
1261 if (busy_up > max_avg) {
1262 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
1263 new_delay = dev_priv->ips.cur_delay - 1;
1264 if (new_delay < dev_priv->ips.max_delay)
1265 new_delay = dev_priv->ips.max_delay;
1266 } else if (busy_down < min_avg) {
1267 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
1268 new_delay = dev_priv->ips.cur_delay + 1;
1269 if (new_delay > dev_priv->ips.min_delay)
1270 new_delay = dev_priv->ips.min_delay;
1273 if (ironlake_set_drps(dev_priv, new_delay))
1274 dev_priv->ips.cur_delay = new_delay;
1276 spin_unlock(&mchdev_lock);
1281 static void vlv_c0_read(struct drm_i915_private *dev_priv,
1282 struct intel_rps_ei *ei)
1284 ei->ktime = ktime_get_raw();
1285 ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
1286 ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
1289 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
1291 memset(&dev_priv->gt_pm.rps.ei, 0, sizeof(dev_priv->gt_pm.rps.ei));
1294 static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
1296 struct intel_rps *rps = &dev_priv->gt_pm.rps;
1297 const struct intel_rps_ei *prev = &rps->ei;
1298 struct intel_rps_ei now;
1301 if ((pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) == 0)
1304 vlv_c0_read(dev_priv, &now);
1310 time = ktime_us_delta(now.ktime, prev->ktime);
1312 time *= dev_priv->czclk_freq;
1314 /* Workload can be split between render + media,
1315 * e.g. SwapBuffers being blitted in X after being rendered in
1316 * mesa. To account for this we need to combine both engines
1317 * into our activity counter.
1319 render = now.render_c0 - prev->render_c0;
1320 media = now.media_c0 - prev->media_c0;
1321 c0 = max(render, media);
1322 c0 *= 1000 * 100 << 8; /* to usecs and scale to threshold% */
1324 if (c0 > time * rps->power.up_threshold)
1325 events = GEN6_PM_RP_UP_THRESHOLD;
1326 else if (c0 < time * rps->power.down_threshold)
1327 events = GEN6_PM_RP_DOWN_THRESHOLD;
1334 static void gen6_pm_rps_work(struct work_struct *work)
1336 struct drm_i915_private *dev_priv =
1337 container_of(work, struct drm_i915_private, gt_pm.rps.work);
1338 struct intel_rps *rps = &dev_priv->gt_pm.rps;
1339 bool client_boost = false;
1340 int new_delay, adj, min, max;
1343 spin_lock_irq(&dev_priv->irq_lock);
1344 if (rps->interrupts_enabled) {
1345 pm_iir = fetch_and_zero(&rps->pm_iir);
1346 client_boost = atomic_read(&rps->num_waiters);
1348 spin_unlock_irq(&dev_priv->irq_lock);
1350 /* Make sure we didn't queue anything we're not going to process. */
1351 WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1352 if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
1355 mutex_lock(&rps->lock);
1357 pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
1359 adj = rps->last_adj;
1360 new_delay = rps->cur_freq;
1361 min = rps->min_freq_softlimit;
1362 max = rps->max_freq_softlimit;
1364 max = rps->max_freq;
1365 if (client_boost && new_delay < rps->boost_freq) {
1366 new_delay = rps->boost_freq;
1368 } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1371 else /* CHV needs even encode values */
1372 adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
1374 if (new_delay >= rps->max_freq_softlimit)
1376 } else if (client_boost) {
1378 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1379 if (rps->cur_freq > rps->efficient_freq)
1380 new_delay = rps->efficient_freq;
1381 else if (rps->cur_freq > rps->min_freq_softlimit)
1382 new_delay = rps->min_freq_softlimit;
1384 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1387 else /* CHV needs even encode values */
1388 adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
1390 if (new_delay <= rps->min_freq_softlimit)
1392 } else { /* unknown event */
1396 rps->last_adj = adj;
1399 * Limit deboosting and boosting to keep ourselves at the extremes
1400 * when in the respective power modes (i.e. slowly decrease frequencies
1401 * while in the HIGH_POWER zone and slowly increase frequencies while
1402 * in the LOW_POWER zone). On idle, we will hit the timeout and drop
1403 * to the next level quickly, and conversely if busy we expect to
1404 * hit a waitboost and rapidly switch into max power.
1406 if ((adj < 0 && rps->power.mode == HIGH_POWER) ||
1407 (adj > 0 && rps->power.mode == LOW_POWER))
1410 /* sysfs frequency interfaces may have snuck in while servicing the
1414 new_delay = clamp_t(int, new_delay, min, max);
1416 if (intel_set_rps(dev_priv, new_delay)) {
1417 DRM_DEBUG_DRIVER("Failed to set new GPU frequency\n");
1421 mutex_unlock(&rps->lock);
1424 /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1425 spin_lock_irq(&dev_priv->irq_lock);
1426 if (rps->interrupts_enabled)
1427 gen6_unmask_pm_irq(dev_priv, dev_priv->pm_rps_events);
1428 spin_unlock_irq(&dev_priv->irq_lock);
1433 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1435 * @work: workqueue struct
1437 * Doesn't actually do anything except notify userspace. As a consequence of
1438 * this event, userspace should try to remap the bad rows since statistically
1439 * it is likely the same row is more likely to go bad again.
1441 static void ivybridge_parity_work(struct work_struct *work)
1443 struct drm_i915_private *dev_priv =
1444 container_of(work, typeof(*dev_priv), l3_parity.error_work);
1445 u32 error_status, row, bank, subbank;
1446 char *parity_event[6];
1450 /* We must turn off DOP level clock gating to access the L3 registers.
1451 * In order to prevent a get/put style interface, acquire struct mutex
1452 * any time we access those registers.
1454 mutex_lock(&dev_priv->drm.struct_mutex);
1456 /* If we've screwed up tracking, just let the interrupt fire again */
1457 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1460 misccpctl = I915_READ(GEN7_MISCCPCTL);
1461 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1462 POSTING_READ(GEN7_MISCCPCTL);
1464 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1468 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv)))
1471 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1473 reg = GEN7_L3CDERRST1(slice);
1475 error_status = I915_READ(reg);
1476 row = GEN7_PARITY_ERROR_ROW(error_status);
1477 bank = GEN7_PARITY_ERROR_BANK(error_status);
1478 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1480 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1483 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1484 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1485 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1486 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1487 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1488 parity_event[5] = NULL;
1490 kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj,
1491 KOBJ_CHANGE, parity_event);
1493 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1494 slice, row, bank, subbank);
1496 kfree(parity_event[4]);
1497 kfree(parity_event[3]);
1498 kfree(parity_event[2]);
1499 kfree(parity_event[1]);
1502 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1505 WARN_ON(dev_priv->l3_parity.which_slice);
1506 spin_lock_irq(&dev_priv->irq_lock);
1507 gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1508 spin_unlock_irq(&dev_priv->irq_lock);
1510 mutex_unlock(&dev_priv->drm.struct_mutex);
1513 static void ivybridge_parity_error_irq_handler(struct drm_i915_private *dev_priv,
1516 if (!HAS_L3_DPF(dev_priv))
1519 spin_lock(&dev_priv->irq_lock);
1520 gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1521 spin_unlock(&dev_priv->irq_lock);
1523 iir &= GT_PARITY_ERROR(dev_priv);
1524 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1525 dev_priv->l3_parity.which_slice |= 1 << 1;
1527 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1528 dev_priv->l3_parity.which_slice |= 1 << 0;
1530 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1533 static void ilk_gt_irq_handler(struct drm_i915_private *dev_priv,
1536 if (gt_iir & GT_RENDER_USER_INTERRUPT)
1537 intel_engine_breadcrumbs_irq(dev_priv->engine[RCS0]);
1538 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1539 intel_engine_breadcrumbs_irq(dev_priv->engine[VCS0]);
1542 static void snb_gt_irq_handler(struct drm_i915_private *dev_priv,
1545 if (gt_iir & GT_RENDER_USER_INTERRUPT)
1546 intel_engine_breadcrumbs_irq(dev_priv->engine[RCS0]);
1547 if (gt_iir & GT_BSD_USER_INTERRUPT)
1548 intel_engine_breadcrumbs_irq(dev_priv->engine[VCS0]);
1549 if (gt_iir & GT_BLT_USER_INTERRUPT)
1550 intel_engine_breadcrumbs_irq(dev_priv->engine[BCS0]);
1552 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1553 GT_BSD_CS_ERROR_INTERRUPT |
1554 GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1555 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1557 if (gt_iir & GT_PARITY_ERROR(dev_priv))
1558 ivybridge_parity_error_irq_handler(dev_priv, gt_iir);
1562 gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
1564 bool tasklet = false;
1566 if (iir & GT_CONTEXT_SWITCH_INTERRUPT)
1569 if (iir & GT_RENDER_USER_INTERRUPT) {
1570 intel_engine_breadcrumbs_irq(engine);
1571 tasklet |= intel_engine_needs_breadcrumb_tasklet(engine);
1575 tasklet_hi_schedule(&engine->execlists.tasklet);
1578 static void gen8_gt_irq_ack(struct drm_i915_private *i915,
1579 u32 master_ctl, u32 gt_iir[4])
1581 void __iomem * const regs = i915->uncore.regs;
1583 #define GEN8_GT_IRQS (GEN8_GT_RCS_IRQ | \
1585 GEN8_GT_VCS0_IRQ | \
1586 GEN8_GT_VCS1_IRQ | \
1587 GEN8_GT_VECS_IRQ | \
1591 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1592 gt_iir[0] = raw_reg_read(regs, GEN8_GT_IIR(0));
1593 if (likely(gt_iir[0]))
1594 raw_reg_write(regs, GEN8_GT_IIR(0), gt_iir[0]);
1597 if (master_ctl & (GEN8_GT_VCS0_IRQ | GEN8_GT_VCS1_IRQ)) {
1598 gt_iir[1] = raw_reg_read(regs, GEN8_GT_IIR(1));
1599 if (likely(gt_iir[1]))
1600 raw_reg_write(regs, GEN8_GT_IIR(1), gt_iir[1]);
1603 if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
1604 gt_iir[2] = raw_reg_read(regs, GEN8_GT_IIR(2));
1605 if (likely(gt_iir[2]))
1606 raw_reg_write(regs, GEN8_GT_IIR(2), gt_iir[2]);
1609 if (master_ctl & GEN8_GT_VECS_IRQ) {
1610 gt_iir[3] = raw_reg_read(regs, GEN8_GT_IIR(3));
1611 if (likely(gt_iir[3]))
1612 raw_reg_write(regs, GEN8_GT_IIR(3), gt_iir[3]);
1616 static void gen8_gt_irq_handler(struct drm_i915_private *i915,
1617 u32 master_ctl, u32 gt_iir[4])
1619 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1620 gen8_cs_irq_handler(i915->engine[RCS0],
1621 gt_iir[0] >> GEN8_RCS_IRQ_SHIFT);
1622 gen8_cs_irq_handler(i915->engine[BCS0],
1623 gt_iir[0] >> GEN8_BCS_IRQ_SHIFT);
1626 if (master_ctl & (GEN8_GT_VCS0_IRQ | GEN8_GT_VCS1_IRQ)) {
1627 gen8_cs_irq_handler(i915->engine[VCS0],
1628 gt_iir[1] >> GEN8_VCS0_IRQ_SHIFT);
1629 gen8_cs_irq_handler(i915->engine[VCS1],
1630 gt_iir[1] >> GEN8_VCS1_IRQ_SHIFT);
1633 if (master_ctl & GEN8_GT_VECS_IRQ) {
1634 gen8_cs_irq_handler(i915->engine[VECS0],
1635 gt_iir[3] >> GEN8_VECS_IRQ_SHIFT);
1638 if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
1639 gen6_rps_irq_handler(i915, gt_iir[2]);
1640 gen9_guc_irq_handler(i915, gt_iir[2]);
1644 static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1648 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC1);
1650 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC2);
1652 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC3);
1654 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC4);
1660 static bool bxt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1664 return val & PORTA_HOTPLUG_LONG_DETECT;
1666 return val & PORTB_HOTPLUG_LONG_DETECT;
1668 return val & PORTC_HOTPLUG_LONG_DETECT;
1674 static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1678 return val & ICP_DDIA_HPD_LONG_DETECT;
1680 return val & ICP_DDIB_HPD_LONG_DETECT;
1686 static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1690 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
1692 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
1694 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
1696 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
1702 static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val)
1706 return val & PORTE_HOTPLUG_LONG_DETECT;
1712 static bool spt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1716 return val & PORTA_HOTPLUG_LONG_DETECT;
1718 return val & PORTB_HOTPLUG_LONG_DETECT;
1720 return val & PORTC_HOTPLUG_LONG_DETECT;
1722 return val & PORTD_HOTPLUG_LONG_DETECT;
1728 static bool ilk_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1732 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
1738 static bool pch_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1742 return val & PORTB_HOTPLUG_LONG_DETECT;
1744 return val & PORTC_HOTPLUG_LONG_DETECT;
1746 return val & PORTD_HOTPLUG_LONG_DETECT;
1752 static bool i9xx_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1756 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1758 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1760 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1767 * Get a bit mask of pins that have triggered, and which ones may be long.
1768 * This can be called multiple times with the same masks to accumulate
1769 * hotplug detection results from several registers.
1771 * Note that the caller is expected to zero out the masks initially.
1773 static void intel_get_hpd_pins(struct drm_i915_private *dev_priv,
1774 u32 *pin_mask, u32 *long_mask,
1775 u32 hotplug_trigger, u32 dig_hotplug_reg,
1776 const u32 hpd[HPD_NUM_PINS],
1777 bool long_pulse_detect(enum hpd_pin pin, u32 val))
1781 for_each_hpd_pin(pin) {
1782 if ((hpd[pin] & hotplug_trigger) == 0)
1785 *pin_mask |= BIT(pin);
1787 if (long_pulse_detect(pin, dig_hotplug_reg))
1788 *long_mask |= BIT(pin);
1791 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x, long 0x%08x\n",
1792 hotplug_trigger, dig_hotplug_reg, *pin_mask, *long_mask);
1796 static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
1798 wake_up_all(&dev_priv->gmbus_wait_queue);
1801 static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
1803 wake_up_all(&dev_priv->gmbus_wait_queue);
1806 #if defined(CONFIG_DEBUG_FS)
1807 static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1813 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1814 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1815 u32 crcs[5] = { crc0, crc1, crc2, crc3, crc4 };
1817 trace_intel_pipe_crc(crtc, crcs);
1819 spin_lock(&pipe_crc->lock);
1821 * For some not yet identified reason, the first CRC is
1822 * bonkers. So let's just wait for the next vblank and read
1823 * out the buggy result.
1825 * On GEN8+ sometimes the second CRC is bonkers as well, so
1826 * don't trust that one either.
1828 if (pipe_crc->skipped <= 0 ||
1829 (INTEL_GEN(dev_priv) >= 8 && pipe_crc->skipped == 1)) {
1830 pipe_crc->skipped++;
1831 spin_unlock(&pipe_crc->lock);
1834 spin_unlock(&pipe_crc->lock);
1836 drm_crtc_add_crc_entry(&crtc->base, true,
1837 drm_crtc_accurate_vblank_count(&crtc->base),
1842 display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1850 static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1853 display_pipe_crc_irq_handler(dev_priv, pipe,
1854 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1858 static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1861 display_pipe_crc_irq_handler(dev_priv, pipe,
1862 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1863 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1864 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1865 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1866 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1869 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1874 if (INTEL_GEN(dev_priv) >= 3)
1875 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1879 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1880 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1884 display_pipe_crc_irq_handler(dev_priv, pipe,
1885 I915_READ(PIPE_CRC_RES_RED(pipe)),
1886 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1887 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1891 /* The RPS events need forcewake, so we add them to a work queue and mask their
1892 * IMR bits until the work is done. Other interrupts can be processed without
1893 * the work queue. */
1894 static void gen11_rps_irq_handler(struct drm_i915_private *i915, u32 pm_iir)
1896 struct intel_rps *rps = &i915->gt_pm.rps;
1897 const u32 events = i915->pm_rps_events & pm_iir;
1899 lockdep_assert_held(&i915->irq_lock);
1901 if (unlikely(!events))
1904 gen6_mask_pm_irq(i915, events);
1906 if (!rps->interrupts_enabled)
1909 rps->pm_iir |= events;
1910 schedule_work(&rps->work);
1913 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1915 struct intel_rps *rps = &dev_priv->gt_pm.rps;
1917 if (pm_iir & dev_priv->pm_rps_events) {
1918 spin_lock(&dev_priv->irq_lock);
1919 gen6_mask_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1920 if (rps->interrupts_enabled) {
1921 rps->pm_iir |= pm_iir & dev_priv->pm_rps_events;
1922 schedule_work(&rps->work);
1924 spin_unlock(&dev_priv->irq_lock);
1927 if (INTEL_GEN(dev_priv) >= 8)
1930 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1931 intel_engine_breadcrumbs_irq(dev_priv->engine[VECS0]);
1933 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1934 DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
1937 static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir)
1939 if (gt_iir & GEN9_GUC_TO_HOST_INT_EVENT)
1940 intel_guc_to_host_event_handler(&dev_priv->guc);
1943 static void gen11_guc_irq_handler(struct drm_i915_private *i915, u16 iir)
1945 if (iir & GEN11_GUC_INTR_GUC2HOST)
1946 intel_guc_to_host_event_handler(&i915->guc);
1949 static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
1953 for_each_pipe(dev_priv, pipe) {
1954 I915_WRITE(PIPESTAT(pipe),
1955 PIPESTAT_INT_STATUS_MASK |
1956 PIPE_FIFO_UNDERRUN_STATUS);
1958 dev_priv->pipestat_irq_mask[pipe] = 0;
1962 static void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,
1963 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1967 spin_lock(&dev_priv->irq_lock);
1969 if (!dev_priv->display_irqs_enabled) {
1970 spin_unlock(&dev_priv->irq_lock);
1974 for_each_pipe(dev_priv, pipe) {
1976 u32 status_mask, enable_mask, iir_bit = 0;
1979 * PIPESTAT bits get signalled even when the interrupt is
1980 * disabled with the mask bits, and some of the status bits do
1981 * not generate interrupts at all (like the underrun bit). Hence
1982 * we need to be careful that we only handle what we want to
1986 /* fifo underruns are filterered in the underrun handler. */
1987 status_mask = PIPE_FIFO_UNDERRUN_STATUS;
1991 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1994 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1997 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
2001 status_mask |= dev_priv->pipestat_irq_mask[pipe];
2006 reg = PIPESTAT(pipe);
2007 pipe_stats[pipe] = I915_READ(reg) & status_mask;
2008 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
2011 * Clear the PIPE*STAT regs before the IIR
2013 * Toggle the enable bits to make sure we get an
2014 * edge in the ISR pipe event bit if we don't clear
2015 * all the enabled status bits. Otherwise the edge
2016 * triggered IIR on i965/g4x wouldn't notice that
2017 * an interrupt is still pending.
2019 if (pipe_stats[pipe]) {
2020 I915_WRITE(reg, pipe_stats[pipe]);
2021 I915_WRITE(reg, enable_mask);
2024 spin_unlock(&dev_priv->irq_lock);
2027 static void i8xx_pipestat_irq_handler(struct drm_i915_private *dev_priv,
2028 u16 iir, u32 pipe_stats[I915_MAX_PIPES])
2032 for_each_pipe(dev_priv, pipe) {
2033 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
2034 drm_handle_vblank(&dev_priv->drm, pipe);
2036 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
2037 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2039 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2040 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2044 static void i915_pipestat_irq_handler(struct drm_i915_private *dev_priv,
2045 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
2047 bool blc_event = false;
2050 for_each_pipe(dev_priv, pipe) {
2051 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
2052 drm_handle_vblank(&dev_priv->drm, pipe);
2054 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2057 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
2058 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2060 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2061 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2064 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2065 intel_opregion_asle_intr(dev_priv);
2068 static void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv,
2069 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
2071 bool blc_event = false;
2074 for_each_pipe(dev_priv, pipe) {
2075 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
2076 drm_handle_vblank(&dev_priv->drm, pipe);
2078 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2081 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
2082 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2084 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2085 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2088 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2089 intel_opregion_asle_intr(dev_priv);
2091 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
2092 gmbus_irq_handler(dev_priv);
2095 static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
2096 u32 pipe_stats[I915_MAX_PIPES])
2100 for_each_pipe(dev_priv, pipe) {
2101 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
2102 drm_handle_vblank(&dev_priv->drm, pipe);
2104 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
2105 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2107 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2108 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2111 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
2112 gmbus_irq_handler(dev_priv);
2115 static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
2117 u32 hotplug_status = 0, hotplug_status_mask;
2120 if (IS_G4X(dev_priv) ||
2121 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2122 hotplug_status_mask = HOTPLUG_INT_STATUS_G4X |
2123 DP_AUX_CHANNEL_MASK_INT_STATUS_G4X;
2125 hotplug_status_mask = HOTPLUG_INT_STATUS_I915;
2128 * We absolutely have to clear all the pending interrupt
2129 * bits in PORT_HOTPLUG_STAT. Otherwise the ISR port
2130 * interrupt bit won't have an edge, and the i965/g4x
2131 * edge triggered IIR will not notice that an interrupt
2132 * is still pending. We can't use PORT_HOTPLUG_EN to
2133 * guarantee the edge as the act of toggling the enable
2134 * bits can itself generate a new hotplug interrupt :(
2136 for (i = 0; i < 10; i++) {
2137 u32 tmp = I915_READ(PORT_HOTPLUG_STAT) & hotplug_status_mask;
2140 return hotplug_status;
2142 hotplug_status |= tmp;
2143 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2147 "PORT_HOTPLUG_STAT did not clear (0x%08x)\n",
2148 I915_READ(PORT_HOTPLUG_STAT));
2150 return hotplug_status;
2153 static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
2156 u32 pin_mask = 0, long_mask = 0;
2158 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
2159 IS_CHERRYVIEW(dev_priv)) {
2160 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
2162 if (hotplug_trigger) {
2163 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2164 hotplug_trigger, hotplug_trigger,
2166 i9xx_port_hotplug_long_detect);
2168 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2171 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
2172 dp_aux_irq_handler(dev_priv);
2174 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
2176 if (hotplug_trigger) {
2177 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2178 hotplug_trigger, hotplug_trigger,
2180 i9xx_port_hotplug_long_detect);
2181 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2186 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
2188 struct drm_device *dev = arg;
2189 struct drm_i915_private *dev_priv = to_i915(dev);
2190 irqreturn_t ret = IRQ_NONE;
2192 if (!intel_irqs_enabled(dev_priv))
2195 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2196 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2199 u32 iir, gt_iir, pm_iir;
2200 u32 pipe_stats[I915_MAX_PIPES] = {};
2201 u32 hotplug_status = 0;
2204 gt_iir = I915_READ(GTIIR);
2205 pm_iir = I915_READ(GEN6_PMIIR);
2206 iir = I915_READ(VLV_IIR);
2208 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
2214 * Theory on interrupt generation, based on empirical evidence:
2216 * x = ((VLV_IIR & VLV_IER) ||
2217 * (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
2218 * (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
2220 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
2221 * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
2222 * guarantee the CPU interrupt will be raised again even if we
2223 * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
2224 * bits this time around.
2226 I915_WRITE(VLV_MASTER_IER, 0);
2227 ier = I915_READ(VLV_IER);
2228 I915_WRITE(VLV_IER, 0);
2231 I915_WRITE(GTIIR, gt_iir);
2233 I915_WRITE(GEN6_PMIIR, pm_iir);
2235 if (iir & I915_DISPLAY_PORT_INTERRUPT)
2236 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
2238 /* Call regardless, as some status bits might not be
2239 * signalled in iir */
2240 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
2242 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
2243 I915_LPE_PIPE_B_INTERRUPT))
2244 intel_lpe_audio_irq_handler(dev_priv);
2247 * VLV_IIR is single buffered, and reflects the level
2248 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
2251 I915_WRITE(VLV_IIR, iir);
2253 I915_WRITE(VLV_IER, ier);
2254 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2257 snb_gt_irq_handler(dev_priv, gt_iir);
2259 gen6_rps_irq_handler(dev_priv, pm_iir);
2262 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
2264 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
2267 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2272 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
2274 struct drm_device *dev = arg;
2275 struct drm_i915_private *dev_priv = to_i915(dev);
2276 irqreturn_t ret = IRQ_NONE;
2278 if (!intel_irqs_enabled(dev_priv))
2281 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2282 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2285 u32 master_ctl, iir;
2286 u32 pipe_stats[I915_MAX_PIPES] = {};
2287 u32 hotplug_status = 0;
2291 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
2292 iir = I915_READ(VLV_IIR);
2294 if (master_ctl == 0 && iir == 0)
2300 * Theory on interrupt generation, based on empirical evidence:
2302 * x = ((VLV_IIR & VLV_IER) ||
2303 * ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
2304 * (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
2306 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
2307 * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
2308 * guarantee the CPU interrupt will be raised again even if we
2309 * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
2310 * bits this time around.
2312 I915_WRITE(GEN8_MASTER_IRQ, 0);
2313 ier = I915_READ(VLV_IER);
2314 I915_WRITE(VLV_IER, 0);
2316 gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
2318 if (iir & I915_DISPLAY_PORT_INTERRUPT)
2319 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
2321 /* Call regardless, as some status bits might not be
2322 * signalled in iir */
2323 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
2325 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
2326 I915_LPE_PIPE_B_INTERRUPT |
2327 I915_LPE_PIPE_C_INTERRUPT))
2328 intel_lpe_audio_irq_handler(dev_priv);
2331 * VLV_IIR is single buffered, and reflects the level
2332 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
2335 I915_WRITE(VLV_IIR, iir);
2337 I915_WRITE(VLV_IER, ier);
2338 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2340 gen8_gt_irq_handler(dev_priv, master_ctl, gt_iir);
2343 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
2345 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
2348 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2353 static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
2354 u32 hotplug_trigger,
2355 const u32 hpd[HPD_NUM_PINS])
2357 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2360 * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
2361 * unless we touch the hotplug register, even if hotplug_trigger is
2362 * zero. Not acking leads to "The master control interrupt lied (SDE)!"
2365 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2366 if (!hotplug_trigger) {
2367 u32 mask = PORTA_HOTPLUG_STATUS_MASK |
2368 PORTD_HOTPLUG_STATUS_MASK |
2369 PORTC_HOTPLUG_STATUS_MASK |
2370 PORTB_HOTPLUG_STATUS_MASK;
2371 dig_hotplug_reg &= ~mask;
2374 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2375 if (!hotplug_trigger)
2378 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
2379 dig_hotplug_reg, hpd,
2380 pch_port_hotplug_long_detect);
2382 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2385 static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2388 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
2390 ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ibx);
2392 if (pch_iir & SDE_AUDIO_POWER_MASK) {
2393 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
2394 SDE_AUDIO_POWER_SHIFT);
2395 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
2399 if (pch_iir & SDE_AUX_MASK)
2400 dp_aux_irq_handler(dev_priv);
2402 if (pch_iir & SDE_GMBUS)
2403 gmbus_irq_handler(dev_priv);
2405 if (pch_iir & SDE_AUDIO_HDCP_MASK)
2406 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
2408 if (pch_iir & SDE_AUDIO_TRANS_MASK)
2409 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
2411 if (pch_iir & SDE_POISON)
2412 DRM_ERROR("PCH poison interrupt\n");
2414 if (pch_iir & SDE_FDI_MASK)
2415 for_each_pipe(dev_priv, pipe)
2416 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2418 I915_READ(FDI_RX_IIR(pipe)));
2420 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
2421 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
2423 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
2424 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
2426 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
2427 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A);
2429 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
2430 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B);
2433 static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
2435 u32 err_int = I915_READ(GEN7_ERR_INT);
2438 if (err_int & ERR_INT_POISON)
2439 DRM_ERROR("Poison interrupt\n");
2441 for_each_pipe(dev_priv, pipe) {
2442 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
2443 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2445 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
2446 if (IS_IVYBRIDGE(dev_priv))
2447 ivb_pipe_crc_irq_handler(dev_priv, pipe);
2449 hsw_pipe_crc_irq_handler(dev_priv, pipe);
2453 I915_WRITE(GEN7_ERR_INT, err_int);
2456 static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
2458 u32 serr_int = I915_READ(SERR_INT);
2461 if (serr_int & SERR_INT_POISON)
2462 DRM_ERROR("PCH poison interrupt\n");
2464 for_each_pipe(dev_priv, pipe)
2465 if (serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pipe))
2466 intel_pch_fifo_underrun_irq_handler(dev_priv, pipe);
2468 I915_WRITE(SERR_INT, serr_int);
2471 static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2474 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2476 ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_cpt);
2478 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2479 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2480 SDE_AUDIO_POWER_SHIFT_CPT);
2481 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2485 if (pch_iir & SDE_AUX_MASK_CPT)
2486 dp_aux_irq_handler(dev_priv);
2488 if (pch_iir & SDE_GMBUS_CPT)
2489 gmbus_irq_handler(dev_priv);
2491 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2492 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2494 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2495 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2497 if (pch_iir & SDE_FDI_MASK_CPT)
2498 for_each_pipe(dev_priv, pipe)
2499 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2501 I915_READ(FDI_RX_IIR(pipe)));
2503 if (pch_iir & SDE_ERROR_CPT)
2504 cpt_serr_int_handler(dev_priv);
2507 static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir,
2510 u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
2511 u32 tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
2512 u32 pin_mask = 0, long_mask = 0;
2514 if (ddi_hotplug_trigger) {
2515 u32 dig_hotplug_reg;
2517 dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI);
2518 I915_WRITE(SHOTPLUG_CTL_DDI, dig_hotplug_reg);
2520 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2521 ddi_hotplug_trigger,
2522 dig_hotplug_reg, pins,
2523 icp_ddi_port_hotplug_long_detect);
2526 if (tc_hotplug_trigger) {
2527 u32 dig_hotplug_reg;
2529 dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC);
2530 I915_WRITE(SHOTPLUG_CTL_TC, dig_hotplug_reg);
2532 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2534 dig_hotplug_reg, pins,
2535 icp_tc_port_hotplug_long_detect);
2539 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2541 if (pch_iir & SDE_GMBUS_ICP)
2542 gmbus_irq_handler(dev_priv);
2545 static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2547 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
2548 ~SDE_PORTE_HOTPLUG_SPT;
2549 u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
2550 u32 pin_mask = 0, long_mask = 0;
2552 if (hotplug_trigger) {
2553 u32 dig_hotplug_reg;
2555 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2556 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2558 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2559 hotplug_trigger, dig_hotplug_reg, hpd_spt,
2560 spt_port_hotplug_long_detect);
2563 if (hotplug2_trigger) {
2564 u32 dig_hotplug_reg;
2566 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
2567 I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
2569 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2570 hotplug2_trigger, dig_hotplug_reg, hpd_spt,
2571 spt_port_hotplug2_long_detect);
2575 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2577 if (pch_iir & SDE_GMBUS_CPT)
2578 gmbus_irq_handler(dev_priv);
2581 static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
2582 u32 hotplug_trigger,
2583 const u32 hpd[HPD_NUM_PINS])
2585 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2587 dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
2588 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
2590 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
2591 dig_hotplug_reg, hpd,
2592 ilk_port_hotplug_long_detect);
2594 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2597 static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
2601 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
2603 if (hotplug_trigger)
2604 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk);
2606 if (de_iir & DE_AUX_CHANNEL_A)
2607 dp_aux_irq_handler(dev_priv);
2609 if (de_iir & DE_GSE)
2610 intel_opregion_asle_intr(dev_priv);
2612 if (de_iir & DE_POISON)
2613 DRM_ERROR("Poison interrupt\n");
2615 for_each_pipe(dev_priv, pipe) {
2616 if (de_iir & DE_PIPE_VBLANK(pipe))
2617 drm_handle_vblank(&dev_priv->drm, pipe);
2619 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2620 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2622 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2623 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2626 /* check event from PCH */
2627 if (de_iir & DE_PCH_EVENT) {
2628 u32 pch_iir = I915_READ(SDEIIR);
2630 if (HAS_PCH_CPT(dev_priv))
2631 cpt_irq_handler(dev_priv, pch_iir);
2633 ibx_irq_handler(dev_priv, pch_iir);
2635 /* should clear PCH hotplug event before clear CPU irq */
2636 I915_WRITE(SDEIIR, pch_iir);
2639 if (IS_GEN(dev_priv, 5) && de_iir & DE_PCU_EVENT)
2640 ironlake_rps_change_irq_handler(dev_priv);
2643 static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
2647 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2649 if (hotplug_trigger)
2650 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb);
2652 if (de_iir & DE_ERR_INT_IVB)
2653 ivb_err_int_handler(dev_priv);
2655 if (de_iir & DE_EDP_PSR_INT_HSW) {
2656 u32 psr_iir = I915_READ(EDP_PSR_IIR);
2658 intel_psr_irq_handler(dev_priv, psr_iir);
2659 I915_WRITE(EDP_PSR_IIR, psr_iir);
2662 if (de_iir & DE_AUX_CHANNEL_A_IVB)
2663 dp_aux_irq_handler(dev_priv);
2665 if (de_iir & DE_GSE_IVB)
2666 intel_opregion_asle_intr(dev_priv);
2668 for_each_pipe(dev_priv, pipe) {
2669 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
2670 drm_handle_vblank(&dev_priv->drm, pipe);
2673 /* check event from PCH */
2674 if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
2675 u32 pch_iir = I915_READ(SDEIIR);
2677 cpt_irq_handler(dev_priv, pch_iir);
2679 /* clear PCH hotplug event before clear CPU irq */
2680 I915_WRITE(SDEIIR, pch_iir);
2685 * To handle irqs with the minimum potential races with fresh interrupts, we:
2686 * 1 - Disable Master Interrupt Control.
2687 * 2 - Find the source(s) of the interrupt.
2688 * 3 - Clear the Interrupt Identity bits (IIR).
2689 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2690 * 5 - Re-enable Master Interrupt Control.
2692 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2694 struct drm_device *dev = arg;
2695 struct drm_i915_private *dev_priv = to_i915(dev);
2696 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2697 irqreturn_t ret = IRQ_NONE;
2699 if (!intel_irqs_enabled(dev_priv))
2702 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2703 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2705 /* disable master interrupt before clearing iir */
2706 de_ier = I915_READ(DEIER);
2707 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2709 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2710 * interrupts will will be stored on its back queue, and then we'll be
2711 * able to process them after we restore SDEIER (as soon as we restore
2712 * it, we'll get an interrupt if SDEIIR still has something to process
2713 * due to its back queue). */
2714 if (!HAS_PCH_NOP(dev_priv)) {
2715 sde_ier = I915_READ(SDEIER);
2716 I915_WRITE(SDEIER, 0);
2719 /* Find, clear, then process each source of interrupt */
2721 gt_iir = I915_READ(GTIIR);
2723 I915_WRITE(GTIIR, gt_iir);
2725 if (INTEL_GEN(dev_priv) >= 6)
2726 snb_gt_irq_handler(dev_priv, gt_iir);
2728 ilk_gt_irq_handler(dev_priv, gt_iir);
2731 de_iir = I915_READ(DEIIR);
2733 I915_WRITE(DEIIR, de_iir);
2735 if (INTEL_GEN(dev_priv) >= 7)
2736 ivb_display_irq_handler(dev_priv, de_iir);
2738 ilk_display_irq_handler(dev_priv, de_iir);
2741 if (INTEL_GEN(dev_priv) >= 6) {
2742 u32 pm_iir = I915_READ(GEN6_PMIIR);
2744 I915_WRITE(GEN6_PMIIR, pm_iir);
2746 gen6_rps_irq_handler(dev_priv, pm_iir);
2750 I915_WRITE(DEIER, de_ier);
2751 if (!HAS_PCH_NOP(dev_priv))
2752 I915_WRITE(SDEIER, sde_ier);
2754 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2755 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2760 static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
2761 u32 hotplug_trigger,
2762 const u32 hpd[HPD_NUM_PINS])
2764 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2766 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2767 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2769 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
2770 dig_hotplug_reg, hpd,
2771 bxt_port_hotplug_long_detect);
2773 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2776 static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
2778 u32 pin_mask = 0, long_mask = 0;
2779 u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK;
2780 u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK;
2783 u32 dig_hotplug_reg;
2785 dig_hotplug_reg = I915_READ(GEN11_TC_HOTPLUG_CTL);
2786 I915_WRITE(GEN11_TC_HOTPLUG_CTL, dig_hotplug_reg);
2788 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, trigger_tc,
2789 dig_hotplug_reg, hpd_gen11,
2790 gen11_port_hotplug_long_detect);
2794 u32 dig_hotplug_reg;
2796 dig_hotplug_reg = I915_READ(GEN11_TBT_HOTPLUG_CTL);
2797 I915_WRITE(GEN11_TBT_HOTPLUG_CTL, dig_hotplug_reg);
2799 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, trigger_tbt,
2800 dig_hotplug_reg, hpd_gen11,
2801 gen11_port_hotplug_long_detect);
2805 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2807 DRM_ERROR("Unexpected DE HPD interrupt 0x%08x\n", iir);
2810 static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
2812 u32 mask = GEN8_AUX_CHANNEL_A;
2814 if (INTEL_GEN(dev_priv) >= 9)
2815 mask |= GEN9_AUX_CHANNEL_B |
2816 GEN9_AUX_CHANNEL_C |
2819 if (IS_CNL_WITH_PORT_F(dev_priv))
2820 mask |= CNL_AUX_CHANNEL_F;
2822 if (INTEL_GEN(dev_priv) >= 11)
2823 mask |= ICL_AUX_CHANNEL_E |
2830 gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2832 irqreturn_t ret = IRQ_NONE;
2836 if (master_ctl & GEN8_DE_MISC_IRQ) {
2837 iir = I915_READ(GEN8_DE_MISC_IIR);
2841 I915_WRITE(GEN8_DE_MISC_IIR, iir);
2844 if (iir & GEN8_DE_MISC_GSE) {
2845 intel_opregion_asle_intr(dev_priv);
2849 if (iir & GEN8_DE_EDP_PSR) {
2850 u32 psr_iir = I915_READ(EDP_PSR_IIR);
2852 intel_psr_irq_handler(dev_priv, psr_iir);
2853 I915_WRITE(EDP_PSR_IIR, psr_iir);
2858 DRM_ERROR("Unexpected DE Misc interrupt\n");
2861 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2864 if (INTEL_GEN(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) {
2865 iir = I915_READ(GEN11_DE_HPD_IIR);
2867 I915_WRITE(GEN11_DE_HPD_IIR, iir);
2869 gen11_hpd_irq_handler(dev_priv, iir);
2871 DRM_ERROR("The master control interrupt lied, (DE HPD)!\n");
2875 if (master_ctl & GEN8_DE_PORT_IRQ) {
2876 iir = I915_READ(GEN8_DE_PORT_IIR);
2881 I915_WRITE(GEN8_DE_PORT_IIR, iir);
2884 if (iir & gen8_de_port_aux_mask(dev_priv)) {
2885 dp_aux_irq_handler(dev_priv);
2889 if (IS_GEN9_LP(dev_priv)) {
2890 tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
2892 bxt_hpd_irq_handler(dev_priv, tmp_mask,
2896 } else if (IS_BROADWELL(dev_priv)) {
2897 tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
2899 ilk_hpd_irq_handler(dev_priv,
2905 if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
2906 gmbus_irq_handler(dev_priv);
2911 DRM_ERROR("Unexpected DE Port interrupt\n");
2914 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2917 for_each_pipe(dev_priv, pipe) {
2920 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2923 iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2925 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2930 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
2932 if (iir & GEN8_PIPE_VBLANK)
2933 drm_handle_vblank(&dev_priv->drm, pipe);
2935 if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
2936 hsw_pipe_crc_irq_handler(dev_priv, pipe);
2938 if (iir & GEN8_PIPE_FIFO_UNDERRUN)
2939 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2942 if (INTEL_GEN(dev_priv) >= 9)
2943 fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2945 fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2948 DRM_ERROR("Fault errors on pipe %c: 0x%08x\n",
2953 if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
2954 master_ctl & GEN8_DE_PCH_IRQ) {
2956 * FIXME(BDW): Assume for now that the new interrupt handling
2957 * scheme also closed the SDE interrupt handling race we've seen
2958 * on older pch-split platforms. But this needs testing.
2960 iir = I915_READ(SDEIIR);
2962 I915_WRITE(SDEIIR, iir);
2965 if (INTEL_PCH_TYPE(dev_priv) >= PCH_MCC)
2966 icp_irq_handler(dev_priv, iir, hpd_mcc);
2967 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2968 icp_irq_handler(dev_priv, iir, hpd_icp);
2969 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
2970 spt_irq_handler(dev_priv, iir);
2972 cpt_irq_handler(dev_priv, iir);
2975 * Like on previous PCH there seems to be something
2976 * fishy going on with forwarding PCH interrupts.
2978 DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
2985 static inline u32 gen8_master_intr_disable(void __iomem * const regs)
2987 raw_reg_write(regs, GEN8_MASTER_IRQ, 0);
2990 * Now with master disabled, get a sample of level indications
2991 * for this interrupt. Indications will be cleared on related acks.
2992 * New indications can and will light up during processing,
2993 * and will generate new interrupt after enabling master.
2995 return raw_reg_read(regs, GEN8_MASTER_IRQ);
2998 static inline void gen8_master_intr_enable(void __iomem * const regs)
3000 raw_reg_write(regs, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3003 static irqreturn_t gen8_irq_handler(int irq, void *arg)
3005 struct drm_i915_private *dev_priv = to_i915(arg);
3006 void __iomem * const regs = dev_priv->uncore.regs;
3010 if (!intel_irqs_enabled(dev_priv))
3013 master_ctl = gen8_master_intr_disable(regs);
3015 gen8_master_intr_enable(regs);
3019 /* Find, clear, then process each source of interrupt */
3020 gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
3022 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3023 if (master_ctl & ~GEN8_GT_IRQS) {
3024 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
3025 gen8_de_irq_handler(dev_priv, master_ctl);
3026 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
3029 gen8_master_intr_enable(regs);
3031 gen8_gt_irq_handler(dev_priv, master_ctl, gt_iir);
3037 gen11_gt_engine_identity(struct drm_i915_private * const i915,
3038 const unsigned int bank, const unsigned int bit)
3040 void __iomem * const regs = i915->uncore.regs;
3044 lockdep_assert_held(&i915->irq_lock);
3046 raw_reg_write(regs, GEN11_IIR_REG_SELECTOR(bank), BIT(bit));
3049 * NB: Specs do not specify how long to spin wait,
3050 * so we do ~100us as an educated guess.
3052 timeout_ts = (local_clock() >> 10) + 100;
3054 ident = raw_reg_read(regs, GEN11_INTR_IDENTITY_REG(bank));
3055 } while (!(ident & GEN11_INTR_DATA_VALID) &&
3056 !time_after32(local_clock() >> 10, timeout_ts));
3058 if (unlikely(!(ident & GEN11_INTR_DATA_VALID))) {
3059 DRM_ERROR("INTR_IDENTITY_REG%u:%u 0x%08x not valid!\n",
3064 raw_reg_write(regs, GEN11_INTR_IDENTITY_REG(bank),
3065 GEN11_INTR_DATA_VALID);
3071 gen11_other_irq_handler(struct drm_i915_private * const i915,
3072 const u8 instance, const u16 iir)
3074 if (instance == OTHER_GUC_INSTANCE)
3075 return gen11_guc_irq_handler(i915, iir);
3077 if (instance == OTHER_GTPM_INSTANCE)
3078 return gen11_rps_irq_handler(i915, iir);
3080 WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
3085 gen11_engine_irq_handler(struct drm_i915_private * const i915,
3086 const u8 class, const u8 instance, const u16 iir)
3088 struct intel_engine_cs *engine;
3090 if (instance <= MAX_ENGINE_INSTANCE)
3091 engine = i915->engine_class[class][instance];
3096 return gen8_cs_irq_handler(engine, iir);
3098 WARN_ONCE(1, "unhandled engine interrupt class=0x%x, instance=0x%x\n",
3103 gen11_gt_identity_handler(struct drm_i915_private * const i915,
3106 const u8 class = GEN11_INTR_ENGINE_CLASS(identity);
3107 const u8 instance = GEN11_INTR_ENGINE_INSTANCE(identity);
3108 const u16 intr = GEN11_INTR_ENGINE_INTR(identity);
3110 if (unlikely(!intr))
3113 if (class <= COPY_ENGINE_CLASS)
3114 return gen11_engine_irq_handler(i915, class, instance, intr);
3116 if (class == OTHER_CLASS)
3117 return gen11_other_irq_handler(i915, instance, intr);
3119 WARN_ONCE(1, "unknown interrupt class=0x%x, instance=0x%x, intr=0x%x\n",
3120 class, instance, intr);
3124 gen11_gt_bank_handler(struct drm_i915_private * const i915,
3125 const unsigned int bank)
3127 void __iomem * const regs = i915->uncore.regs;
3128 unsigned long intr_dw;
3131 lockdep_assert_held(&i915->irq_lock);
3133 intr_dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));
3135 for_each_set_bit(bit, &intr_dw, 32) {
3136 const u32 ident = gen11_gt_engine_identity(i915, bank, bit);
3138 gen11_gt_identity_handler(i915, ident);
3141 /* Clear must be after shared has been served for engine */
3142 raw_reg_write(regs, GEN11_GT_INTR_DW(bank), intr_dw);
3146 gen11_gt_irq_handler(struct drm_i915_private * const i915,
3147 const u32 master_ctl)
3151 spin_lock(&i915->irq_lock);
3153 for (bank = 0; bank < 2; bank++) {
3154 if (master_ctl & GEN11_GT_DW_IRQ(bank))
3155 gen11_gt_bank_handler(i915, bank);
3158 spin_unlock(&i915->irq_lock);
3162 gen11_gu_misc_irq_ack(struct drm_i915_private *dev_priv, const u32 master_ctl)
3164 void __iomem * const regs = dev_priv->uncore.regs;
3167 if (!(master_ctl & GEN11_GU_MISC_IRQ))
3170 iir = raw_reg_read(regs, GEN11_GU_MISC_IIR);
3172 raw_reg_write(regs, GEN11_GU_MISC_IIR, iir);
3178 gen11_gu_misc_irq_handler(struct drm_i915_private *dev_priv, const u32 iir)
3180 if (iir & GEN11_GU_MISC_GSE)
3181 intel_opregion_asle_intr(dev_priv);
3184 static inline u32 gen11_master_intr_disable(void __iomem * const regs)
3186 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, 0);
3189 * Now with master disabled, get a sample of level indications
3190 * for this interrupt. Indications will be cleared on related acks.
3191 * New indications can and will light up during processing,
3192 * and will generate new interrupt after enabling master.
3194 return raw_reg_read(regs, GEN11_GFX_MSTR_IRQ);
3197 static inline void gen11_master_intr_enable(void __iomem * const regs)
3199 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
3202 static irqreturn_t gen11_irq_handler(int irq, void *arg)
3204 struct drm_i915_private * const i915 = to_i915(arg);
3205 void __iomem * const regs = i915->uncore.regs;
3209 if (!intel_irqs_enabled(i915))
3212 master_ctl = gen11_master_intr_disable(regs);
3214 gen11_master_intr_enable(regs);
3218 /* Find, clear, then process each source of interrupt. */
3219 gen11_gt_irq_handler(i915, master_ctl);
3221 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3222 if (master_ctl & GEN11_DISPLAY_IRQ) {
3223 const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL);
3225 disable_rpm_wakeref_asserts(&i915->runtime_pm);
3227 * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ
3228 * for the display related bits.
3230 gen8_de_irq_handler(i915, disp_ctl);
3231 enable_rpm_wakeref_asserts(&i915->runtime_pm);
3234 gu_misc_iir = gen11_gu_misc_irq_ack(i915, master_ctl);
3236 gen11_master_intr_enable(regs);
3238 gen11_gu_misc_irq_handler(i915, gu_misc_iir);
3243 /* Called from drm generic code, passed 'crtc' which
3244 * we use as a pipe index
3246 static int i8xx_enable_vblank(struct drm_device *dev, unsigned int pipe)
3248 struct drm_i915_private *dev_priv = to_i915(dev);
3249 unsigned long irqflags;
3251 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3252 i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
3253 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3258 static int i945gm_enable_vblank(struct drm_device *dev, unsigned int pipe)
3260 struct drm_i915_private *dev_priv = to_i915(dev);
3262 if (dev_priv->i945gm_vblank.enabled++ == 0)
3263 schedule_work(&dev_priv->i945gm_vblank.work);
3265 return i8xx_enable_vblank(dev, pipe);
3268 static int i965_enable_vblank(struct drm_device *dev, unsigned int pipe)
3270 struct drm_i915_private *dev_priv = to_i915(dev);
3271 unsigned long irqflags;
3273 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3274 i915_enable_pipestat(dev_priv, pipe,
3275 PIPE_START_VBLANK_INTERRUPT_STATUS);
3276 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3281 static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)
3283 struct drm_i915_private *dev_priv = to_i915(dev);
3284 unsigned long irqflags;
3285 u32 bit = INTEL_GEN(dev_priv) >= 7 ?
3286 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
3288 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3289 ilk_enable_display_irq(dev_priv, bit);
3290 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3292 /* Even though there is no DMC, frame counter can get stuck when
3293 * PSR is active as no frames are generated.
3295 if (HAS_PSR(dev_priv))
3296 drm_vblank_restore(dev, pipe);
3301 static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe)
3303 struct drm_i915_private *dev_priv = to_i915(dev);
3304 unsigned long irqflags;
3306 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3307 bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
3308 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3310 /* Even if there is no DMC, frame counter can get stuck when
3311 * PSR is active as no frames are generated, so check only for PSR.
3313 if (HAS_PSR(dev_priv))
3314 drm_vblank_restore(dev, pipe);
3319 /* Called from drm generic code, passed 'crtc' which
3320 * we use as a pipe index
3322 static void i8xx_disable_vblank(struct drm_device *dev, unsigned int pipe)
3324 struct drm_i915_private *dev_priv = to_i915(dev);
3325 unsigned long irqflags;
3327 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3328 i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
3329 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3332 static void i945gm_disable_vblank(struct drm_device *dev, unsigned int pipe)
3334 struct drm_i915_private *dev_priv = to_i915(dev);
3336 i8xx_disable_vblank(dev, pipe);
3338 if (--dev_priv->i945gm_vblank.enabled == 0)
3339 schedule_work(&dev_priv->i945gm_vblank.work);
3342 static void i965_disable_vblank(struct drm_device *dev, unsigned int pipe)
3344 struct drm_i915_private *dev_priv = to_i915(dev);
3345 unsigned long irqflags;
3347 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3348 i915_disable_pipestat(dev_priv, pipe,
3349 PIPE_START_VBLANK_INTERRUPT_STATUS);
3350 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3353 static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)
3355 struct drm_i915_private *dev_priv = to_i915(dev);
3356 unsigned long irqflags;
3357 u32 bit = INTEL_GEN(dev_priv) >= 7 ?
3358 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
3360 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3361 ilk_disable_display_irq(dev_priv, bit);
3362 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3365 static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe)
3367 struct drm_i915_private *dev_priv = to_i915(dev);
3368 unsigned long irqflags;
3370 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3371 bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
3372 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3375 static void i945gm_vblank_work_func(struct work_struct *work)
3377 struct drm_i915_private *dev_priv =
3378 container_of(work, struct drm_i915_private, i945gm_vblank.work);
3381 * Vblank interrupts fail to wake up the device from C3,
3382 * hence we want to prevent C3 usage while vblank interrupts
3385 pm_qos_update_request(&dev_priv->i945gm_vblank.pm_qos,
3386 READ_ONCE(dev_priv->i945gm_vblank.enabled) ?
3387 dev_priv->i945gm_vblank.c3_disable_latency :
3388 PM_QOS_DEFAULT_VALUE);
3391 static int cstate_disable_latency(const char *name)
3393 const struct cpuidle_driver *drv;
3396 drv = cpuidle_get_driver();
3400 for (i = 0; i < drv->state_count; i++) {
3401 const struct cpuidle_state *state = &drv->states[i];
3403 if (!strcmp(state->name, name))
3404 return state->exit_latency ?
3405 state->exit_latency - 1 : 0;
3411 static void i945gm_vblank_work_init(struct drm_i915_private *dev_priv)
3413 INIT_WORK(&dev_priv->i945gm_vblank.work,
3414 i945gm_vblank_work_func);
3416 dev_priv->i945gm_vblank.c3_disable_latency =
3417 cstate_disable_latency("C3");
3418 pm_qos_add_request(&dev_priv->i945gm_vblank.pm_qos,
3419 PM_QOS_CPU_DMA_LATENCY,
3420 PM_QOS_DEFAULT_VALUE);
3423 static void i945gm_vblank_work_fini(struct drm_i915_private *dev_priv)
3425 cancel_work_sync(&dev_priv->i945gm_vblank.work);
3426 pm_qos_remove_request(&dev_priv->i945gm_vblank.pm_qos);
3429 static void ibx_irq_reset(struct drm_i915_private *dev_priv)
3431 struct intel_uncore *uncore = &dev_priv->uncore;
3433 if (HAS_PCH_NOP(dev_priv))
3436 GEN3_IRQ_RESET(uncore, SDE);
3438 if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
3439 I915_WRITE(SERR_INT, 0xffffffff);
3443 * SDEIER is also touched by the interrupt handler to work around missed PCH
3444 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3445 * instead we unconditionally enable all PCH interrupt sources here, but then
3446 * only unmask them as needed with SDEIMR.
3448 * This function needs to be called before interrupts are enabled.
3450 static void ibx_irq_pre_postinstall(struct drm_device *dev)
3452 struct drm_i915_private *dev_priv = to_i915(dev);
3454 if (HAS_PCH_NOP(dev_priv))
3457 WARN_ON(I915_READ(SDEIER) != 0);
3458 I915_WRITE(SDEIER, 0xffffffff);
3459 POSTING_READ(SDEIER);
3462 static void gen5_gt_irq_reset(struct drm_i915_private *dev_priv)
3464 struct intel_uncore *uncore = &dev_priv->uncore;
3466 GEN3_IRQ_RESET(uncore, GT);
3467 if (INTEL_GEN(dev_priv) >= 6)
3468 GEN3_IRQ_RESET(uncore, GEN6_PM);
3471 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
3473 struct intel_uncore *uncore = &dev_priv->uncore;
3475 if (IS_CHERRYVIEW(dev_priv))
3476 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3478 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3480 i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
3481 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3483 i9xx_pipestat_irq_reset(dev_priv);
3485 GEN3_IRQ_RESET(uncore, VLV_);
3486 dev_priv->irq_mask = ~0u;
3489 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
3491 struct intel_uncore *uncore = &dev_priv->uncore;
3497 pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS;
3499 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3500 for_each_pipe(dev_priv, pipe)
3501 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
3503 enable_mask = I915_DISPLAY_PORT_INTERRUPT |
3504 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3505 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3506 I915_LPE_PIPE_A_INTERRUPT |
3507 I915_LPE_PIPE_B_INTERRUPT;
3509 if (IS_CHERRYVIEW(dev_priv))
3510 enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT |
3511 I915_LPE_PIPE_C_INTERRUPT;
3513 WARN_ON(dev_priv->irq_mask != ~0u);
3515 dev_priv->irq_mask = ~enable_mask;
3517 GEN3_IRQ_INIT(uncore, VLV_, dev_priv->irq_mask, enable_mask);
3522 static void ironlake_irq_reset(struct drm_device *dev)
3524 struct drm_i915_private *dev_priv = to_i915(dev);
3525 struct intel_uncore *uncore = &dev_priv->uncore;
3527 GEN3_IRQ_RESET(uncore, DE);
3528 if (IS_GEN(dev_priv, 7))
3529 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
3531 if (IS_HASWELL(dev_priv)) {
3532 I915_WRITE(EDP_PSR_IMR, 0xffffffff);
3533 I915_WRITE(EDP_PSR_IIR, 0xffffffff);
3536 gen5_gt_irq_reset(dev_priv);
3538 ibx_irq_reset(dev_priv);
3541 static void valleyview_irq_reset(struct drm_device *dev)
3543 struct drm_i915_private *dev_priv = to_i915(dev);
3545 I915_WRITE(VLV_MASTER_IER, 0);
3546 POSTING_READ(VLV_MASTER_IER);
3548 gen5_gt_irq_reset(dev_priv);
3550 spin_lock_irq(&dev_priv->irq_lock);
3551 if (dev_priv->display_irqs_enabled)
3552 vlv_display_irq_reset(dev_priv);
3553 spin_unlock_irq(&dev_priv->irq_lock);
3556 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3558 struct intel_uncore *uncore = &dev_priv->uncore;
3560 GEN8_IRQ_RESET_NDX(uncore, GT, 0);
3561 GEN8_IRQ_RESET_NDX(uncore, GT, 1);
3562 GEN8_IRQ_RESET_NDX(uncore, GT, 2);
3563 GEN8_IRQ_RESET_NDX(uncore, GT, 3);
3566 static void gen8_irq_reset(struct drm_device *dev)
3568 struct drm_i915_private *dev_priv = to_i915(dev);
3569 struct intel_uncore *uncore = &dev_priv->uncore;
3572 gen8_master_intr_disable(dev_priv->uncore.regs);
3574 gen8_gt_irq_reset(dev_priv);
3576 I915_WRITE(EDP_PSR_IMR, 0xffffffff);
3577 I915_WRITE(EDP_PSR_IIR, 0xffffffff);
3579 for_each_pipe(dev_priv, pipe)
3580 if (intel_display_power_is_enabled(dev_priv,
3581 POWER_DOMAIN_PIPE(pipe)))
3582 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
3584 GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);
3585 GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
3586 GEN3_IRQ_RESET(uncore, GEN8_PCU_);
3588 if (HAS_PCH_SPLIT(dev_priv))
3589 ibx_irq_reset(dev_priv);
3592 static void gen11_gt_irq_reset(struct drm_i915_private *dev_priv)
3594 /* Disable RCS, BCS, VCS and VECS class engines. */
3595 I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, 0);
3596 I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE, 0);
3598 /* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
3599 I915_WRITE(GEN11_RCS0_RSVD_INTR_MASK, ~0);
3600 I915_WRITE(GEN11_BCS_RSVD_INTR_MASK, ~0);
3601 I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK, ~0);
3602 I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK, ~0);
3603 I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK, ~0);
3605 I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
3606 I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
3607 I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, 0);
3608 I915_WRITE(GEN11_GUC_SG_INTR_MASK, ~0);
3611 static void gen11_irq_reset(struct drm_device *dev)
3613 struct drm_i915_private *dev_priv = dev->dev_private;
3614 struct intel_uncore *uncore = &dev_priv->uncore;
3617 gen11_master_intr_disable(dev_priv->uncore.regs);
3619 gen11_gt_irq_reset(dev_priv);
3621 I915_WRITE(GEN11_DISPLAY_INT_CTL, 0);
3623 I915_WRITE(EDP_PSR_IMR, 0xffffffff);
3624 I915_WRITE(EDP_PSR_IIR, 0xffffffff);
3626 for_each_pipe(dev_priv, pipe)
3627 if (intel_display_power_is_enabled(dev_priv,
3628 POWER_DOMAIN_PIPE(pipe)))
3629 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
3631 GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);
3632 GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
3633 GEN3_IRQ_RESET(uncore, GEN11_DE_HPD_);
3634 GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
3635 GEN3_IRQ_RESET(uncore, GEN8_PCU_);
3637 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3638 GEN3_IRQ_RESET(uncore, SDE);
3641 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
3644 struct intel_uncore *uncore = &dev_priv->uncore;
3646 u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3649 spin_lock_irq(&dev_priv->irq_lock);
3651 if (!intel_irqs_enabled(dev_priv)) {
3652 spin_unlock_irq(&dev_priv->irq_lock);
3656 for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3657 GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,
3658 dev_priv->de_irq_mask[pipe],
3659 ~dev_priv->de_irq_mask[pipe] | extra_ier);
3661 spin_unlock_irq(&dev_priv->irq_lock);
3664 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
3667 struct intel_uncore *uncore = &dev_priv->uncore;
3670 spin_lock_irq(&dev_priv->irq_lock);
3672 if (!intel_irqs_enabled(dev_priv)) {
3673 spin_unlock_irq(&dev_priv->irq_lock);
3677 for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3678 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
3680 spin_unlock_irq(&dev_priv->irq_lock);
3682 /* make sure we're done processing display irqs */
3683 synchronize_irq(dev_priv->drm.irq);
3686 static void cherryview_irq_reset(struct drm_device *dev)
3688 struct drm_i915_private *dev_priv = to_i915(dev);
3689 struct intel_uncore *uncore = &dev_priv->uncore;
3691 I915_WRITE(GEN8_MASTER_IRQ, 0);
3692 POSTING_READ(GEN8_MASTER_IRQ);
3694 gen8_gt_irq_reset(dev_priv);
3696 GEN3_IRQ_RESET(uncore, GEN8_PCU_);
3698 spin_lock_irq(&dev_priv->irq_lock);
3699 if (dev_priv->display_irqs_enabled)
3700 vlv_display_irq_reset(dev_priv);
3701 spin_unlock_irq(&dev_priv->irq_lock);
3704 static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
3705 const u32 hpd[HPD_NUM_PINS])
3707 struct intel_encoder *encoder;
3708 u32 enabled_irqs = 0;
3710 for_each_intel_encoder(&dev_priv->drm, encoder)
3711 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
3712 enabled_irqs |= hpd[encoder->hpd_pin];
3714 return enabled_irqs;
3717 static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
3722 * Enable digital hotplug on the PCH, and configure the DP short pulse
3723 * duration to 2ms (which is the minimum in the Display Port spec).
3724 * The pulse duration bits are reserved on LPT+.
3726 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3727 hotplug &= ~(PORTB_PULSE_DURATION_MASK |
3728 PORTC_PULSE_DURATION_MASK |
3729 PORTD_PULSE_DURATION_MASK);
3730 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3731 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3732 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3734 * When CPU and PCH are on the same package, port A
3735 * HPD must be enabled in both north and south.
3737 if (HAS_PCH_LPT_LP(dev_priv))
3738 hotplug |= PORTA_HOTPLUG_ENABLE;
3739 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3742 static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
3744 u32 hotplug_irqs, enabled_irqs;
3746 if (HAS_PCH_IBX(dev_priv)) {
3747 hotplug_irqs = SDE_HOTPLUG_MASK;
3748 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ibx);
3750 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3751 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_cpt);
3754 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3756 ibx_hpd_detection_setup(dev_priv);
3759 static void icp_hpd_detection_setup(struct drm_i915_private *dev_priv)
3763 hotplug = I915_READ(SHOTPLUG_CTL_DDI);
3764 hotplug |= ICP_DDIA_HPD_ENABLE |
3765 ICP_DDIB_HPD_ENABLE;
3766 I915_WRITE(SHOTPLUG_CTL_DDI, hotplug);
3768 hotplug = I915_READ(SHOTPLUG_CTL_TC);
3769 hotplug |= ICP_TC_HPD_ENABLE(PORT_TC1) |
3770 ICP_TC_HPD_ENABLE(PORT_TC2) |
3771 ICP_TC_HPD_ENABLE(PORT_TC3) |
3772 ICP_TC_HPD_ENABLE(PORT_TC4);
3773 I915_WRITE(SHOTPLUG_CTL_TC, hotplug);
3776 static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv)
3778 u32 hotplug_irqs, enabled_irqs;
3780 hotplug_irqs = SDE_DDI_MASK_ICP | SDE_TC_MASK_ICP;
3781 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_icp);
3783 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3785 icp_hpd_detection_setup(dev_priv);
3788 static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
3792 hotplug = I915_READ(GEN11_TC_HOTPLUG_CTL);
3793 hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) |
3794 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) |
3795 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) |
3796 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4);
3797 I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug);
3799 hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL);
3800 hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) |
3801 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) |
3802 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) |
3803 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4);
3804 I915_WRITE(GEN11_TBT_HOTPLUG_CTL, hotplug);
3807 static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
3809 u32 hotplug_irqs, enabled_irqs;
3812 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_gen11);
3813 hotplug_irqs = GEN11_DE_TC_HOTPLUG_MASK | GEN11_DE_TBT_HOTPLUG_MASK;
3815 val = I915_READ(GEN11_DE_HPD_IMR);
3816 val &= ~hotplug_irqs;
3817 I915_WRITE(GEN11_DE_HPD_IMR, val);
3818 POSTING_READ(GEN11_DE_HPD_IMR);
3820 gen11_hpd_detection_setup(dev_priv);
3822 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3823 icp_hpd_irq_setup(dev_priv);
3826 static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3830 /* Display WA #1179 WaHardHangonHotPlug: cnp */
3831 if (HAS_PCH_CNP(dev_priv)) {
3832 val = I915_READ(SOUTH_CHICKEN1);
3833 val &= ~CHASSIS_CLK_REQ_DURATION_MASK;
3834 val |= CHASSIS_CLK_REQ_DURATION(0xf);
3835 I915_WRITE(SOUTH_CHICKEN1, val);
3838 /* Enable digital hotplug on the PCH */
3839 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3840 hotplug |= PORTA_HOTPLUG_ENABLE |
3841 PORTB_HOTPLUG_ENABLE |
3842 PORTC_HOTPLUG_ENABLE |
3843 PORTD_HOTPLUG_ENABLE;
3844 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3846 hotplug = I915_READ(PCH_PORT_HOTPLUG2);
3847 hotplug |= PORTE_HOTPLUG_ENABLE;
3848 I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
3851 static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3853 u32 hotplug_irqs, enabled_irqs;
3855 hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
3856 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt);
3858 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3860 spt_hpd_detection_setup(dev_priv);
3863 static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv)
3868 * Enable digital hotplug on the CPU, and configure the DP short pulse
3869 * duration to 2ms (which is the minimum in the Display Port spec)
3870 * The pulse duration bits are reserved on HSW+.
3872 hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
3873 hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
3874 hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE |
3875 DIGITAL_PORTA_PULSE_DURATION_2ms;
3876 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
3879 static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
3881 u32 hotplug_irqs, enabled_irqs;
3883 if (INTEL_GEN(dev_priv) >= 8) {
3884 hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
3885 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw);
3887 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3888 } else if (INTEL_GEN(dev_priv) >= 7) {
3889 hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
3890 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ivb);
3892 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3894 hotplug_irqs = DE_DP_A_HOTPLUG;
3895 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ilk);
3897 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3900 ilk_hpd_detection_setup(dev_priv);
3902 ibx_hpd_irq_setup(dev_priv);
3905 static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
3910 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3911 hotplug |= PORTA_HOTPLUG_ENABLE |
3912 PORTB_HOTPLUG_ENABLE |
3913 PORTC_HOTPLUG_ENABLE;
3915 DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x\n",
3916 hotplug, enabled_irqs);
3917 hotplug &= ~BXT_DDI_HPD_INVERT_MASK;
3920 * For BXT invert bit has to be set based on AOB design
3921 * for HPD detection logic, update it based on VBT fields.
3923 if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) &&
3924 intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
3925 hotplug |= BXT_DDIA_HPD_INVERT;
3926 if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) &&
3927 intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
3928 hotplug |= BXT_DDIB_HPD_INVERT;
3929 if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) &&
3930 intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
3931 hotplug |= BXT_DDIC_HPD_INVERT;
3933 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3936 static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3938 __bxt_hpd_detection_setup(dev_priv, BXT_DE_PORT_HOTPLUG_MASK);
3941 static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3943 u32 hotplug_irqs, enabled_irqs;
3945 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bxt);
3946 hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK;
3948 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3950 __bxt_hpd_detection_setup(dev_priv, enabled_irqs);
3953 static void ibx_irq_postinstall(struct drm_device *dev)
3955 struct drm_i915_private *dev_priv = to_i915(dev);
3958 if (HAS_PCH_NOP(dev_priv))
3961 if (HAS_PCH_IBX(dev_priv))
3962 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3963 else if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
3964 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3966 mask = SDE_GMBUS_CPT;
3968 gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
3969 I915_WRITE(SDEIMR, ~mask);
3971 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
3972 HAS_PCH_LPT(dev_priv))
3973 ibx_hpd_detection_setup(dev_priv);
3975 spt_hpd_detection_setup(dev_priv);
3978 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3980 struct drm_i915_private *dev_priv = to_i915(dev);
3981 struct intel_uncore *uncore = &dev_priv->uncore;
3982 u32 pm_irqs, gt_irqs;
3984 pm_irqs = gt_irqs = 0;
3986 dev_priv->gt_irq_mask = ~0;
3987 if (HAS_L3_DPF(dev_priv)) {
3988 /* L3 parity interrupt is always unmasked. */
3989 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev_priv);
3990 gt_irqs |= GT_PARITY_ERROR(dev_priv);
3993 gt_irqs |= GT_RENDER_USER_INTERRUPT;
3994 if (IS_GEN(dev_priv, 5)) {
3995 gt_irqs |= ILK_BSD_USER_INTERRUPT;
3997 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
4000 GEN3_IRQ_INIT(uncore, GT, dev_priv->gt_irq_mask, gt_irqs);
4002 if (INTEL_GEN(dev_priv) >= 6) {
4004 * RPS interrupts will get enabled/disabled on demand when RPS
4005 * itself is enabled/disabled.
4007 if (HAS_ENGINE(dev_priv, VECS0)) {
4008 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
4009 dev_priv->pm_ier |= PM_VEBOX_USER_INTERRUPT;
4012 dev_priv->pm_imr = 0xffffffff;
4013 GEN3_IRQ_INIT(uncore, GEN6_PM, dev_priv->pm_imr, pm_irqs);
4017 static int ironlake_irq_postinstall(struct drm_device *dev)
4019 struct drm_i915_private *dev_priv = to_i915(dev);
4020 struct intel_uncore *uncore = &dev_priv->uncore;
4021 u32 display_mask, extra_mask;
4023 if (INTEL_GEN(dev_priv) >= 7) {
4024 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
4025 DE_PCH_EVENT_IVB | DE_AUX_CHANNEL_A_IVB);
4026 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
4027 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
4028 DE_DP_A_HOTPLUG_IVB);
4030 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
4031 DE_AUX_CHANNEL_A | DE_PIPEB_CRC_DONE |
4032 DE_PIPEA_CRC_DONE | DE_POISON);
4033 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
4034 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
4038 if (IS_HASWELL(dev_priv)) {
4039 gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
4040 intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
4041 display_mask |= DE_EDP_PSR_INT_HSW;
4044 dev_priv->irq_mask = ~display_mask;
4046 ibx_irq_pre_postinstall(dev);
4048 GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask,
4049 display_mask | extra_mask);
4051 gen5_gt_irq_postinstall(dev);
4053 ilk_hpd_detection_setup(dev_priv);
4055 ibx_irq_postinstall(dev);
4057 if (IS_IRONLAKE_M(dev_priv)) {
4058 /* Enable PCU event interrupts
4060 * spinlocking not required here for correctness since interrupt
4061 * setup is guaranteed to run in single-threaded context. But we
4062 * need it to make the assert_spin_locked happy. */
4063 spin_lock_irq(&dev_priv->irq_lock);
4064 ilk_enable_display_irq(dev_priv, DE_PCU_EVENT);
4065 spin_unlock_irq(&dev_priv->irq_lock);
4071 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
4073 lockdep_assert_held(&dev_priv->irq_lock);
4075 if (dev_priv->display_irqs_enabled)
4078 dev_priv->display_irqs_enabled = true;
4080 if (intel_irqs_enabled(dev_priv)) {
4081 vlv_display_irq_reset(dev_priv);
4082 vlv_display_irq_postinstall(dev_priv);
4086 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
4088 lockdep_assert_held(&dev_priv->irq_lock);
4090 if (!dev_priv->display_irqs_enabled)
4093 dev_priv->display_irqs_enabled = false;
4095 if (intel_irqs_enabled(dev_priv))
4096 vlv_display_irq_reset(dev_priv);
4100 static int valleyview_irq_postinstall(struct drm_device *dev)
4102 struct drm_i915_private *dev_priv = to_i915(dev);
4104 gen5_gt_irq_postinstall(dev);
4106 spin_lock_irq(&dev_priv->irq_lock);
4107 if (dev_priv->display_irqs_enabled)
4108 vlv_display_irq_postinstall(dev_priv);
4109 spin_unlock_irq(&dev_priv->irq_lock);
4111 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
4112 POSTING_READ(VLV_MASTER_IER);
4117 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
4119 struct intel_uncore *uncore = &dev_priv->uncore;
4121 /* These are interrupts we'll toggle with the ring mask register */
4122 u32 gt_interrupts[] = {
4123 (GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
4124 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
4125 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
4126 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT),
4128 (GT_RENDER_USER_INTERRUPT << GEN8_VCS0_IRQ_SHIFT |
4129 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS0_IRQ_SHIFT |
4130 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
4131 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT),
4135 (GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
4136 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT)
4139 dev_priv->pm_ier = 0x0;
4140 dev_priv->pm_imr = ~dev_priv->pm_ier;
4141 GEN8_IRQ_INIT_NDX(uncore, GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
4142 GEN8_IRQ_INIT_NDX(uncore, GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
4144 * RPS interrupts will get enabled/disabled on demand when RPS itself
4145 * is enabled/disabled. Same wil be the case for GuC interrupts.
4147 GEN8_IRQ_INIT_NDX(uncore, GT, 2, dev_priv->pm_imr, dev_priv->pm_ier);
4148 GEN8_IRQ_INIT_NDX(uncore, GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
4151 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
4153 struct intel_uncore *uncore = &dev_priv->uncore;
4155 u32 de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
4156 u32 de_pipe_enables;
4157 u32 de_port_masked = GEN8_AUX_CHANNEL_A;
4158 u32 de_port_enables;
4159 u32 de_misc_masked = GEN8_DE_EDP_PSR;
4162 if (INTEL_GEN(dev_priv) <= 10)
4163 de_misc_masked |= GEN8_DE_MISC_GSE;
4165 if (INTEL_GEN(dev_priv) >= 9) {
4166 de_pipe_masked |= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
4167 de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
4169 if (IS_GEN9_LP(dev_priv))
4170 de_port_masked |= BXT_DE_PORT_GMBUS;
4172 de_pipe_masked |= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
4175 if (INTEL_GEN(dev_priv) >= 11)
4176 de_port_masked |= ICL_AUX_CHANNEL_E;
4178 if (IS_CNL_WITH_PORT_F(dev_priv) || INTEL_GEN(dev_priv) >= 11)
4179 de_port_masked |= CNL_AUX_CHANNEL_F;
4181 de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
4182 GEN8_PIPE_FIFO_UNDERRUN;
4184 de_port_enables = de_port_masked;
4185 if (IS_GEN9_LP(dev_priv))
4186 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
4187 else if (IS_BROADWELL(dev_priv))
4188 de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
4190 gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
4191 intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
4193 for_each_pipe(dev_priv, pipe) {
4194 dev_priv->de_irq_mask[pipe] = ~de_pipe_masked;
4196 if (intel_display_power_is_enabled(dev_priv,
4197 POWER_DOMAIN_PIPE(pipe)))
4198 GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,
4199 dev_priv->de_irq_mask[pipe],
4203 GEN3_IRQ_INIT(uncore, GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
4204 GEN3_IRQ_INIT(uncore, GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
4206 if (INTEL_GEN(dev_priv) >= 11) {
4207 u32 de_hpd_masked = 0;
4208 u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK |
4209 GEN11_DE_TBT_HOTPLUG_MASK;
4211 GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked,
4213 gen11_hpd_detection_setup(dev_priv);
4214 } else if (IS_GEN9_LP(dev_priv)) {
4215 bxt_hpd_detection_setup(dev_priv);
4216 } else if (IS_BROADWELL(dev_priv)) {
4217 ilk_hpd_detection_setup(dev_priv);
4221 static int gen8_irq_postinstall(struct drm_device *dev)
4223 struct drm_i915_private *dev_priv = to_i915(dev);
4225 if (HAS_PCH_SPLIT(dev_priv))
4226 ibx_irq_pre_postinstall(dev);
4228 gen8_gt_irq_postinstall(dev_priv);
4229 gen8_de_irq_postinstall(dev_priv);
4231 if (HAS_PCH_SPLIT(dev_priv))
4232 ibx_irq_postinstall(dev);
4234 gen8_master_intr_enable(dev_priv->uncore.regs);
4239 static void gen11_gt_irq_postinstall(struct drm_i915_private *dev_priv)
4241 const u32 irqs = GT_RENDER_USER_INTERRUPT | GT_CONTEXT_SWITCH_INTERRUPT;
4243 BUILD_BUG_ON(irqs & 0xffff0000);
4245 /* Enable RCS, BCS, VCS and VECS class interrupts. */
4246 I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, irqs << 16 | irqs);
4247 I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE, irqs << 16 | irqs);
4249 /* Unmask irqs on RCS, BCS, VCS and VECS engines. */
4250 I915_WRITE(GEN11_RCS0_RSVD_INTR_MASK, ~(irqs << 16));
4251 I915_WRITE(GEN11_BCS_RSVD_INTR_MASK, ~(irqs << 16));
4252 I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK, ~(irqs | irqs << 16));
4253 I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK, ~(irqs | irqs << 16));
4254 I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK, ~(irqs | irqs << 16));
4257 * RPS interrupts will get enabled/disabled on demand when RPS itself
4258 * is enabled/disabled.
4260 dev_priv->pm_ier = 0x0;
4261 dev_priv->pm_imr = ~dev_priv->pm_ier;
4262 I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
4263 I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
4265 /* Same thing for GuC interrupts */
4266 I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, 0);
4267 I915_WRITE(GEN11_GUC_SG_INTR_MASK, ~0);
4270 static void icp_irq_postinstall(struct drm_device *dev)
4272 struct drm_i915_private *dev_priv = to_i915(dev);
4273 u32 mask = SDE_GMBUS_ICP;
4275 WARN_ON(I915_READ(SDEIER) != 0);
4276 I915_WRITE(SDEIER, 0xffffffff);
4277 POSTING_READ(SDEIER);
4279 gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
4280 I915_WRITE(SDEIMR, ~mask);
4282 icp_hpd_detection_setup(dev_priv);
4285 static int gen11_irq_postinstall(struct drm_device *dev)
4287 struct drm_i915_private *dev_priv = dev->dev_private;
4288 struct intel_uncore *uncore = &dev_priv->uncore;
4289 u32 gu_misc_masked = GEN11_GU_MISC_GSE;
4291 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
4292 icp_irq_postinstall(dev);
4294 gen11_gt_irq_postinstall(dev_priv);
4295 gen8_de_irq_postinstall(dev_priv);
4297 GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
4299 I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
4301 gen11_master_intr_enable(dev_priv->uncore.regs);
4302 POSTING_READ(GEN11_GFX_MSTR_IRQ);
4307 static int cherryview_irq_postinstall(struct drm_device *dev)
4309 struct drm_i915_private *dev_priv = to_i915(dev);
4311 gen8_gt_irq_postinstall(dev_priv);
4313 spin_lock_irq(&dev_priv->irq_lock);
4314 if (dev_priv->display_irqs_enabled)
4315 vlv_display_irq_postinstall(dev_priv);
4316 spin_unlock_irq(&dev_priv->irq_lock);
4318 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
4319 POSTING_READ(GEN8_MASTER_IRQ);
4324 static void i8xx_irq_reset(struct drm_device *dev)
4326 struct drm_i915_private *dev_priv = to_i915(dev);
4327 struct intel_uncore *uncore = &dev_priv->uncore;
4329 i9xx_pipestat_irq_reset(dev_priv);
4331 GEN2_IRQ_RESET(uncore);
4334 static int i8xx_irq_postinstall(struct drm_device *dev)
4336 struct drm_i915_private *dev_priv = to_i915(dev);
4337 struct intel_uncore *uncore = &dev_priv->uncore;
4340 intel_uncore_write16(uncore,
4342 ~(I915_ERROR_PAGE_TABLE |
4343 I915_ERROR_MEMORY_REFRESH));
4345 /* Unmask the interrupts that we always want on. */
4346 dev_priv->irq_mask =
4347 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4348 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4349 I915_MASTER_ERROR_INTERRUPT);
4352 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4353 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4354 I915_MASTER_ERROR_INTERRUPT |
4355 I915_USER_INTERRUPT;
4357 GEN2_IRQ_INIT(uncore, dev_priv->irq_mask, enable_mask);
4359 /* Interrupt setup is already guaranteed to be single-threaded, this is
4360 * just to make the assert_spin_locked check happy. */
4361 spin_lock_irq(&dev_priv->irq_lock);
4362 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4363 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4364 spin_unlock_irq(&dev_priv->irq_lock);
4369 static void i8xx_error_irq_ack(struct drm_i915_private *i915,
4370 u16 *eir, u16 *eir_stuck)
4372 struct intel_uncore *uncore = &i915->uncore;
4375 *eir = intel_uncore_read16(uncore, EIR);
4378 intel_uncore_write16(uncore, EIR, *eir);
4380 *eir_stuck = intel_uncore_read16(uncore, EIR);
4381 if (*eir_stuck == 0)
4385 * Toggle all EMR bits to make sure we get an edge
4386 * in the ISR master error bit if we don't clear
4387 * all the EIR bits. Otherwise the edge triggered
4388 * IIR on i965/g4x wouldn't notice that an interrupt
4389 * is still pending. Also some EIR bits can't be
4390 * cleared except by handling the underlying error
4391 * (or by a GPU reset) so we mask any bit that
4394 emr = intel_uncore_read16(uncore, EMR);
4395 intel_uncore_write16(uncore, EMR, 0xffff);
4396 intel_uncore_write16(uncore, EMR, emr | *eir_stuck);
4399 static void i8xx_error_irq_handler(struct drm_i915_private *dev_priv,
4400 u16 eir, u16 eir_stuck)
4402 DRM_DEBUG("Master Error: EIR 0x%04x\n", eir);
4405 DRM_DEBUG_DRIVER("EIR stuck: 0x%04x, masked\n", eir_stuck);
4408 static void i9xx_error_irq_ack(struct drm_i915_private *dev_priv,
4409 u32 *eir, u32 *eir_stuck)
4413 *eir = I915_READ(EIR);
4415 I915_WRITE(EIR, *eir);
4417 *eir_stuck = I915_READ(EIR);
4418 if (*eir_stuck == 0)
4422 * Toggle all EMR bits to make sure we get an edge
4423 * in the ISR master error bit if we don't clear
4424 * all the EIR bits. Otherwise the edge triggered
4425 * IIR on i965/g4x wouldn't notice that an interrupt
4426 * is still pending. Also some EIR bits can't be
4427 * cleared except by handling the underlying error
4428 * (or by a GPU reset) so we mask any bit that
4431 emr = I915_READ(EMR);
4432 I915_WRITE(EMR, 0xffffffff);
4433 I915_WRITE(EMR, emr | *eir_stuck);
4436 static void i9xx_error_irq_handler(struct drm_i915_private *dev_priv,
4437 u32 eir, u32 eir_stuck)
4439 DRM_DEBUG("Master Error, EIR 0x%08x\n", eir);
4442 DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masked\n", eir_stuck);
4445 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
4447 struct drm_device *dev = arg;
4448 struct drm_i915_private *dev_priv = to_i915(dev);
4449 irqreturn_t ret = IRQ_NONE;
4451 if (!intel_irqs_enabled(dev_priv))
4454 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4455 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4458 u32 pipe_stats[I915_MAX_PIPES] = {};
4459 u16 eir = 0, eir_stuck = 0;
4462 iir = intel_uncore_read16(&dev_priv->uncore, GEN2_IIR);
4468 /* Call regardless, as some status bits might not be
4469 * signalled in iir */
4470 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
4472 if (iir & I915_MASTER_ERROR_INTERRUPT)
4473 i8xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
4475 intel_uncore_write16(&dev_priv->uncore, GEN2_IIR, iir);
4477 if (iir & I915_USER_INTERRUPT)
4478 intel_engine_breadcrumbs_irq(dev_priv->engine[RCS0]);
4480 if (iir & I915_MASTER_ERROR_INTERRUPT)
4481 i8xx_error_irq_handler(dev_priv, eir, eir_stuck);
4483 i8xx_pipestat_irq_handler(dev_priv, iir, pipe_stats);
4486 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4491 static void i915_irq_reset(struct drm_device *dev)
4493 struct drm_i915_private *dev_priv = to_i915(dev);
4494 struct intel_uncore *uncore = &dev_priv->uncore;
4496 if (I915_HAS_HOTPLUG(dev_priv)) {
4497 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4498 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4501 i9xx_pipestat_irq_reset(dev_priv);
4503 GEN3_IRQ_RESET(uncore, GEN2_);
4506 static int i915_irq_postinstall(struct drm_device *dev)
4508 struct drm_i915_private *dev_priv = to_i915(dev);
4509 struct intel_uncore *uncore = &dev_priv->uncore;
4512 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE |
4513 I915_ERROR_MEMORY_REFRESH));
4515 /* Unmask the interrupts that we always want on. */
4516 dev_priv->irq_mask =
4517 ~(I915_ASLE_INTERRUPT |
4518 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4519 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4520 I915_MASTER_ERROR_INTERRUPT);
4523 I915_ASLE_INTERRUPT |
4524 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4525 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4526 I915_MASTER_ERROR_INTERRUPT |
4527 I915_USER_INTERRUPT;
4529 if (I915_HAS_HOTPLUG(dev_priv)) {
4530 /* Enable in IER... */
4531 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
4532 /* and unmask in IMR */
4533 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
4536 GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);
4538 /* Interrupt setup is already guaranteed to be single-threaded, this is
4539 * just to make the assert_spin_locked check happy. */
4540 spin_lock_irq(&dev_priv->irq_lock);
4541 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4542 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4543 spin_unlock_irq(&dev_priv->irq_lock);
4545 i915_enable_asle_pipestat(dev_priv);
4550 static irqreturn_t i915_irq_handler(int irq, void *arg)
4552 struct drm_device *dev = arg;
4553 struct drm_i915_private *dev_priv = to_i915(dev);
4554 irqreturn_t ret = IRQ_NONE;
4556 if (!intel_irqs_enabled(dev_priv))
4559 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4560 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4563 u32 pipe_stats[I915_MAX_PIPES] = {};
4564 u32 eir = 0, eir_stuck = 0;
4565 u32 hotplug_status = 0;
4568 iir = I915_READ(GEN2_IIR);
4574 if (I915_HAS_HOTPLUG(dev_priv) &&
4575 iir & I915_DISPLAY_PORT_INTERRUPT)
4576 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4578 /* Call regardless, as some status bits might not be
4579 * signalled in iir */
4580 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
4582 if (iir & I915_MASTER_ERROR_INTERRUPT)
4583 i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
4585 I915_WRITE(GEN2_IIR, iir);
4587 if (iir & I915_USER_INTERRUPT)
4588 intel_engine_breadcrumbs_irq(dev_priv->engine[RCS0]);
4590 if (iir & I915_MASTER_ERROR_INTERRUPT)
4591 i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
4594 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4596 i915_pipestat_irq_handler(dev_priv, iir, pipe_stats);
4599 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4604 static void i965_irq_reset(struct drm_device *dev)
4606 struct drm_i915_private *dev_priv = to_i915(dev);
4607 struct intel_uncore *uncore = &dev_priv->uncore;
4609 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4610 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4612 i9xx_pipestat_irq_reset(dev_priv);
4614 GEN3_IRQ_RESET(uncore, GEN2_);
4617 static int i965_irq_postinstall(struct drm_device *dev)
4619 struct drm_i915_private *dev_priv = to_i915(dev);
4620 struct intel_uncore *uncore = &dev_priv->uncore;
4625 * Enable some error detection, note the instruction error mask
4626 * bit is reserved, so we leave it masked.
4628 if (IS_G4X(dev_priv)) {
4629 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4630 GM45_ERROR_MEM_PRIV |
4631 GM45_ERROR_CP_PRIV |
4632 I915_ERROR_MEMORY_REFRESH);
4634 error_mask = ~(I915_ERROR_PAGE_TABLE |
4635 I915_ERROR_MEMORY_REFRESH);
4637 I915_WRITE(EMR, error_mask);
4639 /* Unmask the interrupts that we always want on. */
4640 dev_priv->irq_mask =
4641 ~(I915_ASLE_INTERRUPT |
4642 I915_DISPLAY_PORT_INTERRUPT |
4643 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4644 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4645 I915_MASTER_ERROR_INTERRUPT);
4648 I915_ASLE_INTERRUPT |
4649 I915_DISPLAY_PORT_INTERRUPT |
4650 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4651 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4652 I915_MASTER_ERROR_INTERRUPT |
4653 I915_USER_INTERRUPT;
4655 if (IS_G4X(dev_priv))
4656 enable_mask |= I915_BSD_USER_INTERRUPT;
4658 GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);
4660 /* Interrupt setup is already guaranteed to be single-threaded, this is
4661 * just to make the assert_spin_locked check happy. */
4662 spin_lock_irq(&dev_priv->irq_lock);
4663 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4664 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4665 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4666 spin_unlock_irq(&dev_priv->irq_lock);
4668 i915_enable_asle_pipestat(dev_priv);
4673 static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
4677 lockdep_assert_held(&dev_priv->irq_lock);
4679 /* Note HDMI and DP share hotplug bits */
4680 /* enable bits are the same for all generations */
4681 hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);
4682 /* Programming the CRT detection parameters tends
4683 to generate a spurious hotplug event about three
4684 seconds later. So just do it once.
4686 if (IS_G4X(dev_priv))
4687 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4688 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4690 /* Ignore TV since it's buggy */
4691 i915_hotplug_interrupt_update_locked(dev_priv,
4692 HOTPLUG_INT_EN_MASK |
4693 CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
4694 CRT_HOTPLUG_ACTIVATION_PERIOD_64,
4698 static irqreturn_t i965_irq_handler(int irq, void *arg)
4700 struct drm_device *dev = arg;
4701 struct drm_i915_private *dev_priv = to_i915(dev);
4702 irqreturn_t ret = IRQ_NONE;
4704 if (!intel_irqs_enabled(dev_priv))
4707 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4708 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4711 u32 pipe_stats[I915_MAX_PIPES] = {};
4712 u32 eir = 0, eir_stuck = 0;
4713 u32 hotplug_status = 0;
4716 iir = I915_READ(GEN2_IIR);
4722 if (iir & I915_DISPLAY_PORT_INTERRUPT)
4723 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4725 /* Call regardless, as some status bits might not be
4726 * signalled in iir */
4727 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
4729 if (iir & I915_MASTER_ERROR_INTERRUPT)
4730 i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
4732 I915_WRITE(GEN2_IIR, iir);
4734 if (iir & I915_USER_INTERRUPT)
4735 intel_engine_breadcrumbs_irq(dev_priv->engine[RCS0]);
4737 if (iir & I915_BSD_USER_INTERRUPT)
4738 intel_engine_breadcrumbs_irq(dev_priv->engine[VCS0]);
4740 if (iir & I915_MASTER_ERROR_INTERRUPT)
4741 i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
4744 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4746 i965_pipestat_irq_handler(dev_priv, iir, pipe_stats);
4749 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4755 * intel_irq_init - initializes irq support
4756 * @dev_priv: i915 device instance
4758 * This function initializes all the irq support including work items, timers
4759 * and all the vtables. It does not setup the interrupt itself though.
4761 void intel_irq_init(struct drm_i915_private *dev_priv)
4763 struct drm_device *dev = &dev_priv->drm;
4764 struct intel_rps *rps = &dev_priv->gt_pm.rps;
4767 if (IS_I945GM(dev_priv))
4768 i945gm_vblank_work_init(dev_priv);
4770 intel_hpd_init_work(dev_priv);
4772 INIT_WORK(&rps->work, gen6_pm_rps_work);
4774 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4775 for (i = 0; i < MAX_L3_SLICES; ++i)
4776 dev_priv->l3_parity.remap_info[i] = NULL;
4778 if (HAS_GUC_SCHED(dev_priv) && INTEL_GEN(dev_priv) < 11)
4779 dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT;
4781 /* Let's track the enabled rps events */
4782 if (IS_VALLEYVIEW(dev_priv))
4783 /* WaGsvRC0ResidencyMethod:vlv */
4784 dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED;
4786 dev_priv->pm_rps_events = (GEN6_PM_RP_UP_THRESHOLD |
4787 GEN6_PM_RP_DOWN_THRESHOLD |
4788 GEN6_PM_RP_DOWN_TIMEOUT);
4790 /* We share the register with other engine */
4791 if (INTEL_GEN(dev_priv) > 9)
4792 GEM_WARN_ON(dev_priv->pm_rps_events & 0xffff0000);
4794 rps->pm_intrmsk_mbz = 0;
4797 * SNB,IVB,HSW can while VLV,CHV may hard hang on looping batchbuffer
4798 * if GEN6_PM_UP_EI_EXPIRED is masked.
4800 * TODO: verify if this can be reproduced on VLV,CHV.
4802 if (INTEL_GEN(dev_priv) <= 7)
4803 rps->pm_intrmsk_mbz |= GEN6_PM_RP_UP_EI_EXPIRED;
4805 if (INTEL_GEN(dev_priv) >= 8)
4806 rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
4808 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
4809 dev->driver->get_vblank_counter = g4x_get_vblank_counter;
4810 else if (INTEL_GEN(dev_priv) >= 3)
4811 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4813 dev->vblank_disable_immediate = true;
4815 /* Most platforms treat the display irq block as an always-on
4816 * power domain. vlv/chv can disable it at runtime and need
4817 * special care to avoid writing any of the display block registers
4818 * outside of the power domain. We defer setting up the display irqs
4819 * in this case to the runtime pm.
4821 dev_priv->display_irqs_enabled = true;
4822 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4823 dev_priv->display_irqs_enabled = false;
4825 dev_priv->hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD;
4826 /* If we have MST support, we want to avoid doing short HPD IRQ storm
4827 * detection, as short HPD storms will occur as a natural part of
4828 * sideband messaging with MST.
4829 * On older platforms however, IRQ storms can occur with both long and
4830 * short pulses, as seen on some G4x systems.
4832 dev_priv->hotplug.hpd_short_storm_enabled = !HAS_DP_MST(dev_priv);
4834 dev->driver->get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos;
4835 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4837 if (IS_CHERRYVIEW(dev_priv)) {
4838 dev->driver->irq_handler = cherryview_irq_handler;
4839 dev->driver->irq_preinstall = cherryview_irq_reset;
4840 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4841 dev->driver->irq_uninstall = cherryview_irq_reset;
4842 dev->driver->enable_vblank = i965_enable_vblank;
4843 dev->driver->disable_vblank = i965_disable_vblank;
4844 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4845 } else if (IS_VALLEYVIEW(dev_priv)) {
4846 dev->driver->irq_handler = valleyview_irq_handler;
4847 dev->driver->irq_preinstall = valleyview_irq_reset;
4848 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4849 dev->driver->irq_uninstall = valleyview_irq_reset;
4850 dev->driver->enable_vblank = i965_enable_vblank;
4851 dev->driver->disable_vblank = i965_disable_vblank;
4852 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4853 } else if (INTEL_GEN(dev_priv) >= 11) {
4854 dev->driver->irq_handler = gen11_irq_handler;
4855 dev->driver->irq_preinstall = gen11_irq_reset;
4856 dev->driver->irq_postinstall = gen11_irq_postinstall;
4857 dev->driver->irq_uninstall = gen11_irq_reset;
4858 dev->driver->enable_vblank = gen8_enable_vblank;
4859 dev->driver->disable_vblank = gen8_disable_vblank;
4860 dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
4861 } else if (INTEL_GEN(dev_priv) >= 8) {
4862 dev->driver->irq_handler = gen8_irq_handler;
4863 dev->driver->irq_preinstall = gen8_irq_reset;
4864 dev->driver->irq_postinstall = gen8_irq_postinstall;
4865 dev->driver->irq_uninstall = gen8_irq_reset;
4866 dev->driver->enable_vblank = gen8_enable_vblank;
4867 dev->driver->disable_vblank = gen8_disable_vblank;
4868 if (IS_GEN9_LP(dev_priv))
4869 dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4870 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
4871 dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4873 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4874 } else if (HAS_PCH_SPLIT(dev_priv)) {
4875 dev->driver->irq_handler = ironlake_irq_handler;
4876 dev->driver->irq_preinstall = ironlake_irq_reset;
4877 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4878 dev->driver->irq_uninstall = ironlake_irq_reset;
4879 dev->driver->enable_vblank = ironlake_enable_vblank;
4880 dev->driver->disable_vblank = ironlake_disable_vblank;
4881 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4883 if (IS_GEN(dev_priv, 2)) {
4884 dev->driver->irq_preinstall = i8xx_irq_reset;
4885 dev->driver->irq_postinstall = i8xx_irq_postinstall;
4886 dev->driver->irq_handler = i8xx_irq_handler;
4887 dev->driver->irq_uninstall = i8xx_irq_reset;
4888 dev->driver->enable_vblank = i8xx_enable_vblank;
4889 dev->driver->disable_vblank = i8xx_disable_vblank;
4890 } else if (IS_I945GM(dev_priv)) {
4891 dev->driver->irq_preinstall = i915_irq_reset;
4892 dev->driver->irq_postinstall = i915_irq_postinstall;
4893 dev->driver->irq_uninstall = i915_irq_reset;
4894 dev->driver->irq_handler = i915_irq_handler;
4895 dev->driver->enable_vblank = i945gm_enable_vblank;
4896 dev->driver->disable_vblank = i945gm_disable_vblank;
4897 } else if (IS_GEN(dev_priv, 3)) {
4898 dev->driver->irq_preinstall = i915_irq_reset;
4899 dev->driver->irq_postinstall = i915_irq_postinstall;
4900 dev->driver->irq_uninstall = i915_irq_reset;
4901 dev->driver->irq_handler = i915_irq_handler;
4902 dev->driver->enable_vblank = i8xx_enable_vblank;
4903 dev->driver->disable_vblank = i8xx_disable_vblank;
4905 dev->driver->irq_preinstall = i965_irq_reset;
4906 dev->driver->irq_postinstall = i965_irq_postinstall;
4907 dev->driver->irq_uninstall = i965_irq_reset;
4908 dev->driver->irq_handler = i965_irq_handler;
4909 dev->driver->enable_vblank = i965_enable_vblank;
4910 dev->driver->disable_vblank = i965_disable_vblank;
4912 if (I915_HAS_HOTPLUG(dev_priv))
4913 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4918 * intel_irq_fini - deinitializes IRQ support
4919 * @i915: i915 device instance
4921 * This function deinitializes all the IRQ support.
4923 void intel_irq_fini(struct drm_i915_private *i915)
4927 if (IS_I945GM(i915))
4928 i945gm_vblank_work_fini(i915);
4930 for (i = 0; i < MAX_L3_SLICES; ++i)
4931 kfree(i915->l3_parity.remap_info[i]);
4935 * intel_irq_install - enables the hardware interrupt
4936 * @dev_priv: i915 device instance
4938 * This function enables the hardware interrupt handling, but leaves the hotplug
4939 * handling still disabled. It is called after intel_irq_init().
4941 * In the driver load and resume code we need working interrupts in a few places
4942 * but don't want to deal with the hassle of concurrent probe and hotplug
4943 * workers. Hence the split into this two-stage approach.
4945 int intel_irq_install(struct drm_i915_private *dev_priv)
4948 * We enable some interrupt sources in our postinstall hooks, so mark
4949 * interrupts as enabled _before_ actually enabling them to avoid
4950 * special cases in our ordering checks.
4952 dev_priv->runtime_pm.irqs_enabled = true;
4954 return drm_irq_install(&dev_priv->drm, dev_priv->drm.pdev->irq);
4958 * intel_irq_uninstall - finilizes all irq handling
4959 * @dev_priv: i915 device instance
4961 * This stops interrupt and hotplug handling and unregisters and frees all
4962 * resources acquired in the init functions.
4964 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4966 drm_irq_uninstall(&dev_priv->drm);
4967 intel_hpd_cancel_work(dev_priv);
4968 dev_priv->runtime_pm.irqs_enabled = false;
4972 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4973 * @dev_priv: i915 device instance
4975 * This function is used to disable interrupts at runtime, both in the runtime
4976 * pm and the system suspend/resume code.
4978 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4980 dev_priv->drm.driver->irq_uninstall(&dev_priv->drm);
4981 dev_priv->runtime_pm.irqs_enabled = false;
4982 synchronize_irq(dev_priv->drm.irq);
4986 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4987 * @dev_priv: i915 device instance
4989 * This function is used to enable interrupts at runtime, both in the runtime
4990 * pm and the system suspend/resume code.
4992 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4994 dev_priv->runtime_pm.irqs_enabled = true;
4995 dev_priv->drm.driver->irq_preinstall(&dev_priv->drm);
4996 dev_priv->drm.driver->irq_postinstall(&dev_priv->drm);