drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/circ_buf.h>
  32 #include <linux/slab.h>
  33 #include <linux/sysrq.h>
  34
  35 #include <drm/drm_drv.h>
  36 #include <drm/drm_irq.h>
  37
  38 #include "display/intel_de.h"
  39 #include "display/intel_display_types.h"
  40 #include "display/intel_fifo_underrun.h"
  41 #include "display/intel_hotplug.h"
  42 #include "display/intel_lpe_audio.h"
  43 #include "display/intel_psr.h"
  44
  45 #include "gt/intel_breadcrumbs.h"
  46 #include "gt/intel_gt.h"
  47 #include "gt/intel_gt_irq.h"
  48 #include "gt/intel_gt_pm_irq.h"
  49 #include "gt/intel_rps.h"
  50
  51 #include "i915_drv.h"
  52 #include "i915_irq.h"
  53 #include "i915_trace.h"
  54 #include "intel_pm.h"
  55
  56 /**
  57  * DOC: interrupt handling
  58  *
  59  * These functions provide the basic support for enabling and disabling the
  60  * interrupt handling support. There's a lot more functionality in i915_irq.c
  61  * and related files, but that will be described in separate chapters.
  62  */
  63
  64 /*
  65  * Interrupt statistic for PMU. Increments the counter only if the
  66  * interrupt originated from the the GPU so interrupts from a device which
  67  * shares the interrupt line are not accounted.
  68  */
  69 static inline void pmu_irq_stats(struct drm_i915_private *i915,
  70                                  irqreturn_t res)
  71 {
  72         if (unlikely(res != IRQ_HANDLED))
  73                 return;
  74
  75         /*
  76          * A clever compiler translates that into INC. A not so clever one
  77          * should at least prevent store tearing.
  78          */
  79         WRITE_ONCE(i915->pmu.irq_count, i915->pmu.irq_count + 1);
  80 }
  81
  82 typedef bool (*long_pulse_detect_func)(enum hpd_pin pin, u32 val);
  83 typedef u32 (*hotplug_enables_func)(struct drm_i915_private *i915,
  84                                     enum hpd_pin pin);
  85
  86 static const u32 hpd_ilk[HPD_NUM_PINS] = {
  87         [HPD_PORT_A] = DE_DP_A_HOTPLUG,
  88 };
  89
  90 static const u32 hpd_ivb[HPD_NUM_PINS] = {
  91         [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
  92 };
  93
  94 static const u32 hpd_bdw[HPD_NUM_PINS] = {
  95         [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A),
  96 };
  97
  98 static const u32 hpd_ibx[HPD_NUM_PINS] = {
  99         [HPD_CRT] = SDE_CRT_HOTPLUG,
 100         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
 101         [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
 102         [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
 103         [HPD_PORT_D] = SDE_PORTD_HOTPLUG,
 104 };
 105
 106 static const u32 hpd_cpt[HPD_NUM_PINS] = {
 107         [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
 108         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
 109         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
 110         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
 111         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
 112 };
 113
 114 static const u32 hpd_spt[HPD_NUM_PINS] = {
 115         [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
 116         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
 117         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
 118         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
 119         [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT,
 120 };
 121
 122 static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
 123         [HPD_CRT] = CRT_HOTPLUG_INT_EN,
 124         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
 125         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
 126         [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
 127         [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
 128         [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN,
 129 };
 130
 131 static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
 132         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
 133         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
 134         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
 135         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
 136         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
 137         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS,
 138 };
 139
 140 static const u32 hpd_status_i915[HPD_NUM_PINS] = {
 141         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
 142         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
 143         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
 144         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
 145         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
 146         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS,
 147 };
 148
 149 static const u32 hpd_bxt[HPD_NUM_PINS] = {
 150         [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A),
 151         [HPD_PORT_B] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_B),
 152         [HPD_PORT_C] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_C),
 153 };
 154
 155 static const u32 hpd_gen11[HPD_NUM_PINS] = {
 156         [HPD_PORT_TC1] = GEN11_TC_HOTPLUG(HPD_PORT_TC1) | GEN11_TBT_HOTPLUG(HPD_PORT_TC1),
 157         [HPD_PORT_TC2] = GEN11_TC_HOTPLUG(HPD_PORT_TC2) | GEN11_TBT_HOTPLUG(HPD_PORT_TC2),
 158         [HPD_PORT_TC3] = GEN11_TC_HOTPLUG(HPD_PORT_TC3) | GEN11_TBT_HOTPLUG(HPD_PORT_TC3),
 159         [HPD_PORT_TC4] = GEN11_TC_HOTPLUG(HPD_PORT_TC4) | GEN11_TBT_HOTPLUG(HPD_PORT_TC4),
 160         [HPD_PORT_TC5] = GEN11_TC_HOTPLUG(HPD_PORT_TC5) | GEN11_TBT_HOTPLUG(HPD_PORT_TC5),
 161         [HPD_PORT_TC6] = GEN11_TC_HOTPLUG(HPD_PORT_TC6) | GEN11_TBT_HOTPLUG(HPD_PORT_TC6),
 162 };
 163
 164 static const u32 hpd_icp[HPD_NUM_PINS] = {
 165         [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
 166         [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
 167         [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
 168         [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1),
 169         [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2),
 170         [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3),
 171         [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4),
 172         [HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5),
 173         [HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6),
 174 };
 175
 176 static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
 177         [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
 178         [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
 179         [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
 180         [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_D),
 181 };
 182
 183 static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
 184 {
 185         struct i915_hotplug *hpd = &dev_priv->hotplug;
 186
 187         if (HAS_GMCH(dev_priv)) {
 188                 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
 189                     IS_CHERRYVIEW(dev_priv))
 190                         hpd->hpd = hpd_status_g4x;
 191                 else
 192                         hpd->hpd = hpd_status_i915;
 193                 return;
 194         }
 195
 196         if (DISPLAY_VER(dev_priv) >= 11)
 197                 hpd->hpd = hpd_gen11;
 198         else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
 199                 hpd->hpd = hpd_bxt;
 200         else if (DISPLAY_VER(dev_priv) >= 8)
 201                 hpd->hpd = hpd_bdw;
 202         else if (DISPLAY_VER(dev_priv) >= 7)
 203                 hpd->hpd = hpd_ivb;
 204         else
 205                 hpd->hpd = hpd_ilk;
 206
 207         if ((INTEL_PCH_TYPE(dev_priv) < PCH_DG1) &&
 208             (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)))
 209                 return;
 210
 211         if (HAS_PCH_DG1(dev_priv))
 212                 hpd->pch_hpd = hpd_sde_dg1;
 213         else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
 214                 hpd->pch_hpd = hpd_icp;
 215         else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv))
 216                 hpd->pch_hpd = hpd_spt;
 217         else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_CPT(dev_priv))
 218                 hpd->pch_hpd = hpd_cpt;
 219         else if (HAS_PCH_IBX(dev_priv))
 220                 hpd->pch_hpd = hpd_ibx;
 221         else
 222                 MISSING_CASE(INTEL_PCH_TYPE(dev_priv));
 223 }
 224
 225 static void
 226 intel_handle_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
 227 {
 228         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
 229
 230         drm_crtc_handle_vblank(&crtc->base);
 231 }
 232
 233 void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
 234                     i915_reg_t iir, i915_reg_t ier)
 235 {
 236         intel_uncore_write(uncore, imr, 0xffffffff);
 237         intel_uncore_posting_read(uncore, imr);
 238
 239         intel_uncore_write(uncore, ier, 0);
 240
 241         /* IIR can theoretically queue up two events. Be paranoid. */
 242         intel_uncore_write(uncore, iir, 0xffffffff);
 243         intel_uncore_posting_read(uncore, iir);
 244         intel_uncore_write(uncore, iir, 0xffffffff);
 245         intel_uncore_posting_read(uncore, iir);
 246 }
 247
 248 void gen2_irq_reset(struct intel_uncore *uncore)
 249 {
 250         intel_uncore_write16(uncore, GEN2_IMR, 0xffff);
 251         intel_uncore_posting_read16(uncore, GEN2_IMR);
 252
 253         intel_uncore_write16(uncore, GEN2_IER, 0);
 254
 255         /* IIR can theoretically queue up two events. Be paranoid. */
 256         intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
 257         intel_uncore_posting_read16(uncore, GEN2_IIR);
 258         intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
 259         intel_uncore_posting_read16(uncore, GEN2_IIR);
 260 }
 261
 262 /*
 263  * We should clear IMR at preinstall/uninstall, and just check at postinstall.
 264  */
 265 static void gen3_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg)
 266 {
 267         u32 val = intel_uncore_read(uncore, reg);
 268
 269         if (val == 0)
 270                 return;
 271
 272         drm_WARN(&uncore->i915->drm, 1,
 273                  "Interrupt register 0x%x is not zero: 0x%08x\n",
 274                  i915_mmio_reg_offset(reg), val);
 275         intel_uncore_write(uncore, reg, 0xffffffff);
 276         intel_uncore_posting_read(uncore, reg);
 277         intel_uncore_write(uncore, reg, 0xffffffff);
 278         intel_uncore_posting_read(uncore, reg);
 279 }
 280
 281 static void gen2_assert_iir_is_zero(struct intel_uncore *uncore)
 282 {
 283         u16 val = intel_uncore_read16(uncore, GEN2_IIR);
 284
 285         if (val == 0)
 286                 return;
 287
 288         drm_WARN(&uncore->i915->drm, 1,
 289                  "Interrupt register 0x%x is not zero: 0x%08x\n",
 290                  i915_mmio_reg_offset(GEN2_IIR), val);
 291         intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
 292         intel_uncore_posting_read16(uncore, GEN2_IIR);
 293         intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
 294         intel_uncore_posting_read16(uncore, GEN2_IIR);
 295 }
 296
 297 void gen3_irq_init(struct intel_uncore *uncore,
 298                    i915_reg_t imr, u32 imr_val,
 299                    i915_reg_t ier, u32 ier_val,
 300                    i915_reg_t iir)
 301 {
 302         gen3_assert_iir_is_zero(uncore, iir);
 303
 304         intel_uncore_write(uncore, ier, ier_val);
 305         intel_uncore_write(uncore, imr, imr_val);
 306         intel_uncore_posting_read(uncore, imr);
 307 }
 308
 309 void gen2_irq_init(struct intel_uncore *uncore,
 310                    u32 imr_val, u32 ier_val)
 311 {
 312         gen2_assert_iir_is_zero(uncore);
 313
 314         intel_uncore_write16(uncore, GEN2_IER, ier_val);
 315         intel_uncore_write16(uncore, GEN2_IMR, imr_val);
 316         intel_uncore_posting_read16(uncore, GEN2_IMR);
 317 }
 318
 319 /* For display hotplug interrupt */
 320 static inline void
 321 i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
 322                                      u32 mask,
 323                                      u32 bits)
 324 {
 325         u32 val;
 326
 327         lockdep_assert_held(&dev_priv->irq_lock);
 328         drm_WARN_ON(&dev_priv->drm, bits & ~mask);
 329
 330         val = intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_EN);
 331         val &= ~mask;
 332         val |= bits;
 333         intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_EN, val);
 334 }
 335
 336 /**
 337  * i915_hotplug_interrupt_update - update hotplug interrupt enable
 338  * @dev_priv: driver private
 339  * @mask: bits to update
 340  * @bits: bits to enable
 341  * NOTE: the HPD enable bits are modified both inside and outside
 342  * of an interrupt context. To avoid that read-modify-write cycles
 343  * interfer, these bits are protected by a spinlock. Since this
 344  * function is usually not called from a context where the lock is
 345  * held already, this function acquires the lock itself. A non-locking
 346  * version is also available.
 347  */
 348 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
 349                                    u32 mask,
 350                                    u32 bits)
 351 {
 352         spin_lock_irq(&dev_priv->irq_lock);
 353         i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
 354         spin_unlock_irq(&dev_priv->irq_lock);
 355 }
 356
 357 /**
 358  * ilk_update_display_irq - update DEIMR
 359  * @dev_priv: driver private
 360  * @interrupt_mask: mask of interrupt bits to update
 361  * @enabled_irq_mask: mask of interrupt bits to enable
 362  */
 363 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
 364                             u32 interrupt_mask,
 365                             u32 enabled_irq_mask)
 366 {
 367         u32 new_val;
 368
 369         lockdep_assert_held(&dev_priv->irq_lock);
 370         drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
 371
 372         new_val = dev_priv->irq_mask;
 373         new_val &= ~interrupt_mask;
 374         new_val |= (~enabled_irq_mask & interrupt_mask);
 375
 376         if (new_val != dev_priv->irq_mask &&
 377             !drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) {
 378                 dev_priv->irq_mask = new_val;
 379                 intel_uncore_write(&dev_priv->uncore, DEIMR, dev_priv->irq_mask);
 380                 intel_uncore_posting_read(&dev_priv->uncore, DEIMR);
 381         }
 382 }
 383
 384 /**
 385  * bdw_update_port_irq - update DE port interrupt
 386  * @dev_priv: driver private
 387  * @interrupt_mask: mask of interrupt bits to update
 388  * @enabled_irq_mask: mask of interrupt bits to enable
 389  */
 390 static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
 391                                 u32 interrupt_mask,
 392                                 u32 enabled_irq_mask)
 393 {
 394         u32 new_val;
 395         u32 old_val;
 396
 397         lockdep_assert_held(&dev_priv->irq_lock);
 398
 399         drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
 400
 401         if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
 402                 return;
 403
 404         old_val = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IMR);
 405
 406         new_val = old_val;
 407         new_val &= ~interrupt_mask;
 408         new_val |= (~enabled_irq_mask & interrupt_mask);
 409
 410         if (new_val != old_val) {
 411                 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PORT_IMR, new_val);
 412                 intel_uncore_posting_read(&dev_priv->uncore, GEN8_DE_PORT_IMR);
 413         }
 414 }
 415
 416 /**
 417  * bdw_update_pipe_irq - update DE pipe interrupt
 418  * @dev_priv: driver private
 419  * @pipe: pipe whose interrupt to update
 420  * @interrupt_mask: mask of interrupt bits to update
 421  * @enabled_irq_mask: mask of interrupt bits to enable
 422  */
 423 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
 424                          enum pipe pipe,
 425                          u32 interrupt_mask,
 426                          u32 enabled_irq_mask)
 427 {
 428         u32 new_val;
 429
 430         lockdep_assert_held(&dev_priv->irq_lock);
 431
 432         drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
 433
 434         if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
 435                 return;
 436
 437         new_val = dev_priv->de_irq_mask[pipe];
 438         new_val &= ~interrupt_mask;
 439         new_val |= (~enabled_irq_mask & interrupt_mask);
 440
 441         if (new_val != dev_priv->de_irq_mask[pipe]) {
 442                 dev_priv->de_irq_mask[pipe] = new_val;
 443                 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
 444                 intel_uncore_posting_read(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe));
 445         }
 446 }
 447
 448 /**
 449  * ibx_display_interrupt_update - update SDEIMR
 450  * @dev_priv: driver private
 451  * @interrupt_mask: mask of interrupt bits to update
 452  * @enabled_irq_mask: mask of interrupt bits to enable
 453  */
 454 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
 455                                   u32 interrupt_mask,
 456                                   u32 enabled_irq_mask)
 457 {
 458         u32 sdeimr = intel_uncore_read(&dev_priv->uncore, SDEIMR);
 459         sdeimr &= ~interrupt_mask;
 460         sdeimr |= (~enabled_irq_mask & interrupt_mask);
 461
 462         drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
 463
 464         lockdep_assert_held(&dev_priv->irq_lock);
 465
 466         if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
 467                 return;
 468
 469         intel_uncore_write(&dev_priv->uncore, SDEIMR, sdeimr);
 470         intel_uncore_posting_read(&dev_priv->uncore, SDEIMR);
 471 }
 472
 473 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
 474                               enum pipe pipe)
 475 {
 476         u32 status_mask = dev_priv->pipestat_irq_mask[pipe];
 477         u32 enable_mask = status_mask << 16;
 478
 479         lockdep_assert_held(&dev_priv->irq_lock);
 480
 481         if (DISPLAY_VER(dev_priv) < 5)
 482                 goto out;
 483
 484         /*
 485          * On pipe A we don't support the PSR interrupt yet,
 486          * on pipe B and C the same bit MBZ.
 487          */
 488         if (drm_WARN_ON_ONCE(&dev_priv->drm,
 489                              status_mask & PIPE_A_PSR_STATUS_VLV))
 490                 return 0;
 491         /*
 492          * On pipe B and C we don't support the PSR interrupt yet, on pipe
 493          * A the same bit is for perf counters which we don't use either.
 494          */
 495         if (drm_WARN_ON_ONCE(&dev_priv->drm,
 496                              status_mask & PIPE_B_PSR_STATUS_VLV))
 497                 return 0;
 498
 499         enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
 500                          SPRITE0_FLIP_DONE_INT_EN_VLV |
 501                          SPRITE1_FLIP_DONE_INT_EN_VLV);
 502         if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
 503                 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
 504         if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
 505                 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
 506
 507 out:
 508         drm_WARN_ONCE(&dev_priv->drm,
 509                       enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 510                       status_mask & ~PIPESTAT_INT_STATUS_MASK,
 511                       "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
 512                       pipe_name(pipe), enable_mask, status_mask);
 513
 514         return enable_mask;
 515 }
 516
 517 void i915_enable_pipestat(struct drm_i915_private *dev_priv,
 518                           enum pipe pipe, u32 status_mask)
 519 {
 520         i915_reg_t reg = PIPESTAT(pipe);
 521         u32 enable_mask;
 522
 523         drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,
 524                       "pipe %c: status_mask=0x%x\n",
 525                       pipe_name(pipe), status_mask);
 526
 527         lockdep_assert_held(&dev_priv->irq_lock);
 528         drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv));
 529
 530         if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == status_mask)
 531                 return;
 532
 533         dev_priv->pipestat_irq_mask[pipe] |= status_mask;
 534         enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
 535
 536         intel_uncore_write(&dev_priv->uncore, reg, enable_mask | status_mask);
 537         intel_uncore_posting_read(&dev_priv->uncore, reg);
 538 }
 539
 540 void i915_disable_pipestat(struct drm_i915_private *dev_priv,
 541                            enum pipe pipe, u32 status_mask)
 542 {
 543         i915_reg_t reg = PIPESTAT(pipe);
 544         u32 enable_mask;
 545
 546         drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,
 547                       "pipe %c: status_mask=0x%x\n",
 548                       pipe_name(pipe), status_mask);
 549
 550         lockdep_assert_held(&dev_priv->irq_lock);
 551         drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv));
 552
 553         if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == 0)
 554                 return;
 555
 556         dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
 557         enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
 558
 559         intel_uncore_write(&dev_priv->uncore, reg, enable_mask | status_mask);
 560         intel_uncore_posting_read(&dev_priv->uncore, reg);
 561 }
 562
 563 static bool i915_has_asle(struct drm_i915_private *dev_priv)
 564 {
 565         if (!dev_priv->opregion.asle)
 566                 return false;
 567
 568         return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
 569 }
 570
 571 /**
 572  * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
 573  * @dev_priv: i915 device private
 574  */
 575 static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
 576 {
 577         if (!i915_has_asle(dev_priv))
 578                 return;
 579
 580         spin_lock_irq(&dev_priv->irq_lock);
 581
 582         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
 583         if (DISPLAY_VER(dev_priv) >= 4)
 584                 i915_enable_pipestat(dev_priv, PIPE_A,
 585                                      PIPE_LEGACY_BLC_EVENT_STATUS);
 586
 587         spin_unlock_irq(&dev_priv->irq_lock);
 588 }
 589
 590 /*
 591  * This timing diagram depicts the video signal in and
 592  * around the vertical blanking period.
 593  *
 594  * Assumptions about the fictitious mode used in this example:
 595  *  vblank_start >= 3
 596  *  vsync_start = vblank_start + 1
 597  *  vsync_end = vblank_start + 2
 598  *  vtotal = vblank_start + 3
 599  *
 600  *           start of vblank:
 601  *           latch double buffered registers
 602  *           increment frame counter (ctg+)
 603  *           generate start of vblank interrupt (gen4+)
 604  *           |
 605  *           |          frame start:
 606  *           |          generate frame start interrupt (aka. vblank interrupt) (gmch)
 607  *           |          may be shifted forward 1-3 extra lines via PIPECONF
 608  *           |          |
 609  *           |          |  start of vsync:
 610  *           |          |  generate vsync interrupt
 611  *           |          |  |
 612  * ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx
 613  *       .   \hs/   .      \hs/          \hs/          \hs/   .      \hs/
 614  * ----va---> <-----------------vb--------------------> <--------va-------------
 615  *       |          |       <----vs----->                     |
 616  * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
 617  * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
 618  * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
 619  *       |          |                                         |
 620  *       last visible pixel                                   first visible pixel
 621  *                  |                                         increment frame counter (gen3/4)
 622  *                  pixel counter = vblank_start * htotal     pixel counter = 0 (gen3/4)
 623  *
 624  * x  = horizontal active
 625  * _  = horizontal blanking
 626  * hs = horizontal sync
 627  * va = vertical active
 628  * vb = vertical blanking
 629  * vs = vertical sync
 630  * vbs = vblank_start (number)
 631  *
 632  * Summary:
 633  * - most events happen at the start of horizontal sync
 634  * - frame start happens at the start of horizontal blank, 1-4 lines
 635  *   (depending on PIPECONF settings) after the start of vblank
 636  * - gen3/4 pixel and frame counter are synchronized with the start
 637  *   of horizontal active on the first line of vertical active
 638  */
 639
 640 /* Called from drm generic code, passed a 'crtc', which
 641  * we use as a pipe index
 642  */
 643 u32 i915_get_vblank_counter(struct drm_crtc *crtc)
 644 {
 645         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 646         struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)];
 647         const struct drm_display_mode *mode = &vblank->hwmode;
 648         enum pipe pipe = to_intel_crtc(crtc)->pipe;
 649         i915_reg_t high_frame, low_frame;
 650         u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
 651         unsigned long irqflags;
 652
 653         /*
 654          * On i965gm TV output the frame counter only works up to
 655          * the point when we enable the TV encoder. After that the
 656          * frame counter ceases to work and reads zero. We need a
 657          * vblank wait before enabling the TV encoder and so we
 658          * have to enable vblank interrupts while the frame counter
 659          * is still in a working state. However the core vblank code
 660          * does not like us returning non-zero frame counter values
 661          * when we've told it that we don't have a working frame
 662          * counter. Thus we must stop non-zero values leaking out.
 663          */
 664         if (!vblank->max_vblank_count)
 665                 return 0;
 666
 667         htotal = mode->crtc_htotal;
 668         hsync_start = mode->crtc_hsync_start;
 669         vbl_start = mode->crtc_vblank_start;
 670         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 671                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 672
 673         /* Convert to pixel count */
 674         vbl_start *= htotal;
 675
 676         /* Start of vblank event occurs at start of hsync */
 677         vbl_start -= htotal - hsync_start;
 678
 679         high_frame = PIPEFRAME(pipe);
 680         low_frame = PIPEFRAMEPIXEL(pipe);
 681
 682         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 683
 684         /*
 685          * High & low register fields aren't synchronized, so make sure
 686          * we get a low value that's stable across two reads of the high
 687          * register.
 688          */
 689         do {
 690                 high1 = intel_de_read_fw(dev_priv, high_frame) & PIPE_FRAME_HIGH_MASK;
 691                 low   = intel_de_read_fw(dev_priv, low_frame);
 692                 high2 = intel_de_read_fw(dev_priv, high_frame) & PIPE_FRAME_HIGH_MASK;
 693         } while (high1 != high2);
 694
 695         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 696
 697         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 698         pixel = low & PIPE_PIXEL_MASK;
 699         low >>= PIPE_FRAME_LOW_SHIFT;
 700
 701         /*
 702          * The frame counter increments at beginning of active.
 703          * Cook up a vblank counter by also checking the pixel
 704          * counter against vblank start.
 705          */
 706         return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
 707 }
 708
 709 u32 g4x_get_vblank_counter(struct drm_crtc *crtc)
 710 {
 711         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 712         struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)];
 713         enum pipe pipe = to_intel_crtc(crtc)->pipe;
 714
 715         if (!vblank->max_vblank_count)
 716                 return 0;
 717
 718         return intel_uncore_read(&dev_priv->uncore, PIPE_FRMCOUNT_G4X(pipe));
 719 }
 720
 721 static u32 intel_crtc_scanlines_since_frame_timestamp(struct intel_crtc *crtc)
 722 {
 723         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 724         struct drm_vblank_crtc *vblank =
 725                 &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
 726         const struct drm_display_mode *mode = &vblank->hwmode;
 727         u32 htotal = mode->crtc_htotal;
 728         u32 clock = mode->crtc_clock;
 729         u32 scan_prev_time, scan_curr_time, scan_post_time;
 730
 731         /*
 732          * To avoid the race condition where we might cross into the
 733          * next vblank just between the PIPE_FRMTMSTMP and TIMESTAMP_CTR
 734          * reads. We make sure we read PIPE_FRMTMSTMP and TIMESTAMP_CTR
 735          * during the same frame.
 736          */
 737         do {
 738                 /*
 739                  * This field provides read back of the display
 740                  * pipe frame time stamp. The time stamp value
 741                  * is sampled at every start of vertical blank.
 742                  */
 743                 scan_prev_time = intel_de_read_fw(dev_priv,
 744                                                   PIPE_FRMTMSTMP(crtc->pipe));
 745
 746                 /*
 747                  * The TIMESTAMP_CTR register has the current
 748                  * time stamp value.
 749                  */
 750                 scan_curr_time = intel_de_read_fw(dev_priv, IVB_TIMESTAMP_CTR);
 751
 752                 scan_post_time = intel_de_read_fw(dev_priv,
 753                                                   PIPE_FRMTMSTMP(crtc->pipe));
 754         } while (scan_post_time != scan_prev_time);
 755
 756         return div_u64(mul_u32_u32(scan_curr_time - scan_prev_time,
 757                                    clock), 1000 * htotal);
 758 }
 759
 760 /*
 761  * On certain encoders on certain platforms, pipe
 762  * scanline register will not work to get the scanline,
 763  * since the timings are driven from the PORT or issues
 764  * with scanline register updates.
 765  * This function will use Framestamp and current
 766  * timestamp registers to calculate the scanline.
 767  */
 768 static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)
 769 {
 770         struct drm_vblank_crtc *vblank =
 771                 &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
 772         const struct drm_display_mode *mode = &vblank->hwmode;
 773         u32 vblank_start = mode->crtc_vblank_start;
 774         u32 vtotal = mode->crtc_vtotal;
 775         u32 scanline;
 776
 777         scanline = intel_crtc_scanlines_since_frame_timestamp(crtc);
 778         scanline = min(scanline, vtotal - 1);
 779         scanline = (scanline + vblank_start) % vtotal;
 780
 781         return scanline;
 782 }
 783
 784 /*
 785  * intel_de_read_fw(), only for fast reads of display block, no need for
 786  * forcewake etc.
 787  */
 788 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
 789 {
 790         struct drm_device *dev = crtc->base.dev;
 791         struct drm_i915_private *dev_priv = to_i915(dev);
 792         const struct drm_display_mode *mode;
 793         struct drm_vblank_crtc *vblank;
 794         enum pipe pipe = crtc->pipe;
 795         int position, vtotal;
 796
 797         if (!crtc->active)
 798                 return 0;
 799
 800         vblank = &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
 801         mode = &vblank->hwmode;
 802
 803         if (crtc->mode_flags & I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP)
 804                 return __intel_get_crtc_scanline_from_timestamp(crtc);
 805
 806         vtotal = mode->crtc_vtotal;
 807         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 808                 vtotal /= 2;
 809
 810         if (DISPLAY_VER(dev_priv) == 2)
 811                 position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
 812         else
 813                 position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
 814
 815         /*
 816          * On HSW, the DSL reg (0x70000) appears to return 0 if we
 817          * read it just before the start of vblank.  So try it again
 818          * so we don't accidentally end up spanning a vblank frame
 819          * increment, causing the pipe_update_end() code to squak at us.
 820          *
 821          * The nature of this problem means we can't simply check the ISR
 822          * bit and return the vblank start value; nor can we use the scanline
 823          * debug register in the transcoder as it appears to have the same
 824          * problem.  We may need to extend this to include other platforms,
 825          * but so far testing only shows the problem on HSW.
 826          */
 827         if (HAS_DDI(dev_priv) && !position) {
 828                 int i, temp;
 829
 830                 for (i = 0; i < 100; i++) {
 831                         udelay(1);
 832                         temp = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
 833                         if (temp != position) {
 834                                 position = temp;
 835                                 break;
 836                         }
 837                 }
 838         }
 839
 840         /*
 841          * See update_scanline_offset() for the details on the
 842          * scanline_offset adjustment.
 843          */
 844         return (position + crtc->scanline_offset) % vtotal;
 845 }
 846
 847 static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
 848                                      bool in_vblank_irq,
 849                                      int *vpos, int *hpos,
 850                                      ktime_t *stime, ktime_t *etime,
 851                                      const struct drm_display_mode *mode)
 852 {
 853         struct drm_device *dev = _crtc->dev;
 854         struct drm_i915_private *dev_priv = to_i915(dev);
 855         struct intel_crtc *crtc = to_intel_crtc(_crtc);
 856         enum pipe pipe = crtc->pipe;
 857         int position;
 858         int vbl_start, vbl_end, hsync_start, htotal, vtotal;
 859         unsigned long irqflags;
 860         bool use_scanline_counter = DISPLAY_VER(dev_priv) >= 5 ||
 861                 IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) == 2 ||
 862                 crtc->mode_flags & I915_MODE_FLAG_USE_SCANLINE_COUNTER;
 863
 864         if (drm_WARN_ON(&dev_priv->drm, !mode->crtc_clock)) {
 865                 drm_dbg(&dev_priv->drm,
 866                         "trying to get scanoutpos for disabled "
 867                         "pipe %c\n", pipe_name(pipe));
 868                 return false;
 869         }
 870
 871         htotal = mode->crtc_htotal;
 872         hsync_start = mode->crtc_hsync_start;
 873         vtotal = mode->crtc_vtotal;
 874         vbl_start = mode->crtc_vblank_start;
 875         vbl_end = mode->crtc_vblank_end;
 876
 877         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 878                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 879                 vbl_end /= 2;
 880                 vtotal /= 2;
 881         }
 882
 883         /*
 884          * Lock uncore.lock, as we will do multiple timing critical raw
 885          * register reads, potentially with preemption disabled, so the
 886          * following code must not block on uncore.lock.
 887          */
 888         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 889
 890         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 891
 892         /* Get optional system timestamp before query. */
 893         if (stime)
 894                 *stime = ktime_get();
 895
 896         if (crtc->mode_flags & I915_MODE_FLAG_VRR) {
 897                 int scanlines = intel_crtc_scanlines_since_frame_timestamp(crtc);
 898
 899                 position = __intel_get_crtc_scanline(crtc);
 900
 901                 /*
 902                  * Already exiting vblank? If so, shift our position
 903                  * so it looks like we're already apporaching the full
 904                  * vblank end. This should make the generated timestamp
 905                  * more or less match when the active portion will start.
 906                  */
 907                 if (position >= vbl_start && scanlines < position)
 908                         position = min(crtc->vmax_vblank_start + scanlines, vtotal - 1);
 909         } else if (use_scanline_counter) {
 910                 /* No obvious pixelcount register. Only query vertical
 911                  * scanout position from Display scan line register.
 912                  */
 913                 position = __intel_get_crtc_scanline(crtc);
 914         } else {
 915                 /* Have access to pixelcount since start of frame.
 916                  * We can split this into vertical and horizontal
 917                  * scanout position.
 918                  */
 919                 position = (intel_de_read_fw(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 920
 921                 /* convert to pixel counts */
 922                 vbl_start *= htotal;
 923                 vbl_end *= htotal;
 924                 vtotal *= htotal;
 925
 926                 /*
 927                  * In interlaced modes, the pixel counter counts all pixels,
 928                  * so one field will have htotal more pixels. In order to avoid
 929                  * the reported position from jumping backwards when the pixel
 930                  * counter is beyond the length of the shorter field, just
 931                  * clamp the position the length of the shorter field. This
 932                  * matches how the scanline counter based position works since
 933                  * the scanline counter doesn't count the two half lines.
 934                  */
 935                 if (position >= vtotal)
 936                         position = vtotal - 1;
 937
 938                 /*
 939                  * Start of vblank interrupt is triggered at start of hsync,
 940                  * just prior to the first active line of vblank. However we
 941                  * consider lines to start at the leading edge of horizontal
 942                  * active. So, should we get here before we've crossed into
 943                  * the horizontal active of the first line in vblank, we would
 944                  * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
 945                  * always add htotal-hsync_start to the current pixel position.
 946                  */
 947                 position = (position + htotal - hsync_start) % vtotal;
 948         }
 949
 950         /* Get optional system timestamp after query. */
 951         if (etime)
 952                 *etime = ktime_get();
 953
 954         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 955
 956         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 957
 958         /*
 959          * While in vblank, position will be negative
 960          * counting up towards 0 at vbl_end. And outside
 961          * vblank, position will be positive counting
 962          * up since vbl_end.
 963          */
 964         if (position >= vbl_start)
 965                 position -= vbl_end;
 966         else
 967                 position += vtotal - vbl_end;
 968
 969         if (use_scanline_counter) {
 970                 *vpos = position;
 971                 *hpos = 0;
 972         } else {
 973                 *vpos = position / htotal;
 974                 *hpos = position - (*vpos * htotal);
 975         }
 976
 977         return true;
 978 }
 979
 980 bool intel_crtc_get_vblank_timestamp(struct drm_crtc *crtc, int *max_error,
 981                                      ktime_t *vblank_time, bool in_vblank_irq)
 982 {
 983         return drm_crtc_vblank_helper_get_vblank_timestamp_internal(
 984                 crtc, max_error, vblank_time, in_vblank_irq,
 985                 i915_get_crtc_scanoutpos);
 986 }
 987
 988 int intel_get_crtc_scanline(struct intel_crtc *crtc)
 989 {
 990         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 991         unsigned long irqflags;
 992         int position;
 993
 994         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 995         position = __intel_get_crtc_scanline(crtc);
 996         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 997
 998         return position;
 999 }
1000
1001 /**
1002  * ivb_parity_work - Workqueue called when a parity error interrupt
1003  * occurred.
1004  * @work: workqueue struct
1005  *
1006  * Doesn't actually do anything except notify userspace. As a consequence of
1007  * this event, userspace should try to remap the bad rows since statistically
1008  * it is likely the same row is more likely to go bad again.
1009  */
1010 static void ivb_parity_work(struct work_struct *work)
1011 {
1012         struct drm_i915_private *dev_priv =
1013                 container_of(work, typeof(*dev_priv), l3_parity.error_work);
1014         struct intel_gt *gt = &dev_priv->gt;
1015         u32 error_status, row, bank, subbank;
1016         char *parity_event[6];
1017         u32 misccpctl;
1018         u8 slice = 0;
1019
1020         /* We must turn off DOP level clock gating to access the L3 registers.
1021          * In order to prevent a get/put style interface, acquire struct mutex
1022          * any time we access those registers.
1023          */
1024         mutex_lock(&dev_priv->drm.struct_mutex);
1025
1026         /* If we've screwed up tracking, just let the interrupt fire again */
1027         if (drm_WARN_ON(&dev_priv->drm, !dev_priv->l3_parity.which_slice))
1028                 goto out;
1029
1030         misccpctl = intel_uncore_read(&dev_priv->uncore, GEN7_MISCCPCTL);
1031         intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1032         intel_uncore_posting_read(&dev_priv->uncore, GEN7_MISCCPCTL);
1033
1034         while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1035                 i915_reg_t reg;
1036
1037                 slice--;
1038                 if (drm_WARN_ON_ONCE(&dev_priv->drm,
1039                                      slice >= NUM_L3_SLICES(dev_priv)))
1040                         break;
1041
1042                 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1043
1044                 reg = GEN7_L3CDERRST1(slice);
1045
1046                 error_status = intel_uncore_read(&dev_priv->uncore, reg);
1047                 row = GEN7_PARITY_ERROR_ROW(error_status);
1048                 bank = GEN7_PARITY_ERROR_BANK(error_status);
1049                 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1050
1051                 intel_uncore_write(&dev_priv->uncore, reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1052                 intel_uncore_posting_read(&dev_priv->uncore, reg);
1053
1054                 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1055                 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1056                 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1057                 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1058                 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1059                 parity_event[5] = NULL;
1060
1061                 kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj,
1062                                    KOBJ_CHANGE, parity_event);
1063
1064                 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1065                           slice, row, bank, subbank);
1066
1067                 kfree(parity_event[4]);
1068                 kfree(parity_event[3]);
1069                 kfree(parity_event[2]);
1070                 kfree(parity_event[1]);
1071         }
1072
1073         intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl);
1074
1075 out:
1076         drm_WARN_ON(&dev_priv->drm, dev_priv->l3_parity.which_slice);
1077         spin_lock_irq(&gt->irq_lock);
1078         gen5_gt_enable_irq(gt, GT_PARITY_ERROR(dev_priv));
1079         spin_unlock_irq(&gt->irq_lock);
1080
1081         mutex_unlock(&dev_priv->drm.struct_mutex);
1082 }
1083
1084 static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1085 {
1086         switch (pin) {
1087         case HPD_PORT_TC1:
1088         case HPD_PORT_TC2:
1089         case HPD_PORT_TC3:
1090         case HPD_PORT_TC4:
1091         case HPD_PORT_TC5:
1092         case HPD_PORT_TC6:
1093                 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(pin);
1094         default:
1095                 return false;
1096         }
1097 }
1098
1099 static bool bxt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1100 {
1101         switch (pin) {
1102         case HPD_PORT_A:
1103                 return val & PORTA_HOTPLUG_LONG_DETECT;
1104         case HPD_PORT_B:
1105                 return val & PORTB_HOTPLUG_LONG_DETECT;
1106         case HPD_PORT_C:
1107                 return val & PORTC_HOTPLUG_LONG_DETECT;
1108         default:
1109                 return false;
1110         }
1111 }
1112
1113 static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1114 {
1115         switch (pin) {
1116         case HPD_PORT_A:
1117         case HPD_PORT_B:
1118         case HPD_PORT_C:
1119         case HPD_PORT_D:
1120                 return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(pin);
1121         default:
1122                 return false;
1123         }
1124 }
1125
1126 static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1127 {
1128         switch (pin) {
1129         case HPD_PORT_TC1:
1130         case HPD_PORT_TC2:
1131         case HPD_PORT_TC3:
1132         case HPD_PORT_TC4:
1133         case HPD_PORT_TC5:
1134         case HPD_PORT_TC6:
1135                 return val & ICP_TC_HPD_LONG_DETECT(pin);
1136         default:
1137                 return false;
1138         }
1139 }
1140
1141 static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val)
1142 {
1143         switch (pin) {
1144         case HPD_PORT_E:
1145                 return val & PORTE_HOTPLUG_LONG_DETECT;
1146         default:
1147                 return false;
1148         }
1149 }
1150
1151 static bool spt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1152 {
1153         switch (pin) {
1154         case HPD_PORT_A:
1155                 return val & PORTA_HOTPLUG_LONG_DETECT;
1156         case HPD_PORT_B:
1157                 return val & PORTB_HOTPLUG_LONG_DETECT;
1158         case HPD_PORT_C:
1159                 return val & PORTC_HOTPLUG_LONG_DETECT;
1160         case HPD_PORT_D:
1161                 return val & PORTD_HOTPLUG_LONG_DETECT;
1162         default:
1163                 return false;
1164         }
1165 }
1166
1167 static bool ilk_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1168 {
1169         switch (pin) {
1170         case HPD_PORT_A:
1171                 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
1172         default:
1173                 return false;
1174         }
1175 }
1176
1177 static bool pch_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1178 {
1179         switch (pin) {
1180         case HPD_PORT_B:
1181                 return val & PORTB_HOTPLUG_LONG_DETECT;
1182         case HPD_PORT_C:
1183                 return val & PORTC_HOTPLUG_LONG_DETECT;
1184         case HPD_PORT_D:
1185                 return val & PORTD_HOTPLUG_LONG_DETECT;
1186         default:
1187                 return false;
1188         }
1189 }
1190
1191 static bool i9xx_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1192 {
1193         switch (pin) {
1194         case HPD_PORT_B:
1195                 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1196         case HPD_PORT_C:
1197                 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1198         case HPD_PORT_D:
1199                 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1200         default:
1201                 return false;
1202         }
1203 }
1204
1205 /*
1206  * Get a bit mask of pins that have triggered, and which ones may be long.
1207  * This can be called multiple times with the same masks to accumulate
1208  * hotplug detection results from several registers.
1209  *
1210  * Note that the caller is expected to zero out the masks initially.
1211  */
1212 static void intel_get_hpd_pins(struct drm_i915_private *dev_priv,
1213                                u32 *pin_mask, u32 *long_mask,
1214                                u32 hotplug_trigger, u32 dig_hotplug_reg,
1215                                const u32 hpd[HPD_NUM_PINS],
1216                                bool long_pulse_detect(enum hpd_pin pin, u32 val))
1217 {
1218         enum hpd_pin pin;
1219
1220         BUILD_BUG_ON(BITS_PER_TYPE(*pin_mask) < HPD_NUM_PINS);
1221
1222         for_each_hpd_pin(pin) {
1223                 if ((hpd[pin] & hotplug_trigger) == 0)
1224                         continue;
1225
1226                 *pin_mask |= BIT(pin);
1227
1228                 if (long_pulse_detect(pin, dig_hotplug_reg))
1229                         *long_mask |= BIT(pin);
1230         }
1231
1232         drm_dbg(&dev_priv->drm,
1233                 "hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x, long 0x%08x\n",
1234                 hotplug_trigger, dig_hotplug_reg, *pin_mask, *long_mask);
1235
1236 }
1237
1238 static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
1239                                   const u32 hpd[HPD_NUM_PINS])
1240 {
1241         struct intel_encoder *encoder;
1242         u32 enabled_irqs = 0;
1243
1244         for_each_intel_encoder(&dev_priv->drm, encoder)
1245                 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
1246                         enabled_irqs |= hpd[encoder->hpd_pin];
1247
1248         return enabled_irqs;
1249 }
1250
1251 static u32 intel_hpd_hotplug_irqs(struct drm_i915_private *dev_priv,
1252                                   const u32 hpd[HPD_NUM_PINS])
1253 {
1254         struct intel_encoder *encoder;
1255         u32 hotplug_irqs = 0;
1256
1257         for_each_intel_encoder(&dev_priv->drm, encoder)
1258                 hotplug_irqs |= hpd[encoder->hpd_pin];
1259
1260         return hotplug_irqs;
1261 }
1262
1263 static u32 intel_hpd_hotplug_enables(struct drm_i915_private *i915,
1264                                      hotplug_enables_func hotplug_enables)
1265 {
1266         struct intel_encoder *encoder;
1267         u32 hotplug = 0;
1268
1269         for_each_intel_encoder(&i915->drm, encoder)
1270                 hotplug |= hotplug_enables(i915, encoder->hpd_pin);
1271
1272         return hotplug;
1273 }
1274
1275 static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
1276 {
1277         wake_up_all(&dev_priv->gmbus_wait_queue);
1278 }
1279
1280 static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
1281 {
1282         wake_up_all(&dev_priv->gmbus_wait_queue);
1283 }
1284
1285 #if defined(CONFIG_DEBUG_FS)
1286 static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1287                                          enum pipe pipe,
1288                                          u32 crc0, u32 crc1,
1289                                          u32 crc2, u32 crc3,
1290                                          u32 crc4)
1291 {
1292         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1293         struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
1294         u32 crcs[5] = { crc0, crc1, crc2, crc3, crc4 };
1295
1296         trace_intel_pipe_crc(crtc, crcs);
1297
1298         spin_lock(&pipe_crc->lock);
1299         /*
1300          * For some not yet identified reason, the first CRC is
1301          * bonkers. So let's just wait for the next vblank and read
1302          * out the buggy result.
1303          *
1304          * On GEN8+ sometimes the second CRC is bonkers as well, so
1305          * don't trust that one either.
1306          */
1307         if (pipe_crc->skipped <= 0 ||
1308             (DISPLAY_VER(dev_priv) >= 8 && pipe_crc->skipped == 1)) {
1309                 pipe_crc->skipped++;
1310                 spin_unlock(&pipe_crc->lock);
1311                 return;
1312         }
1313         spin_unlock(&pipe_crc->lock);
1314
1315         drm_crtc_add_crc_entry(&crtc->base, true,
1316                                 drm_crtc_accurate_vblank_count(&crtc->base),
1317                                 crcs);
1318 }
1319 #else
1320 static inline void
1321 display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1322                              enum pipe pipe,
1323                              u32 crc0, u32 crc1,
1324                              u32 crc2, u32 crc3,
1325                              u32 crc4) {}
1326 #endif
1327
1328 static void flip_done_handler(struct drm_i915_private *i915,
1329                               enum pipe pipe)
1330 {
1331         struct intel_crtc *crtc = intel_get_crtc_for_pipe(i915, pipe);
1332         struct drm_crtc_state *crtc_state = crtc->base.state;
1333         struct drm_pending_vblank_event *e = crtc_state->event;
1334         struct drm_device *dev = &i915->drm;
1335         unsigned long irqflags;
1336
1337         spin_lock_irqsave(&dev->event_lock, irqflags);
1338
1339         crtc_state->event = NULL;
1340
1341         drm_crtc_send_vblank_event(&crtc->base, e);
1342
1343         spin_unlock_irqrestore(&dev->event_lock, irqflags);
1344 }
1345
1346 static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1347                                      enum pipe pipe)
1348 {
1349         display_pipe_crc_irq_handler(dev_priv, pipe,
1350                                      intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)),
1351                                      0, 0, 0, 0);
1352 }
1353
1354 static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1355                                      enum pipe pipe)
1356 {
1357         display_pipe_crc_irq_handler(dev_priv, pipe,
1358                                      intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)),
1359                                      intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_2_IVB(pipe)),
1360                                      intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_3_IVB(pipe)),
1361                                      intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_4_IVB(pipe)),
1362                                      intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_5_IVB(pipe)));
1363 }
1364
1365 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1366                                       enum pipe pipe)
1367 {
1368         u32 res1, res2;
1369
1370         if (DISPLAY_VER(dev_priv) >= 3)
1371                 res1 = intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RES1_I915(pipe));
1372         else
1373                 res1 = 0;
1374
1375         if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
1376                 res2 = intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RES2_G4X(pipe));
1377         else
1378                 res2 = 0;
1379
1380         display_pipe_crc_irq_handler(dev_priv, pipe,
1381                                      intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RED(pipe)),
1382                                      intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_GREEN(pipe)),
1383                                      intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_BLUE(pipe)),
1384                                      res1, res2);
1385 }
1386
1387 static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
1388 {
1389         enum pipe pipe;
1390
1391         for_each_pipe(dev_priv, pipe) {
1392                 intel_uncore_write(&dev_priv->uncore, PIPESTAT(pipe),
1393                            PIPESTAT_INT_STATUS_MASK |
1394                            PIPE_FIFO_UNDERRUN_STATUS);
1395
1396                 dev_priv->pipestat_irq_mask[pipe] = 0;
1397         }
1398 }
1399
1400 static void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,
1401                                   u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1402 {
1403         enum pipe pipe;
1404
1405         spin_lock(&dev_priv->irq_lock);
1406
1407         if (!dev_priv->display_irqs_enabled) {
1408                 spin_unlock(&dev_priv->irq_lock);
1409                 return;
1410         }
1411
1412         for_each_pipe(dev_priv, pipe) {
1413                 i915_reg_t reg;
1414                 u32 status_mask, enable_mask, iir_bit = 0;
1415
1416                 /*
1417                  * PIPESTAT bits get signalled even when the interrupt is
1418                  * disabled with the mask bits, and some of the status bits do
1419                  * not generate interrupts at all (like the underrun bit). Hence
1420                  * we need to be careful that we only handle what we want to
1421                  * handle.
1422                  */
1423
1424                 /* fifo underruns are filterered in the underrun handler. */
1425                 status_mask = PIPE_FIFO_UNDERRUN_STATUS;
1426
1427                 switch (pipe) {
1428                 default:
1429                 case PIPE_A:
1430                         iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1431                         break;
1432                 case PIPE_B:
1433                         iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1434                         break;
1435                 case PIPE_C:
1436                         iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1437                         break;
1438                 }
1439                 if (iir & iir_bit)
1440                         status_mask |= dev_priv->pipestat_irq_mask[pipe];
1441
1442                 if (!status_mask)
1443                         continue;
1444
1445                 reg = PIPESTAT(pipe);
1446                 pipe_stats[pipe] = intel_uncore_read(&dev_priv->uncore, reg) & status_mask;
1447                 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
1448
1449                 /*
1450                  * Clear the PIPE*STAT regs before the IIR
1451                  *
1452                  * Toggle the enable bits to make sure we get an
1453                  * edge in the ISR pipe event bit if we don't clear
1454                  * all the enabled status bits. Otherwise the edge
1455                  * triggered IIR on i965/g4x wouldn't notice that
1456                  * an interrupt is still pending.
1457                  */
1458                 if (pipe_stats[pipe]) {
1459                         intel_uncore_write(&dev_priv->uncore, reg, pipe_stats[pipe]);
1460                         intel_uncore_write(&dev_priv->uncore, reg, enable_mask);
1461                 }
1462         }
1463         spin_unlock(&dev_priv->irq_lock);
1464 }
1465
1466 static void i8xx_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1467                                       u16 iir, u32 pipe_stats[I915_MAX_PIPES])
1468 {
1469         enum pipe pipe;
1470
1471         for_each_pipe(dev_priv, pipe) {
1472                 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1473                         intel_handle_vblank(dev_priv, pipe);
1474
1475                 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1476                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1477
1478                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1479                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1480         }
1481 }
1482
1483 static void i915_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1484                                       u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1485 {
1486         bool blc_event = false;
1487         enum pipe pipe;
1488
1489         for_each_pipe(dev_priv, pipe) {
1490                 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1491                         intel_handle_vblank(dev_priv, pipe);
1492
1493                 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1494                         blc_event = true;
1495
1496                 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1497                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1498
1499                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1500                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1501         }
1502
1503         if (blc_event || (iir & I915_ASLE_INTERRUPT))
1504                 intel_opregion_asle_intr(dev_priv);
1505 }
1506
1507 static void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1508                                       u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1509 {
1510         bool blc_event = false;
1511         enum pipe pipe;
1512
1513         for_each_pipe(dev_priv, pipe) {
1514                 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1515                         intel_handle_vblank(dev_priv, pipe);
1516
1517                 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1518                         blc_event = true;
1519
1520                 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1521                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1522
1523                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1524                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1525         }
1526
1527         if (blc_event || (iir & I915_ASLE_INTERRUPT))
1528                 intel_opregion_asle_intr(dev_priv);
1529
1530         if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1531                 gmbus_irq_handler(dev_priv);
1532 }
1533
1534 static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1535                                             u32 pipe_stats[I915_MAX_PIPES])
1536 {
1537         enum pipe pipe;
1538
1539         for_each_pipe(dev_priv, pipe) {
1540                 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1541                         intel_handle_vblank(dev_priv, pipe);
1542
1543                 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV)
1544                         flip_done_handler(dev_priv, pipe);
1545
1546                 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1547                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1548
1549                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1550                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1551         }
1552
1553         if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1554                 gmbus_irq_handler(dev_priv);
1555 }
1556
1557 static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
1558 {
1559         u32 hotplug_status = 0, hotplug_status_mask;
1560         int i;
1561
1562         if (IS_G4X(dev_priv) ||
1563             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1564                 hotplug_status_mask = HOTPLUG_INT_STATUS_G4X |
1565                         DP_AUX_CHANNEL_MASK_INT_STATUS_G4X;
1566         else
1567                 hotplug_status_mask = HOTPLUG_INT_STATUS_I915;
1568
1569         /*
1570          * We absolutely have to clear all the pending interrupt
1571          * bits in PORT_HOTPLUG_STAT. Otherwise the ISR port
1572          * interrupt bit won't have an edge, and the i965/g4x
1573          * edge triggered IIR will not notice that an interrupt
1574          * is still pending. We can't use PORT_HOTPLUG_EN to
1575          * guarantee the edge as the act of toggling the enable
1576          * bits can itself generate a new hotplug interrupt :(
1577          */
1578         for (i = 0; i < 10; i++) {
1579                 u32 tmp = intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT) & hotplug_status_mask;
1580
1581                 if (tmp == 0)
1582                         return hotplug_status;
1583
1584                 hotplug_status |= tmp;
1585                 intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_STAT, hotplug_status);
1586         }
1587
1588         drm_WARN_ONCE(&dev_priv->drm, 1,
1589                       "PORT_HOTPLUG_STAT did not clear (0x%08x)\n",
1590                       intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT));
1591
1592         return hotplug_status;
1593 }
1594
1595 static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1596                                  u32 hotplug_status)
1597 {
1598         u32 pin_mask = 0, long_mask = 0;
1599         u32 hotplug_trigger;
1600
1601         if (IS_G4X(dev_priv) ||
1602             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1603                 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1604         else
1605                 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1606
1607         if (hotplug_trigger) {
1608                 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1609                                    hotplug_trigger, hotplug_trigger,
1610                                    dev_priv->hotplug.hpd,
1611                                    i9xx_port_hotplug_long_detect);
1612
1613                 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1614         }
1615
1616         if ((IS_G4X(dev_priv) ||
1617              IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1618             hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1619                 dp_aux_irq_handler(dev_priv);
1620 }
1621
1622 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1623 {
1624         struct drm_i915_private *dev_priv = arg;
1625         irqreturn_t ret = IRQ_NONE;
1626
1627         if (!intel_irqs_enabled(dev_priv))
1628                 return IRQ_NONE;
1629
1630         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1631         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1632
1633         do {
1634                 u32 iir, gt_iir, pm_iir;
1635                 u32 pipe_stats[I915_MAX_PIPES] = {};
1636                 u32 hotplug_status = 0;
1637                 u32 ier = 0;
1638
1639                 gt_iir = intel_uncore_read(&dev_priv->uncore, GTIIR);
1640                 pm_iir = intel_uncore_read(&dev_priv->uncore, GEN6_PMIIR);
1641                 iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);
1642
1643                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1644                         break;
1645
1646                 ret = IRQ_HANDLED;
1647
1648                 /*
1649                  * Theory on interrupt generation, based on empirical evidence:
1650                  *
1651                  * x = ((VLV_IIR & VLV_IER) ||
1652                  *      (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
1653                  *       (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
1654                  *
1655                  * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1656                  * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
1657                  * guarantee the CPU interrupt will be raised again even if we
1658                  * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
1659                  * bits this time around.
1660                  */
1661                 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, 0);
1662                 ier = intel_uncore_read(&dev_priv->uncore, VLV_IER);
1663                 intel_uncore_write(&dev_priv->uncore, VLV_IER, 0);
1664
1665                 if (gt_iir)
1666                         intel_uncore_write(&dev_priv->uncore, GTIIR, gt_iir);
1667                 if (pm_iir)
1668                         intel_uncore_write(&dev_priv->uncore, GEN6_PMIIR, pm_iir);
1669
1670                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1671                         hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1672
1673                 /* Call regardless, as some status bits might not be
1674                  * signalled in iir */
1675                 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1676
1677                 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
1678                            I915_LPE_PIPE_B_INTERRUPT))
1679                         intel_lpe_audio_irq_handler(dev_priv);
1680
1681                 /*
1682                  * VLV_IIR is single buffered, and reflects the level
1683                  * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1684                  */
1685                 if (iir)
1686                         intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir);
1687
1688                 intel_uncore_write(&dev_priv->uncore, VLV_IER, ier);
1689                 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1690
1691                 if (gt_iir)
1692                         gen6_gt_irq_handler(&dev_priv->gt, gt_iir);
1693                 if (pm_iir)
1694                         gen6_rps_irq_handler(&dev_priv->gt.rps, pm_iir);
1695
1696                 if (hotplug_status)
1697                         i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1698
1699                 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1700         } while (0);
1701
1702         pmu_irq_stats(dev_priv, ret);
1703
1704         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1705
1706         return ret;
1707 }
1708
1709 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1710 {
1711         struct drm_i915_private *dev_priv = arg;
1712         irqreturn_t ret = IRQ_NONE;
1713
1714         if (!intel_irqs_enabled(dev_priv))
1715                 return IRQ_NONE;
1716
1717         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1718         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1719
1720         do {
1721                 u32 master_ctl, iir;
1722                 u32 pipe_stats[I915_MAX_PIPES] = {};
1723                 u32 hotplug_status = 0;
1724                 u32 ier = 0;
1725
1726                 master_ctl = intel_uncore_read(&dev_priv->uncore, GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1727                 iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);
1728
1729                 if (master_ctl == 0 && iir == 0)
1730                         break;
1731
1732                 ret = IRQ_HANDLED;
1733
1734                 /*
1735                  * Theory on interrupt generation, based on empirical evidence:
1736                  *
1737                  * x = ((VLV_IIR & VLV_IER) ||
1738                  *      ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
1739                  *       (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
1740                  *
1741                  * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1742                  * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
1743                  * guarantee the CPU interrupt will be raised again even if we
1744                  * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
1745                  * bits this time around.
1746                  */
1747                 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, 0);
1748                 ier = intel_uncore_read(&dev_priv->uncore, VLV_IER);
1749                 intel_uncore_write(&dev_priv->uncore, VLV_IER, 0);
1750
1751                 gen8_gt_irq_handler(&dev_priv->gt, master_ctl);
1752
1753                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1754                         hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1755
1756                 /* Call regardless, as some status bits might not be
1757                  * signalled in iir */
1758                 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1759
1760                 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
1761                            I915_LPE_PIPE_B_INTERRUPT |
1762                            I915_LPE_PIPE_C_INTERRUPT))
1763                         intel_lpe_audio_irq_handler(dev_priv);
1764
1765                 /*
1766                  * VLV_IIR is single buffered, and reflects the level
1767                  * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1768                  */
1769                 if (iir)
1770                         intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir);
1771
1772                 intel_uncore_write(&dev_priv->uncore, VLV_IER, ier);
1773                 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
1774
1775                 if (hotplug_status)
1776                         i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1777
1778                 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1779         } while (0);
1780
1781         pmu_irq_stats(dev_priv, ret);
1782
1783         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1784
1785         return ret;
1786 }
1787
1788 static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1789                                 u32 hotplug_trigger)
1790 {
1791         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
1792
1793         /*
1794          * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
1795          * unless we touch the hotplug register, even if hotplug_trigger is
1796          * zero. Not acking leads to "The master control interrupt lied (SDE)!"
1797          * errors.
1798          */
1799         dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);
1800         if (!hotplug_trigger) {
1801                 u32 mask = PORTA_HOTPLUG_STATUS_MASK |
1802                         PORTD_HOTPLUG_STATUS_MASK |
1803                         PORTC_HOTPLUG_STATUS_MASK |
1804                         PORTB_HOTPLUG_STATUS_MASK;
1805                 dig_hotplug_reg &= ~mask;
1806         }
1807
1808         intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, dig_hotplug_reg);
1809         if (!hotplug_trigger)
1810                 return;
1811
1812         intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1813                            hotplug_trigger, dig_hotplug_reg,
1814                            dev_priv->hotplug.pch_hpd,
1815                            pch_port_hotplug_long_detect);
1816
1817         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1818 }
1819
1820 static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1821 {
1822         enum pipe pipe;
1823         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1824
1825         ibx_hpd_irq_handler(dev_priv, hotplug_trigger);
1826
1827         if (pch_iir & SDE_AUDIO_POWER_MASK) {
1828                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1829                                SDE_AUDIO_POWER_SHIFT);
1830                 drm_dbg(&dev_priv->drm, "PCH audio power change on port %d\n",
1831                         port_name(port));
1832         }
1833
1834         if (pch_iir & SDE_AUX_MASK)
1835                 dp_aux_irq_handler(dev_priv);
1836
1837         if (pch_iir & SDE_GMBUS)
1838                 gmbus_irq_handler(dev_priv);
1839
1840         if (pch_iir & SDE_AUDIO_HDCP_MASK)
1841                 drm_dbg(&dev_priv->drm, "PCH HDCP audio interrupt\n");
1842
1843         if (pch_iir & SDE_AUDIO_TRANS_MASK)
1844                 drm_dbg(&dev_priv->drm, "PCH transcoder audio interrupt\n");
1845
1846         if (pch_iir & SDE_POISON)
1847                 drm_err(&dev_priv->drm, "PCH poison interrupt\n");
1848
1849         if (pch_iir & SDE_FDI_MASK) {
1850                 for_each_pipe(dev_priv, pipe)
1851                         drm_dbg(&dev_priv->drm, "  pipe %c FDI IIR: 0x%08x\n",
1852                                 pipe_name(pipe),
1853                                 intel_uncore_read(&dev_priv->uncore, FDI_RX_IIR(pipe)));
1854         }
1855
1856         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1857                 drm_dbg(&dev_priv->drm, "PCH transcoder CRC done interrupt\n");
1858
1859         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1860                 drm_dbg(&dev_priv->drm,
1861                         "PCH transcoder CRC error interrupt\n");
1862
1863         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1864                 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A);
1865
1866         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1867                 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B);
1868 }
1869
1870 static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
1871 {
1872         u32 err_int = intel_uncore_read(&dev_priv->uncore, GEN7_ERR_INT);
1873         enum pipe pipe;
1874
1875         if (err_int & ERR_INT_POISON)
1876                 drm_err(&dev_priv->drm, "Poison interrupt\n");
1877
1878         for_each_pipe(dev_priv, pipe) {
1879                 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
1880                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1881
1882                 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1883                         if (IS_IVYBRIDGE(dev_priv))
1884                                 ivb_pipe_crc_irq_handler(dev_priv, pipe);
1885                         else
1886                                 hsw_pipe_crc_irq_handler(dev_priv, pipe);
1887                 }
1888         }
1889
1890         intel_uncore_write(&dev_priv->uncore, GEN7_ERR_INT, err_int);
1891 }
1892
1893 static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
1894 {
1895         u32 serr_int = intel_uncore_read(&dev_priv->uncore, SERR_INT);
1896         enum pipe pipe;
1897
1898         if (serr_int & SERR_INT_POISON)
1899                 drm_err(&dev_priv->drm, "PCH poison interrupt\n");
1900
1901         for_each_pipe(dev_priv, pipe)
1902                 if (serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pipe))
1903                         intel_pch_fifo_underrun_irq_handler(dev_priv, pipe);
1904
1905         intel_uncore_write(&dev_priv->uncore, SERR_INT, serr_int);
1906 }
1907
1908 static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1909 {
1910         enum pipe pipe;
1911         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1912
1913         ibx_hpd_irq_handler(dev_priv, hotplug_trigger);
1914
1915         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1916                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1917                                SDE_AUDIO_POWER_SHIFT_CPT);
1918                 drm_dbg(&dev_priv->drm, "PCH audio power change on port %c\n",
1919                         port_name(port));
1920         }
1921
1922         if (pch_iir & SDE_AUX_MASK_CPT)
1923                 dp_aux_irq_handler(dev_priv);
1924
1925         if (pch_iir & SDE_GMBUS_CPT)
1926                 gmbus_irq_handler(dev_priv);
1927
1928         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1929                 drm_dbg(&dev_priv->drm, "Audio CP request interrupt\n");
1930
1931         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1932                 drm_dbg(&dev_priv->drm, "Audio CP change interrupt\n");
1933
1934         if (pch_iir & SDE_FDI_MASK_CPT) {
1935                 for_each_pipe(dev_priv, pipe)
1936                         drm_dbg(&dev_priv->drm, "  pipe %c FDI IIR: 0x%08x\n",
1937                                 pipe_name(pipe),
1938                                 intel_uncore_read(&dev_priv->uncore, FDI_RX_IIR(pipe)));
1939         }
1940
1941         if (pch_iir & SDE_ERROR_CPT)
1942                 cpt_serr_int_handler(dev_priv);
1943 }
1944
1945 static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1946 {
1947         u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_HOTPLUG_MASK_ICP;
1948         u32 tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_MASK_ICP;
1949         u32 pin_mask = 0, long_mask = 0;
1950
1951         if (ddi_hotplug_trigger) {
1952                 u32 dig_hotplug_reg;
1953
1954                 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_DDI);
1955                 intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_DDI, dig_hotplug_reg);
1956
1957                 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1958                                    ddi_hotplug_trigger, dig_hotplug_reg,
1959                                    dev_priv->hotplug.pch_hpd,
1960                                    icp_ddi_port_hotplug_long_detect);
1961         }
1962
1963         if (tc_hotplug_trigger) {
1964                 u32 dig_hotplug_reg;
1965
1966                 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_TC);
1967                 intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_TC, dig_hotplug_reg);
1968
1969                 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1970                                    tc_hotplug_trigger, dig_hotplug_reg,
1971                                    dev_priv->hotplug.pch_hpd,
1972                                    icp_tc_port_hotplug_long_detect);
1973         }
1974
1975         if (pin_mask)
1976                 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1977
1978         if (pch_iir & SDE_GMBUS_ICP)
1979                 gmbus_irq_handler(dev_priv);
1980 }
1981
1982 static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1983 {
1984         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
1985                 ~SDE_PORTE_HOTPLUG_SPT;
1986         u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
1987         u32 pin_mask = 0, long_mask = 0;
1988
1989         if (hotplug_trigger) {
1990                 u32 dig_hotplug_reg;
1991
1992                 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);
1993                 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, dig_hotplug_reg);
1994
1995                 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1996                                    hotplug_trigger, dig_hotplug_reg,
1997                                    dev_priv->hotplug.pch_hpd,
1998                                    spt_port_hotplug_long_detect);
1999         }
2000
2001         if (hotplug2_trigger) {
2002                 u32 dig_hotplug_reg;
2003
2004                 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG2);
2005                 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG2, dig_hotplug_reg);
2006
2007                 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2008                                    hotplug2_trigger, dig_hotplug_reg,
2009                                    dev_priv->hotplug.pch_hpd,
2010                                    spt_port_hotplug2_long_detect);
2011         }
2012
2013         if (pin_mask)
2014                 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2015
2016         if (pch_iir & SDE_GMBUS_CPT)
2017                 gmbus_irq_handler(dev_priv);
2018 }
2019
2020 static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
2021                                 u32 hotplug_trigger)
2022 {
2023         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2024
2025         dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL);
2026         intel_uncore_write(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
2027
2028         intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2029                            hotplug_trigger, dig_hotplug_reg,
2030                            dev_priv->hotplug.hpd,
2031                            ilk_port_hotplug_long_detect);
2032
2033         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2034 }
2035
2036 static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
2037                                     u32 de_iir)
2038 {
2039         enum pipe pipe;
2040         u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
2041
2042         if (hotplug_trigger)
2043                 ilk_hpd_irq_handler(dev_priv, hotplug_trigger);
2044
2045         if (de_iir & DE_AUX_CHANNEL_A)
2046                 dp_aux_irq_handler(dev_priv);
2047
2048         if (de_iir & DE_GSE)
2049                 intel_opregion_asle_intr(dev_priv);
2050
2051         if (de_iir & DE_POISON)
2052                 drm_err(&dev_priv->drm, "Poison interrupt\n");
2053
2054         for_each_pipe(dev_priv, pipe) {
2055                 if (de_iir & DE_PIPE_VBLANK(pipe))
2056                         intel_handle_vblank(dev_priv, pipe);
2057
2058                 if (de_iir & DE_PLANE_FLIP_DONE(pipe))
2059                         flip_done_handler(dev_priv, pipe);
2060
2061                 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2062                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2063
2064                 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2065                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2066         }
2067
2068         /* check event from PCH */
2069         if (de_iir & DE_PCH_EVENT) {
2070                 u32 pch_iir = intel_uncore_read(&dev_priv->uncore, SDEIIR);
2071
2072                 if (HAS_PCH_CPT(dev_priv))
2073                         cpt_irq_handler(dev_priv, pch_iir);
2074                 else
2075                         ibx_irq_handler(dev_priv, pch_iir);
2076
2077                 /* should clear PCH hotplug event before clear CPU irq */
2078                 intel_uncore_write(&dev_priv->uncore, SDEIIR, pch_iir);
2079         }
2080
2081         if (DISPLAY_VER(dev_priv) == 5 && de_iir & DE_PCU_EVENT)
2082                 gen5_rps_irq_handler(&dev_priv->gt.rps);
2083 }
2084
2085 static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
2086                                     u32 de_iir)
2087 {
2088         enum pipe pipe;
2089         u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2090
2091         if (hotplug_trigger)
2092                 ilk_hpd_irq_handler(dev_priv, hotplug_trigger);
2093
2094         if (de_iir & DE_ERR_INT_IVB)
2095                 ivb_err_int_handler(dev_priv);
2096
2097         if (de_iir & DE_EDP_PSR_INT_HSW) {
2098                 struct intel_encoder *encoder;
2099
2100                 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
2101                         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2102
2103                         u32 psr_iir = intel_uncore_read(&dev_priv->uncore,
2104                                                         EDP_PSR_IIR);
2105
2106                         intel_psr_irq_handler(intel_dp, psr_iir);
2107                         intel_uncore_write(&dev_priv->uncore,
2108                                            EDP_PSR_IIR, psr_iir);
2109                         break;
2110                 }
2111         }
2112
2113         if (de_iir & DE_AUX_CHANNEL_A_IVB)
2114                 dp_aux_irq_handler(dev_priv);
2115
2116         if (de_iir & DE_GSE_IVB)
2117                 intel_opregion_asle_intr(dev_priv);
2118
2119         for_each_pipe(dev_priv, pipe) {
2120                 if (de_iir & DE_PIPE_VBLANK_IVB(pipe))
2121                         intel_handle_vblank(dev_priv, pipe);
2122
2123                 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe))
2124                         flip_done_handler(dev_priv, pipe);
2125         }
2126
2127         /* check event from PCH */
2128         if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
2129                 u32 pch_iir = intel_uncore_read(&dev_priv->uncore, SDEIIR);
2130
2131                 cpt_irq_handler(dev_priv, pch_iir);
2132
2133                 /* clear PCH hotplug event before clear CPU irq */
2134                 intel_uncore_write(&dev_priv->uncore, SDEIIR, pch_iir);
2135         }
2136 }
2137
2138 /*
2139  * To handle irqs with the minimum potential races with fresh interrupts, we:
2140  * 1 - Disable Master Interrupt Control.
2141  * 2 - Find the source(s) of the interrupt.
2142  * 3 - Clear the Interrupt Identity bits (IIR).
2143  * 4 - Process the interrupt(s) that had bits set in the IIRs.
2144  * 5 - Re-enable Master Interrupt Control.
2145  */
2146 static irqreturn_t ilk_irq_handler(int irq, void *arg)
2147 {
2148         struct drm_i915_private *i915 = arg;
2149         void __iomem * const regs = i915->uncore.regs;
2150         u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2151         irqreturn_t ret = IRQ_NONE;
2152
2153         if (unlikely(!intel_irqs_enabled(i915)))
2154                 return IRQ_NONE;
2155
2156         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2157         disable_rpm_wakeref_asserts(&i915->runtime_pm);
2158
2159         /* disable master interrupt before clearing iir  */
2160         de_ier = raw_reg_read(regs, DEIER);
2161         raw_reg_write(regs, DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2162
2163         /* Disable south interrupts. We'll only write to SDEIIR once, so further
2164          * interrupts will will be stored on its back queue, and then we'll be
2165          * able to process them after we restore SDEIER (as soon as we restore
2166          * it, we'll get an interrupt if SDEIIR still has something to process
2167          * due to its back queue). */
2168         if (!HAS_PCH_NOP(i915)) {
2169                 sde_ier = raw_reg_read(regs, SDEIER);
2170                 raw_reg_write(regs, SDEIER, 0);
2171         }
2172
2173         /* Find, clear, then process each source of interrupt */
2174
2175         gt_iir = raw_reg_read(regs, GTIIR);
2176         if (gt_iir) {
2177                 raw_reg_write(regs, GTIIR, gt_iir);
2178                 if (GRAPHICS_VER(i915) >= 6)
2179                         gen6_gt_irq_handler(&i915->gt, gt_iir);
2180                 else
2181                         gen5_gt_irq_handler(&i915->gt, gt_iir);
2182                 ret = IRQ_HANDLED;
2183         }
2184
2185         de_iir = raw_reg_read(regs, DEIIR);
2186         if (de_iir) {
2187                 raw_reg_write(regs, DEIIR, de_iir);
2188                 if (DISPLAY_VER(i915) >= 7)
2189                         ivb_display_irq_handler(i915, de_iir);
2190                 else
2191                         ilk_display_irq_handler(i915, de_iir);
2192                 ret = IRQ_HANDLED;
2193         }
2194
2195         if (GRAPHICS_VER(i915) >= 6) {
2196                 u32 pm_iir = raw_reg_read(regs, GEN6_PMIIR);
2197                 if (pm_iir) {
2198                         raw_reg_write(regs, GEN6_PMIIR, pm_iir);
2199                         gen6_rps_irq_handler(&i915->gt.rps, pm_iir);
2200                         ret = IRQ_HANDLED;
2201                 }
2202         }
2203
2204         raw_reg_write(regs, DEIER, de_ier);
2205         if (sde_ier)
2206                 raw_reg_write(regs, SDEIER, sde_ier);
2207
2208         pmu_irq_stats(i915, ret);
2209
2210         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2211         enable_rpm_wakeref_asserts(&i915->runtime_pm);
2212
2213         return ret;
2214 }
2215
2216 static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
2217                                 u32 hotplug_trigger)
2218 {
2219         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2220
2221         dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);
2222         intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, dig_hotplug_reg);
2223
2224         intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2225                            hotplug_trigger, dig_hotplug_reg,
2226                            dev_priv->hotplug.hpd,
2227                            bxt_port_hotplug_long_detect);
2228
2229         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2230 }
2231
2232 static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
2233 {
2234         u32 pin_mask = 0, long_mask = 0;
2235         u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK;
2236         u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK;
2237
2238         if (trigger_tc) {
2239                 u32 dig_hotplug_reg;
2240
2241                 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL);
2242                 intel_uncore_write(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL, dig_hotplug_reg);
2243
2244                 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2245                                    trigger_tc, dig_hotplug_reg,
2246                                    dev_priv->hotplug.hpd,
2247                                    gen11_port_hotplug_long_detect);
2248         }
2249
2250         if (trigger_tbt) {
2251                 u32 dig_hotplug_reg;
2252
2253                 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL);
2254                 intel_uncore_write(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL, dig_hotplug_reg);
2255
2256                 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2257                                    trigger_tbt, dig_hotplug_reg,
2258                                    dev_priv->hotplug.hpd,
2259                                    gen11_port_hotplug_long_detect);
2260         }
2261
2262         if (pin_mask)
2263                 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2264         else
2265                 drm_err(&dev_priv->drm,
2266                         "Unexpected DE HPD interrupt 0x%08x\n", iir);
2267 }
2268
2269 static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
2270 {
2271         u32 mask;
2272
2273         if (DISPLAY_VER(dev_priv) >= 13)
2274                 return TGL_DE_PORT_AUX_DDIA |
2275                         TGL_DE_PORT_AUX_DDIB |
2276                         TGL_DE_PORT_AUX_DDIC |
2277                         XELPD_DE_PORT_AUX_DDID |
2278                         XELPD_DE_PORT_AUX_DDIE |
2279                         TGL_DE_PORT_AUX_USBC1 |
2280                         TGL_DE_PORT_AUX_USBC2 |
2281                         TGL_DE_PORT_AUX_USBC3 |
2282                         TGL_DE_PORT_AUX_USBC4;
2283         else if (DISPLAY_VER(dev_priv) >= 12)
2284                 return TGL_DE_PORT_AUX_DDIA |
2285                         TGL_DE_PORT_AUX_DDIB |
2286                         TGL_DE_PORT_AUX_DDIC |
2287                         TGL_DE_PORT_AUX_USBC1 |
2288                         TGL_DE_PORT_AUX_USBC2 |
2289                         TGL_DE_PORT_AUX_USBC3 |
2290                         TGL_DE_PORT_AUX_USBC4 |
2291                         TGL_DE_PORT_AUX_USBC5 |
2292                         TGL_DE_PORT_AUX_USBC6;
2293
2294
2295         mask = GEN8_AUX_CHANNEL_A;
2296         if (DISPLAY_VER(dev_priv) >= 9)
2297                 mask |= GEN9_AUX_CHANNEL_B |
2298                         GEN9_AUX_CHANNEL_C |
2299                         GEN9_AUX_CHANNEL_D;
2300
2301         if (IS_CNL_WITH_PORT_F(dev_priv) || DISPLAY_VER(dev_priv) == 11)
2302                 mask |= CNL_AUX_CHANNEL_F;
2303
2304         if (DISPLAY_VER(dev_priv) == 11)
2305                 mask |= ICL_AUX_CHANNEL_E;
2306
2307         return mask;
2308 }
2309
2310 static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
2311 {
2312         if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv))
2313                 return RKL_DE_PIPE_IRQ_FAULT_ERRORS;
2314         else if (DISPLAY_VER(dev_priv) >= 11)
2315                 return GEN11_DE_PIPE_IRQ_FAULT_ERRORS;
2316         else if (DISPLAY_VER(dev_priv) >= 9)
2317                 return GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2318         else
2319                 return GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2320 }
2321
2322 static void
2323 gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
2324 {
2325         bool found = false;
2326
2327         if (iir & GEN8_DE_MISC_GSE) {
2328                 intel_opregion_asle_intr(dev_priv);
2329                 found = true;
2330         }
2331
2332         if (iir & GEN8_DE_EDP_PSR) {
2333                 struct intel_encoder *encoder;
2334                 u32 psr_iir;
2335                 i915_reg_t iir_reg;
2336
2337                 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
2338                         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2339
2340                         if (DISPLAY_VER(dev_priv) >= 12)
2341                                 iir_reg = TRANS_PSR_IIR(intel_dp->psr.transcoder);
2342                         else
2343                                 iir_reg = EDP_PSR_IIR;
2344
2345                         psr_iir = intel_uncore_read(&dev_priv->uncore, iir_reg);
2346                         intel_uncore_write(&dev_priv->uncore, iir_reg, psr_iir);
2347
2348                         if (psr_iir)
2349                                 found = true;
2350
2351                         intel_psr_irq_handler(intel_dp, psr_iir);
2352
2353                         /* prior GEN12 only have one EDP PSR */
2354                         if (DISPLAY_VER(dev_priv) < 12)
2355                                 break;
2356                 }
2357         }
2358
2359         if (!found)
2360                 drm_err(&dev_priv->drm, "Unexpected DE Misc interrupt\n");
2361 }
2362
2363 static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,
2364                                            u32 te_trigger)
2365 {
2366         enum pipe pipe = INVALID_PIPE;
2367         enum transcoder dsi_trans;
2368         enum port port;
2369         u32 val, tmp;
2370
2371         /*
2372          * Incase of dual link, TE comes from DSI_1
2373          * this is to check if dual link is enabled
2374          */
2375         val = intel_uncore_read(&dev_priv->uncore, TRANS_DDI_FUNC_CTL2(TRANSCODER_DSI_0));
2376         val &= PORT_SYNC_MODE_ENABLE;
2377
2378         /*
2379          * if dual link is enabled, then read DSI_0
2380          * transcoder registers
2381          */
2382         port = ((te_trigger & DSI1_TE && val) || (te_trigger & DSI0_TE)) ?
2383                                                   PORT_A : PORT_B;
2384         dsi_trans = (port == PORT_A) ? TRANSCODER_DSI_0 : TRANSCODER_DSI_1;
2385
2386         /* Check if DSI configured in command mode */
2387         val = intel_uncore_read(&dev_priv->uncore, DSI_TRANS_FUNC_CONF(dsi_trans));
2388         val = val & OP_MODE_MASK;
2389
2390         if (val != CMD_MODE_NO_GATE && val != CMD_MODE_TE_GATE) {
2391                 drm_err(&dev_priv->drm, "DSI trancoder not configured in command mode\n");
2392                 return;
2393         }
2394
2395         /* Get PIPE for handling VBLANK event */
2396         val = intel_uncore_read(&dev_priv->uncore, TRANS_DDI_FUNC_CTL(dsi_trans));
2397         switch (val & TRANS_DDI_EDP_INPUT_MASK) {
2398         case TRANS_DDI_EDP_INPUT_A_ON:
2399                 pipe = PIPE_A;
2400                 break;
2401         case TRANS_DDI_EDP_INPUT_B_ONOFF:
2402                 pipe = PIPE_B;
2403                 break;
2404         case TRANS_DDI_EDP_INPUT_C_ONOFF:
2405                 pipe = PIPE_C;
2406                 break;
2407         default:
2408                 drm_err(&dev_priv->drm, "Invalid PIPE\n");
2409                 return;
2410         }
2411
2412         intel_handle_vblank(dev_priv, pipe);
2413
2414         /* clear TE in dsi IIR */
2415         port = (te_trigger & DSI1_TE) ? PORT_B : PORT_A;
2416         tmp = intel_uncore_read(&dev_priv->uncore, DSI_INTR_IDENT_REG(port));
2417         intel_uncore_write(&dev_priv->uncore, DSI_INTR_IDENT_REG(port), tmp);
2418 }
2419
2420 static u32 gen8_de_pipe_flip_done_mask(struct drm_i915_private *i915)
2421 {
2422         if (DISPLAY_VER(i915) >= 9)
2423                 return GEN9_PIPE_PLANE1_FLIP_DONE;
2424         else
2425                 return GEN8_PIPE_PRIMARY_FLIP_DONE;
2426 }
2427
2428 u32 gen8_de_pipe_underrun_mask(struct drm_i915_private *dev_priv)
2429 {
2430         u32 mask = GEN8_PIPE_FIFO_UNDERRUN;
2431
2432         if (DISPLAY_VER(dev_priv) >= 13)
2433                 mask |= XELPD_PIPE_SOFT_UNDERRUN |
2434                         XELPD_PIPE_HARD_UNDERRUN;
2435
2436         return mask;
2437 }
2438
2439 static irqreturn_t
2440 gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2441 {
2442         irqreturn_t ret = IRQ_NONE;
2443         u32 iir;
2444         enum pipe pipe;
2445
2446         drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DISPLAY(dev_priv));
2447
2448         if (master_ctl & GEN8_DE_MISC_IRQ) {
2449                 iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_MISC_IIR);
2450                 if (iir) {
2451                         intel_uncore_write(&dev_priv->uncore, GEN8_DE_MISC_IIR, iir);
2452                         ret = IRQ_HANDLED;
2453                         gen8_de_misc_irq_handler(dev_priv, iir);
2454                 } else {
2455                         drm_err(&dev_priv->drm,
2456                                 "The master control interrupt lied (DE MISC)!\n");
2457                 }
2458         }
2459
2460         if (DISPLAY_VER(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) {
2461                 iir = intel_uncore_read(&dev_priv->uncore, GEN11_DE_HPD_IIR);
2462                 if (iir) {
2463                         intel_uncore_write(&dev_priv->uncore, GEN11_DE_HPD_IIR, iir);
2464                         ret = IRQ_HANDLED;
2465                         gen11_hpd_irq_handler(dev_priv, iir);
2466                 } else {
2467                         drm_err(&dev_priv->drm,
2468                                 "The master control interrupt lied, (DE HPD)!\n");
2469                 }
2470         }
2471
2472         if (master_ctl & GEN8_DE_PORT_IRQ) {
2473                 iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IIR);
2474                 if (iir) {
2475                         bool found = false;
2476
2477                         intel_uncore_write(&dev_priv->uncore, GEN8_DE_PORT_IIR, iir);
2478                         ret = IRQ_HANDLED;
2479
2480                         if (iir & gen8_de_port_aux_mask(dev_priv)) {
2481                                 dp_aux_irq_handler(dev_priv);
2482                                 found = true;
2483                         }
2484
2485                         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
2486                                 u32 hotplug_trigger = iir & BXT_DE_PORT_HOTPLUG_MASK;
2487
2488                                 if (hotplug_trigger) {
2489                                         bxt_hpd_irq_handler(dev_priv, hotplug_trigger);
2490                                         found = true;
2491                                 }
2492                         } else if (IS_BROADWELL(dev_priv)) {
2493                                 u32 hotplug_trigger = iir & BDW_DE_PORT_HOTPLUG_MASK;
2494
2495                                 if (hotplug_trigger) {
2496                                         ilk_hpd_irq_handler(dev_priv, hotplug_trigger);
2497                                         found = true;
2498                                 }
2499                         }
2500
2501                         if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
2502                             (iir & BXT_DE_PORT_GMBUS)) {
2503                                 gmbus_irq_handler(dev_priv);
2504                                 found = true;
2505                         }
2506
2507                         if (DISPLAY_VER(dev_priv) >= 11) {
2508                                 u32 te_trigger = iir & (DSI0_TE | DSI1_TE);
2509
2510                                 if (te_trigger) {
2511                                         gen11_dsi_te_interrupt_handler(dev_priv, te_trigger);
2512                                         found = true;
2513                                 }
2514                         }
2515
2516                         if (!found)
2517                                 drm_err(&dev_priv->drm,
2518                                         "Unexpected DE Port interrupt\n");
2519                 }
2520                 else
2521                         drm_err(&dev_priv->drm,
2522                                 "The master control interrupt lied (DE PORT)!\n");
2523         }
2524
2525         for_each_pipe(dev_priv, pipe) {
2526                 u32 fault_errors;
2527
2528                 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2529                         continue;
2530
2531                 iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe));
2532                 if (!iir) {
2533                         drm_err(&dev_priv->drm,
2534                                 "The master control interrupt lied (DE PIPE)!\n");
2535                         continue;
2536                 }
2537
2538                 ret = IRQ_HANDLED;
2539                 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe), iir);
2540
2541                 if (iir & GEN8_PIPE_VBLANK)
2542                         intel_handle_vblank(dev_priv, pipe);
2543
2544                 if (iir & gen8_de_pipe_flip_done_mask(dev_priv))
2545                         flip_done_handler(dev_priv, pipe);
2546
2547                 if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
2548                         hsw_pipe_crc_irq_handler(dev_priv, pipe);
2549
2550                 if (iir & gen8_de_pipe_underrun_mask(dev_priv))
2551                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2552
2553                 fault_errors = iir & gen8_de_pipe_fault_mask(dev_priv);
2554                 if (fault_errors)
2555                         drm_err(&dev_priv->drm,
2556                                 "Fault errors on pipe %c: 0x%08x\n",
2557                                 pipe_name(pipe),
2558                                 fault_errors);
2559         }
2560
2561         if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
2562             master_ctl & GEN8_DE_PCH_IRQ) {
2563                 /*
2564                  * FIXME(BDW): Assume for now that the new interrupt handling
2565                  * scheme also closed the SDE interrupt handling race we've seen
2566                  * on older pch-split platforms. But this needs testing.
2567                  */
2568                 iir = intel_uncore_read(&dev_priv->uncore, SDEIIR);
2569                 if (iir) {
2570                         intel_uncore_write(&dev_priv->uncore, SDEIIR, iir);
2571                         ret = IRQ_HANDLED;
2572
2573                         if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2574                                 icp_irq_handler(dev_priv, iir);
2575                         else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
2576                                 spt_irq_handler(dev_priv, iir);
2577                         else
2578                                 cpt_irq_handler(dev_priv, iir);
2579                 } else {
2580                         /*
2581                          * Like on previous PCH there seems to be something
2582                          * fishy going on with forwarding PCH interrupts.
2583                          */
2584                         drm_dbg(&dev_priv->drm,
2585                                 "The master control interrupt lied (SDE)!\n");
2586                 }
2587         }
2588
2589         return ret;
2590 }
2591
2592 static inline u32 gen8_master_intr_disable(void __iomem * const regs)
2593 {
2594         raw_reg_write(regs, GEN8_MASTER_IRQ, 0);
2595
2596         /*
2597          * Now with master disabled, get a sample of level indications
2598          * for this interrupt. Indications will be cleared on related acks.
2599          * New indications can and will light up during processing,
2600          * and will generate new interrupt after enabling master.
2601          */
2602         return raw_reg_read(regs, GEN8_MASTER_IRQ);
2603 }
2604
2605 static inline void gen8_master_intr_enable(void __iomem * const regs)
2606 {
2607         raw_reg_write(regs, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2608 }
2609
2610 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2611 {
2612         struct drm_i915_private *dev_priv = arg;
2613         void __iomem * const regs = dev_priv->uncore.regs;
2614         u32 master_ctl;
2615
2616         if (!intel_irqs_enabled(dev_priv))
2617                 return IRQ_NONE;
2618
2619         master_ctl = gen8_master_intr_disable(regs);
2620         if (!master_ctl) {
2621                 gen8_master_intr_enable(regs);
2622                 return IRQ_NONE;
2623         }
2624
2625         /* Find, queue (onto bottom-halves), then clear each source */
2626         gen8_gt_irq_handler(&dev_priv->gt, master_ctl);
2627
2628         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2629         if (master_ctl & ~GEN8_GT_IRQS) {
2630                 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2631                 gen8_de_irq_handler(dev_priv, master_ctl);
2632                 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2633         }
2634
2635         gen8_master_intr_enable(regs);
2636
2637         pmu_irq_stats(dev_priv, IRQ_HANDLED);
2638
2639         return IRQ_HANDLED;
2640 }
2641
2642 static u32
2643 gen11_gu_misc_irq_ack(struct intel_gt *gt, const u32 master_ctl)
2644 {
2645         void __iomem * const regs = gt->uncore->regs;
2646         u32 iir;
2647
2648         if (!(master_ctl & GEN11_GU_MISC_IRQ))
2649                 return 0;
2650
2651         iir = raw_reg_read(regs, GEN11_GU_MISC_IIR);
2652         if (likely(iir))
2653                 raw_reg_write(regs, GEN11_GU_MISC_IIR, iir);
2654
2655         return iir;
2656 }
2657
2658 static void
2659 gen11_gu_misc_irq_handler(struct intel_gt *gt, const u32 iir)
2660 {
2661         if (iir & GEN11_GU_MISC_GSE)
2662                 intel_opregion_asle_intr(gt->i915);
2663 }
2664
2665 static inline u32 gen11_master_intr_disable(void __iomem * const regs)
2666 {
2667         raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, 0);
2668
2669         /*
2670          * Now with master disabled, get a sample of level indications
2671          * for this interrupt. Indications will be cleared on related acks.
2672          * New indications can and will light up during processing,
2673          * and will generate new interrupt after enabling master.
2674          */
2675         return raw_reg_read(regs, GEN11_GFX_MSTR_IRQ);
2676 }
2677
2678 static inline void gen11_master_intr_enable(void __iomem * const regs)
2679 {
2680         raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
2681 }
2682
2683 static void
2684 gen11_display_irq_handler(struct drm_i915_private *i915)
2685 {
2686         void __iomem * const regs = i915->uncore.regs;
2687         const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL);
2688
2689         disable_rpm_wakeref_asserts(&i915->runtime_pm);
2690         /*
2691          * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ
2692          * for the display related bits.
2693          */
2694         raw_reg_write(regs, GEN11_DISPLAY_INT_CTL, 0x0);
2695         gen8_de_irq_handler(i915, disp_ctl);
2696         raw_reg_write(regs, GEN11_DISPLAY_INT_CTL,
2697                       GEN11_DISPLAY_IRQ_ENABLE);
2698
2699         enable_rpm_wakeref_asserts(&i915->runtime_pm);
2700 }
2701
2702 static __always_inline irqreturn_t
2703 __gen11_irq_handler(struct drm_i915_private * const i915,
2704                     u32 (*intr_disable)(void __iomem * const regs),
2705                     void (*intr_enable)(void __iomem * const regs))
2706 {
2707         void __iomem * const regs = i915->uncore.regs;
2708         struct intel_gt *gt = &i915->gt;
2709         u32 master_ctl;
2710         u32 gu_misc_iir;
2711
2712         if (!intel_irqs_enabled(i915))
2713                 return IRQ_NONE;
2714
2715         master_ctl = intr_disable(regs);
2716         if (!master_ctl) {
2717                 intr_enable(regs);
2718                 return IRQ_NONE;
2719         }
2720
2721         /* Find, queue (onto bottom-halves), then clear each source */
2722         gen11_gt_irq_handler(gt, master_ctl);
2723
2724         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2725         if (master_ctl & GEN11_DISPLAY_IRQ)
2726                 gen11_display_irq_handler(i915);
2727
2728         gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
2729
2730         intr_enable(regs);
2731
2732         gen11_gu_misc_irq_handler(gt, gu_misc_iir);
2733
2734         pmu_irq_stats(i915, IRQ_HANDLED);
2735
2736         return IRQ_HANDLED;
2737 }
2738
2739 static irqreturn_t gen11_irq_handler(int irq, void *arg)
2740 {
2741         return __gen11_irq_handler(arg,
2742                                    gen11_master_intr_disable,
2743                                    gen11_master_intr_enable);
2744 }
2745
2746 static u32 dg1_master_intr_disable_and_ack(void __iomem * const regs)
2747 {
2748         u32 val;
2749
2750         /* First disable interrupts */
2751         raw_reg_write(regs, DG1_MSTR_UNIT_INTR, 0);
2752
2753         /* Get the indication levels and ack the master unit */
2754         val = raw_reg_read(regs, DG1_MSTR_UNIT_INTR);
2755         if (unlikely(!val))
2756                 return 0;
2757
2758         raw_reg_write(regs, DG1_MSTR_UNIT_INTR, val);
2759
2760         /*
2761          * Now with master disabled, get a sample of level indications
2762          * for this interrupt and ack them right away - we keep GEN11_MASTER_IRQ
2763          * out as this bit doesn't exist anymore for DG1
2764          */
2765         val = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ) & ~GEN11_MASTER_IRQ;
2766         if (unlikely(!val))
2767                 return 0;
2768
2769         raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, val);
2770
2771         return val;
2772 }
2773
2774 static inline void dg1_master_intr_enable(void __iomem * const regs)
2775 {
2776         raw_reg_write(regs, DG1_MSTR_UNIT_INTR, DG1_MSTR_IRQ);
2777 }
2778
2779 static irqreturn_t dg1_irq_handler(int irq, void *arg)
2780 {
2781         return __gen11_irq_handler(arg,
2782                                    dg1_master_intr_disable_and_ack,
2783                                    dg1_master_intr_enable);
2784 }
2785
2786 /* Called from drm generic code, passed 'crtc' which
2787  * we use as a pipe index
2788  */
2789 int i8xx_enable_vblank(struct drm_crtc *crtc)
2790 {
2791         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2792         enum pipe pipe = to_intel_crtc(crtc)->pipe;
2793         unsigned long irqflags;
2794
2795         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2796         i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
2797         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2798
2799         return 0;
2800 }
2801
2802 int i915gm_enable_vblank(struct drm_crtc *crtc)
2803 {
2804         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2805
2806         /*
2807          * Vblank interrupts fail to wake the device up from C2+.
2808          * Disabling render clock gating during C-states avoids
2809          * the problem. There is a small power cost so we do this
2810          * only when vblank interrupts are actually enabled.
2811          */
2812         if (dev_priv->vblank_enabled++ == 0)
2813                 intel_uncore_write(&dev_priv->uncore, SCPD0, _MASKED_BIT_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));
2814
2815         return i8xx_enable_vblank(crtc);
2816 }
2817
2818 int i965_enable_vblank(struct drm_crtc *crtc)
2819 {
2820         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2821         enum pipe pipe = to_intel_crtc(crtc)->pipe;
2822         unsigned long irqflags;
2823
2824         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2825         i915_enable_pipestat(dev_priv, pipe,
2826                              PIPE_START_VBLANK_INTERRUPT_STATUS);
2827         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2828
2829         return 0;
2830 }
2831
2832 int ilk_enable_vblank(struct drm_crtc *crtc)
2833 {
2834         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2835         enum pipe pipe = to_intel_crtc(crtc)->pipe;
2836         unsigned long irqflags;
2837         u32 bit = DISPLAY_VER(dev_priv) >= 7 ?
2838                 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
2839
2840         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2841         ilk_enable_display_irq(dev_priv, bit);
2842         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2843
2844         /* Even though there is no DMC, frame counter can get stuck when
2845          * PSR is active as no frames are generated.
2846          */
2847         if (HAS_PSR(dev_priv))
2848                 drm_crtc_vblank_restore(crtc);
2849
2850         return 0;
2851 }
2852
2853 static bool gen11_dsi_configure_te(struct intel_crtc *intel_crtc,
2854                                    bool enable)
2855 {
2856         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
2857         enum port port;
2858         u32 tmp;
2859
2860         if (!(intel_crtc->mode_flags &
2861             (I915_MODE_FLAG_DSI_USE_TE1 | I915_MODE_FLAG_DSI_USE_TE0)))
2862                 return false;
2863
2864         /* for dual link cases we consider TE from slave */
2865         if (intel_crtc->mode_flags & I915_MODE_FLAG_DSI_USE_TE1)
2866                 port = PORT_B;
2867         else
2868                 port = PORT_A;
2869
2870         tmp =  intel_uncore_read(&dev_priv->uncore, DSI_INTR_MASK_REG(port));
2871         if (enable)
2872                 tmp &= ~DSI_TE_EVENT;
2873         else
2874                 tmp |= DSI_TE_EVENT;
2875
2876         intel_uncore_write(&dev_priv->uncore, DSI_INTR_MASK_REG(port), tmp);
2877
2878         tmp = intel_uncore_read(&dev_priv->uncore, DSI_INTR_IDENT_REG(port));
2879         intel_uncore_write(&dev_priv->uncore, DSI_INTR_IDENT_REG(port), tmp);
2880
2881         return true;
2882 }
2883
2884 int bdw_enable_vblank(struct drm_crtc *crtc)
2885 {
2886         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2887         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2888         enum pipe pipe = intel_crtc->pipe;
2889         unsigned long irqflags;
2890
2891         if (gen11_dsi_configure_te(intel_crtc, true))
2892                 return 0;
2893
2894         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2895         bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2896         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2897
2898         /* Even if there is no DMC, frame counter can get stuck when
2899          * PSR is active as no frames are generated, so check only for PSR.
2900          */
2901         if (HAS_PSR(dev_priv))
2902                 drm_crtc_vblank_restore(crtc);
2903
2904         return 0;
2905 }
2906
2907 /* Called from drm generic code, passed 'crtc' which
2908  * we use as a pipe index
2909  */
2910 void i8xx_disable_vblank(struct drm_crtc *crtc)
2911 {
2912         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2913         enum pipe pipe = to_intel_crtc(crtc)->pipe;
2914         unsigned long irqflags;
2915
2916         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2917         i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
2918         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2919 }
2920
2921 void i915gm_disable_vblank(struct drm_crtc *crtc)
2922 {
2923         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2924
2925         i8xx_disable_vblank(crtc);
2926
2927         if (--dev_priv->vblank_enabled == 0)
2928                 intel_uncore_write(&dev_priv->uncore, SCPD0, _MASKED_BIT_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));
2929 }
2930
2931 void i965_disable_vblank(struct drm_crtc *crtc)
2932 {
2933         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2934         enum pipe pipe = to_intel_crtc(crtc)->pipe;
2935         unsigned long irqflags;
2936
2937         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2938         i915_disable_pipestat(dev_priv, pipe,
2939                               PIPE_START_VBLANK_INTERRUPT_STATUS);
2940         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2941 }
2942
2943 void ilk_disable_vblank(struct drm_crtc *crtc)
2944 {
2945         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2946         enum pipe pipe = to_intel_crtc(crtc)->pipe;
2947         unsigned long irqflags;
2948         u32 bit = DISPLAY_VER(dev_priv) >= 7 ?
2949                 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
2950
2951         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2952         ilk_disable_display_irq(dev_priv, bit);
2953         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2954 }
2955
2956 void bdw_disable_vblank(struct drm_crtc *crtc)
2957 {
2958         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2959         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2960         enum pipe pipe = intel_crtc->pipe;
2961         unsigned long irqflags;
2962
2963         if (gen11_dsi_configure_te(intel_crtc, false))
2964                 return;
2965
2966         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2967         bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2968         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2969 }
2970
2971 static void ibx_irq_reset(struct drm_i915_private *dev_priv)
2972 {
2973         struct intel_uncore *uncore = &dev_priv->uncore;
2974
2975         if (HAS_PCH_NOP(dev_priv))
2976                 return;
2977
2978         GEN3_IRQ_RESET(uncore, SDE);
2979
2980         if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
2981                 intel_uncore_write(&dev_priv->uncore, SERR_INT, 0xffffffff);
2982 }
2983
2984 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
2985 {
2986         struct intel_uncore *uncore = &dev_priv->uncore;
2987
2988         if (IS_CHERRYVIEW(dev_priv))
2989                 intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
2990         else
2991                 intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK);
2992
2993         i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
2994         intel_uncore_write(uncore, PORT_HOTPLUG_STAT, intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT));
2995
2996         i9xx_pipestat_irq_reset(dev_priv);
2997
2998         GEN3_IRQ_RESET(uncore, VLV_);
2999         dev_priv->irq_mask = ~0u;
3000 }
3001
3002 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
3003 {
3004         struct intel_uncore *uncore = &dev_priv->uncore;
3005
3006         u32 pipestat_mask;
3007         u32 enable_mask;
3008         enum pipe pipe;
3009
3010         pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS;
3011
3012         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3013         for_each_pipe(dev_priv, pipe)
3014                 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
3015
3016         enable_mask = I915_DISPLAY_PORT_INTERRUPT |
3017                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3018                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3019                 I915_LPE_PIPE_A_INTERRUPT |
3020                 I915_LPE_PIPE_B_INTERRUPT;
3021
3022         if (IS_CHERRYVIEW(dev_priv))
3023                 enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT |
3024                         I915_LPE_PIPE_C_INTERRUPT;
3025
3026         drm_WARN_ON(&dev_priv->drm, dev_priv->irq_mask != ~0u);
3027
3028         dev_priv->irq_mask = ~enable_mask;
3029
3030         GEN3_IRQ_INIT(uncore, VLV_, dev_priv->irq_mask, enable_mask);
3031 }
3032
3033 /* drm_dma.h hooks
3034 */
3035 static void ilk_irq_reset(struct drm_i915_private *dev_priv)
3036 {
3037         struct intel_uncore *uncore = &dev_priv->uncore;
3038
3039         GEN3_IRQ_RESET(uncore, DE);
3040         dev_priv->irq_mask = ~0u;
3041
3042         if (GRAPHICS_VER(dev_priv) == 7)
3043                 intel_uncore_write(uncore, GEN7_ERR_INT, 0xffffffff);
3044
3045         if (IS_HASWELL(dev_priv)) {
3046                 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
3047                 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
3048         }
3049
3050         gen5_gt_irq_reset(&dev_priv->gt);
3051
3052         ibx_irq_reset(dev_priv);
3053 }
3054
3055 static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
3056 {
3057         intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, 0);
3058         intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER);
3059
3060         gen5_gt_irq_reset(&dev_priv->gt);
3061
3062         spin_lock_irq(&dev_priv->irq_lock);
3063         if (dev_priv->display_irqs_enabled)
3064                 vlv_display_irq_reset(dev_priv);
3065         spin_unlock_irq(&dev_priv->irq_lock);
3066 }
3067
3068 static void cnp_display_clock_wa(struct drm_i915_private *dev_priv)
3069 {
3070         struct intel_uncore *uncore = &dev_priv->uncore;
3071
3072         /*
3073          * Wa_14010685332:cnp/cmp,tgp,adp
3074          * TODO: Clarify which platforms this applies to
3075          * TODO: Figure out if this workaround can be applied in the s0ix suspend/resume handlers as
3076          * on earlier platforms and whether the workaround is also needed for runtime suspend/resume
3077          */
3078         if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
3079             (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
3080                 intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS,
3081                                  SBCLK_RUN_REFCLK_DIS);
3082                 intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
3083         }
3084 }
3085
3086 static void gen8_display_irq_reset(struct drm_i915_private *dev_priv)
3087 {
3088         struct intel_uncore *uncore = &dev_priv->uncore;
3089         enum pipe pipe;
3090
3091         if (!HAS_DISPLAY(dev_priv))
3092                 return;
3093
3094         intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
3095         intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
3096
3097         for_each_pipe(dev_priv, pipe)
3098                 if (intel_display_power_is_enabled(dev_priv,
3099                                                    POWER_DOMAIN_PIPE(pipe)))
3100                         GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
3101
3102         GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);
3103         GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
3104 }
3105
3106 static void gen8_irq_reset(struct drm_i915_private *dev_priv)
3107 {
3108         struct intel_uncore *uncore = &dev_priv->uncore;
3109
3110         gen8_master_intr_disable(dev_priv->uncore.regs);
3111
3112         gen8_gt_irq_reset(&dev_priv->gt);
3113         gen8_display_irq_reset(dev_priv);
3114         GEN3_IRQ_RESET(uncore, GEN8_PCU_);
3115
3116         if (HAS_PCH_SPLIT(dev_priv))
3117                 ibx_irq_reset(dev_priv);
3118
3119         cnp_display_clock_wa(dev_priv);
3120 }
3121
3122 static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
3123 {
3124         struct intel_uncore *uncore = &dev_priv->uncore;
3125         enum pipe pipe;
3126         u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
3127                 BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
3128
3129         if (!HAS_DISPLAY(dev_priv))
3130                 return;
3131
3132         intel_uncore_write(uncore, GEN11_DISPLAY_INT_CTL, 0);
3133
3134         if (DISPLAY_VER(dev_priv) >= 12) {
3135                 enum transcoder trans;
3136
3137                 for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {
3138                         enum intel_display_power_domain domain;
3139
3140                         domain = POWER_DOMAIN_TRANSCODER(trans);
3141                         if (!intel_display_power_is_enabled(dev_priv, domain))
3142                                 continue;
3143
3144                         intel_uncore_write(uncore, TRANS_PSR_IMR(trans), 0xffffffff);
3145                         intel_uncore_write(uncore, TRANS_PSR_IIR(trans), 0xffffffff);
3146                 }
3147         } else {
3148                 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
3149                 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
3150         }
3151
3152         for_each_pipe(dev_priv, pipe)
3153                 if (intel_display_power_is_enabled(dev_priv,
3154                                                    POWER_DOMAIN_PIPE(pipe)))
3155                         GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
3156
3157         GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);
3158         GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
3159         GEN3_IRQ_RESET(uncore, GEN11_DE_HPD_);
3160
3161         if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3162                 GEN3_IRQ_RESET(uncore, SDE);
3163
3164         cnp_display_clock_wa(dev_priv);
3165 }
3166
3167 static void gen11_irq_reset(struct drm_i915_private *dev_priv)
3168 {
3169         struct intel_uncore *uncore = &dev_priv->uncore;
3170
3171         if (HAS_MASTER_UNIT_IRQ(dev_priv))
3172                 dg1_master_intr_disable_and_ack(dev_priv->uncore.regs);
3173         else
3174                 gen11_master_intr_disable(dev_priv->uncore.regs);
3175
3176         gen11_gt_irq_reset(&dev_priv->gt);
3177         gen11_display_irq_reset(dev_priv);
3178
3179         GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
3180         GEN3_IRQ_RESET(uncore, GEN8_PCU_);
3181 }
3182
3183 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
3184                                      u8 pipe_mask)
3185 {
3186         struct intel_uncore *uncore = &dev_priv->uncore;
3187         u32 extra_ier = GEN8_PIPE_VBLANK |
3188                 gen8_de_pipe_underrun_mask(dev_priv) |
3189                 gen8_de_pipe_flip_done_mask(dev_priv);
3190         enum pipe pipe;
3191
3192         spin_lock_irq(&dev_priv->irq_lock);
3193
3194         if (!intel_irqs_enabled(dev_priv)) {
3195                 spin_unlock_irq(&dev_priv->irq_lock);
3196                 return;
3197         }
3198
3199         for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3200                 GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,
3201                                   dev_priv->de_irq_mask[pipe],
3202                                   ~dev_priv->de_irq_mask[pipe] | extra_ier);
3203
3204         spin_unlock_irq(&dev_priv->irq_lock);
3205 }
3206
3207 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
3208                                      u8 pipe_mask)
3209 {
3210         struct intel_uncore *uncore = &dev_priv->uncore;
3211         enum pipe pipe;
3212
3213         spin_lock_irq(&dev_priv->irq_lock);
3214
3215         if (!intel_irqs_enabled(dev_priv)) {
3216                 spin_unlock_irq(&dev_priv->irq_lock);
3217                 return;
3218         }
3219
3220         for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3221                 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
3222
3223         spin_unlock_irq(&dev_priv->irq_lock);
3224
3225         /* make sure we're done processing display irqs */
3226         intel_synchronize_irq(dev_priv);
3227 }
3228
3229 static void cherryview_irq_reset(struct drm_i915_private *dev_priv)
3230 {
3231         struct intel_uncore *uncore = &dev_priv->uncore;
3232
3233         intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, 0);
3234         intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ);
3235
3236         gen8_gt_irq_reset(&dev_priv->gt);
3237
3238         GEN3_IRQ_RESET(uncore, GEN8_PCU_);
3239
3240         spin_lock_irq(&dev_priv->irq_lock);
3241         if (dev_priv->display_irqs_enabled)
3242                 vlv_display_irq_reset(dev_priv);
3243         spin_unlock_irq(&dev_priv->irq_lock);
3244 }
3245
3246 static u32 ibx_hotplug_enables(struct drm_i915_private *i915,
3247                                enum hpd_pin pin)
3248 {
3249         switch (pin) {
3250         case HPD_PORT_A:
3251                 /*
3252                  * When CPU and PCH are on the same package, port A
3253                  * HPD must be enabled in both north and south.
3254                  */
3255                 return HAS_PCH_LPT_LP(i915) ?
3256                         PORTA_HOTPLUG_ENABLE : 0;
3257         case HPD_PORT_B:
3258                 return PORTB_HOTPLUG_ENABLE |
3259                         PORTB_PULSE_DURATION_2ms;
3260         case HPD_PORT_C:
3261                 return PORTC_HOTPLUG_ENABLE |
3262                         PORTC_PULSE_DURATION_2ms;
3263         case HPD_PORT_D:
3264                 return PORTD_HOTPLUG_ENABLE |
3265                         PORTD_PULSE_DURATION_2ms;
3266         default:
3267                 return 0;
3268         }
3269 }
3270
3271 static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
3272 {
3273         u32 hotplug;
3274
3275         /*
3276          * Enable digital hotplug on the PCH, and configure the DP short pulse
3277          * duration to 2ms (which is the minimum in the Display Port spec).
3278          * The pulse duration bits are reserved on LPT+.
3279          */
3280         hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);
3281         hotplug &= ~(PORTA_HOTPLUG_ENABLE |
3282                      PORTB_HOTPLUG_ENABLE |
3283                      PORTC_HOTPLUG_ENABLE |
3284                      PORTD_HOTPLUG_ENABLE |
3285                      PORTB_PULSE_DURATION_MASK |
3286                      PORTC_PULSE_DURATION_MASK |
3287                      PORTD_PULSE_DURATION_MASK);
3288         hotplug |= intel_hpd_hotplug_enables(dev_priv, ibx_hotplug_enables);
3289         intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, hotplug);
3290 }
3291
3292 static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
3293 {
3294         u32 hotplug_irqs, enabled_irqs;
3295
3296         enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3297         hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3298
3299         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3300
3301         ibx_hpd_detection_setup(dev_priv);
3302 }
3303
3304 static u32 icp_ddi_hotplug_enables(struct drm_i915_private *i915,
3305                                    enum hpd_pin pin)
3306 {
3307         switch (pin) {
3308         case HPD_PORT_A:
3309         case HPD_PORT_B:
3310         case HPD_PORT_C:
3311         case HPD_PORT_D:
3312                 return SHOTPLUG_CTL_DDI_HPD_ENABLE(pin);
3313         default:
3314                 return 0;
3315         }
3316 }
3317
3318 static u32 icp_tc_hotplug_enables(struct drm_i915_private *i915,
3319                                   enum hpd_pin pin)
3320 {
3321         switch (pin) {
3322         case HPD_PORT_TC1:
3323         case HPD_PORT_TC2:
3324         case HPD_PORT_TC3:
3325         case HPD_PORT_TC4:
3326         case HPD_PORT_TC5:
3327         case HPD_PORT_TC6:
3328                 return ICP_TC_HPD_ENABLE(pin);
3329         default:
3330                 return 0;
3331         }
3332 }
3333
3334 static void icp_ddi_hpd_detection_setup(struct drm_i915_private *dev_priv)
3335 {
3336         u32 hotplug;
3337
3338         hotplug = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_DDI);
3339         hotplug &= ~(SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A) |
3340                      SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) |
3341                      SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_C) |
3342                      SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_D));
3343         hotplug |= intel_hpd_hotplug_enables(dev_priv, icp_ddi_hotplug_enables);
3344         intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_DDI, hotplug);
3345 }
3346
3347 static void icp_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
3348 {
3349         u32 hotplug;
3350
3351         hotplug = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_TC);
3352         hotplug &= ~(ICP_TC_HPD_ENABLE(HPD_PORT_TC1) |
3353                      ICP_TC_HPD_ENABLE(HPD_PORT_TC2) |
3354                      ICP_TC_HPD_ENABLE(HPD_PORT_TC3) |
3355                      ICP_TC_HPD_ENABLE(HPD_PORT_TC4) |
3356                      ICP_TC_HPD_ENABLE(HPD_PORT_TC5) |
3357                      ICP_TC_HPD_ENABLE(HPD_PORT_TC6));
3358         hotplug |= intel_hpd_hotplug_enables(dev_priv, icp_tc_hotplug_enables);
3359         intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_TC, hotplug);
3360 }
3361
3362 static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv)
3363 {
3364         u32 hotplug_irqs, enabled_irqs;
3365
3366         enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3367         hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3368
3369         if (INTEL_PCH_TYPE(dev_priv) <= PCH_TGP)
3370                 intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
3371
3372         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3373
3374         icp_ddi_hpd_detection_setup(dev_priv);
3375         icp_tc_hpd_detection_setup(dev_priv);
3376 }
3377
3378 static u32 gen11_hotplug_enables(struct drm_i915_private *i915,
3379                                  enum hpd_pin pin)
3380 {
3381         switch (pin) {
3382         case HPD_PORT_TC1:
3383         case HPD_PORT_TC2:
3384         case HPD_PORT_TC3:
3385         case HPD_PORT_TC4:
3386         case HPD_PORT_TC5:
3387         case HPD_PORT_TC6:
3388                 return GEN11_HOTPLUG_CTL_ENABLE(pin);
3389         default:
3390                 return 0;
3391         }
3392 }
3393
3394 static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv)
3395 {
3396         u32 val;
3397
3398         val = intel_uncore_read(&dev_priv->uncore, SOUTH_CHICKEN1);
3399         val |= (INVERT_DDIA_HPD |
3400                 INVERT_DDIB_HPD |
3401                 INVERT_DDIC_HPD |
3402                 INVERT_DDID_HPD);
3403         intel_uncore_write(&dev_priv->uncore, SOUTH_CHICKEN1, val);
3404
3405         icp_hpd_irq_setup(dev_priv);
3406 }
3407
3408 static void gen11_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
3409 {
3410         u32 hotplug;
3411
3412         hotplug = intel_uncore_read(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL);
3413         hotplug &= ~(GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
3414                      GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) |
3415                      GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) |
3416                      GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) |
3417                      GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
3418                      GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6));
3419         hotplug |= intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables);
3420         intel_uncore_write(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL, hotplug);
3421 }
3422
3423 static void gen11_tbt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3424 {
3425         u32 hotplug;
3426
3427         hotplug = intel_uncore_read(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL);
3428         hotplug &= ~(GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
3429                      GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) |
3430                      GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) |
3431                      GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) |
3432                      GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
3433                      GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6));
3434         hotplug |= intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables);
3435         intel_uncore_write(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL, hotplug);
3436 }
3437
3438 static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
3439 {
3440         u32 hotplug_irqs, enabled_irqs;
3441         u32 val;
3442
3443         enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
3444         hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd);
3445
3446         val = intel_uncore_read(&dev_priv->uncore, GEN11_DE_HPD_IMR);
3447         val &= ~hotplug_irqs;
3448         val |= ~enabled_irqs & hotplug_irqs;
3449         intel_uncore_write(&dev_priv->uncore, GEN11_DE_HPD_IMR, val);
3450         intel_uncore_posting_read(&dev_priv->uncore, GEN11_DE_HPD_IMR);
3451
3452         gen11_tc_hpd_detection_setup(dev_priv);
3453         gen11_tbt_hpd_detection_setup(dev_priv);
3454
3455         if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3456                 icp_hpd_irq_setup(dev_priv);
3457 }
3458
3459 static u32 spt_hotplug_enables(struct drm_i915_private *i915,
3460                                enum hpd_pin pin)
3461 {
3462         switch (pin) {
3463         case HPD_PORT_A:
3464                 return PORTA_HOTPLUG_ENABLE;
3465         case HPD_PORT_B:
3466                 return PORTB_HOTPLUG_ENABLE;
3467         case HPD_PORT_C:
3468                 return PORTC_HOTPLUG_ENABLE;
3469         case HPD_PORT_D:
3470                 return PORTD_HOTPLUG_ENABLE;
3471         default:
3472                 return 0;
3473         }
3474 }
3475
3476 static u32 spt_hotplug2_enables(struct drm_i915_private *i915,
3477                                 enum hpd_pin pin)
3478 {
3479         switch (pin) {
3480         case HPD_PORT_E:
3481                 return PORTE_HOTPLUG_ENABLE;
3482         default:
3483                 return 0;
3484         }
3485 }
3486
3487 static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3488 {
3489         u32 val, hotplug;
3490
3491         /* Display WA #1179 WaHardHangonHotPlug: cnp */
3492         if (HAS_PCH_CNP(dev_priv)) {
3493                 val = intel_uncore_read(&dev_priv->uncore, SOUTH_CHICKEN1);
3494                 val &= ~CHASSIS_CLK_REQ_DURATION_MASK;
3495                 val |= CHASSIS_CLK_REQ_DURATION(0xf);
3496                 intel_uncore_write(&dev_priv->uncore, SOUTH_CHICKEN1, val);
3497         }
3498
3499         /* Enable digital hotplug on the PCH */
3500         hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);
3501         hotplug &= ~(PORTA_HOTPLUG_ENABLE |
3502                      PORTB_HOTPLUG_ENABLE |
3503                      PORTC_HOTPLUG_ENABLE |
3504                      PORTD_HOTPLUG_ENABLE);
3505         hotplug |= intel_hpd_hotplug_enables(dev_priv, spt_hotplug_enables);
3506         intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, hotplug);
3507
3508         hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG2);
3509         hotplug &= ~PORTE_HOTPLUG_ENABLE;
3510         hotplug |= intel_hpd_hotplug_enables(dev_priv, spt_hotplug2_enables);
3511         intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG2, hotplug);
3512 }
3513
3514 static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3515 {
3516         u32 hotplug_irqs, enabled_irqs;
3517
3518         if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
3519                 intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
3520
3521         enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3522         hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3523
3524         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3525
3526         spt_hpd_detection_setup(dev_priv);
3527 }
3528
3529 static u32 ilk_hotplug_enables(struct drm_i915_private *i915,
3530                                enum hpd_pin pin)
3531 {
3532         switch (pin) {
3533         case HPD_PORT_A:
3534                 return DIGITAL_PORTA_HOTPLUG_ENABLE |
3535                         DIGITAL_PORTA_PULSE_DURATION_2ms;
3536         default:
3537                 return 0;
3538         }
3539 }
3540
3541 static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv)
3542 {
3543         u32 hotplug;
3544
3545         /*
3546          * Enable digital hotplug on the CPU, and configure the DP short pulse
3547          * duration to 2ms (which is the minimum in the Display Port spec)
3548          * The pulse duration bits are reserved on HSW+.
3549          */
3550         hotplug = intel_uncore_read(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL);
3551         hotplug &= ~(DIGITAL_PORTA_HOTPLUG_ENABLE |
3552                      DIGITAL_PORTA_PULSE_DURATION_MASK);
3553         hotplug |= intel_hpd_hotplug_enables(dev_priv, ilk_hotplug_enables);
3554         intel_uncore_write(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
3555 }
3556
3557 static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
3558 {
3559         u32 hotplug_irqs, enabled_irqs;
3560
3561         enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
3562         hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd);
3563
3564         if (DISPLAY_VER(dev_priv) >= 8)
3565                 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3566         else
3567                 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3568
3569         ilk_hpd_detection_setup(dev_priv);
3570
3571         ibx_hpd_irq_setup(dev_priv);
3572 }
3573
3574 static u32 bxt_hotplug_enables(struct drm_i915_private *i915,
3575                                enum hpd_pin pin)
3576 {
3577         u32 hotplug;
3578
3579         switch (pin) {
3580         case HPD_PORT_A:
3581                 hotplug = PORTA_HOTPLUG_ENABLE;
3582                 if (intel_bios_is_port_hpd_inverted(i915, PORT_A))
3583                         hotplug |= BXT_DDIA_HPD_INVERT;
3584                 return hotplug;
3585         case HPD_PORT_B:
3586                 hotplug = PORTB_HOTPLUG_ENABLE;
3587                 if (intel_bios_is_port_hpd_inverted(i915, PORT_B))
3588                         hotplug |= BXT_DDIB_HPD_INVERT;
3589                 return hotplug;
3590         case HPD_PORT_C:
3591                 hotplug = PORTC_HOTPLUG_ENABLE;
3592                 if (intel_bios_is_port_hpd_inverted(i915, PORT_C))
3593                         hotplug |= BXT_DDIC_HPD_INVERT;
3594                 return hotplug;
3595         default:
3596                 return 0;
3597         }
3598 }
3599
3600 static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3601 {
3602         u32 hotplug;
3603
3604         hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);
3605         hotplug &= ~(PORTA_HOTPLUG_ENABLE |
3606                      PORTB_HOTPLUG_ENABLE |
3607                      PORTC_HOTPLUG_ENABLE |
3608                      BXT_DDIA_HPD_INVERT |
3609                      BXT_DDIB_HPD_INVERT |
3610                      BXT_DDIC_HPD_INVERT);
3611         hotplug |= intel_hpd_hotplug_enables(dev_priv, bxt_hotplug_enables);
3612         intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, hotplug);
3613 }
3614
3615 static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3616 {
3617         u32 hotplug_irqs, enabled_irqs;
3618
3619         enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
3620         hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd);
3621
3622         bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3623
3624         bxt_hpd_detection_setup(dev_priv);
3625 }
3626
3627 /*
3628  * SDEIER is also touched by the interrupt handler to work around missed PCH
3629  * interrupts. Hence we can't update it after the interrupt handler is enabled -
3630  * instead we unconditionally enable all PCH interrupt sources here, but then
3631  * only unmask them as needed with SDEIMR.
3632  *
3633  * Note that we currently do this after installing the interrupt handler,
3634  * but before we enable the master interrupt. That should be sufficient
3635  * to avoid races with the irq handler, assuming we have MSI. Shared legacy
3636  * interrupts could still race.
3637  */
3638 static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
3639 {
3640         struct intel_uncore *uncore = &dev_priv->uncore;
3641         u32 mask;
3642
3643         if (HAS_PCH_NOP(dev_priv))
3644                 return;
3645
3646         if (HAS_PCH_IBX(dev_priv))
3647                 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3648         else if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
3649                 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3650         else
3651                 mask = SDE_GMBUS_CPT;
3652
3653         GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
3654 }
3655
3656 static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
3657 {
3658         struct intel_uncore *uncore = &dev_priv->uncore;
3659         u32 display_mask, extra_mask;
3660
3661         if (GRAPHICS_VER(dev_priv) >= 7) {
3662                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3663                                 DE_PCH_EVENT_IVB | DE_AUX_CHANNEL_A_IVB);
3664                 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3665                               DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
3666                               DE_PLANE_FLIP_DONE_IVB(PLANE_C) |
3667                               DE_PLANE_FLIP_DONE_IVB(PLANE_B) |
3668                               DE_PLANE_FLIP_DONE_IVB(PLANE_A) |
3669                               DE_DP_A_HOTPLUG_IVB);
3670         } else {
3671                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3672                                 DE_AUX_CHANNEL_A | DE_PIPEB_CRC_DONE |
3673                                 DE_PIPEA_CRC_DONE | DE_POISON);
3674                 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK |
3675                               DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
3676                               DE_PLANE_FLIP_DONE(PLANE_A) |
3677                               DE_PLANE_FLIP_DONE(PLANE_B) |
3678                               DE_DP_A_HOTPLUG);
3679         }
3680
3681         if (IS_HASWELL(dev_priv)) {
3682                 gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
3683                 display_mask |= DE_EDP_PSR_INT_HSW;
3684         }
3685
3686         if (IS_IRONLAKE_M(dev_priv))
3687                 extra_mask |= DE_PCU_EVENT;
3688
3689         dev_priv->irq_mask = ~display_mask;
3690
3691         ibx_irq_postinstall(dev_priv);
3692
3693         gen5_gt_irq_postinstall(&dev_priv->gt);
3694
3695         GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask,
3696                       display_mask | extra_mask);
3697 }
3698
3699 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3700 {
3701         lockdep_assert_held(&dev_priv->irq_lock);
3702
3703         if (dev_priv->display_irqs_enabled)
3704                 return;
3705
3706         dev_priv->display_irqs_enabled = true;
3707
3708         if (intel_irqs_enabled(dev_priv)) {
3709                 vlv_display_irq_reset(dev_priv);
3710                 vlv_display_irq_postinstall(dev_priv);
3711         }
3712 }
3713
3714 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3715 {
3716         lockdep_assert_held(&dev_priv->irq_lock);
3717
3718         if (!dev_priv->display_irqs_enabled)
3719                 return;
3720
3721         dev_priv->display_irqs_enabled = false;
3722
3723         if (intel_irqs_enabled(dev_priv))
3724                 vlv_display_irq_reset(dev_priv);
3725 }
3726
3727
3728 static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv)
3729 {
3730         gen5_gt_irq_postinstall(&dev_priv->gt);
3731
3732         spin_lock_irq(&dev_priv->irq_lock);
3733         if (dev_priv->display_irqs_enabled)
3734                 vlv_display_irq_postinstall(dev_priv);
3735         spin_unlock_irq(&dev_priv->irq_lock);
3736
3737         intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3738         intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER);
3739 }
3740
3741 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3742 {
3743         struct intel_uncore *uncore = &dev_priv->uncore;
3744
3745         u32 de_pipe_masked = gen8_de_pipe_fault_mask(dev_priv) |
3746                 GEN8_PIPE_CDCLK_CRC_DONE;
3747         u32 de_pipe_enables;
3748         u32 de_port_masked = gen8_de_port_aux_mask(dev_priv);
3749         u32 de_port_enables;
3750         u32 de_misc_masked = GEN8_DE_EDP_PSR;
3751         u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
3752                 BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
3753         enum pipe pipe;
3754
3755         if (!HAS_DISPLAY(dev_priv))
3756                 return;
3757
3758         if (DISPLAY_VER(dev_priv) <= 10)
3759                 de_misc_masked |= GEN8_DE_MISC_GSE;
3760
3761         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
3762                 de_port_masked |= BXT_DE_PORT_GMBUS;
3763
3764         if (DISPLAY_VER(dev_priv) >= 11) {
3765                 enum port port;
3766
3767                 if (intel_bios_is_dsi_present(dev_priv, &port))
3768                         de_port_masked |= DSI0_TE | DSI1_TE;
3769         }
3770
3771         de_pipe_enables = de_pipe_masked |
3772                 GEN8_PIPE_VBLANK |
3773                 gen8_de_pipe_underrun_mask(dev_priv) |
3774                 gen8_de_pipe_flip_done_mask(dev_priv);
3775
3776         de_port_enables = de_port_masked;
3777         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
3778                 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
3779         else if (IS_BROADWELL(dev_priv))
3780                 de_port_enables |= BDW_DE_PORT_HOTPLUG_MASK;
3781
3782         if (DISPLAY_VER(dev_priv) >= 12) {
3783                 enum transcoder trans;
3784
3785                 for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {
3786                         enum intel_display_power_domain domain;
3787
3788                         domain = POWER_DOMAIN_TRANSCODER(trans);
3789                         if (!intel_display_power_is_enabled(dev_priv, domain))
3790                                 continue;
3791
3792                         gen3_assert_iir_is_zero(uncore, TRANS_PSR_IIR(trans));
3793                 }
3794         } else {
3795                 gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
3796         }
3797
3798         for_each_pipe(dev_priv, pipe) {
3799                 dev_priv->de_irq_mask[pipe] = ~de_pipe_masked;
3800
3801                 if (intel_display_power_is_enabled(dev_priv,
3802                                 POWER_DOMAIN_PIPE(pipe)))
3803                         GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,
3804                                           dev_priv->de_irq_mask[pipe],
3805                                           de_pipe_enables);
3806         }
3807
3808         GEN3_IRQ_INIT(uncore, GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
3809         GEN3_IRQ_INIT(uncore, GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
3810
3811         if (DISPLAY_VER(dev_priv) >= 11) {
3812                 u32 de_hpd_masked = 0;
3813                 u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK |
3814                                      GEN11_DE_TBT_HOTPLUG_MASK;
3815
3816                 GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked,
3817                               de_hpd_enables);
3818         }
3819 }
3820
3821 static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
3822 {
3823         struct intel_uncore *uncore = &dev_priv->uncore;
3824         u32 mask = SDE_GMBUS_ICP;
3825
3826         GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
3827 }
3828
3829 static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
3830 {
3831         if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3832                 icp_irq_postinstall(dev_priv);
3833         else if (HAS_PCH_SPLIT(dev_priv))
3834                 ibx_irq_postinstall(dev_priv);
3835
3836         gen8_gt_irq_postinstall(&dev_priv->gt);
3837         gen8_de_irq_postinstall(dev_priv);
3838
3839         gen8_master_intr_enable(dev_priv->uncore.regs);
3840 }
3841
3842 static void gen11_de_irq_postinstall(struct drm_i915_private *dev_priv)
3843 {
3844         if (!HAS_DISPLAY(dev_priv))
3845                 return;
3846
3847         gen8_de_irq_postinstall(dev_priv);
3848
3849         intel_uncore_write(&dev_priv->uncore, GEN11_DISPLAY_INT_CTL,
3850                            GEN11_DISPLAY_IRQ_ENABLE);
3851 }
3852
3853 static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
3854 {
3855         struct intel_uncore *uncore = &dev_priv->uncore;
3856         u32 gu_misc_masked = GEN11_GU_MISC_GSE;
3857
3858         if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3859                 icp_irq_postinstall(dev_priv);
3860
3861         gen11_gt_irq_postinstall(&dev_priv->gt);
3862         gen11_de_irq_postinstall(dev_priv);
3863
3864         GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
3865
3866         if (HAS_MASTER_UNIT_IRQ(dev_priv)) {
3867                 dg1_master_intr_enable(uncore->regs);
3868                 intel_uncore_posting_read(&dev_priv->uncore, DG1_MSTR_UNIT_INTR);
3869         } else {
3870                 gen11_master_intr_enable(uncore->regs);
3871                 intel_uncore_posting_read(&dev_priv->uncore, GEN11_GFX_MSTR_IRQ);
3872         }
3873 }
3874
3875 static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
3876 {
3877         gen8_gt_irq_postinstall(&dev_priv->gt);
3878
3879         spin_lock_irq(&dev_priv->irq_lock);
3880         if (dev_priv->display_irqs_enabled)
3881                 vlv_display_irq_postinstall(dev_priv);
3882         spin_unlock_irq(&dev_priv->irq_lock);
3883
3884         intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3885         intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ);
3886 }
3887
3888 static void i8xx_irq_reset(struct drm_i915_private *dev_priv)
3889 {
3890         struct intel_uncore *uncore = &dev_priv->uncore;
3891
3892         i9xx_pipestat_irq_reset(dev_priv);
3893
3894         GEN2_IRQ_RESET(uncore);
3895         dev_priv->irq_mask = ~0u;
3896 }
3897
3898 static void i8xx_irq_postinstall(struct drm_i915_private *dev_priv)
3899 {
3900         struct intel_uncore *uncore = &dev_priv->uncore;
3901         u16 enable_mask;
3902
3903         intel_uncore_write16(uncore,
3904                              EMR,
3905                              ~(I915_ERROR_PAGE_TABLE |
3906                                I915_ERROR_MEMORY_REFRESH));
3907
3908         /* Unmask the interrupts that we always want on. */
3909         dev_priv->irq_mask =
3910                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3911                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3912                   I915_MASTER_ERROR_INTERRUPT);
3913
3914         enable_mask =
3915                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3916                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3917                 I915_MASTER_ERROR_INTERRUPT |
3918                 I915_USER_INTERRUPT;
3919
3920         GEN2_IRQ_INIT(uncore, dev_priv->irq_mask, enable_mask);
3921
3922         /* Interrupt setup is already guaranteed to be single-threaded, this is
3923          * just to make the assert_spin_locked check happy. */
3924         spin_lock_irq(&dev_priv->irq_lock);
3925         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3926         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3927         spin_unlock_irq(&dev_priv->irq_lock);
3928 }
3929
3930 static void i8xx_error_irq_ack(struct drm_i915_private *i915,
3931                                u16 *eir, u16 *eir_stuck)
3932 {
3933         struct intel_uncore *uncore = &i915->uncore;
3934         u16 emr;
3935
3936         *eir = intel_uncore_read16(uncore, EIR);
3937
3938         if (*eir)
3939                 intel_uncore_write16(uncore, EIR, *eir);
3940
3941         *eir_stuck = intel_uncore_read16(uncore, EIR);
3942         if (*eir_stuck == 0)
3943                 return;
3944
3945         /*
3946          * Toggle all EMR bits to make sure we get an edge
3947          * in the ISR master error bit if we don't clear
3948          * all the EIR bits. Otherwise the edge triggered
3949          * IIR on i965/g4x wouldn't notice that an interrupt
3950          * is still pending. Also some EIR bits can't be
3951          * cleared except by handling the underlying error
3952          * (or by a GPU reset) so we mask any bit that
3953          * remains set.
3954          */
3955         emr = intel_uncore_read16(uncore, EMR);
3956         intel_uncore_write16(uncore, EMR, 0xffff);
3957         intel_uncore_write16(uncore, EMR, emr | *eir_stuck);
3958 }
3959
3960 static void i8xx_error_irq_handler(struct drm_i915_private *dev_priv,
3961                                    u16 eir, u16 eir_stuck)
3962 {
3963         DRM_DEBUG("Master Error: EIR 0x%04x\n", eir);
3964
3965         if (eir_stuck)
3966                 drm_dbg(&dev_priv->drm, "EIR stuck: 0x%04x, masked\n",
3967                         eir_stuck);
3968 }
3969
3970 static void i9xx_error_irq_ack(struct drm_i915_private *dev_priv,
3971                                u32 *eir, u32 *eir_stuck)
3972 {
3973         u32 emr;
3974
3975         *eir = intel_uncore_read(&dev_priv->uncore, EIR);
3976
3977         intel_uncore_write(&dev_priv->uncore, EIR, *eir);
3978
3979         *eir_stuck = intel_uncore_read(&dev_priv->uncore, EIR);
3980         if (*eir_stuck == 0)
3981                 return;
3982
3983         /*
3984          * Toggle all EMR bits to make sure we get an edge
3985          * in the ISR master error bit if we don't clear
3986          * all the EIR bits. Otherwise the edge triggered
3987          * IIR on i965/g4x wouldn't notice that an interrupt
3988          * is still pending. Also some EIR bits can't be
3989          * cleared except by handling the underlying error
3990          * (or by a GPU reset) so we mask any bit that
3991          * remains set.
3992          */
3993         emr = intel_uncore_read(&dev_priv->uncore, EMR);
3994         intel_uncore_write(&dev_priv->uncore, EMR, 0xffffffff);
3995         intel_uncore_write(&dev_priv->uncore, EMR, emr | *eir_stuck);
3996 }
3997
3998 static void i9xx_error_irq_handler(struct drm_i915_private *dev_priv,
3999                                    u32 eir, u32 eir_stuck)
4000 {
4001         DRM_DEBUG("Master Error, EIR 0x%08x\n", eir);
4002
4003         if (eir_stuck)
4004                 drm_dbg(&dev_priv->drm, "EIR stuck: 0x%08x, masked\n",
4005                         eir_stuck);
4006 }
4007
4008 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
4009 {
4010         struct drm_i915_private *dev_priv = arg;
4011         irqreturn_t ret = IRQ_NONE;
4012
4013         if (!intel_irqs_enabled(dev_priv))
4014                 return IRQ_NONE;
4015
4016         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4017         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4018
4019         do {
4020                 u32 pipe_stats[I915_MAX_PIPES] = {};
4021                 u16 eir = 0, eir_stuck = 0;
4022                 u16 iir;
4023
4024                 iir = intel_uncore_read16(&dev_priv->uncore, GEN2_IIR);
4025                 if (iir == 0)
4026                         break;
4027
4028                 ret = IRQ_HANDLED;
4029
4030                 /* Call regardless, as some status bits might not be
4031                  * signalled in iir */
4032                 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
4033
4034                 if (iir & I915_MASTER_ERROR_INTERRUPT)
4035                         i8xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
4036
4037                 intel_uncore_write16(&dev_priv->uncore, GEN2_IIR, iir);
4038
4039                 if (iir & I915_USER_INTERRUPT)
4040                         intel_engine_cs_irq(dev_priv->gt.engine[RCS0], iir);
4041
4042                 if (iir & I915_MASTER_ERROR_INTERRUPT)
4043                         i8xx_error_irq_handler(dev_priv, eir, eir_stuck);
4044
4045                 i8xx_pipestat_irq_handler(dev_priv, iir, pipe_stats);
4046         } while (0);
4047
4048         pmu_irq_stats(dev_priv, ret);
4049
4050         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4051
4052         return ret;
4053 }
4054
4055 static void i915_irq_reset(struct drm_i915_private *dev_priv)
4056 {
4057         struct intel_uncore *uncore = &dev_priv->uncore;
4058
4059         if (I915_HAS_HOTPLUG(dev_priv)) {
4060                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4061                 intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_STAT, intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT));
4062         }
4063
4064         i9xx_pipestat_irq_reset(dev_priv);
4065
4066         GEN3_IRQ_RESET(uncore, GEN2_);
4067         dev_priv->irq_mask = ~0u;
4068 }
4069
4070 static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
4071 {
4072         struct intel_uncore *uncore = &dev_priv->uncore;
4073         u32 enable_mask;
4074
4075         intel_uncore_write(&dev_priv->uncore, EMR, ~(I915_ERROR_PAGE_TABLE |
4076                           I915_ERROR_MEMORY_REFRESH));
4077
4078         /* Unmask the interrupts that we always want on. */
4079         dev_priv->irq_mask =
4080                 ~(I915_ASLE_INTERRUPT |
4081                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4082                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4083                   I915_MASTER_ERROR_INTERRUPT);
4084
4085         enable_mask =
4086                 I915_ASLE_INTERRUPT |
4087                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4088                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4089                 I915_MASTER_ERROR_INTERRUPT |
4090                 I915_USER_INTERRUPT;
4091
4092         if (I915_HAS_HOTPLUG(dev_priv)) {
4093                 /* Enable in IER... */
4094                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
4095                 /* and unmask in IMR */
4096                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
4097         }
4098
4099         GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);
4100
4101         /* Interrupt setup is already guaranteed to be single-threaded, this is
4102          * just to make the assert_spin_locked check happy. */
4103         spin_lock_irq(&dev_priv->irq_lock);
4104         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4105         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4106         spin_unlock_irq(&dev_priv->irq_lock);
4107
4108         i915_enable_asle_pipestat(dev_priv);
4109 }
4110
4111 static irqreturn_t i915_irq_handler(int irq, void *arg)
4112 {
4113         struct drm_i915_private *dev_priv = arg;
4114         irqreturn_t ret = IRQ_NONE;
4115
4116         if (!intel_irqs_enabled(dev_priv))
4117                 return IRQ_NONE;
4118
4119         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4120         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4121
4122         do {
4123                 u32 pipe_stats[I915_MAX_PIPES] = {};
4124                 u32 eir = 0, eir_stuck = 0;
4125                 u32 hotplug_status = 0;
4126                 u32 iir;
4127
4128                 iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);
4129                 if (iir == 0)
4130                         break;
4131
4132                 ret = IRQ_HANDLED;
4133
4134                 if (I915_HAS_HOTPLUG(dev_priv) &&
4135                     iir & I915_DISPLAY_PORT_INTERRUPT)
4136                         hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4137
4138                 /* Call regardless, as some status bits might not be
4139                  * signalled in iir */
4140                 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
4141
4142                 if (iir & I915_MASTER_ERROR_INTERRUPT)
4143                         i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
4144
4145                 intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir);
4146
4147                 if (iir & I915_USER_INTERRUPT)
4148                         intel_engine_cs_irq(dev_priv->gt.engine[RCS0], iir);
4149
4150                 if (iir & I915_MASTER_ERROR_INTERRUPT)
4151                         i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
4152
4153                 if (hotplug_status)
4154                         i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4155
4156                 i915_pipestat_irq_handler(dev_priv, iir, pipe_stats);
4157         } while (0);
4158
4159         pmu_irq_stats(dev_priv, ret);
4160
4161         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4162
4163         return ret;
4164 }
4165
4166 static void i965_irq_reset(struct drm_i915_private *dev_priv)
4167 {
4168         struct intel_uncore *uncore = &dev_priv->uncore;
4169
4170         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4171         intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_STAT, intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT));
4172
4173         i9xx_pipestat_irq_reset(dev_priv);
4174
4175         GEN3_IRQ_RESET(uncore, GEN2_);
4176         dev_priv->irq_mask = ~0u;
4177 }
4178
4179 static void i965_irq_postinstall(struct drm_i915_private *dev_priv)
4180 {
4181         struct intel_uncore *uncore = &dev_priv->uncore;
4182         u32 enable_mask;
4183         u32 error_mask;
4184
4185         /*
4186          * Enable some error detection, note the instruction error mask
4187          * bit is reserved, so we leave it masked.
4188          */
4189         if (IS_G4X(dev_priv)) {
4190                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4191                                GM45_ERROR_MEM_PRIV |
4192                                GM45_ERROR_CP_PRIV |
4193                                I915_ERROR_MEMORY_REFRESH);
4194         } else {
4195                 error_mask = ~(I915_ERROR_PAGE_TABLE |
4196                                I915_ERROR_MEMORY_REFRESH);
4197         }
4198         intel_uncore_write(&dev_priv->uncore, EMR, error_mask);
4199
4200         /* Unmask the interrupts that we always want on. */
4201         dev_priv->irq_mask =
4202                 ~(I915_ASLE_INTERRUPT |
4203                   I915_DISPLAY_PORT_INTERRUPT |
4204                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4205                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4206                   I915_MASTER_ERROR_INTERRUPT);
4207
4208         enable_mask =
4209                 I915_ASLE_INTERRUPT |
4210                 I915_DISPLAY_PORT_INTERRUPT |
4211                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4212                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4213                 I915_MASTER_ERROR_INTERRUPT |
4214                 I915_USER_INTERRUPT;
4215
4216         if (IS_G4X(dev_priv))
4217                 enable_mask |= I915_BSD_USER_INTERRUPT;
4218
4219         GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);
4220
4221         /* Interrupt setup is already guaranteed to be single-threaded, this is
4222          * just to make the assert_spin_locked check happy. */
4223         spin_lock_irq(&dev_priv->irq_lock);
4224         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4225         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4226         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4227         spin_unlock_irq(&dev_priv->irq_lock);
4228
4229         i915_enable_asle_pipestat(dev_priv);
4230 }
4231
4232 static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
4233 {
4234         u32 hotplug_en;
4235
4236         lockdep_assert_held(&dev_priv->irq_lock);
4237
4238         /* Note HDMI and DP share hotplug bits */
4239         /* enable bits are the same for all generations */
4240         hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);
4241         /* Programming the CRT detection parameters tends
4242            to generate a spurious hotplug event about three
4243            seconds later.  So just do it once.
4244         */
4245         if (IS_G4X(dev_priv))
4246                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4247         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4248
4249         /* Ignore TV since it's buggy */
4250         i915_hotplug_interrupt_update_locked(dev_priv,
4251                                              HOTPLUG_INT_EN_MASK |
4252                                              CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
4253                                              CRT_HOTPLUG_ACTIVATION_PERIOD_64,
4254                                              hotplug_en);
4255 }
4256
4257 static irqreturn_t i965_irq_handler(int irq, void *arg)
4258 {
4259         struct drm_i915_private *dev_priv = arg;
4260         irqreturn_t ret = IRQ_NONE;
4261
4262         if (!intel_irqs_enabled(dev_priv))
4263                 return IRQ_NONE;
4264
4265         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4266         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4267
4268         do {
4269                 u32 pipe_stats[I915_MAX_PIPES] = {};
4270                 u32 eir = 0, eir_stuck = 0;
4271                 u32 hotplug_status = 0;
4272                 u32 iir;
4273
4274                 iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);
4275                 if (iir == 0)
4276                         break;
4277
4278                 ret = IRQ_HANDLED;
4279
4280                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
4281                         hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4282
4283                 /* Call regardless, as some status bits might not be
4284                  * signalled in iir */
4285                 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
4286
4287                 if (iir & I915_MASTER_ERROR_INTERRUPT)
4288                         i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
4289
4290                 intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir);
4291
4292                 if (iir & I915_USER_INTERRUPT)
4293                         intel_engine_cs_irq(dev_priv->gt.engine[RCS0],
4294                                             iir);
4295
4296                 if (iir & I915_BSD_USER_INTERRUPT)
4297                         intel_engine_cs_irq(dev_priv->gt.engine[VCS0],
4298                                             iir >> 25);
4299
4300                 if (iir & I915_MASTER_ERROR_INTERRUPT)
4301                         i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
4302
4303                 if (hotplug_status)
4304                         i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4305
4306                 i965_pipestat_irq_handler(dev_priv, iir, pipe_stats);
4307         } while (0);
4308
4309         pmu_irq_stats(dev_priv, IRQ_HANDLED);
4310
4311         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4312
4313         return ret;
4314 }
4315
4316 /**
4317  * intel_irq_init - initializes irq support
4318  * @dev_priv: i915 device instance
4319  *
4320  * This function initializes all the irq support including work items, timers
4321  * and all the vtables. It does not setup the interrupt itself though.
4322  */
4323 void intel_irq_init(struct drm_i915_private *dev_priv)
4324 {
4325         struct drm_device *dev = &dev_priv->drm;
4326         int i;
4327
4328         INIT_WORK(&dev_priv->l3_parity.error_work, ivb_parity_work);
4329         for (i = 0; i < MAX_L3_SLICES; ++i)
4330                 dev_priv->l3_parity.remap_info[i] = NULL;
4331
4332         /* pre-gen11 the guc irqs bits are in the upper 16 bits of the pm reg */
4333         if (HAS_GT_UC(dev_priv) && GRAPHICS_VER(dev_priv) < 11)
4334                 dev_priv->gt.pm_guc_events = GUC_INTR_GUC2HOST << 16;
4335
4336         if (!HAS_DISPLAY(dev_priv))
4337                 return;
4338
4339         intel_hpd_init_pins(dev_priv);
4340
4341         intel_hpd_init_work(dev_priv);
4342
4343         dev->vblank_disable_immediate = true;
4344
4345         /* Most platforms treat the display irq block as an always-on
4346          * power domain. vlv/chv can disable it at runtime and need
4347          * special care to avoid writing any of the display block registers
4348          * outside of the power domain. We defer setting up the display irqs
4349          * in this case to the runtime pm.
4350          */
4351         dev_priv->display_irqs_enabled = true;
4352         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4353                 dev_priv->display_irqs_enabled = false;
4354
4355         dev_priv->hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD;
4356         /* If we have MST support, we want to avoid doing short HPD IRQ storm
4357          * detection, as short HPD storms will occur as a natural part of
4358          * sideband messaging with MST.
4359          * On older platforms however, IRQ storms can occur with both long and
4360          * short pulses, as seen on some G4x systems.
4361          */
4362         dev_priv->hotplug.hpd_short_storm_enabled = !HAS_DP_MST(dev_priv);
4363
4364         if (HAS_GMCH(dev_priv)) {
4365                 if (I915_HAS_HOTPLUG(dev_priv))
4366                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4367         } else {
4368                 if (HAS_PCH_DG1(dev_priv))
4369                         dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup;
4370                 else if (DISPLAY_VER(dev_priv) >= 11)
4371                         dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
4372                 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
4373                         dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4374                 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
4375                         dev_priv->display.hpd_irq_setup = icp_hpd_irq_setup;
4376                 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
4377                         dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4378                 else
4379                         dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4380         }
4381 }
4382
4383 /**
4384  * intel_irq_fini - deinitializes IRQ support
4385  * @i915: i915 device instance
4386  *
4387  * This function deinitializes all the IRQ support.
4388  */
4389 void intel_irq_fini(struct drm_i915_private *i915)
4390 {
4391         int i;
4392
4393         for (i = 0; i < MAX_L3_SLICES; ++i)
4394                 kfree(i915->l3_parity.remap_info[i]);
4395 }
4396
4397 static irq_handler_t intel_irq_handler(struct drm_i915_private *dev_priv)
4398 {
4399         if (HAS_GMCH(dev_priv)) {
4400                 if (IS_CHERRYVIEW(dev_priv))
4401                         return cherryview_irq_handler;
4402                 else if (IS_VALLEYVIEW(dev_priv))
4403                         return valleyview_irq_handler;
4404                 else if (GRAPHICS_VER(dev_priv) == 4)
4405                         return i965_irq_handler;
4406                 else if (GRAPHICS_VER(dev_priv) == 3)
4407                         return i915_irq_handler;
4408                 else
4409                         return i8xx_irq_handler;
4410         } else {
4411                 if (HAS_MASTER_UNIT_IRQ(dev_priv))
4412                         return dg1_irq_handler;
4413                 if (GRAPHICS_VER(dev_priv) >= 11)
4414                         return gen11_irq_handler;
4415                 else if (GRAPHICS_VER(dev_priv) >= 8)
4416                         return gen8_irq_handler;
4417                 else
4418                         return ilk_irq_handler;
4419         }
4420 }
4421
4422 static void intel_irq_reset(struct drm_i915_private *dev_priv)
4423 {
4424         if (HAS_GMCH(dev_priv)) {
4425                 if (IS_CHERRYVIEW(dev_priv))
4426                         cherryview_irq_reset(dev_priv);
4427                 else if (IS_VALLEYVIEW(dev_priv))
4428                         valleyview_irq_reset(dev_priv);
4429                 else if (GRAPHICS_VER(dev_priv) == 4)
4430                         i965_irq_reset(dev_priv);
4431                 else if (GRAPHICS_VER(dev_priv) == 3)
4432                         i915_irq_reset(dev_priv);
4433                 else
4434                         i8xx_irq_reset(dev_priv);
4435         } else {
4436                 if (GRAPHICS_VER(dev_priv) >= 11)
4437                         gen11_irq_reset(dev_priv);
4438                 else if (GRAPHICS_VER(dev_priv) >= 8)
4439                         gen8_irq_reset(dev_priv);
4440                 else
4441                         ilk_irq_reset(dev_priv);
4442         }
4443 }
4444
4445 static void intel_irq_postinstall(struct drm_i915_private *dev_priv)
4446 {
4447         if (HAS_GMCH(dev_priv)) {
4448                 if (IS_CHERRYVIEW(dev_priv))
4449                         cherryview_irq_postinstall(dev_priv);
4450                 else if (IS_VALLEYVIEW(dev_priv))
4451                         valleyview_irq_postinstall(dev_priv);
4452                 else if (GRAPHICS_VER(dev_priv) == 4)
4453                         i965_irq_postinstall(dev_priv);
4454                 else if (GRAPHICS_VER(dev_priv) == 3)
4455                         i915_irq_postinstall(dev_priv);
4456                 else
4457                         i8xx_irq_postinstall(dev_priv);
4458         } else {
4459                 if (GRAPHICS_VER(dev_priv) >= 11)
4460                         gen11_irq_postinstall(dev_priv);
4461                 else if (GRAPHICS_VER(dev_priv) >= 8)
4462                         gen8_irq_postinstall(dev_priv);
4463                 else
4464                         ilk_irq_postinstall(dev_priv);
4465         }
4466 }
4467
4468 /**
4469  * intel_irq_install - enables the hardware interrupt
4470  * @dev_priv: i915 device instance
4471  *
4472  * This function enables the hardware interrupt handling, but leaves the hotplug
4473  * handling still disabled. It is called after intel_irq_init().
4474  *
4475  * In the driver load and resume code we need working interrupts in a few places
4476  * but don't want to deal with the hassle of concurrent probe and hotplug
4477  * workers. Hence the split into this two-stage approach.
4478  */
4479 int intel_irq_install(struct drm_i915_private *dev_priv)
4480 {
4481         int irq = to_pci_dev(dev_priv->drm.dev)->irq;
4482         int ret;
4483
4484         /*
4485          * We enable some interrupt sources in our postinstall hooks, so mark
4486          * interrupts as enabled _before_ actually enabling them to avoid
4487          * special cases in our ordering checks.
4488          */
4489         dev_priv->runtime_pm.irqs_enabled = true;
4490
4491         dev_priv->drm.irq_enabled = true;
4492
4493         intel_irq_reset(dev_priv);
4494
4495         ret = request_irq(irq, intel_irq_handler(dev_priv),
4496                           IRQF_SHARED, DRIVER_NAME, dev_priv);
4497         if (ret < 0) {
4498                 dev_priv->drm.irq_enabled = false;
4499                 return ret;
4500         }
4501
4502         intel_irq_postinstall(dev_priv);
4503
4504         return ret;
4505 }
4506
4507 /**
4508  * intel_irq_uninstall - finilizes all irq handling
4509  * @dev_priv: i915 device instance
4510  *
4511  * This stops interrupt and hotplug handling and unregisters and frees all
4512  * resources acquired in the init functions.
4513  */
4514 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4515 {
4516         int irq = to_pci_dev(dev_priv->drm.dev)->irq;
4517
4518         /*
4519          * FIXME we can get called twice during driver probe
4520          * error handling as well as during driver remove due to
4521          * intel_modeset_driver_remove() calling us out of sequence.
4522          * Would be nice if it didn't do that...
4523          */
4524         if (!dev_priv->drm.irq_enabled)
4525                 return;
4526
4527         dev_priv->drm.irq_enabled = false;
4528
4529         intel_irq_reset(dev_priv);
4530
4531         free_irq(irq, dev_priv);
4532
4533         intel_hpd_cancel_work(dev_priv);
4534         dev_priv->runtime_pm.irqs_enabled = false;
4535 }
4536
4537 /**
4538  * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4539  * @dev_priv: i915 device instance
4540  *
4541  * This function is used to disable interrupts at runtime, both in the runtime
4542  * pm and the system suspend/resume code.
4543  */
4544 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4545 {
4546         intel_irq_reset(dev_priv);
4547         dev_priv->runtime_pm.irqs_enabled = false;
4548         intel_synchronize_irq(dev_priv);
4549 }
4550
4551 /**
4552  * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4553  * @dev_priv: i915 device instance
4554  *
4555  * This function is used to enable interrupts at runtime, both in the runtime
4556  * pm and the system suspend/resume code.
4557  */
4558 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4559 {
4560         dev_priv->runtime_pm.irqs_enabled = true;
4561         intel_irq_reset(dev_priv);
4562         intel_irq_postinstall(dev_priv);
4563 }
4564
4565 bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
4566 {
4567         /*
4568          * We only use drm_irq_uninstall() at unload and VT switch, so
4569          * this is the only thing we need to check.
4570          */
4571         return dev_priv->runtime_pm.irqs_enabled;
4572 }
4573
4574 void intel_synchronize_irq(struct drm_i915_private *i915)
4575 {
4576         synchronize_irq(to_pci_dev(i915->drm.dev)->irq);
4577 }