1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/circ_buf.h>
32 #include <linux/slab.h>
33 #include <linux/sysrq.h>
35 #include <drm/drm_drv.h>
36 #include <drm/drm_irq.h>
38 #include "display/intel_display_types.h"
39 #include "display/intel_fifo_underrun.h"
40 #include "display/intel_hotplug.h"
41 #include "display/intel_lpe_audio.h"
42 #include "display/intel_psr.h"
44 #include "gt/intel_breadcrumbs.h"
45 #include "gt/intel_gt.h"
46 #include "gt/intel_gt_irq.h"
47 #include "gt/intel_gt_pm_irq.h"
48 #include "gt/intel_rps.h"
52 #include "i915_trace.h"
56 * DOC: interrupt handling
58 * These functions provide the basic support for enabling and disabling the
59 * interrupt handling support. There's a lot more functionality in i915_irq.c
60 * and related files, but that will be described in separate chapters.
64 * Interrupt statistic for PMU. Increments the counter only if the
65 * interrupt originated from the the GPU so interrupts from a device which
66 * shares the interrupt line are not accounted.
68 static inline void pmu_irq_stats(struct drm_i915_private *i915,
71 if (unlikely(res != IRQ_HANDLED))
75 * A clever compiler translates that into INC. A not so clever one
76 * should at least prevent store tearing.
78 WRITE_ONCE(i915->pmu.irq_count, i915->pmu.irq_count + 1);
81 typedef bool (*long_pulse_detect_func)(enum hpd_pin pin, u32 val);
82 typedef u32 (*hotplug_enables_func)(struct drm_i915_private *i915,
85 static const u32 hpd_ilk[HPD_NUM_PINS] = {
86 [HPD_PORT_A] = DE_DP_A_HOTPLUG,
89 static const u32 hpd_ivb[HPD_NUM_PINS] = {
90 [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
93 static const u32 hpd_bdw[HPD_NUM_PINS] = {
94 [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A),
97 static const u32 hpd_ibx[HPD_NUM_PINS] = {
98 [HPD_CRT] = SDE_CRT_HOTPLUG,
99 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
100 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
101 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
102 [HPD_PORT_D] = SDE_PORTD_HOTPLUG,
105 static const u32 hpd_cpt[HPD_NUM_PINS] = {
106 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
107 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
108 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
109 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
110 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
113 static const u32 hpd_spt[HPD_NUM_PINS] = {
114 [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
115 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
116 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
117 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
118 [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT,
121 static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
122 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
123 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
124 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
125 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
126 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
127 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN,
130 static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
131 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
132 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
133 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
134 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
135 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
136 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS,
139 static const u32 hpd_status_i915[HPD_NUM_PINS] = {
140 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
141 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
142 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
143 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
144 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
145 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS,
148 static const u32 hpd_bxt[HPD_NUM_PINS] = {
149 [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A),
150 [HPD_PORT_B] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_B),
151 [HPD_PORT_C] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_C),
154 static const u32 hpd_gen11[HPD_NUM_PINS] = {
155 [HPD_PORT_TC1] = GEN11_TC_HOTPLUG(HPD_PORT_TC1) | GEN11_TBT_HOTPLUG(HPD_PORT_TC1),
156 [HPD_PORT_TC2] = GEN11_TC_HOTPLUG(HPD_PORT_TC2) | GEN11_TBT_HOTPLUG(HPD_PORT_TC2),
157 [HPD_PORT_TC3] = GEN11_TC_HOTPLUG(HPD_PORT_TC3) | GEN11_TBT_HOTPLUG(HPD_PORT_TC3),
158 [HPD_PORT_TC4] = GEN11_TC_HOTPLUG(HPD_PORT_TC4) | GEN11_TBT_HOTPLUG(HPD_PORT_TC4),
159 [HPD_PORT_TC5] = GEN11_TC_HOTPLUG(HPD_PORT_TC5) | GEN11_TBT_HOTPLUG(HPD_PORT_TC5),
160 [HPD_PORT_TC6] = GEN11_TC_HOTPLUG(HPD_PORT_TC6) | GEN11_TBT_HOTPLUG(HPD_PORT_TC6),
163 static const u32 hpd_icp[HPD_NUM_PINS] = {
164 [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
165 [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
166 [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
167 [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1),
168 [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2),
169 [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3),
170 [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4),
171 [HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5),
172 [HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6),
175 static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
176 [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
177 [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
178 [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
179 [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_D),
182 static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
184 struct i915_hotplug *hpd = &dev_priv->hotplug;
186 if (HAS_GMCH(dev_priv)) {
187 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
188 IS_CHERRYVIEW(dev_priv))
189 hpd->hpd = hpd_status_g4x;
191 hpd->hpd = hpd_status_i915;
195 if (DISPLAY_VER(dev_priv) >= 11)
196 hpd->hpd = hpd_gen11;
197 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
199 else if (DISPLAY_VER(dev_priv) >= 8)
201 else if (DISPLAY_VER(dev_priv) >= 7)
206 if ((INTEL_PCH_TYPE(dev_priv) < PCH_DG1) &&
207 (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)))
210 if (HAS_PCH_DG1(dev_priv))
211 hpd->pch_hpd = hpd_sde_dg1;
212 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
213 hpd->pch_hpd = hpd_icp;
214 else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv))
215 hpd->pch_hpd = hpd_spt;
216 else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_CPT(dev_priv))
217 hpd->pch_hpd = hpd_cpt;
218 else if (HAS_PCH_IBX(dev_priv))
219 hpd->pch_hpd = hpd_ibx;
221 MISSING_CASE(INTEL_PCH_TYPE(dev_priv));
225 intel_handle_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
227 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
229 drm_crtc_handle_vblank(&crtc->base);
232 void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
233 i915_reg_t iir, i915_reg_t ier)
235 intel_uncore_write(uncore, imr, 0xffffffff);
236 intel_uncore_posting_read(uncore, imr);
238 intel_uncore_write(uncore, ier, 0);
240 /* IIR can theoretically queue up two events. Be paranoid. */
241 intel_uncore_write(uncore, iir, 0xffffffff);
242 intel_uncore_posting_read(uncore, iir);
243 intel_uncore_write(uncore, iir, 0xffffffff);
244 intel_uncore_posting_read(uncore, iir);
247 void gen2_irq_reset(struct intel_uncore *uncore)
249 intel_uncore_write16(uncore, GEN2_IMR, 0xffff);
250 intel_uncore_posting_read16(uncore, GEN2_IMR);
252 intel_uncore_write16(uncore, GEN2_IER, 0);
254 /* IIR can theoretically queue up two events. Be paranoid. */
255 intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
256 intel_uncore_posting_read16(uncore, GEN2_IIR);
257 intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
258 intel_uncore_posting_read16(uncore, GEN2_IIR);
262 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
264 static void gen3_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg)
266 u32 val = intel_uncore_read(uncore, reg);
271 drm_WARN(&uncore->i915->drm, 1,
272 "Interrupt register 0x%x is not zero: 0x%08x\n",
273 i915_mmio_reg_offset(reg), val);
274 intel_uncore_write(uncore, reg, 0xffffffff);
275 intel_uncore_posting_read(uncore, reg);
276 intel_uncore_write(uncore, reg, 0xffffffff);
277 intel_uncore_posting_read(uncore, reg);
280 static void gen2_assert_iir_is_zero(struct intel_uncore *uncore)
282 u16 val = intel_uncore_read16(uncore, GEN2_IIR);
287 drm_WARN(&uncore->i915->drm, 1,
288 "Interrupt register 0x%x is not zero: 0x%08x\n",
289 i915_mmio_reg_offset(GEN2_IIR), val);
290 intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
291 intel_uncore_posting_read16(uncore, GEN2_IIR);
292 intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
293 intel_uncore_posting_read16(uncore, GEN2_IIR);
296 void gen3_irq_init(struct intel_uncore *uncore,
297 i915_reg_t imr, u32 imr_val,
298 i915_reg_t ier, u32 ier_val,
301 gen3_assert_iir_is_zero(uncore, iir);
303 intel_uncore_write(uncore, ier, ier_val);
304 intel_uncore_write(uncore, imr, imr_val);
305 intel_uncore_posting_read(uncore, imr);
308 void gen2_irq_init(struct intel_uncore *uncore,
309 u32 imr_val, u32 ier_val)
311 gen2_assert_iir_is_zero(uncore);
313 intel_uncore_write16(uncore, GEN2_IER, ier_val);
314 intel_uncore_write16(uncore, GEN2_IMR, imr_val);
315 intel_uncore_posting_read16(uncore, GEN2_IMR);
318 /* For display hotplug interrupt */
320 i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
326 lockdep_assert_held(&dev_priv->irq_lock);
327 drm_WARN_ON(&dev_priv->drm, bits & ~mask);
329 val = intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_EN);
332 intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_EN, val);
336 * i915_hotplug_interrupt_update - update hotplug interrupt enable
337 * @dev_priv: driver private
338 * @mask: bits to update
339 * @bits: bits to enable
340 * NOTE: the HPD enable bits are modified both inside and outside
341 * of an interrupt context. To avoid that read-modify-write cycles
342 * interfer, these bits are protected by a spinlock. Since this
343 * function is usually not called from a context where the lock is
344 * held already, this function acquires the lock itself. A non-locking
345 * version is also available.
347 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
351 spin_lock_irq(&dev_priv->irq_lock);
352 i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
353 spin_unlock_irq(&dev_priv->irq_lock);
357 * ilk_update_display_irq - update DEIMR
358 * @dev_priv: driver private
359 * @interrupt_mask: mask of interrupt bits to update
360 * @enabled_irq_mask: mask of interrupt bits to enable
362 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
364 u32 enabled_irq_mask)
368 lockdep_assert_held(&dev_priv->irq_lock);
369 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
371 new_val = dev_priv->irq_mask;
372 new_val &= ~interrupt_mask;
373 new_val |= (~enabled_irq_mask & interrupt_mask);
375 if (new_val != dev_priv->irq_mask &&
376 !drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) {
377 dev_priv->irq_mask = new_val;
378 intel_uncore_write(&dev_priv->uncore, DEIMR, dev_priv->irq_mask);
379 intel_uncore_posting_read(&dev_priv->uncore, DEIMR);
384 * bdw_update_port_irq - update DE port interrupt
385 * @dev_priv: driver private
386 * @interrupt_mask: mask of interrupt bits to update
387 * @enabled_irq_mask: mask of interrupt bits to enable
389 static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
391 u32 enabled_irq_mask)
396 lockdep_assert_held(&dev_priv->irq_lock);
398 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
400 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
403 old_val = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IMR);
406 new_val &= ~interrupt_mask;
407 new_val |= (~enabled_irq_mask & interrupt_mask);
409 if (new_val != old_val) {
410 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PORT_IMR, new_val);
411 intel_uncore_posting_read(&dev_priv->uncore, GEN8_DE_PORT_IMR);
416 * bdw_update_pipe_irq - update DE pipe interrupt
417 * @dev_priv: driver private
418 * @pipe: pipe whose interrupt to update
419 * @interrupt_mask: mask of interrupt bits to update
420 * @enabled_irq_mask: mask of interrupt bits to enable
422 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
425 u32 enabled_irq_mask)
429 lockdep_assert_held(&dev_priv->irq_lock);
431 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
433 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
436 new_val = dev_priv->de_irq_mask[pipe];
437 new_val &= ~interrupt_mask;
438 new_val |= (~enabled_irq_mask & interrupt_mask);
440 if (new_val != dev_priv->de_irq_mask[pipe]) {
441 dev_priv->de_irq_mask[pipe] = new_val;
442 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
443 intel_uncore_posting_read(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe));
448 * ibx_display_interrupt_update - update SDEIMR
449 * @dev_priv: driver private
450 * @interrupt_mask: mask of interrupt bits to update
451 * @enabled_irq_mask: mask of interrupt bits to enable
453 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
455 u32 enabled_irq_mask)
457 u32 sdeimr = intel_uncore_read(&dev_priv->uncore, SDEIMR);
458 sdeimr &= ~interrupt_mask;
459 sdeimr |= (~enabled_irq_mask & interrupt_mask);
461 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
463 lockdep_assert_held(&dev_priv->irq_lock);
465 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
468 intel_uncore_write(&dev_priv->uncore, SDEIMR, sdeimr);
469 intel_uncore_posting_read(&dev_priv->uncore, SDEIMR);
472 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
475 u32 status_mask = dev_priv->pipestat_irq_mask[pipe];
476 u32 enable_mask = status_mask << 16;
478 lockdep_assert_held(&dev_priv->irq_lock);
480 if (DISPLAY_VER(dev_priv) < 5)
484 * On pipe A we don't support the PSR interrupt yet,
485 * on pipe B and C the same bit MBZ.
487 if (drm_WARN_ON_ONCE(&dev_priv->drm,
488 status_mask & PIPE_A_PSR_STATUS_VLV))
491 * On pipe B and C we don't support the PSR interrupt yet, on pipe
492 * A the same bit is for perf counters which we don't use either.
494 if (drm_WARN_ON_ONCE(&dev_priv->drm,
495 status_mask & PIPE_B_PSR_STATUS_VLV))
498 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
499 SPRITE0_FLIP_DONE_INT_EN_VLV |
500 SPRITE1_FLIP_DONE_INT_EN_VLV);
501 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
502 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
503 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
504 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
507 drm_WARN_ONCE(&dev_priv->drm,
508 enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
509 status_mask & ~PIPESTAT_INT_STATUS_MASK,
510 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
511 pipe_name(pipe), enable_mask, status_mask);
516 void i915_enable_pipestat(struct drm_i915_private *dev_priv,
517 enum pipe pipe, u32 status_mask)
519 i915_reg_t reg = PIPESTAT(pipe);
522 drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,
523 "pipe %c: status_mask=0x%x\n",
524 pipe_name(pipe), status_mask);
526 lockdep_assert_held(&dev_priv->irq_lock);
527 drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv));
529 if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == status_mask)
532 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
533 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
535 intel_uncore_write(&dev_priv->uncore, reg, enable_mask | status_mask);
536 intel_uncore_posting_read(&dev_priv->uncore, reg);
539 void i915_disable_pipestat(struct drm_i915_private *dev_priv,
540 enum pipe pipe, u32 status_mask)
542 i915_reg_t reg = PIPESTAT(pipe);
545 drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,
546 "pipe %c: status_mask=0x%x\n",
547 pipe_name(pipe), status_mask);
549 lockdep_assert_held(&dev_priv->irq_lock);
550 drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv));
552 if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == 0)
555 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
556 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
558 intel_uncore_write(&dev_priv->uncore, reg, enable_mask | status_mask);
559 intel_uncore_posting_read(&dev_priv->uncore, reg);
562 static bool i915_has_asle(struct drm_i915_private *dev_priv)
564 if (!dev_priv->opregion.asle)
567 return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
571 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
572 * @dev_priv: i915 device private
574 static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
576 if (!i915_has_asle(dev_priv))
579 spin_lock_irq(&dev_priv->irq_lock);
581 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
582 if (DISPLAY_VER(dev_priv) >= 4)
583 i915_enable_pipestat(dev_priv, PIPE_A,
584 PIPE_LEGACY_BLC_EVENT_STATUS);
586 spin_unlock_irq(&dev_priv->irq_lock);
590 * This timing diagram depicts the video signal in and
591 * around the vertical blanking period.
593 * Assumptions about the fictitious mode used in this example:
595 * vsync_start = vblank_start + 1
596 * vsync_end = vblank_start + 2
597 * vtotal = vblank_start + 3
600 * latch double buffered registers
601 * increment frame counter (ctg+)
602 * generate start of vblank interrupt (gen4+)
605 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
606 * | may be shifted forward 1-3 extra lines via PIPECONF
608 * | | start of vsync:
609 * | | generate vsync interrupt
611 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
612 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
613 * ----va---> <-----------------vb--------------------> <--------va-------------
614 * | | <----vs-----> |
615 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
616 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
617 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
619 * last visible pixel first visible pixel
620 * | increment frame counter (gen3/4)
621 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
623 * x = horizontal active
624 * _ = horizontal blanking
625 * hs = horizontal sync
626 * va = vertical active
627 * vb = vertical blanking
629 * vbs = vblank_start (number)
632 * - most events happen at the start of horizontal sync
633 * - frame start happens at the start of horizontal blank, 1-4 lines
634 * (depending on PIPECONF settings) after the start of vblank
635 * - gen3/4 pixel and frame counter are synchronized with the start
636 * of horizontal active on the first line of vertical active
639 /* Called from drm generic code, passed a 'crtc', which
640 * we use as a pipe index
642 u32 i915_get_vblank_counter(struct drm_crtc *crtc)
644 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
645 struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)];
646 const struct drm_display_mode *mode = &vblank->hwmode;
647 enum pipe pipe = to_intel_crtc(crtc)->pipe;
648 i915_reg_t high_frame, low_frame;
649 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
650 unsigned long irqflags;
653 * On i965gm TV output the frame counter only works up to
654 * the point when we enable the TV encoder. After that the
655 * frame counter ceases to work and reads zero. We need a
656 * vblank wait before enabling the TV encoder and so we
657 * have to enable vblank interrupts while the frame counter
658 * is still in a working state. However the core vblank code
659 * does not like us returning non-zero frame counter values
660 * when we've told it that we don't have a working frame
661 * counter. Thus we must stop non-zero values leaking out.
663 if (!vblank->max_vblank_count)
666 htotal = mode->crtc_htotal;
667 hsync_start = mode->crtc_hsync_start;
668 vbl_start = mode->crtc_vblank_start;
669 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
670 vbl_start = DIV_ROUND_UP(vbl_start, 2);
672 /* Convert to pixel count */
675 /* Start of vblank event occurs at start of hsync */
676 vbl_start -= htotal - hsync_start;
678 high_frame = PIPEFRAME(pipe);
679 low_frame = PIPEFRAMEPIXEL(pipe);
681 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
684 * High & low register fields aren't synchronized, so make sure
685 * we get a low value that's stable across two reads of the high
689 high1 = intel_de_read_fw(dev_priv, high_frame) & PIPE_FRAME_HIGH_MASK;
690 low = intel_de_read_fw(dev_priv, low_frame);
691 high2 = intel_de_read_fw(dev_priv, high_frame) & PIPE_FRAME_HIGH_MASK;
692 } while (high1 != high2);
694 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
696 high1 >>= PIPE_FRAME_HIGH_SHIFT;
697 pixel = low & PIPE_PIXEL_MASK;
698 low >>= PIPE_FRAME_LOW_SHIFT;
701 * The frame counter increments at beginning of active.
702 * Cook up a vblank counter by also checking the pixel
703 * counter against vblank start.
705 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
708 u32 g4x_get_vblank_counter(struct drm_crtc *crtc)
710 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
711 struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)];
712 enum pipe pipe = to_intel_crtc(crtc)->pipe;
714 if (!vblank->max_vblank_count)
717 return intel_uncore_read(&dev_priv->uncore, PIPE_FRMCOUNT_G4X(pipe));
720 static u32 intel_crtc_scanlines_since_frame_timestamp(struct intel_crtc *crtc)
722 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
723 struct drm_vblank_crtc *vblank =
724 &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
725 const struct drm_display_mode *mode = &vblank->hwmode;
726 u32 htotal = mode->crtc_htotal;
727 u32 clock = mode->crtc_clock;
728 u32 scan_prev_time, scan_curr_time, scan_post_time;
731 * To avoid the race condition where we might cross into the
732 * next vblank just between the PIPE_FRMTMSTMP and TIMESTAMP_CTR
733 * reads. We make sure we read PIPE_FRMTMSTMP and TIMESTAMP_CTR
734 * during the same frame.
738 * This field provides read back of the display
739 * pipe frame time stamp. The time stamp value
740 * is sampled at every start of vertical blank.
742 scan_prev_time = intel_de_read_fw(dev_priv,
743 PIPE_FRMTMSTMP(crtc->pipe));
746 * The TIMESTAMP_CTR register has the current
749 scan_curr_time = intel_de_read_fw(dev_priv, IVB_TIMESTAMP_CTR);
751 scan_post_time = intel_de_read_fw(dev_priv,
752 PIPE_FRMTMSTMP(crtc->pipe));
753 } while (scan_post_time != scan_prev_time);
755 return div_u64(mul_u32_u32(scan_curr_time - scan_prev_time,
756 clock), 1000 * htotal);
760 * On certain encoders on certain platforms, pipe
761 * scanline register will not work to get the scanline,
762 * since the timings are driven from the PORT or issues
763 * with scanline register updates.
764 * This function will use Framestamp and current
765 * timestamp registers to calculate the scanline.
767 static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)
769 struct drm_vblank_crtc *vblank =
770 &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
771 const struct drm_display_mode *mode = &vblank->hwmode;
772 u32 vblank_start = mode->crtc_vblank_start;
773 u32 vtotal = mode->crtc_vtotal;
776 scanline = intel_crtc_scanlines_since_frame_timestamp(crtc);
777 scanline = min(scanline, vtotal - 1);
778 scanline = (scanline + vblank_start) % vtotal;
784 * intel_de_read_fw(), only for fast reads of display block, no need for
787 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
789 struct drm_device *dev = crtc->base.dev;
790 struct drm_i915_private *dev_priv = to_i915(dev);
791 const struct drm_display_mode *mode;
792 struct drm_vblank_crtc *vblank;
793 enum pipe pipe = crtc->pipe;
794 int position, vtotal;
799 vblank = &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
800 mode = &vblank->hwmode;
802 if (crtc->mode_flags & I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP)
803 return __intel_get_crtc_scanline_from_timestamp(crtc);
805 vtotal = mode->crtc_vtotal;
806 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
809 if (IS_DISPLAY_VER(dev_priv, 2))
810 position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
812 position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
815 * On HSW, the DSL reg (0x70000) appears to return 0 if we
816 * read it just before the start of vblank. So try it again
817 * so we don't accidentally end up spanning a vblank frame
818 * increment, causing the pipe_update_end() code to squak at us.
820 * The nature of this problem means we can't simply check the ISR
821 * bit and return the vblank start value; nor can we use the scanline
822 * debug register in the transcoder as it appears to have the same
823 * problem. We may need to extend this to include other platforms,
824 * but so far testing only shows the problem on HSW.
826 if (HAS_DDI(dev_priv) && !position) {
829 for (i = 0; i < 100; i++) {
831 temp = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
832 if (temp != position) {
840 * See update_scanline_offset() for the details on the
841 * scanline_offset adjustment.
843 return (position + crtc->scanline_offset) % vtotal;
846 static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
848 int *vpos, int *hpos,
849 ktime_t *stime, ktime_t *etime,
850 const struct drm_display_mode *mode)
852 struct drm_device *dev = _crtc->dev;
853 struct drm_i915_private *dev_priv = to_i915(dev);
854 struct intel_crtc *crtc = to_intel_crtc(_crtc);
855 enum pipe pipe = crtc->pipe;
857 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
858 unsigned long irqflags;
859 bool use_scanline_counter = DISPLAY_VER(dev_priv) >= 5 ||
860 IS_G4X(dev_priv) || IS_DISPLAY_VER(dev_priv, 2) ||
861 crtc->mode_flags & I915_MODE_FLAG_USE_SCANLINE_COUNTER;
863 if (drm_WARN_ON(&dev_priv->drm, !mode->crtc_clock)) {
864 drm_dbg(&dev_priv->drm,
865 "trying to get scanoutpos for disabled "
866 "pipe %c\n", pipe_name(pipe));
870 htotal = mode->crtc_htotal;
871 hsync_start = mode->crtc_hsync_start;
872 vtotal = mode->crtc_vtotal;
873 vbl_start = mode->crtc_vblank_start;
874 vbl_end = mode->crtc_vblank_end;
876 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
877 vbl_start = DIV_ROUND_UP(vbl_start, 2);
883 * Lock uncore.lock, as we will do multiple timing critical raw
884 * register reads, potentially with preemption disabled, so the
885 * following code must not block on uncore.lock.
887 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
889 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
891 /* Get optional system timestamp before query. */
893 *stime = ktime_get();
895 if (crtc->mode_flags & I915_MODE_FLAG_VRR) {
896 int scanlines = intel_crtc_scanlines_since_frame_timestamp(crtc);
898 position = __intel_get_crtc_scanline(crtc);
901 * Already exiting vblank? If so, shift our position
902 * so it looks like we're already apporaching the full
903 * vblank end. This should make the generated timestamp
904 * more or less match when the active portion will start.
906 if (position >= vbl_start && scanlines < position)
907 position = min(crtc->vmax_vblank_start + scanlines, vtotal - 1);
908 } else if (use_scanline_counter) {
909 /* No obvious pixelcount register. Only query vertical
910 * scanout position from Display scan line register.
912 position = __intel_get_crtc_scanline(crtc);
914 /* Have access to pixelcount since start of frame.
915 * We can split this into vertical and horizontal
918 position = (intel_de_read_fw(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
920 /* convert to pixel counts */
926 * In interlaced modes, the pixel counter counts all pixels,
927 * so one field will have htotal more pixels. In order to avoid
928 * the reported position from jumping backwards when the pixel
929 * counter is beyond the length of the shorter field, just
930 * clamp the position the length of the shorter field. This
931 * matches how the scanline counter based position works since
932 * the scanline counter doesn't count the two half lines.
934 if (position >= vtotal)
935 position = vtotal - 1;
938 * Start of vblank interrupt is triggered at start of hsync,
939 * just prior to the first active line of vblank. However we
940 * consider lines to start at the leading edge of horizontal
941 * active. So, should we get here before we've crossed into
942 * the horizontal active of the first line in vblank, we would
943 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
944 * always add htotal-hsync_start to the current pixel position.
946 position = (position + htotal - hsync_start) % vtotal;
949 /* Get optional system timestamp after query. */
951 *etime = ktime_get();
953 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
955 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
958 * While in vblank, position will be negative
959 * counting up towards 0 at vbl_end. And outside
960 * vblank, position will be positive counting
963 if (position >= vbl_start)
966 position += vtotal - vbl_end;
968 if (use_scanline_counter) {
972 *vpos = position / htotal;
973 *hpos = position - (*vpos * htotal);
979 bool intel_crtc_get_vblank_timestamp(struct drm_crtc *crtc, int *max_error,
980 ktime_t *vblank_time, bool in_vblank_irq)
982 return drm_crtc_vblank_helper_get_vblank_timestamp_internal(
983 crtc, max_error, vblank_time, in_vblank_irq,
984 i915_get_crtc_scanoutpos);
987 int intel_get_crtc_scanline(struct intel_crtc *crtc)
989 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
990 unsigned long irqflags;
993 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
994 position = __intel_get_crtc_scanline(crtc);
995 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1001 * ivb_parity_work - Workqueue called when a parity error interrupt
1003 * @work: workqueue struct
1005 * Doesn't actually do anything except notify userspace. As a consequence of
1006 * this event, userspace should try to remap the bad rows since statistically
1007 * it is likely the same row is more likely to go bad again.
1009 static void ivb_parity_work(struct work_struct *work)
1011 struct drm_i915_private *dev_priv =
1012 container_of(work, typeof(*dev_priv), l3_parity.error_work);
1013 struct intel_gt *gt = &dev_priv->gt;
1014 u32 error_status, row, bank, subbank;
1015 char *parity_event[6];
1019 /* We must turn off DOP level clock gating to access the L3 registers.
1020 * In order to prevent a get/put style interface, acquire struct mutex
1021 * any time we access those registers.
1023 mutex_lock(&dev_priv->drm.struct_mutex);
1025 /* If we've screwed up tracking, just let the interrupt fire again */
1026 if (drm_WARN_ON(&dev_priv->drm, !dev_priv->l3_parity.which_slice))
1029 misccpctl = intel_uncore_read(&dev_priv->uncore, GEN7_MISCCPCTL);
1030 intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1031 intel_uncore_posting_read(&dev_priv->uncore, GEN7_MISCCPCTL);
1033 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1037 if (drm_WARN_ON_ONCE(&dev_priv->drm,
1038 slice >= NUM_L3_SLICES(dev_priv)))
1041 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1043 reg = GEN7_L3CDERRST1(slice);
1045 error_status = intel_uncore_read(&dev_priv->uncore, reg);
1046 row = GEN7_PARITY_ERROR_ROW(error_status);
1047 bank = GEN7_PARITY_ERROR_BANK(error_status);
1048 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1050 intel_uncore_write(&dev_priv->uncore, reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1051 intel_uncore_posting_read(&dev_priv->uncore, reg);
1053 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1054 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1055 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1056 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1057 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1058 parity_event[5] = NULL;
1060 kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj,
1061 KOBJ_CHANGE, parity_event);
1063 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1064 slice, row, bank, subbank);
1066 kfree(parity_event[4]);
1067 kfree(parity_event[3]);
1068 kfree(parity_event[2]);
1069 kfree(parity_event[1]);
1072 intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl);
1075 drm_WARN_ON(&dev_priv->drm, dev_priv->l3_parity.which_slice);
1076 spin_lock_irq(>->irq_lock);
1077 gen5_gt_enable_irq(gt, GT_PARITY_ERROR(dev_priv));
1078 spin_unlock_irq(>->irq_lock);
1080 mutex_unlock(&dev_priv->drm.struct_mutex);
1083 static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1092 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(pin);
1098 static bool bxt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1102 return val & PORTA_HOTPLUG_LONG_DETECT;
1104 return val & PORTB_HOTPLUG_LONG_DETECT;
1106 return val & PORTC_HOTPLUG_LONG_DETECT;
1112 static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1119 return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(pin);
1125 static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1134 return val & ICP_TC_HPD_LONG_DETECT(pin);
1140 static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val)
1144 return val & PORTE_HOTPLUG_LONG_DETECT;
1150 static bool spt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1154 return val & PORTA_HOTPLUG_LONG_DETECT;
1156 return val & PORTB_HOTPLUG_LONG_DETECT;
1158 return val & PORTC_HOTPLUG_LONG_DETECT;
1160 return val & PORTD_HOTPLUG_LONG_DETECT;
1166 static bool ilk_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1170 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
1176 static bool pch_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1180 return val & PORTB_HOTPLUG_LONG_DETECT;
1182 return val & PORTC_HOTPLUG_LONG_DETECT;
1184 return val & PORTD_HOTPLUG_LONG_DETECT;
1190 static bool i9xx_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1194 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1196 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1198 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1205 * Get a bit mask of pins that have triggered, and which ones may be long.
1206 * This can be called multiple times with the same masks to accumulate
1207 * hotplug detection results from several registers.
1209 * Note that the caller is expected to zero out the masks initially.
1211 static void intel_get_hpd_pins(struct drm_i915_private *dev_priv,
1212 u32 *pin_mask, u32 *long_mask,
1213 u32 hotplug_trigger, u32 dig_hotplug_reg,
1214 const u32 hpd[HPD_NUM_PINS],
1215 bool long_pulse_detect(enum hpd_pin pin, u32 val))
1219 BUILD_BUG_ON(BITS_PER_TYPE(*pin_mask) < HPD_NUM_PINS);
1221 for_each_hpd_pin(pin) {
1222 if ((hpd[pin] & hotplug_trigger) == 0)
1225 *pin_mask |= BIT(pin);
1227 if (long_pulse_detect(pin, dig_hotplug_reg))
1228 *long_mask |= BIT(pin);
1231 drm_dbg(&dev_priv->drm,
1232 "hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x, long 0x%08x\n",
1233 hotplug_trigger, dig_hotplug_reg, *pin_mask, *long_mask);
1237 static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
1238 const u32 hpd[HPD_NUM_PINS])
1240 struct intel_encoder *encoder;
1241 u32 enabled_irqs = 0;
1243 for_each_intel_encoder(&dev_priv->drm, encoder)
1244 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
1245 enabled_irqs |= hpd[encoder->hpd_pin];
1247 return enabled_irqs;
1250 static u32 intel_hpd_hotplug_irqs(struct drm_i915_private *dev_priv,
1251 const u32 hpd[HPD_NUM_PINS])
1253 struct intel_encoder *encoder;
1254 u32 hotplug_irqs = 0;
1256 for_each_intel_encoder(&dev_priv->drm, encoder)
1257 hotplug_irqs |= hpd[encoder->hpd_pin];
1259 return hotplug_irqs;
1262 static u32 intel_hpd_hotplug_enables(struct drm_i915_private *i915,
1263 hotplug_enables_func hotplug_enables)
1265 struct intel_encoder *encoder;
1268 for_each_intel_encoder(&i915->drm, encoder)
1269 hotplug |= hotplug_enables(i915, encoder->hpd_pin);
1274 static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
1276 wake_up_all(&dev_priv->gmbus_wait_queue);
1279 static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
1281 wake_up_all(&dev_priv->gmbus_wait_queue);
1284 #if defined(CONFIG_DEBUG_FS)
1285 static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1291 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1292 struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
1293 u32 crcs[5] = { crc0, crc1, crc2, crc3, crc4 };
1295 trace_intel_pipe_crc(crtc, crcs);
1297 spin_lock(&pipe_crc->lock);
1299 * For some not yet identified reason, the first CRC is
1300 * bonkers. So let's just wait for the next vblank and read
1301 * out the buggy result.
1303 * On GEN8+ sometimes the second CRC is bonkers as well, so
1304 * don't trust that one either.
1306 if (pipe_crc->skipped <= 0 ||
1307 (DISPLAY_VER(dev_priv) >= 8 && pipe_crc->skipped == 1)) {
1308 pipe_crc->skipped++;
1309 spin_unlock(&pipe_crc->lock);
1312 spin_unlock(&pipe_crc->lock);
1314 drm_crtc_add_crc_entry(&crtc->base, true,
1315 drm_crtc_accurate_vblank_count(&crtc->base),
1320 display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1327 static void flip_done_handler(struct drm_i915_private *i915,
1330 struct intel_crtc *crtc = intel_get_crtc_for_pipe(i915, pipe);
1331 struct drm_crtc_state *crtc_state = crtc->base.state;
1332 struct drm_pending_vblank_event *e = crtc_state->event;
1333 struct drm_device *dev = &i915->drm;
1334 unsigned long irqflags;
1336 spin_lock_irqsave(&dev->event_lock, irqflags);
1338 crtc_state->event = NULL;
1340 drm_crtc_send_vblank_event(&crtc->base, e);
1342 spin_unlock_irqrestore(&dev->event_lock, irqflags);
1345 static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1348 display_pipe_crc_irq_handler(dev_priv, pipe,
1349 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)),
1353 static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1356 display_pipe_crc_irq_handler(dev_priv, pipe,
1357 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)),
1358 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_2_IVB(pipe)),
1359 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_3_IVB(pipe)),
1360 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_4_IVB(pipe)),
1361 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_5_IVB(pipe)));
1364 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1369 if (DISPLAY_VER(dev_priv) >= 3)
1370 res1 = intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RES1_I915(pipe));
1374 if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
1375 res2 = intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RES2_G4X(pipe));
1379 display_pipe_crc_irq_handler(dev_priv, pipe,
1380 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RED(pipe)),
1381 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_GREEN(pipe)),
1382 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_BLUE(pipe)),
1386 static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
1390 for_each_pipe(dev_priv, pipe) {
1391 intel_uncore_write(&dev_priv->uncore, PIPESTAT(pipe),
1392 PIPESTAT_INT_STATUS_MASK |
1393 PIPE_FIFO_UNDERRUN_STATUS);
1395 dev_priv->pipestat_irq_mask[pipe] = 0;
1399 static void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,
1400 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1404 spin_lock(&dev_priv->irq_lock);
1406 if (!dev_priv->display_irqs_enabled) {
1407 spin_unlock(&dev_priv->irq_lock);
1411 for_each_pipe(dev_priv, pipe) {
1413 u32 status_mask, enable_mask, iir_bit = 0;
1416 * PIPESTAT bits get signalled even when the interrupt is
1417 * disabled with the mask bits, and some of the status bits do
1418 * not generate interrupts at all (like the underrun bit). Hence
1419 * we need to be careful that we only handle what we want to
1423 /* fifo underruns are filterered in the underrun handler. */
1424 status_mask = PIPE_FIFO_UNDERRUN_STATUS;
1429 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1432 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1435 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1439 status_mask |= dev_priv->pipestat_irq_mask[pipe];
1444 reg = PIPESTAT(pipe);
1445 pipe_stats[pipe] = intel_uncore_read(&dev_priv->uncore, reg) & status_mask;
1446 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
1449 * Clear the PIPE*STAT regs before the IIR
1451 * Toggle the enable bits to make sure we get an
1452 * edge in the ISR pipe event bit if we don't clear
1453 * all the enabled status bits. Otherwise the edge
1454 * triggered IIR on i965/g4x wouldn't notice that
1455 * an interrupt is still pending.
1457 if (pipe_stats[pipe]) {
1458 intel_uncore_write(&dev_priv->uncore, reg, pipe_stats[pipe]);
1459 intel_uncore_write(&dev_priv->uncore, reg, enable_mask);
1462 spin_unlock(&dev_priv->irq_lock);
1465 static void i8xx_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1466 u16 iir, u32 pipe_stats[I915_MAX_PIPES])
1470 for_each_pipe(dev_priv, pipe) {
1471 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1472 intel_handle_vblank(dev_priv, pipe);
1474 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1475 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1477 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1478 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1482 static void i915_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1483 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1485 bool blc_event = false;
1488 for_each_pipe(dev_priv, pipe) {
1489 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1490 intel_handle_vblank(dev_priv, pipe);
1492 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1495 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1496 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1498 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1499 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1502 if (blc_event || (iir & I915_ASLE_INTERRUPT))
1503 intel_opregion_asle_intr(dev_priv);
1506 static void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1507 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1509 bool blc_event = false;
1512 for_each_pipe(dev_priv, pipe) {
1513 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1514 intel_handle_vblank(dev_priv, pipe);
1516 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1519 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1520 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1522 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1523 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1526 if (blc_event || (iir & I915_ASLE_INTERRUPT))
1527 intel_opregion_asle_intr(dev_priv);
1529 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1530 gmbus_irq_handler(dev_priv);
1533 static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1534 u32 pipe_stats[I915_MAX_PIPES])
1538 for_each_pipe(dev_priv, pipe) {
1539 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1540 intel_handle_vblank(dev_priv, pipe);
1542 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV)
1543 flip_done_handler(dev_priv, pipe);
1545 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1546 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1548 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1549 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1552 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1553 gmbus_irq_handler(dev_priv);
1556 static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
1558 u32 hotplug_status = 0, hotplug_status_mask;
1561 if (IS_G4X(dev_priv) ||
1562 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1563 hotplug_status_mask = HOTPLUG_INT_STATUS_G4X |
1564 DP_AUX_CHANNEL_MASK_INT_STATUS_G4X;
1566 hotplug_status_mask = HOTPLUG_INT_STATUS_I915;
1569 * We absolutely have to clear all the pending interrupt
1570 * bits in PORT_HOTPLUG_STAT. Otherwise the ISR port
1571 * interrupt bit won't have an edge, and the i965/g4x
1572 * edge triggered IIR will not notice that an interrupt
1573 * is still pending. We can't use PORT_HOTPLUG_EN to
1574 * guarantee the edge as the act of toggling the enable
1575 * bits can itself generate a new hotplug interrupt :(
1577 for (i = 0; i < 10; i++) {
1578 u32 tmp = intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT) & hotplug_status_mask;
1581 return hotplug_status;
1583 hotplug_status |= tmp;
1584 intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_STAT, hotplug_status);
1587 drm_WARN_ONCE(&dev_priv->drm, 1,
1588 "PORT_HOTPLUG_STAT did not clear (0x%08x)\n",
1589 intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT));
1591 return hotplug_status;
1594 static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1597 u32 pin_mask = 0, long_mask = 0;
1598 u32 hotplug_trigger;
1600 if (IS_G4X(dev_priv) ||
1601 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1602 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1604 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1606 if (hotplug_trigger) {
1607 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1608 hotplug_trigger, hotplug_trigger,
1609 dev_priv->hotplug.hpd,
1610 i9xx_port_hotplug_long_detect);
1612 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1615 if ((IS_G4X(dev_priv) ||
1616 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1617 hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1618 dp_aux_irq_handler(dev_priv);
1621 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1623 struct drm_i915_private *dev_priv = arg;
1624 irqreturn_t ret = IRQ_NONE;
1626 if (!intel_irqs_enabled(dev_priv))
1629 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1630 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1633 u32 iir, gt_iir, pm_iir;
1634 u32 pipe_stats[I915_MAX_PIPES] = {};
1635 u32 hotplug_status = 0;
1638 gt_iir = intel_uncore_read(&dev_priv->uncore, GTIIR);
1639 pm_iir = intel_uncore_read(&dev_priv->uncore, GEN6_PMIIR);
1640 iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);
1642 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1648 * Theory on interrupt generation, based on empirical evidence:
1650 * x = ((VLV_IIR & VLV_IER) ||
1651 * (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
1652 * (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
1654 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1655 * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
1656 * guarantee the CPU interrupt will be raised again even if we
1657 * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
1658 * bits this time around.
1660 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, 0);
1661 ier = intel_uncore_read(&dev_priv->uncore, VLV_IER);
1662 intel_uncore_write(&dev_priv->uncore, VLV_IER, 0);
1665 intel_uncore_write(&dev_priv->uncore, GTIIR, gt_iir);
1667 intel_uncore_write(&dev_priv->uncore, GEN6_PMIIR, pm_iir);
1669 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1670 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1672 /* Call regardless, as some status bits might not be
1673 * signalled in iir */
1674 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1676 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
1677 I915_LPE_PIPE_B_INTERRUPT))
1678 intel_lpe_audio_irq_handler(dev_priv);
1681 * VLV_IIR is single buffered, and reflects the level
1682 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1685 intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir);
1687 intel_uncore_write(&dev_priv->uncore, VLV_IER, ier);
1688 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1691 gen6_gt_irq_handler(&dev_priv->gt, gt_iir);
1693 gen6_rps_irq_handler(&dev_priv->gt.rps, pm_iir);
1696 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1698 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1701 pmu_irq_stats(dev_priv, ret);
1703 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1708 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1710 struct drm_i915_private *dev_priv = arg;
1711 irqreturn_t ret = IRQ_NONE;
1713 if (!intel_irqs_enabled(dev_priv))
1716 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1717 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1720 u32 master_ctl, iir;
1721 u32 pipe_stats[I915_MAX_PIPES] = {};
1722 u32 hotplug_status = 0;
1725 master_ctl = intel_uncore_read(&dev_priv->uncore, GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1726 iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);
1728 if (master_ctl == 0 && iir == 0)
1734 * Theory on interrupt generation, based on empirical evidence:
1736 * x = ((VLV_IIR & VLV_IER) ||
1737 * ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
1738 * (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
1740 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1741 * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
1742 * guarantee the CPU interrupt will be raised again even if we
1743 * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
1744 * bits this time around.
1746 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, 0);
1747 ier = intel_uncore_read(&dev_priv->uncore, VLV_IER);
1748 intel_uncore_write(&dev_priv->uncore, VLV_IER, 0);
1750 gen8_gt_irq_handler(&dev_priv->gt, master_ctl);
1752 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1753 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1755 /* Call regardless, as some status bits might not be
1756 * signalled in iir */
1757 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1759 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
1760 I915_LPE_PIPE_B_INTERRUPT |
1761 I915_LPE_PIPE_C_INTERRUPT))
1762 intel_lpe_audio_irq_handler(dev_priv);
1765 * VLV_IIR is single buffered, and reflects the level
1766 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1769 intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir);
1771 intel_uncore_write(&dev_priv->uncore, VLV_IER, ier);
1772 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
1775 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1777 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1780 pmu_irq_stats(dev_priv, ret);
1782 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1787 static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1788 u32 hotplug_trigger)
1790 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
1793 * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
1794 * unless we touch the hotplug register, even if hotplug_trigger is
1795 * zero. Not acking leads to "The master control interrupt lied (SDE)!"
1798 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);
1799 if (!hotplug_trigger) {
1800 u32 mask = PORTA_HOTPLUG_STATUS_MASK |
1801 PORTD_HOTPLUG_STATUS_MASK |
1802 PORTC_HOTPLUG_STATUS_MASK |
1803 PORTB_HOTPLUG_STATUS_MASK;
1804 dig_hotplug_reg &= ~mask;
1807 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, dig_hotplug_reg);
1808 if (!hotplug_trigger)
1811 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1812 hotplug_trigger, dig_hotplug_reg,
1813 dev_priv->hotplug.pch_hpd,
1814 pch_port_hotplug_long_detect);
1816 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1819 static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1822 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1824 ibx_hpd_irq_handler(dev_priv, hotplug_trigger);
1826 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1827 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1828 SDE_AUDIO_POWER_SHIFT);
1829 drm_dbg(&dev_priv->drm, "PCH audio power change on port %d\n",
1833 if (pch_iir & SDE_AUX_MASK)
1834 dp_aux_irq_handler(dev_priv);
1836 if (pch_iir & SDE_GMBUS)
1837 gmbus_irq_handler(dev_priv);
1839 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1840 drm_dbg(&dev_priv->drm, "PCH HDCP audio interrupt\n");
1842 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1843 drm_dbg(&dev_priv->drm, "PCH transcoder audio interrupt\n");
1845 if (pch_iir & SDE_POISON)
1846 drm_err(&dev_priv->drm, "PCH poison interrupt\n");
1848 if (pch_iir & SDE_FDI_MASK) {
1849 for_each_pipe(dev_priv, pipe)
1850 drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n",
1852 intel_uncore_read(&dev_priv->uncore, FDI_RX_IIR(pipe)));
1855 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1856 drm_dbg(&dev_priv->drm, "PCH transcoder CRC done interrupt\n");
1858 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1859 drm_dbg(&dev_priv->drm,
1860 "PCH transcoder CRC error interrupt\n");
1862 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1863 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A);
1865 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1866 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B);
1869 static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
1871 u32 err_int = intel_uncore_read(&dev_priv->uncore, GEN7_ERR_INT);
1874 if (err_int & ERR_INT_POISON)
1875 drm_err(&dev_priv->drm, "Poison interrupt\n");
1877 for_each_pipe(dev_priv, pipe) {
1878 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
1879 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1881 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1882 if (IS_IVYBRIDGE(dev_priv))
1883 ivb_pipe_crc_irq_handler(dev_priv, pipe);
1885 hsw_pipe_crc_irq_handler(dev_priv, pipe);
1889 intel_uncore_write(&dev_priv->uncore, GEN7_ERR_INT, err_int);
1892 static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
1894 u32 serr_int = intel_uncore_read(&dev_priv->uncore, SERR_INT);
1897 if (serr_int & SERR_INT_POISON)
1898 drm_err(&dev_priv->drm, "PCH poison interrupt\n");
1900 for_each_pipe(dev_priv, pipe)
1901 if (serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pipe))
1902 intel_pch_fifo_underrun_irq_handler(dev_priv, pipe);
1904 intel_uncore_write(&dev_priv->uncore, SERR_INT, serr_int);
1907 static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1910 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1912 ibx_hpd_irq_handler(dev_priv, hotplug_trigger);
1914 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1915 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1916 SDE_AUDIO_POWER_SHIFT_CPT);
1917 drm_dbg(&dev_priv->drm, "PCH audio power change on port %c\n",
1921 if (pch_iir & SDE_AUX_MASK_CPT)
1922 dp_aux_irq_handler(dev_priv);
1924 if (pch_iir & SDE_GMBUS_CPT)
1925 gmbus_irq_handler(dev_priv);
1927 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1928 drm_dbg(&dev_priv->drm, "Audio CP request interrupt\n");
1930 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1931 drm_dbg(&dev_priv->drm, "Audio CP change interrupt\n");
1933 if (pch_iir & SDE_FDI_MASK_CPT) {
1934 for_each_pipe(dev_priv, pipe)
1935 drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n",
1937 intel_uncore_read(&dev_priv->uncore, FDI_RX_IIR(pipe)));
1940 if (pch_iir & SDE_ERROR_CPT)
1941 cpt_serr_int_handler(dev_priv);
1944 static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1946 u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_HOTPLUG_MASK_ICP;
1947 u32 tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_MASK_ICP;
1948 u32 pin_mask = 0, long_mask = 0;
1950 if (ddi_hotplug_trigger) {
1951 u32 dig_hotplug_reg;
1953 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_DDI);
1954 intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_DDI, dig_hotplug_reg);
1956 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1957 ddi_hotplug_trigger, dig_hotplug_reg,
1958 dev_priv->hotplug.pch_hpd,
1959 icp_ddi_port_hotplug_long_detect);
1962 if (tc_hotplug_trigger) {
1963 u32 dig_hotplug_reg;
1965 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_TC);
1966 intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_TC, dig_hotplug_reg);
1968 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1969 tc_hotplug_trigger, dig_hotplug_reg,
1970 dev_priv->hotplug.pch_hpd,
1971 icp_tc_port_hotplug_long_detect);
1975 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1977 if (pch_iir & SDE_GMBUS_ICP)
1978 gmbus_irq_handler(dev_priv);
1981 static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1983 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
1984 ~SDE_PORTE_HOTPLUG_SPT;
1985 u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
1986 u32 pin_mask = 0, long_mask = 0;
1988 if (hotplug_trigger) {
1989 u32 dig_hotplug_reg;
1991 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);
1992 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, dig_hotplug_reg);
1994 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1995 hotplug_trigger, dig_hotplug_reg,
1996 dev_priv->hotplug.pch_hpd,
1997 spt_port_hotplug_long_detect);
2000 if (hotplug2_trigger) {
2001 u32 dig_hotplug_reg;
2003 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG2);
2004 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG2, dig_hotplug_reg);
2006 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2007 hotplug2_trigger, dig_hotplug_reg,
2008 dev_priv->hotplug.pch_hpd,
2009 spt_port_hotplug2_long_detect);
2013 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2015 if (pch_iir & SDE_GMBUS_CPT)
2016 gmbus_irq_handler(dev_priv);
2019 static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
2020 u32 hotplug_trigger)
2022 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2024 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL);
2025 intel_uncore_write(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
2027 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2028 hotplug_trigger, dig_hotplug_reg,
2029 dev_priv->hotplug.hpd,
2030 ilk_port_hotplug_long_detect);
2032 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2035 static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
2039 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
2041 if (hotplug_trigger)
2042 ilk_hpd_irq_handler(dev_priv, hotplug_trigger);
2044 if (de_iir & DE_AUX_CHANNEL_A)
2045 dp_aux_irq_handler(dev_priv);
2047 if (de_iir & DE_GSE)
2048 intel_opregion_asle_intr(dev_priv);
2050 if (de_iir & DE_POISON)
2051 drm_err(&dev_priv->drm, "Poison interrupt\n");
2053 for_each_pipe(dev_priv, pipe) {
2054 if (de_iir & DE_PIPE_VBLANK(pipe))
2055 intel_handle_vblank(dev_priv, pipe);
2057 if (de_iir & DE_PLANE_FLIP_DONE(pipe))
2058 flip_done_handler(dev_priv, pipe);
2060 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2061 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2063 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2064 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2067 /* check event from PCH */
2068 if (de_iir & DE_PCH_EVENT) {
2069 u32 pch_iir = intel_uncore_read(&dev_priv->uncore, SDEIIR);
2071 if (HAS_PCH_CPT(dev_priv))
2072 cpt_irq_handler(dev_priv, pch_iir);
2074 ibx_irq_handler(dev_priv, pch_iir);
2076 /* should clear PCH hotplug event before clear CPU irq */
2077 intel_uncore_write(&dev_priv->uncore, SDEIIR, pch_iir);
2080 if (IS_DISPLAY_VER(dev_priv, 5) && de_iir & DE_PCU_EVENT)
2081 gen5_rps_irq_handler(&dev_priv->gt.rps);
2084 static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
2088 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2090 if (hotplug_trigger)
2091 ilk_hpd_irq_handler(dev_priv, hotplug_trigger);
2093 if (de_iir & DE_ERR_INT_IVB)
2094 ivb_err_int_handler(dev_priv);
2096 if (de_iir & DE_EDP_PSR_INT_HSW) {
2097 struct intel_encoder *encoder;
2099 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
2100 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2102 u32 psr_iir = intel_uncore_read(&dev_priv->uncore,
2105 intel_psr_irq_handler(intel_dp, psr_iir);
2106 intel_uncore_write(&dev_priv->uncore,
2107 EDP_PSR_IIR, psr_iir);
2112 if (de_iir & DE_AUX_CHANNEL_A_IVB)
2113 dp_aux_irq_handler(dev_priv);
2115 if (de_iir & DE_GSE_IVB)
2116 intel_opregion_asle_intr(dev_priv);
2118 for_each_pipe(dev_priv, pipe) {
2119 if (de_iir & DE_PIPE_VBLANK_IVB(pipe))
2120 intel_handle_vblank(dev_priv, pipe);
2122 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe))
2123 flip_done_handler(dev_priv, pipe);
2126 /* check event from PCH */
2127 if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
2128 u32 pch_iir = intel_uncore_read(&dev_priv->uncore, SDEIIR);
2130 cpt_irq_handler(dev_priv, pch_iir);
2132 /* clear PCH hotplug event before clear CPU irq */
2133 intel_uncore_write(&dev_priv->uncore, SDEIIR, pch_iir);
2138 * To handle irqs with the minimum potential races with fresh interrupts, we:
2139 * 1 - Disable Master Interrupt Control.
2140 * 2 - Find the source(s) of the interrupt.
2141 * 3 - Clear the Interrupt Identity bits (IIR).
2142 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2143 * 5 - Re-enable Master Interrupt Control.
2145 static irqreturn_t ilk_irq_handler(int irq, void *arg)
2147 struct drm_i915_private *i915 = arg;
2148 void __iomem * const regs = i915->uncore.regs;
2149 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2150 irqreturn_t ret = IRQ_NONE;
2152 if (unlikely(!intel_irqs_enabled(i915)))
2155 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2156 disable_rpm_wakeref_asserts(&i915->runtime_pm);
2158 /* disable master interrupt before clearing iir */
2159 de_ier = raw_reg_read(regs, DEIER);
2160 raw_reg_write(regs, DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2162 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2163 * interrupts will will be stored on its back queue, and then we'll be
2164 * able to process them after we restore SDEIER (as soon as we restore
2165 * it, we'll get an interrupt if SDEIIR still has something to process
2166 * due to its back queue). */
2167 if (!HAS_PCH_NOP(i915)) {
2168 sde_ier = raw_reg_read(regs, SDEIER);
2169 raw_reg_write(regs, SDEIER, 0);
2172 /* Find, clear, then process each source of interrupt */
2174 gt_iir = raw_reg_read(regs, GTIIR);
2176 raw_reg_write(regs, GTIIR, gt_iir);
2177 if (INTEL_GEN(i915) >= 6)
2178 gen6_gt_irq_handler(&i915->gt, gt_iir);
2180 gen5_gt_irq_handler(&i915->gt, gt_iir);
2184 de_iir = raw_reg_read(regs, DEIIR);
2186 raw_reg_write(regs, DEIIR, de_iir);
2187 if (DISPLAY_VER(i915) >= 7)
2188 ivb_display_irq_handler(i915, de_iir);
2190 ilk_display_irq_handler(i915, de_iir);
2194 if (INTEL_GEN(i915) >= 6) {
2195 u32 pm_iir = raw_reg_read(regs, GEN6_PMIIR);
2197 raw_reg_write(regs, GEN6_PMIIR, pm_iir);
2198 gen6_rps_irq_handler(&i915->gt.rps, pm_iir);
2203 raw_reg_write(regs, DEIER, de_ier);
2205 raw_reg_write(regs, SDEIER, sde_ier);
2207 pmu_irq_stats(i915, ret);
2209 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2210 enable_rpm_wakeref_asserts(&i915->runtime_pm);
2215 static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
2216 u32 hotplug_trigger)
2218 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2220 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);
2221 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, dig_hotplug_reg);
2223 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2224 hotplug_trigger, dig_hotplug_reg,
2225 dev_priv->hotplug.hpd,
2226 bxt_port_hotplug_long_detect);
2228 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2231 static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
2233 u32 pin_mask = 0, long_mask = 0;
2234 u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK;
2235 u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK;
2238 u32 dig_hotplug_reg;
2240 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL);
2241 intel_uncore_write(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL, dig_hotplug_reg);
2243 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2244 trigger_tc, dig_hotplug_reg,
2245 dev_priv->hotplug.hpd,
2246 gen11_port_hotplug_long_detect);
2250 u32 dig_hotplug_reg;
2252 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL);
2253 intel_uncore_write(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL, dig_hotplug_reg);
2255 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2256 trigger_tbt, dig_hotplug_reg,
2257 dev_priv->hotplug.hpd,
2258 gen11_port_hotplug_long_detect);
2262 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2264 drm_err(&dev_priv->drm,
2265 "Unexpected DE HPD interrupt 0x%08x\n", iir);
2268 static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
2272 if (DISPLAY_VER(dev_priv) >= 12)
2273 return TGL_DE_PORT_AUX_DDIA |
2274 TGL_DE_PORT_AUX_DDIB |
2275 TGL_DE_PORT_AUX_DDIC |
2276 TGL_DE_PORT_AUX_USBC1 |
2277 TGL_DE_PORT_AUX_USBC2 |
2278 TGL_DE_PORT_AUX_USBC3 |
2279 TGL_DE_PORT_AUX_USBC4 |
2280 TGL_DE_PORT_AUX_USBC5 |
2281 TGL_DE_PORT_AUX_USBC6;
2284 mask = GEN8_AUX_CHANNEL_A;
2285 if (DISPLAY_VER(dev_priv) >= 9)
2286 mask |= GEN9_AUX_CHANNEL_B |
2287 GEN9_AUX_CHANNEL_C |
2290 if (IS_CNL_WITH_PORT_F(dev_priv) || IS_DISPLAY_VER(dev_priv, 11))
2291 mask |= CNL_AUX_CHANNEL_F;
2293 if (IS_DISPLAY_VER(dev_priv, 11))
2294 mask |= ICL_AUX_CHANNEL_E;
2299 static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
2301 if (HAS_D12_PLANE_MINIMIZATION(dev_priv))
2302 return RKL_DE_PIPE_IRQ_FAULT_ERRORS;
2303 else if (DISPLAY_VER(dev_priv) >= 11)
2304 return GEN11_DE_PIPE_IRQ_FAULT_ERRORS;
2305 else if (DISPLAY_VER(dev_priv) >= 9)
2306 return GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2308 return GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2312 gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
2316 if (iir & GEN8_DE_MISC_GSE) {
2317 intel_opregion_asle_intr(dev_priv);
2321 if (iir & GEN8_DE_EDP_PSR) {
2322 struct intel_encoder *encoder;
2326 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
2327 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2329 if (DISPLAY_VER(dev_priv) >= 12)
2330 iir_reg = TRANS_PSR_IIR(intel_dp->psr.transcoder);
2332 iir_reg = EDP_PSR_IIR;
2334 psr_iir = intel_uncore_read(&dev_priv->uncore, iir_reg);
2335 intel_uncore_write(&dev_priv->uncore, iir_reg, psr_iir);
2340 intel_psr_irq_handler(intel_dp, psr_iir);
2342 /* prior GEN12 only have one EDP PSR */
2343 if (DISPLAY_VER(dev_priv) < 12)
2349 drm_err(&dev_priv->drm, "Unexpected DE Misc interrupt\n");
2352 static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,
2355 enum pipe pipe = INVALID_PIPE;
2356 enum transcoder dsi_trans;
2361 * Incase of dual link, TE comes from DSI_1
2362 * this is to check if dual link is enabled
2364 val = intel_uncore_read(&dev_priv->uncore, TRANS_DDI_FUNC_CTL2(TRANSCODER_DSI_0));
2365 val &= PORT_SYNC_MODE_ENABLE;
2368 * if dual link is enabled, then read DSI_0
2369 * transcoder registers
2371 port = ((te_trigger & DSI1_TE && val) || (te_trigger & DSI0_TE)) ?
2373 dsi_trans = (port == PORT_A) ? TRANSCODER_DSI_0 : TRANSCODER_DSI_1;
2375 /* Check if DSI configured in command mode */
2376 val = intel_uncore_read(&dev_priv->uncore, DSI_TRANS_FUNC_CONF(dsi_trans));
2377 val = val & OP_MODE_MASK;
2379 if (val != CMD_MODE_NO_GATE && val != CMD_MODE_TE_GATE) {
2380 drm_err(&dev_priv->drm, "DSI trancoder not configured in command mode\n");
2384 /* Get PIPE for handling VBLANK event */
2385 val = intel_uncore_read(&dev_priv->uncore, TRANS_DDI_FUNC_CTL(dsi_trans));
2386 switch (val & TRANS_DDI_EDP_INPUT_MASK) {
2387 case TRANS_DDI_EDP_INPUT_A_ON:
2390 case TRANS_DDI_EDP_INPUT_B_ONOFF:
2393 case TRANS_DDI_EDP_INPUT_C_ONOFF:
2397 drm_err(&dev_priv->drm, "Invalid PIPE\n");
2401 intel_handle_vblank(dev_priv, pipe);
2403 /* clear TE in dsi IIR */
2404 port = (te_trigger & DSI1_TE) ? PORT_B : PORT_A;
2405 tmp = intel_uncore_read(&dev_priv->uncore, DSI_INTR_IDENT_REG(port));
2406 intel_uncore_write(&dev_priv->uncore, DSI_INTR_IDENT_REG(port), tmp);
2409 static u32 gen8_de_pipe_flip_done_mask(struct drm_i915_private *i915)
2411 if (DISPLAY_VER(i915) >= 9)
2412 return GEN9_PIPE_PLANE1_FLIP_DONE;
2414 return GEN8_PIPE_PRIMARY_FLIP_DONE;
2418 gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2420 irqreturn_t ret = IRQ_NONE;
2424 if (master_ctl & GEN8_DE_MISC_IRQ) {
2425 iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_MISC_IIR);
2427 intel_uncore_write(&dev_priv->uncore, GEN8_DE_MISC_IIR, iir);
2429 gen8_de_misc_irq_handler(dev_priv, iir);
2431 drm_err(&dev_priv->drm,
2432 "The master control interrupt lied (DE MISC)!\n");
2436 if (DISPLAY_VER(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) {
2437 iir = intel_uncore_read(&dev_priv->uncore, GEN11_DE_HPD_IIR);
2439 intel_uncore_write(&dev_priv->uncore, GEN11_DE_HPD_IIR, iir);
2441 gen11_hpd_irq_handler(dev_priv, iir);
2443 drm_err(&dev_priv->drm,
2444 "The master control interrupt lied, (DE HPD)!\n");
2448 if (master_ctl & GEN8_DE_PORT_IRQ) {
2449 iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IIR);
2453 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PORT_IIR, iir);
2456 if (iir & gen8_de_port_aux_mask(dev_priv)) {
2457 dp_aux_irq_handler(dev_priv);
2461 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
2462 u32 hotplug_trigger = iir & BXT_DE_PORT_HOTPLUG_MASK;
2464 if (hotplug_trigger) {
2465 bxt_hpd_irq_handler(dev_priv, hotplug_trigger);
2468 } else if (IS_BROADWELL(dev_priv)) {
2469 u32 hotplug_trigger = iir & BDW_DE_PORT_HOTPLUG_MASK;
2471 if (hotplug_trigger) {
2472 ilk_hpd_irq_handler(dev_priv, hotplug_trigger);
2477 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
2478 (iir & BXT_DE_PORT_GMBUS)) {
2479 gmbus_irq_handler(dev_priv);
2483 if (DISPLAY_VER(dev_priv) >= 11) {
2484 u32 te_trigger = iir & (DSI0_TE | DSI1_TE);
2487 gen11_dsi_te_interrupt_handler(dev_priv, te_trigger);
2493 drm_err(&dev_priv->drm,
2494 "Unexpected DE Port interrupt\n");
2497 drm_err(&dev_priv->drm,
2498 "The master control interrupt lied (DE PORT)!\n");
2501 for_each_pipe(dev_priv, pipe) {
2504 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2507 iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe));
2509 drm_err(&dev_priv->drm,
2510 "The master control interrupt lied (DE PIPE)!\n");
2515 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe), iir);
2517 if (iir & GEN8_PIPE_VBLANK)
2518 intel_handle_vblank(dev_priv, pipe);
2520 if (iir & gen8_de_pipe_flip_done_mask(dev_priv))
2521 flip_done_handler(dev_priv, pipe);
2523 if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
2524 hsw_pipe_crc_irq_handler(dev_priv, pipe);
2526 if (iir & GEN8_PIPE_FIFO_UNDERRUN)
2527 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2529 fault_errors = iir & gen8_de_pipe_fault_mask(dev_priv);
2531 drm_err(&dev_priv->drm,
2532 "Fault errors on pipe %c: 0x%08x\n",
2537 if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
2538 master_ctl & GEN8_DE_PCH_IRQ) {
2540 * FIXME(BDW): Assume for now that the new interrupt handling
2541 * scheme also closed the SDE interrupt handling race we've seen
2542 * on older pch-split platforms. But this needs testing.
2544 iir = intel_uncore_read(&dev_priv->uncore, SDEIIR);
2546 intel_uncore_write(&dev_priv->uncore, SDEIIR, iir);
2549 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2550 icp_irq_handler(dev_priv, iir);
2551 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
2552 spt_irq_handler(dev_priv, iir);
2554 cpt_irq_handler(dev_priv, iir);
2557 * Like on previous PCH there seems to be something
2558 * fishy going on with forwarding PCH interrupts.
2560 drm_dbg(&dev_priv->drm,
2561 "The master control interrupt lied (SDE)!\n");
2568 static inline u32 gen8_master_intr_disable(void __iomem * const regs)
2570 raw_reg_write(regs, GEN8_MASTER_IRQ, 0);
2573 * Now with master disabled, get a sample of level indications
2574 * for this interrupt. Indications will be cleared on related acks.
2575 * New indications can and will light up during processing,
2576 * and will generate new interrupt after enabling master.
2578 return raw_reg_read(regs, GEN8_MASTER_IRQ);
2581 static inline void gen8_master_intr_enable(void __iomem * const regs)
2583 raw_reg_write(regs, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2586 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2588 struct drm_i915_private *dev_priv = arg;
2589 void __iomem * const regs = dev_priv->uncore.regs;
2592 if (!intel_irqs_enabled(dev_priv))
2595 master_ctl = gen8_master_intr_disable(regs);
2597 gen8_master_intr_enable(regs);
2601 /* Find, queue (onto bottom-halves), then clear each source */
2602 gen8_gt_irq_handler(&dev_priv->gt, master_ctl);
2604 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2605 if (master_ctl & ~GEN8_GT_IRQS) {
2606 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2607 gen8_de_irq_handler(dev_priv, master_ctl);
2608 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2611 gen8_master_intr_enable(regs);
2613 pmu_irq_stats(dev_priv, IRQ_HANDLED);
2619 gen11_gu_misc_irq_ack(struct intel_gt *gt, const u32 master_ctl)
2621 void __iomem * const regs = gt->uncore->regs;
2624 if (!(master_ctl & GEN11_GU_MISC_IRQ))
2627 iir = raw_reg_read(regs, GEN11_GU_MISC_IIR);
2629 raw_reg_write(regs, GEN11_GU_MISC_IIR, iir);
2635 gen11_gu_misc_irq_handler(struct intel_gt *gt, const u32 iir)
2637 if (iir & GEN11_GU_MISC_GSE)
2638 intel_opregion_asle_intr(gt->i915);
2641 static inline u32 gen11_master_intr_disable(void __iomem * const regs)
2643 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, 0);
2646 * Now with master disabled, get a sample of level indications
2647 * for this interrupt. Indications will be cleared on related acks.
2648 * New indications can and will light up during processing,
2649 * and will generate new interrupt after enabling master.
2651 return raw_reg_read(regs, GEN11_GFX_MSTR_IRQ);
2654 static inline void gen11_master_intr_enable(void __iomem * const regs)
2656 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
2660 gen11_display_irq_handler(struct drm_i915_private *i915)
2662 void __iomem * const regs = i915->uncore.regs;
2663 const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL);
2665 disable_rpm_wakeref_asserts(&i915->runtime_pm);
2667 * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ
2668 * for the display related bits.
2670 raw_reg_write(regs, GEN11_DISPLAY_INT_CTL, 0x0);
2671 gen8_de_irq_handler(i915, disp_ctl);
2672 raw_reg_write(regs, GEN11_DISPLAY_INT_CTL,
2673 GEN11_DISPLAY_IRQ_ENABLE);
2675 enable_rpm_wakeref_asserts(&i915->runtime_pm);
2678 static __always_inline irqreturn_t
2679 __gen11_irq_handler(struct drm_i915_private * const i915,
2680 u32 (*intr_disable)(void __iomem * const regs),
2681 void (*intr_enable)(void __iomem * const regs))
2683 void __iomem * const regs = i915->uncore.regs;
2684 struct intel_gt *gt = &i915->gt;
2688 if (!intel_irqs_enabled(i915))
2691 master_ctl = intr_disable(regs);
2697 /* Find, queue (onto bottom-halves), then clear each source */
2698 gen11_gt_irq_handler(gt, master_ctl);
2700 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2701 if (master_ctl & GEN11_DISPLAY_IRQ)
2702 gen11_display_irq_handler(i915);
2704 gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
2708 gen11_gu_misc_irq_handler(gt, gu_misc_iir);
2710 pmu_irq_stats(i915, IRQ_HANDLED);
2715 static irqreturn_t gen11_irq_handler(int irq, void *arg)
2717 return __gen11_irq_handler(arg,
2718 gen11_master_intr_disable,
2719 gen11_master_intr_enable);
2722 static u32 dg1_master_intr_disable_and_ack(void __iomem * const regs)
2726 /* First disable interrupts */
2727 raw_reg_write(regs, DG1_MSTR_UNIT_INTR, 0);
2729 /* Get the indication levels and ack the master unit */
2730 val = raw_reg_read(regs, DG1_MSTR_UNIT_INTR);
2734 raw_reg_write(regs, DG1_MSTR_UNIT_INTR, val);
2737 * Now with master disabled, get a sample of level indications
2738 * for this interrupt and ack them right away - we keep GEN11_MASTER_IRQ
2739 * out as this bit doesn't exist anymore for DG1
2741 val = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ) & ~GEN11_MASTER_IRQ;
2745 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, val);
2750 static inline void dg1_master_intr_enable(void __iomem * const regs)
2752 raw_reg_write(regs, DG1_MSTR_UNIT_INTR, DG1_MSTR_IRQ);
2755 static irqreturn_t dg1_irq_handler(int irq, void *arg)
2757 return __gen11_irq_handler(arg,
2758 dg1_master_intr_disable_and_ack,
2759 dg1_master_intr_enable);
2762 /* Called from drm generic code, passed 'crtc' which
2763 * we use as a pipe index
2765 int i8xx_enable_vblank(struct drm_crtc *crtc)
2767 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2768 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2769 unsigned long irqflags;
2771 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2772 i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
2773 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2778 int i915gm_enable_vblank(struct drm_crtc *crtc)
2780 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2783 * Vblank interrupts fail to wake the device up from C2+.
2784 * Disabling render clock gating during C-states avoids
2785 * the problem. There is a small power cost so we do this
2786 * only when vblank interrupts are actually enabled.
2788 if (dev_priv->vblank_enabled++ == 0)
2789 intel_uncore_write(&dev_priv->uncore, SCPD0, _MASKED_BIT_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));
2791 return i8xx_enable_vblank(crtc);
2794 int i965_enable_vblank(struct drm_crtc *crtc)
2796 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2797 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2798 unsigned long irqflags;
2800 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2801 i915_enable_pipestat(dev_priv, pipe,
2802 PIPE_START_VBLANK_INTERRUPT_STATUS);
2803 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2808 int ilk_enable_vblank(struct drm_crtc *crtc)
2810 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2811 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2812 unsigned long irqflags;
2813 u32 bit = DISPLAY_VER(dev_priv) >= 7 ?
2814 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
2816 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2817 ilk_enable_display_irq(dev_priv, bit);
2818 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2820 /* Even though there is no DMC, frame counter can get stuck when
2821 * PSR is active as no frames are generated.
2823 if (HAS_PSR(dev_priv))
2824 drm_crtc_vblank_restore(crtc);
2829 static bool gen11_dsi_configure_te(struct intel_crtc *intel_crtc,
2832 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
2836 if (!(intel_crtc->mode_flags &
2837 (I915_MODE_FLAG_DSI_USE_TE1 | I915_MODE_FLAG_DSI_USE_TE0)))
2840 /* for dual link cases we consider TE from slave */
2841 if (intel_crtc->mode_flags & I915_MODE_FLAG_DSI_USE_TE1)
2846 tmp = intel_uncore_read(&dev_priv->uncore, DSI_INTR_MASK_REG(port));
2848 tmp &= ~DSI_TE_EVENT;
2850 tmp |= DSI_TE_EVENT;
2852 intel_uncore_write(&dev_priv->uncore, DSI_INTR_MASK_REG(port), tmp);
2854 tmp = intel_uncore_read(&dev_priv->uncore, DSI_INTR_IDENT_REG(port));
2855 intel_uncore_write(&dev_priv->uncore, DSI_INTR_IDENT_REG(port), tmp);
2860 int bdw_enable_vblank(struct drm_crtc *crtc)
2862 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2863 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2864 enum pipe pipe = intel_crtc->pipe;
2865 unsigned long irqflags;
2867 if (gen11_dsi_configure_te(intel_crtc, true))
2870 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2871 bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2872 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2874 /* Even if there is no DMC, frame counter can get stuck when
2875 * PSR is active as no frames are generated, so check only for PSR.
2877 if (HAS_PSR(dev_priv))
2878 drm_crtc_vblank_restore(crtc);
2883 /* Called from drm generic code, passed 'crtc' which
2884 * we use as a pipe index
2886 void i8xx_disable_vblank(struct drm_crtc *crtc)
2888 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2889 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2890 unsigned long irqflags;
2892 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2893 i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
2894 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2897 void i915gm_disable_vblank(struct drm_crtc *crtc)
2899 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2901 i8xx_disable_vblank(crtc);
2903 if (--dev_priv->vblank_enabled == 0)
2904 intel_uncore_write(&dev_priv->uncore, SCPD0, _MASKED_BIT_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));
2907 void i965_disable_vblank(struct drm_crtc *crtc)
2909 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2910 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2911 unsigned long irqflags;
2913 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2914 i915_disable_pipestat(dev_priv, pipe,
2915 PIPE_START_VBLANK_INTERRUPT_STATUS);
2916 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2919 void ilk_disable_vblank(struct drm_crtc *crtc)
2921 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2922 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2923 unsigned long irqflags;
2924 u32 bit = DISPLAY_VER(dev_priv) >= 7 ?
2925 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
2927 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2928 ilk_disable_display_irq(dev_priv, bit);
2929 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2932 void bdw_disable_vblank(struct drm_crtc *crtc)
2934 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2935 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2936 enum pipe pipe = intel_crtc->pipe;
2937 unsigned long irqflags;
2939 if (gen11_dsi_configure_te(intel_crtc, false))
2942 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2943 bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2944 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2947 static void ibx_irq_reset(struct drm_i915_private *dev_priv)
2949 struct intel_uncore *uncore = &dev_priv->uncore;
2951 if (HAS_PCH_NOP(dev_priv))
2954 GEN3_IRQ_RESET(uncore, SDE);
2956 if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
2957 intel_uncore_write(&dev_priv->uncore, SERR_INT, 0xffffffff);
2960 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
2962 struct intel_uncore *uncore = &dev_priv->uncore;
2964 if (IS_CHERRYVIEW(dev_priv))
2965 intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
2967 intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK);
2969 i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
2970 intel_uncore_write(uncore, PORT_HOTPLUG_STAT, intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT));
2972 i9xx_pipestat_irq_reset(dev_priv);
2974 GEN3_IRQ_RESET(uncore, VLV_);
2975 dev_priv->irq_mask = ~0u;
2978 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
2980 struct intel_uncore *uncore = &dev_priv->uncore;
2986 pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS;
2988 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
2989 for_each_pipe(dev_priv, pipe)
2990 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
2992 enable_mask = I915_DISPLAY_PORT_INTERRUPT |
2993 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2994 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2995 I915_LPE_PIPE_A_INTERRUPT |
2996 I915_LPE_PIPE_B_INTERRUPT;
2998 if (IS_CHERRYVIEW(dev_priv))
2999 enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT |
3000 I915_LPE_PIPE_C_INTERRUPT;
3002 drm_WARN_ON(&dev_priv->drm, dev_priv->irq_mask != ~0u);
3004 dev_priv->irq_mask = ~enable_mask;
3006 GEN3_IRQ_INIT(uncore, VLV_, dev_priv->irq_mask, enable_mask);
3011 static void ilk_irq_reset(struct drm_i915_private *dev_priv)
3013 struct intel_uncore *uncore = &dev_priv->uncore;
3015 GEN3_IRQ_RESET(uncore, DE);
3016 dev_priv->irq_mask = ~0u;
3018 if (IS_GEN(dev_priv, 7))
3019 intel_uncore_write(uncore, GEN7_ERR_INT, 0xffffffff);
3021 if (IS_HASWELL(dev_priv)) {
3022 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
3023 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
3026 gen5_gt_irq_reset(&dev_priv->gt);
3028 ibx_irq_reset(dev_priv);
3031 static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
3033 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, 0);
3034 intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER);
3036 gen5_gt_irq_reset(&dev_priv->gt);
3038 spin_lock_irq(&dev_priv->irq_lock);
3039 if (dev_priv->display_irqs_enabled)
3040 vlv_display_irq_reset(dev_priv);
3041 spin_unlock_irq(&dev_priv->irq_lock);
3044 static void cnp_display_clock_wa(struct drm_i915_private *dev_priv)
3046 struct intel_uncore *uncore = &dev_priv->uncore;
3049 * Wa_14010685332:cnp/cmp,tgp,adp
3050 * TODO: Clarify which platforms this applies to
3051 * TODO: Figure out if this workaround can be applied in the s0ix suspend/resume handlers as
3052 * on earlier platforms and whether the workaround is also needed for runtime suspend/resume
3054 if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
3055 (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
3056 intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS,
3057 SBCLK_RUN_REFCLK_DIS);
3058 intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
3062 static void gen8_irq_reset(struct drm_i915_private *dev_priv)
3064 struct intel_uncore *uncore = &dev_priv->uncore;
3067 gen8_master_intr_disable(dev_priv->uncore.regs);
3069 gen8_gt_irq_reset(&dev_priv->gt);
3071 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
3072 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
3074 for_each_pipe(dev_priv, pipe)
3075 if (intel_display_power_is_enabled(dev_priv,
3076 POWER_DOMAIN_PIPE(pipe)))
3077 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
3079 GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);
3080 GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
3081 GEN3_IRQ_RESET(uncore, GEN8_PCU_);
3083 if (HAS_PCH_SPLIT(dev_priv))
3084 ibx_irq_reset(dev_priv);
3086 cnp_display_clock_wa(dev_priv);
3089 static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
3091 struct intel_uncore *uncore = &dev_priv->uncore;
3093 u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
3094 BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
3096 intel_uncore_write(uncore, GEN11_DISPLAY_INT_CTL, 0);
3098 if (DISPLAY_VER(dev_priv) >= 12) {
3099 enum transcoder trans;
3101 for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {
3102 enum intel_display_power_domain domain;
3104 domain = POWER_DOMAIN_TRANSCODER(trans);
3105 if (!intel_display_power_is_enabled(dev_priv, domain))
3108 intel_uncore_write(uncore, TRANS_PSR_IMR(trans), 0xffffffff);
3109 intel_uncore_write(uncore, TRANS_PSR_IIR(trans), 0xffffffff);
3112 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
3113 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
3116 for_each_pipe(dev_priv, pipe)
3117 if (intel_display_power_is_enabled(dev_priv,
3118 POWER_DOMAIN_PIPE(pipe)))
3119 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
3121 GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);
3122 GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
3123 GEN3_IRQ_RESET(uncore, GEN11_DE_HPD_);
3125 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3126 GEN3_IRQ_RESET(uncore, SDE);
3128 cnp_display_clock_wa(dev_priv);
3131 static void gen11_irq_reset(struct drm_i915_private *dev_priv)
3133 struct intel_uncore *uncore = &dev_priv->uncore;
3135 if (HAS_MASTER_UNIT_IRQ(dev_priv))
3136 dg1_master_intr_disable_and_ack(dev_priv->uncore.regs);
3138 gen11_master_intr_disable(dev_priv->uncore.regs);
3140 gen11_gt_irq_reset(&dev_priv->gt);
3141 gen11_display_irq_reset(dev_priv);
3143 GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
3144 GEN3_IRQ_RESET(uncore, GEN8_PCU_);
3147 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
3150 struct intel_uncore *uncore = &dev_priv->uncore;
3151 u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN |
3152 gen8_de_pipe_flip_done_mask(dev_priv);
3155 spin_lock_irq(&dev_priv->irq_lock);
3157 if (!intel_irqs_enabled(dev_priv)) {
3158 spin_unlock_irq(&dev_priv->irq_lock);
3162 for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3163 GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,
3164 dev_priv->de_irq_mask[pipe],
3165 ~dev_priv->de_irq_mask[pipe] | extra_ier);
3167 spin_unlock_irq(&dev_priv->irq_lock);
3170 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
3173 struct intel_uncore *uncore = &dev_priv->uncore;
3176 spin_lock_irq(&dev_priv->irq_lock);
3178 if (!intel_irqs_enabled(dev_priv)) {
3179 spin_unlock_irq(&dev_priv->irq_lock);
3183 for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3184 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
3186 spin_unlock_irq(&dev_priv->irq_lock);
3188 /* make sure we're done processing display irqs */
3189 intel_synchronize_irq(dev_priv);
3192 static void cherryview_irq_reset(struct drm_i915_private *dev_priv)
3194 struct intel_uncore *uncore = &dev_priv->uncore;
3196 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, 0);
3197 intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ);
3199 gen8_gt_irq_reset(&dev_priv->gt);
3201 GEN3_IRQ_RESET(uncore, GEN8_PCU_);
3203 spin_lock_irq(&dev_priv->irq_lock);
3204 if (dev_priv->display_irqs_enabled)
3205 vlv_display_irq_reset(dev_priv);
3206 spin_unlock_irq(&dev_priv->irq_lock);
3209 static u32 ibx_hotplug_enables(struct drm_i915_private *i915,
3215 * When CPU and PCH are on the same package, port A
3216 * HPD must be enabled in both north and south.
3218 return HAS_PCH_LPT_LP(i915) ?
3219 PORTA_HOTPLUG_ENABLE : 0;
3221 return PORTB_HOTPLUG_ENABLE |
3222 PORTB_PULSE_DURATION_2ms;
3224 return PORTC_HOTPLUG_ENABLE |
3225 PORTC_PULSE_DURATION_2ms;
3227 return PORTD_HOTPLUG_ENABLE |
3228 PORTD_PULSE_DURATION_2ms;
3234 static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
3239 * Enable digital hotplug on the PCH, and configure the DP short pulse
3240 * duration to 2ms (which is the minimum in the Display Port spec).
3241 * The pulse duration bits are reserved on LPT+.
3243 hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);
3244 hotplug &= ~(PORTA_HOTPLUG_ENABLE |
3245 PORTB_HOTPLUG_ENABLE |
3246 PORTC_HOTPLUG_ENABLE |
3247 PORTD_HOTPLUG_ENABLE |
3248 PORTB_PULSE_DURATION_MASK |
3249 PORTC_PULSE_DURATION_MASK |
3250 PORTD_PULSE_DURATION_MASK);
3251 hotplug |= intel_hpd_hotplug_enables(dev_priv, ibx_hotplug_enables);
3252 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, hotplug);
3255 static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
3257 u32 hotplug_irqs, enabled_irqs;
3259 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3260 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3262 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3264 ibx_hpd_detection_setup(dev_priv);
3267 static u32 icp_ddi_hotplug_enables(struct drm_i915_private *i915,
3275 return SHOTPLUG_CTL_DDI_HPD_ENABLE(pin);
3281 static u32 icp_tc_hotplug_enables(struct drm_i915_private *i915,
3291 return ICP_TC_HPD_ENABLE(pin);
3297 static void icp_ddi_hpd_detection_setup(struct drm_i915_private *dev_priv)
3301 hotplug = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_DDI);
3302 hotplug &= ~(SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A) |
3303 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) |
3304 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_C) |
3305 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_D));
3306 hotplug |= intel_hpd_hotplug_enables(dev_priv, icp_ddi_hotplug_enables);
3307 intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_DDI, hotplug);
3310 static void icp_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
3314 hotplug = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_TC);
3315 hotplug &= ~(ICP_TC_HPD_ENABLE(HPD_PORT_TC1) |
3316 ICP_TC_HPD_ENABLE(HPD_PORT_TC2) |
3317 ICP_TC_HPD_ENABLE(HPD_PORT_TC3) |
3318 ICP_TC_HPD_ENABLE(HPD_PORT_TC4) |
3319 ICP_TC_HPD_ENABLE(HPD_PORT_TC5) |
3320 ICP_TC_HPD_ENABLE(HPD_PORT_TC6));
3321 hotplug |= intel_hpd_hotplug_enables(dev_priv, icp_tc_hotplug_enables);
3322 intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_TC, hotplug);
3325 static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv)
3327 u32 hotplug_irqs, enabled_irqs;
3329 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3330 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3332 if (INTEL_PCH_TYPE(dev_priv) <= PCH_TGP)
3333 intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
3335 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3337 icp_ddi_hpd_detection_setup(dev_priv);
3338 icp_tc_hpd_detection_setup(dev_priv);
3341 static u32 gen11_hotplug_enables(struct drm_i915_private *i915,
3351 return GEN11_HOTPLUG_CTL_ENABLE(pin);
3357 static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv)
3361 val = intel_uncore_read(&dev_priv->uncore, SOUTH_CHICKEN1);
3362 val |= (INVERT_DDIA_HPD |
3366 intel_uncore_write(&dev_priv->uncore, SOUTH_CHICKEN1, val);
3368 icp_hpd_irq_setup(dev_priv);
3371 static void gen11_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
3375 hotplug = intel_uncore_read(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL);
3376 hotplug &= ~(GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
3377 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) |
3378 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) |
3379 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) |
3380 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
3381 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6));
3382 hotplug |= intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables);
3383 intel_uncore_write(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL, hotplug);
3386 static void gen11_tbt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3390 hotplug = intel_uncore_read(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL);
3391 hotplug &= ~(GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
3392 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) |
3393 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) |
3394 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) |
3395 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
3396 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6));
3397 hotplug |= intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables);
3398 intel_uncore_write(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL, hotplug);
3401 static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
3403 u32 hotplug_irqs, enabled_irqs;
3406 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
3407 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd);
3409 val = intel_uncore_read(&dev_priv->uncore, GEN11_DE_HPD_IMR);
3410 val &= ~hotplug_irqs;
3411 val |= ~enabled_irqs & hotplug_irqs;
3412 intel_uncore_write(&dev_priv->uncore, GEN11_DE_HPD_IMR, val);
3413 intel_uncore_posting_read(&dev_priv->uncore, GEN11_DE_HPD_IMR);
3415 gen11_tc_hpd_detection_setup(dev_priv);
3416 gen11_tbt_hpd_detection_setup(dev_priv);
3418 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3419 icp_hpd_irq_setup(dev_priv);
3422 static u32 spt_hotplug_enables(struct drm_i915_private *i915,
3427 return PORTA_HOTPLUG_ENABLE;
3429 return PORTB_HOTPLUG_ENABLE;
3431 return PORTC_HOTPLUG_ENABLE;
3433 return PORTD_HOTPLUG_ENABLE;
3439 static u32 spt_hotplug2_enables(struct drm_i915_private *i915,
3444 return PORTE_HOTPLUG_ENABLE;
3450 static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3454 /* Display WA #1179 WaHardHangonHotPlug: cnp */
3455 if (HAS_PCH_CNP(dev_priv)) {
3456 val = intel_uncore_read(&dev_priv->uncore, SOUTH_CHICKEN1);
3457 val &= ~CHASSIS_CLK_REQ_DURATION_MASK;
3458 val |= CHASSIS_CLK_REQ_DURATION(0xf);
3459 intel_uncore_write(&dev_priv->uncore, SOUTH_CHICKEN1, val);
3462 /* Enable digital hotplug on the PCH */
3463 hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);
3464 hotplug &= ~(PORTA_HOTPLUG_ENABLE |
3465 PORTB_HOTPLUG_ENABLE |
3466 PORTC_HOTPLUG_ENABLE |
3467 PORTD_HOTPLUG_ENABLE);
3468 hotplug |= intel_hpd_hotplug_enables(dev_priv, spt_hotplug_enables);
3469 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, hotplug);
3471 hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG2);
3472 hotplug &= ~PORTE_HOTPLUG_ENABLE;
3473 hotplug |= intel_hpd_hotplug_enables(dev_priv, spt_hotplug2_enables);
3474 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG2, hotplug);
3477 static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3479 u32 hotplug_irqs, enabled_irqs;
3481 if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
3482 intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
3484 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3485 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3487 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3489 spt_hpd_detection_setup(dev_priv);
3492 static u32 ilk_hotplug_enables(struct drm_i915_private *i915,
3497 return DIGITAL_PORTA_HOTPLUG_ENABLE |
3498 DIGITAL_PORTA_PULSE_DURATION_2ms;
3504 static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv)
3509 * Enable digital hotplug on the CPU, and configure the DP short pulse
3510 * duration to 2ms (which is the minimum in the Display Port spec)
3511 * The pulse duration bits are reserved on HSW+.
3513 hotplug = intel_uncore_read(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL);
3514 hotplug &= ~(DIGITAL_PORTA_HOTPLUG_ENABLE |
3515 DIGITAL_PORTA_PULSE_DURATION_MASK);
3516 hotplug |= intel_hpd_hotplug_enables(dev_priv, ilk_hotplug_enables);
3517 intel_uncore_write(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
3520 static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
3522 u32 hotplug_irqs, enabled_irqs;
3524 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
3525 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd);
3527 if (DISPLAY_VER(dev_priv) >= 8)
3528 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3530 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3532 ilk_hpd_detection_setup(dev_priv);
3534 ibx_hpd_irq_setup(dev_priv);
3537 static u32 bxt_hotplug_enables(struct drm_i915_private *i915,
3544 hotplug = PORTA_HOTPLUG_ENABLE;
3545 if (intel_bios_is_port_hpd_inverted(i915, PORT_A))
3546 hotplug |= BXT_DDIA_HPD_INVERT;
3549 hotplug = PORTB_HOTPLUG_ENABLE;
3550 if (intel_bios_is_port_hpd_inverted(i915, PORT_B))
3551 hotplug |= BXT_DDIB_HPD_INVERT;
3554 hotplug = PORTC_HOTPLUG_ENABLE;
3555 if (intel_bios_is_port_hpd_inverted(i915, PORT_C))
3556 hotplug |= BXT_DDIC_HPD_INVERT;
3563 static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3567 hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);
3568 hotplug &= ~(PORTA_HOTPLUG_ENABLE |
3569 PORTB_HOTPLUG_ENABLE |
3570 PORTC_HOTPLUG_ENABLE |
3571 BXT_DDIA_HPD_INVERT |
3572 BXT_DDIB_HPD_INVERT |
3573 BXT_DDIC_HPD_INVERT);
3574 hotplug |= intel_hpd_hotplug_enables(dev_priv, bxt_hotplug_enables);
3575 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, hotplug);
3578 static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3580 u32 hotplug_irqs, enabled_irqs;
3582 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
3583 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd);
3585 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3587 bxt_hpd_detection_setup(dev_priv);
3591 * SDEIER is also touched by the interrupt handler to work around missed PCH
3592 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3593 * instead we unconditionally enable all PCH interrupt sources here, but then
3594 * only unmask them as needed with SDEIMR.
3596 * Note that we currently do this after installing the interrupt handler,
3597 * but before we enable the master interrupt. That should be sufficient
3598 * to avoid races with the irq handler, assuming we have MSI. Shared legacy
3599 * interrupts could still race.
3601 static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
3603 struct intel_uncore *uncore = &dev_priv->uncore;
3606 if (HAS_PCH_NOP(dev_priv))
3609 if (HAS_PCH_IBX(dev_priv))
3610 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3611 else if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
3612 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3614 mask = SDE_GMBUS_CPT;
3616 GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
3619 static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
3621 struct intel_uncore *uncore = &dev_priv->uncore;
3622 u32 display_mask, extra_mask;
3624 if (INTEL_GEN(dev_priv) >= 7) {
3625 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3626 DE_PCH_EVENT_IVB | DE_AUX_CHANNEL_A_IVB);
3627 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3628 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
3629 DE_PLANE_FLIP_DONE_IVB(PLANE_C) |
3630 DE_PLANE_FLIP_DONE_IVB(PLANE_B) |
3631 DE_PLANE_FLIP_DONE_IVB(PLANE_A) |
3632 DE_DP_A_HOTPLUG_IVB);
3634 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3635 DE_AUX_CHANNEL_A | DE_PIPEB_CRC_DONE |
3636 DE_PIPEA_CRC_DONE | DE_POISON);
3637 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK |
3638 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
3639 DE_PLANE_FLIP_DONE(PLANE_A) |
3640 DE_PLANE_FLIP_DONE(PLANE_B) |
3644 if (IS_HASWELL(dev_priv)) {
3645 gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
3646 display_mask |= DE_EDP_PSR_INT_HSW;
3649 if (IS_IRONLAKE_M(dev_priv))
3650 extra_mask |= DE_PCU_EVENT;
3652 dev_priv->irq_mask = ~display_mask;
3654 ibx_irq_postinstall(dev_priv);
3656 gen5_gt_irq_postinstall(&dev_priv->gt);
3658 GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask,
3659 display_mask | extra_mask);
3662 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3664 lockdep_assert_held(&dev_priv->irq_lock);
3666 if (dev_priv->display_irqs_enabled)
3669 dev_priv->display_irqs_enabled = true;
3671 if (intel_irqs_enabled(dev_priv)) {
3672 vlv_display_irq_reset(dev_priv);
3673 vlv_display_irq_postinstall(dev_priv);
3677 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3679 lockdep_assert_held(&dev_priv->irq_lock);
3681 if (!dev_priv->display_irqs_enabled)
3684 dev_priv->display_irqs_enabled = false;
3686 if (intel_irqs_enabled(dev_priv))
3687 vlv_display_irq_reset(dev_priv);
3691 static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv)
3693 gen5_gt_irq_postinstall(&dev_priv->gt);
3695 spin_lock_irq(&dev_priv->irq_lock);
3696 if (dev_priv->display_irqs_enabled)
3697 vlv_display_irq_postinstall(dev_priv);
3698 spin_unlock_irq(&dev_priv->irq_lock);
3700 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3701 intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER);
3704 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3706 struct intel_uncore *uncore = &dev_priv->uncore;
3708 u32 de_pipe_masked = gen8_de_pipe_fault_mask(dev_priv) |
3709 GEN8_PIPE_CDCLK_CRC_DONE;
3710 u32 de_pipe_enables;
3711 u32 de_port_masked = gen8_de_port_aux_mask(dev_priv);
3712 u32 de_port_enables;
3713 u32 de_misc_masked = GEN8_DE_EDP_PSR;
3714 u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
3715 BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
3718 if (DISPLAY_VER(dev_priv) <= 10)
3719 de_misc_masked |= GEN8_DE_MISC_GSE;
3721 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
3722 de_port_masked |= BXT_DE_PORT_GMBUS;
3724 if (DISPLAY_VER(dev_priv) >= 11) {
3727 if (intel_bios_is_dsi_present(dev_priv, &port))
3728 de_port_masked |= DSI0_TE | DSI1_TE;
3731 de_pipe_enables = de_pipe_masked |
3732 GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN |
3733 gen8_de_pipe_flip_done_mask(dev_priv);
3735 de_port_enables = de_port_masked;
3736 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
3737 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
3738 else if (IS_BROADWELL(dev_priv))
3739 de_port_enables |= BDW_DE_PORT_HOTPLUG_MASK;
3741 if (DISPLAY_VER(dev_priv) >= 12) {
3742 enum transcoder trans;
3744 for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {
3745 enum intel_display_power_domain domain;
3747 domain = POWER_DOMAIN_TRANSCODER(trans);
3748 if (!intel_display_power_is_enabled(dev_priv, domain))
3751 gen3_assert_iir_is_zero(uncore, TRANS_PSR_IIR(trans));
3754 gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
3757 for_each_pipe(dev_priv, pipe) {
3758 dev_priv->de_irq_mask[pipe] = ~de_pipe_masked;
3760 if (intel_display_power_is_enabled(dev_priv,
3761 POWER_DOMAIN_PIPE(pipe)))
3762 GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,
3763 dev_priv->de_irq_mask[pipe],
3767 GEN3_IRQ_INIT(uncore, GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
3768 GEN3_IRQ_INIT(uncore, GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
3770 if (DISPLAY_VER(dev_priv) >= 11) {
3771 u32 de_hpd_masked = 0;
3772 u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK |
3773 GEN11_DE_TBT_HOTPLUG_MASK;
3775 GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked,
3780 static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
3782 struct intel_uncore *uncore = &dev_priv->uncore;
3783 u32 mask = SDE_GMBUS_ICP;
3785 GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
3788 static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
3790 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3791 icp_irq_postinstall(dev_priv);
3792 else if (HAS_PCH_SPLIT(dev_priv))
3793 ibx_irq_postinstall(dev_priv);
3795 gen8_gt_irq_postinstall(&dev_priv->gt);
3796 gen8_de_irq_postinstall(dev_priv);
3798 gen8_master_intr_enable(dev_priv->uncore.regs);
3802 static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
3804 struct intel_uncore *uncore = &dev_priv->uncore;
3805 u32 gu_misc_masked = GEN11_GU_MISC_GSE;
3807 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3808 icp_irq_postinstall(dev_priv);
3810 gen11_gt_irq_postinstall(&dev_priv->gt);
3811 gen8_de_irq_postinstall(dev_priv);
3813 GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
3815 intel_uncore_write(&dev_priv->uncore, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
3817 if (HAS_MASTER_UNIT_IRQ(dev_priv)) {
3818 dg1_master_intr_enable(uncore->regs);
3819 intel_uncore_posting_read(&dev_priv->uncore, DG1_MSTR_UNIT_INTR);
3821 gen11_master_intr_enable(uncore->regs);
3822 intel_uncore_posting_read(&dev_priv->uncore, GEN11_GFX_MSTR_IRQ);
3826 static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
3828 gen8_gt_irq_postinstall(&dev_priv->gt);
3830 spin_lock_irq(&dev_priv->irq_lock);
3831 if (dev_priv->display_irqs_enabled)
3832 vlv_display_irq_postinstall(dev_priv);
3833 spin_unlock_irq(&dev_priv->irq_lock);
3835 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3836 intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ);
3839 static void i8xx_irq_reset(struct drm_i915_private *dev_priv)
3841 struct intel_uncore *uncore = &dev_priv->uncore;
3843 i9xx_pipestat_irq_reset(dev_priv);
3845 GEN2_IRQ_RESET(uncore);
3846 dev_priv->irq_mask = ~0u;
3849 static void i8xx_irq_postinstall(struct drm_i915_private *dev_priv)
3851 struct intel_uncore *uncore = &dev_priv->uncore;
3854 intel_uncore_write16(uncore,
3856 ~(I915_ERROR_PAGE_TABLE |
3857 I915_ERROR_MEMORY_REFRESH));
3859 /* Unmask the interrupts that we always want on. */
3860 dev_priv->irq_mask =
3861 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3862 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3863 I915_MASTER_ERROR_INTERRUPT);
3866 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3867 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3868 I915_MASTER_ERROR_INTERRUPT |
3869 I915_USER_INTERRUPT;
3871 GEN2_IRQ_INIT(uncore, dev_priv->irq_mask, enable_mask);
3873 /* Interrupt setup is already guaranteed to be single-threaded, this is
3874 * just to make the assert_spin_locked check happy. */
3875 spin_lock_irq(&dev_priv->irq_lock);
3876 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3877 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3878 spin_unlock_irq(&dev_priv->irq_lock);
3881 static void i8xx_error_irq_ack(struct drm_i915_private *i915,
3882 u16 *eir, u16 *eir_stuck)
3884 struct intel_uncore *uncore = &i915->uncore;
3887 *eir = intel_uncore_read16(uncore, EIR);
3890 intel_uncore_write16(uncore, EIR, *eir);
3892 *eir_stuck = intel_uncore_read16(uncore, EIR);
3893 if (*eir_stuck == 0)
3897 * Toggle all EMR bits to make sure we get an edge
3898 * in the ISR master error bit if we don't clear
3899 * all the EIR bits. Otherwise the edge triggered
3900 * IIR on i965/g4x wouldn't notice that an interrupt
3901 * is still pending. Also some EIR bits can't be
3902 * cleared except by handling the underlying error
3903 * (or by a GPU reset) so we mask any bit that
3906 emr = intel_uncore_read16(uncore, EMR);
3907 intel_uncore_write16(uncore, EMR, 0xffff);
3908 intel_uncore_write16(uncore, EMR, emr | *eir_stuck);
3911 static void i8xx_error_irq_handler(struct drm_i915_private *dev_priv,
3912 u16 eir, u16 eir_stuck)
3914 DRM_DEBUG("Master Error: EIR 0x%04x\n", eir);
3917 drm_dbg(&dev_priv->drm, "EIR stuck: 0x%04x, masked\n",
3921 static void i9xx_error_irq_ack(struct drm_i915_private *dev_priv,
3922 u32 *eir, u32 *eir_stuck)
3926 *eir = intel_uncore_read(&dev_priv->uncore, EIR);
3928 intel_uncore_write(&dev_priv->uncore, EIR, *eir);
3930 *eir_stuck = intel_uncore_read(&dev_priv->uncore, EIR);
3931 if (*eir_stuck == 0)
3935 * Toggle all EMR bits to make sure we get an edge
3936 * in the ISR master error bit if we don't clear
3937 * all the EIR bits. Otherwise the edge triggered
3938 * IIR on i965/g4x wouldn't notice that an interrupt
3939 * is still pending. Also some EIR bits can't be
3940 * cleared except by handling the underlying error
3941 * (or by a GPU reset) so we mask any bit that
3944 emr = intel_uncore_read(&dev_priv->uncore, EMR);
3945 intel_uncore_write(&dev_priv->uncore, EMR, 0xffffffff);
3946 intel_uncore_write(&dev_priv->uncore, EMR, emr | *eir_stuck);
3949 static void i9xx_error_irq_handler(struct drm_i915_private *dev_priv,
3950 u32 eir, u32 eir_stuck)
3952 DRM_DEBUG("Master Error, EIR 0x%08x\n", eir);
3955 drm_dbg(&dev_priv->drm, "EIR stuck: 0x%08x, masked\n",
3959 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3961 struct drm_i915_private *dev_priv = arg;
3962 irqreturn_t ret = IRQ_NONE;
3964 if (!intel_irqs_enabled(dev_priv))
3967 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3968 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
3971 u32 pipe_stats[I915_MAX_PIPES] = {};
3972 u16 eir = 0, eir_stuck = 0;
3975 iir = intel_uncore_read16(&dev_priv->uncore, GEN2_IIR);
3981 /* Call regardless, as some status bits might not be
3982 * signalled in iir */
3983 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
3985 if (iir & I915_MASTER_ERROR_INTERRUPT)
3986 i8xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
3988 intel_uncore_write16(&dev_priv->uncore, GEN2_IIR, iir);
3990 if (iir & I915_USER_INTERRUPT)
3991 intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]);
3993 if (iir & I915_MASTER_ERROR_INTERRUPT)
3994 i8xx_error_irq_handler(dev_priv, eir, eir_stuck);
3996 i8xx_pipestat_irq_handler(dev_priv, iir, pipe_stats);
3999 pmu_irq_stats(dev_priv, ret);
4001 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4006 static void i915_irq_reset(struct drm_i915_private *dev_priv)
4008 struct intel_uncore *uncore = &dev_priv->uncore;
4010 if (I915_HAS_HOTPLUG(dev_priv)) {
4011 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4012 intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_STAT, intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT));
4015 i9xx_pipestat_irq_reset(dev_priv);
4017 GEN3_IRQ_RESET(uncore, GEN2_);
4018 dev_priv->irq_mask = ~0u;
4021 static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
4023 struct intel_uncore *uncore = &dev_priv->uncore;
4026 intel_uncore_write(&dev_priv->uncore, EMR, ~(I915_ERROR_PAGE_TABLE |
4027 I915_ERROR_MEMORY_REFRESH));
4029 /* Unmask the interrupts that we always want on. */
4030 dev_priv->irq_mask =
4031 ~(I915_ASLE_INTERRUPT |
4032 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4033 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4034 I915_MASTER_ERROR_INTERRUPT);
4037 I915_ASLE_INTERRUPT |
4038 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4039 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4040 I915_MASTER_ERROR_INTERRUPT |
4041 I915_USER_INTERRUPT;
4043 if (I915_HAS_HOTPLUG(dev_priv)) {
4044 /* Enable in IER... */
4045 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
4046 /* and unmask in IMR */
4047 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
4050 GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);
4052 /* Interrupt setup is already guaranteed to be single-threaded, this is
4053 * just to make the assert_spin_locked check happy. */
4054 spin_lock_irq(&dev_priv->irq_lock);
4055 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4056 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4057 spin_unlock_irq(&dev_priv->irq_lock);
4059 i915_enable_asle_pipestat(dev_priv);
4062 static irqreturn_t i915_irq_handler(int irq, void *arg)
4064 struct drm_i915_private *dev_priv = arg;
4065 irqreturn_t ret = IRQ_NONE;
4067 if (!intel_irqs_enabled(dev_priv))
4070 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4071 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4074 u32 pipe_stats[I915_MAX_PIPES] = {};
4075 u32 eir = 0, eir_stuck = 0;
4076 u32 hotplug_status = 0;
4079 iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);
4085 if (I915_HAS_HOTPLUG(dev_priv) &&
4086 iir & I915_DISPLAY_PORT_INTERRUPT)
4087 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4089 /* Call regardless, as some status bits might not be
4090 * signalled in iir */
4091 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
4093 if (iir & I915_MASTER_ERROR_INTERRUPT)
4094 i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
4096 intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir);
4098 if (iir & I915_USER_INTERRUPT)
4099 intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]);
4101 if (iir & I915_MASTER_ERROR_INTERRUPT)
4102 i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
4105 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4107 i915_pipestat_irq_handler(dev_priv, iir, pipe_stats);
4110 pmu_irq_stats(dev_priv, ret);
4112 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4117 static void i965_irq_reset(struct drm_i915_private *dev_priv)
4119 struct intel_uncore *uncore = &dev_priv->uncore;
4121 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4122 intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_STAT, intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT));
4124 i9xx_pipestat_irq_reset(dev_priv);
4126 GEN3_IRQ_RESET(uncore, GEN2_);
4127 dev_priv->irq_mask = ~0u;
4130 static void i965_irq_postinstall(struct drm_i915_private *dev_priv)
4132 struct intel_uncore *uncore = &dev_priv->uncore;
4137 * Enable some error detection, note the instruction error mask
4138 * bit is reserved, so we leave it masked.
4140 if (IS_G4X(dev_priv)) {
4141 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4142 GM45_ERROR_MEM_PRIV |
4143 GM45_ERROR_CP_PRIV |
4144 I915_ERROR_MEMORY_REFRESH);
4146 error_mask = ~(I915_ERROR_PAGE_TABLE |
4147 I915_ERROR_MEMORY_REFRESH);
4149 intel_uncore_write(&dev_priv->uncore, EMR, error_mask);
4151 /* Unmask the interrupts that we always want on. */
4152 dev_priv->irq_mask =
4153 ~(I915_ASLE_INTERRUPT |
4154 I915_DISPLAY_PORT_INTERRUPT |
4155 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4156 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4157 I915_MASTER_ERROR_INTERRUPT);
4160 I915_ASLE_INTERRUPT |
4161 I915_DISPLAY_PORT_INTERRUPT |
4162 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4163 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4164 I915_MASTER_ERROR_INTERRUPT |
4165 I915_USER_INTERRUPT;
4167 if (IS_G4X(dev_priv))
4168 enable_mask |= I915_BSD_USER_INTERRUPT;
4170 GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);
4172 /* Interrupt setup is already guaranteed to be single-threaded, this is
4173 * just to make the assert_spin_locked check happy. */
4174 spin_lock_irq(&dev_priv->irq_lock);
4175 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4176 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4177 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4178 spin_unlock_irq(&dev_priv->irq_lock);
4180 i915_enable_asle_pipestat(dev_priv);
4183 static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
4187 lockdep_assert_held(&dev_priv->irq_lock);
4189 /* Note HDMI and DP share hotplug bits */
4190 /* enable bits are the same for all generations */
4191 hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);
4192 /* Programming the CRT detection parameters tends
4193 to generate a spurious hotplug event about three
4194 seconds later. So just do it once.
4196 if (IS_G4X(dev_priv))
4197 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4198 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4200 /* Ignore TV since it's buggy */
4201 i915_hotplug_interrupt_update_locked(dev_priv,
4202 HOTPLUG_INT_EN_MASK |
4203 CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
4204 CRT_HOTPLUG_ACTIVATION_PERIOD_64,
4208 static irqreturn_t i965_irq_handler(int irq, void *arg)
4210 struct drm_i915_private *dev_priv = arg;
4211 irqreturn_t ret = IRQ_NONE;
4213 if (!intel_irqs_enabled(dev_priv))
4216 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4217 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4220 u32 pipe_stats[I915_MAX_PIPES] = {};
4221 u32 eir = 0, eir_stuck = 0;
4222 u32 hotplug_status = 0;
4225 iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);
4231 if (iir & I915_DISPLAY_PORT_INTERRUPT)
4232 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4234 /* Call regardless, as some status bits might not be
4235 * signalled in iir */
4236 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
4238 if (iir & I915_MASTER_ERROR_INTERRUPT)
4239 i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
4241 intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir);
4243 if (iir & I915_USER_INTERRUPT)
4244 intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]);
4246 if (iir & I915_BSD_USER_INTERRUPT)
4247 intel_engine_signal_breadcrumbs(dev_priv->gt.engine[VCS0]);
4249 if (iir & I915_MASTER_ERROR_INTERRUPT)
4250 i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
4253 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4255 i965_pipestat_irq_handler(dev_priv, iir, pipe_stats);
4258 pmu_irq_stats(dev_priv, IRQ_HANDLED);
4260 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4266 * intel_irq_init - initializes irq support
4267 * @dev_priv: i915 device instance
4269 * This function initializes all the irq support including work items, timers
4270 * and all the vtables. It does not setup the interrupt itself though.
4272 void intel_irq_init(struct drm_i915_private *dev_priv)
4274 struct drm_device *dev = &dev_priv->drm;
4277 INIT_WORK(&dev_priv->l3_parity.error_work, ivb_parity_work);
4278 for (i = 0; i < MAX_L3_SLICES; ++i)
4279 dev_priv->l3_parity.remap_info[i] = NULL;
4281 /* pre-gen11 the guc irqs bits are in the upper 16 bits of the pm reg */
4282 if (HAS_GT_UC(dev_priv) && INTEL_GEN(dev_priv) < 11)
4283 dev_priv->gt.pm_guc_events = GUC_INTR_GUC2HOST << 16;
4285 if (!HAS_DISPLAY(dev_priv))
4288 intel_hpd_init_pins(dev_priv);
4290 intel_hpd_init_work(dev_priv);
4292 dev->vblank_disable_immediate = true;
4294 /* Most platforms treat the display irq block as an always-on
4295 * power domain. vlv/chv can disable it at runtime and need
4296 * special care to avoid writing any of the display block registers
4297 * outside of the power domain. We defer setting up the display irqs
4298 * in this case to the runtime pm.
4300 dev_priv->display_irqs_enabled = true;
4301 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4302 dev_priv->display_irqs_enabled = false;
4304 dev_priv->hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD;
4305 /* If we have MST support, we want to avoid doing short HPD IRQ storm
4306 * detection, as short HPD storms will occur as a natural part of
4307 * sideband messaging with MST.
4308 * On older platforms however, IRQ storms can occur with both long and
4309 * short pulses, as seen on some G4x systems.
4311 dev_priv->hotplug.hpd_short_storm_enabled = !HAS_DP_MST(dev_priv);
4313 if (HAS_GMCH(dev_priv)) {
4314 if (I915_HAS_HOTPLUG(dev_priv))
4315 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4317 if (HAS_PCH_DG1(dev_priv))
4318 dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup;
4319 else if (DISPLAY_VER(dev_priv) >= 11)
4320 dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
4321 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
4322 dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4323 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
4324 dev_priv->display.hpd_irq_setup = icp_hpd_irq_setup;
4325 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
4326 dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4328 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4333 * intel_irq_fini - deinitializes IRQ support
4334 * @i915: i915 device instance
4336 * This function deinitializes all the IRQ support.
4338 void intel_irq_fini(struct drm_i915_private *i915)
4342 for (i = 0; i < MAX_L3_SLICES; ++i)
4343 kfree(i915->l3_parity.remap_info[i]);
4346 static irq_handler_t intel_irq_handler(struct drm_i915_private *dev_priv)
4348 if (HAS_GMCH(dev_priv)) {
4349 if (IS_CHERRYVIEW(dev_priv))
4350 return cherryview_irq_handler;
4351 else if (IS_VALLEYVIEW(dev_priv))
4352 return valleyview_irq_handler;
4353 else if (IS_GEN(dev_priv, 4))
4354 return i965_irq_handler;
4355 else if (IS_GEN(dev_priv, 3))
4356 return i915_irq_handler;
4358 return i8xx_irq_handler;
4360 if (HAS_MASTER_UNIT_IRQ(dev_priv))
4361 return dg1_irq_handler;
4362 if (INTEL_GEN(dev_priv) >= 11)
4363 return gen11_irq_handler;
4364 else if (INTEL_GEN(dev_priv) >= 8)
4365 return gen8_irq_handler;
4367 return ilk_irq_handler;
4371 static void intel_irq_reset(struct drm_i915_private *dev_priv)
4373 if (HAS_GMCH(dev_priv)) {
4374 if (IS_CHERRYVIEW(dev_priv))
4375 cherryview_irq_reset(dev_priv);
4376 else if (IS_VALLEYVIEW(dev_priv))
4377 valleyview_irq_reset(dev_priv);
4378 else if (IS_GEN(dev_priv, 4))
4379 i965_irq_reset(dev_priv);
4380 else if (IS_GEN(dev_priv, 3))
4381 i915_irq_reset(dev_priv);
4383 i8xx_irq_reset(dev_priv);
4385 if (INTEL_GEN(dev_priv) >= 11)
4386 gen11_irq_reset(dev_priv);
4387 else if (INTEL_GEN(dev_priv) >= 8)
4388 gen8_irq_reset(dev_priv);
4390 ilk_irq_reset(dev_priv);
4394 static void intel_irq_postinstall(struct drm_i915_private *dev_priv)
4396 if (HAS_GMCH(dev_priv)) {
4397 if (IS_CHERRYVIEW(dev_priv))
4398 cherryview_irq_postinstall(dev_priv);
4399 else if (IS_VALLEYVIEW(dev_priv))
4400 valleyview_irq_postinstall(dev_priv);
4401 else if (IS_GEN(dev_priv, 4))
4402 i965_irq_postinstall(dev_priv);
4403 else if (IS_GEN(dev_priv, 3))
4404 i915_irq_postinstall(dev_priv);
4406 i8xx_irq_postinstall(dev_priv);
4408 if (INTEL_GEN(dev_priv) >= 11)
4409 gen11_irq_postinstall(dev_priv);
4410 else if (INTEL_GEN(dev_priv) >= 8)
4411 gen8_irq_postinstall(dev_priv);
4413 ilk_irq_postinstall(dev_priv);
4418 * intel_irq_install - enables the hardware interrupt
4419 * @dev_priv: i915 device instance
4421 * This function enables the hardware interrupt handling, but leaves the hotplug
4422 * handling still disabled. It is called after intel_irq_init().
4424 * In the driver load and resume code we need working interrupts in a few places
4425 * but don't want to deal with the hassle of concurrent probe and hotplug
4426 * workers. Hence the split into this two-stage approach.
4428 int intel_irq_install(struct drm_i915_private *dev_priv)
4430 int irq = to_pci_dev(dev_priv->drm.dev)->irq;
4434 * We enable some interrupt sources in our postinstall hooks, so mark
4435 * interrupts as enabled _before_ actually enabling them to avoid
4436 * special cases in our ordering checks.
4438 dev_priv->runtime_pm.irqs_enabled = true;
4440 dev_priv->drm.irq_enabled = true;
4442 intel_irq_reset(dev_priv);
4444 ret = request_irq(irq, intel_irq_handler(dev_priv),
4445 IRQF_SHARED, DRIVER_NAME, dev_priv);
4447 dev_priv->drm.irq_enabled = false;
4451 intel_irq_postinstall(dev_priv);
4457 * intel_irq_uninstall - finilizes all irq handling
4458 * @dev_priv: i915 device instance
4460 * This stops interrupt and hotplug handling and unregisters and frees all
4461 * resources acquired in the init functions.
4463 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4465 int irq = to_pci_dev(dev_priv->drm.dev)->irq;
4468 * FIXME we can get called twice during driver probe
4469 * error handling as well as during driver remove due to
4470 * intel_modeset_driver_remove() calling us out of sequence.
4471 * Would be nice if it didn't do that...
4473 if (!dev_priv->drm.irq_enabled)
4476 dev_priv->drm.irq_enabled = false;
4478 intel_irq_reset(dev_priv);
4480 free_irq(irq, dev_priv);
4482 intel_hpd_cancel_work(dev_priv);
4483 dev_priv->runtime_pm.irqs_enabled = false;
4487 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4488 * @dev_priv: i915 device instance
4490 * This function is used to disable interrupts at runtime, both in the runtime
4491 * pm and the system suspend/resume code.
4493 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4495 intel_irq_reset(dev_priv);
4496 dev_priv->runtime_pm.irqs_enabled = false;
4497 intel_synchronize_irq(dev_priv);
4501 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4502 * @dev_priv: i915 device instance
4504 * This function is used to enable interrupts at runtime, both in the runtime
4505 * pm and the system suspend/resume code.
4507 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4509 dev_priv->runtime_pm.irqs_enabled = true;
4510 intel_irq_reset(dev_priv);
4511 intel_irq_postinstall(dev_priv);
4514 bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
4517 * We only use drm_irq_uninstall() at unload and VT switch, so
4518 * this is the only thing we need to check.
4520 return dev_priv->runtime_pm.irqs_enabled;
4523 void intel_synchronize_irq(struct drm_i915_private *i915)
4525 synchronize_irq(to_pci_dev(i915->drm.dev)->irq);