drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include <linux/circ_buf.h>
  34 #include <drm/drmP.h>
  35 #include <drm/i915_drm.h>
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "intel_drv.h"
  39
  40 /**
  41  * DOC: interrupt handling
  42  *
  43  * These functions provide the basic support for enabling and disabling the
  44  * interrupt handling support. There's a lot more functionality in i915_irq.c
  45  * and related files, but that will be described in separate chapters.
  46  */
  47
  48 static const u32 hpd_ilk[HPD_NUM_PINS] = {
  49         [HPD_PORT_A] = DE_DP_A_HOTPLUG,
  50 };
  51
  52 static const u32 hpd_ivb[HPD_NUM_PINS] = {
  53         [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
  54 };
  55
  56 static const u32 hpd_bdw[HPD_NUM_PINS] = {
  57         [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
  58 };
  59
  60 static const u32 hpd_ibx[HPD_NUM_PINS] = {
  61         [HPD_CRT] = SDE_CRT_HOTPLUG,
  62         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
  63         [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
  64         [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
  65         [HPD_PORT_D] = SDE_PORTD_HOTPLUG
  66 };
  67
  68 static const u32 hpd_cpt[HPD_NUM_PINS] = {
  69         [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
  70         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
  71         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  72         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  73         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
  74 };
  75
  76 static const u32 hpd_spt[HPD_NUM_PINS] = {
  77         [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
  78         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  79         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  80         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
  81         [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT
  82 };
  83
  84 static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
  85         [HPD_CRT] = CRT_HOTPLUG_INT_EN,
  86         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
  87         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
  88         [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
  89         [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
  90         [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
  91 };
  92
  93 static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
  94         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  95         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
  96         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
  97         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  98         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  99         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
 100 };
 101
 102 static const u32 hpd_status_i915[HPD_NUM_PINS] = {
 103         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
 104         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
 105         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
 106         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
 107         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
 108         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
 109 };
 110
 111 /* BXT hpd list */
 112 static const u32 hpd_bxt[HPD_NUM_PINS] = {
 113         [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
 114         [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
 115         [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
 116 };
 117
 118 /* IIR can theoretically queue up two events. Be paranoid. */
 119 #define GEN8_IRQ_RESET_NDX(type, which) do { \
 120         I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
 121         POSTING_READ(GEN8_##type##_IMR(which)); \
 122         I915_WRITE(GEN8_##type##_IER(which), 0); \
 123         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
 124         POSTING_READ(GEN8_##type##_IIR(which)); \
 125         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
 126         POSTING_READ(GEN8_##type##_IIR(which)); \
 127 } while (0)
 128
 129 #define GEN5_IRQ_RESET(type) do { \
 130         I915_WRITE(type##IMR, 0xffffffff); \
 131         POSTING_READ(type##IMR); \
 132         I915_WRITE(type##IER, 0); \
 133         I915_WRITE(type##IIR, 0xffffffff); \
 134         POSTING_READ(type##IIR); \
 135         I915_WRITE(type##IIR, 0xffffffff); \
 136         POSTING_READ(type##IIR); \
 137 } while (0)
 138
 139 /*
 140  * We should clear IMR at preinstall/uninstall, and just check at postinstall.
 141  */
 142 static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv,
 143                                     i915_reg_t reg)
 144 {
 145         u32 val = I915_READ(reg);
 146
 147         if (val == 0)
 148                 return;
 149
 150         WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
 151              i915_mmio_reg_offset(reg), val);
 152         I915_WRITE(reg, 0xffffffff);
 153         POSTING_READ(reg);
 154         I915_WRITE(reg, 0xffffffff);
 155         POSTING_READ(reg);
 156 }
 157
 158 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
 159         gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
 160         I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
 161         I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
 162         POSTING_READ(GEN8_##type##_IMR(which)); \
 163 } while (0)
 164
 165 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
 166         gen5_assert_iir_is_zero(dev_priv, type##IIR); \
 167         I915_WRITE(type##IER, (ier_val)); \
 168         I915_WRITE(type##IMR, (imr_val)); \
 169         POSTING_READ(type##IMR); \
 170 } while (0)
 171
 172 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
 173 static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
 174
 175 /* For display hotplug interrupt */
 176 static inline void
 177 i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
 178                                      uint32_t mask,
 179                                      uint32_t bits)
 180 {
 181         uint32_t val;
 182
 183         lockdep_assert_held(&dev_priv->irq_lock);
 184         WARN_ON(bits & ~mask);
 185
 186         val = I915_READ(PORT_HOTPLUG_EN);
 187         val &= ~mask;
 188         val |= bits;
 189         I915_WRITE(PORT_HOTPLUG_EN, val);
 190 }
 191
 192 /**
 193  * i915_hotplug_interrupt_update - update hotplug interrupt enable
 194  * @dev_priv: driver private
 195  * @mask: bits to update
 196  * @bits: bits to enable
 197  * NOTE: the HPD enable bits are modified both inside and outside
 198  * of an interrupt context. To avoid that read-modify-write cycles
 199  * interfer, these bits are protected by a spinlock. Since this
 200  * function is usually not called from a context where the lock is
 201  * held already, this function acquires the lock itself. A non-locking
 202  * version is also available.
 203  */
 204 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
 205                                    uint32_t mask,
 206                                    uint32_t bits)
 207 {
 208         spin_lock_irq(&dev_priv->irq_lock);
 209         i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
 210         spin_unlock_irq(&dev_priv->irq_lock);
 211 }
 212
 213 /**
 214  * ilk_update_display_irq - update DEIMR
 215  * @dev_priv: driver private
 216  * @interrupt_mask: mask of interrupt bits to update
 217  * @enabled_irq_mask: mask of interrupt bits to enable
 218  */
 219 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
 220                             uint32_t interrupt_mask,
 221                             uint32_t enabled_irq_mask)
 222 {
 223         uint32_t new_val;
 224
 225         lockdep_assert_held(&dev_priv->irq_lock);
 226
 227         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 228
 229         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 230                 return;
 231
 232         new_val = dev_priv->irq_mask;
 233         new_val &= ~interrupt_mask;
 234         new_val |= (~enabled_irq_mask & interrupt_mask);
 235
 236         if (new_val != dev_priv->irq_mask) {
 237                 dev_priv->irq_mask = new_val;
 238                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 239                 POSTING_READ(DEIMR);
 240         }
 241 }
 242
 243 /**
 244  * ilk_update_gt_irq - update GTIMR
 245  * @dev_priv: driver private
 246  * @interrupt_mask: mask of interrupt bits to update
 247  * @enabled_irq_mask: mask of interrupt bits to enable
 248  */
 249 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
 250                               uint32_t interrupt_mask,
 251                               uint32_t enabled_irq_mask)
 252 {
 253         lockdep_assert_held(&dev_priv->irq_lock);
 254
 255         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 256
 257         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 258                 return;
 259
 260         dev_priv->gt_irq_mask &= ~interrupt_mask;
 261         dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
 262         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 263 }
 264
 265 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 266 {
 267         ilk_update_gt_irq(dev_priv, mask, mask);
 268         POSTING_READ_FW(GTIMR);
 269 }
 270
 271 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 272 {
 273         ilk_update_gt_irq(dev_priv, mask, 0);
 274 }
 275
 276 static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
 277 {
 278         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
 279 }
 280
 281 static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
 282 {
 283         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
 284 }
 285
 286 static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
 287 {
 288         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
 289 }
 290
 291 /**
 292  * snb_update_pm_irq - update GEN6_PMIMR
 293  * @dev_priv: driver private
 294  * @interrupt_mask: mask of interrupt bits to update
 295  * @enabled_irq_mask: mask of interrupt bits to enable
 296  */
 297 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
 298                               uint32_t interrupt_mask,
 299                               uint32_t enabled_irq_mask)
 300 {
 301         uint32_t new_val;
 302
 303         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 304
 305         lockdep_assert_held(&dev_priv->irq_lock);
 306
 307         new_val = dev_priv->pm_imr;
 308         new_val &= ~interrupt_mask;
 309         new_val |= (~enabled_irq_mask & interrupt_mask);
 310
 311         if (new_val != dev_priv->pm_imr) {
 312                 dev_priv->pm_imr = new_val;
 313                 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_imr);
 314                 POSTING_READ(gen6_pm_imr(dev_priv));
 315         }
 316 }
 317
 318 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
 319 {
 320         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 321                 return;
 322
 323         snb_update_pm_irq(dev_priv, mask, mask);
 324 }
 325
 326 static void __gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
 327 {
 328         snb_update_pm_irq(dev_priv, mask, 0);
 329 }
 330
 331 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
 332 {
 333         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 334                 return;
 335
 336         __gen6_mask_pm_irq(dev_priv, mask);
 337 }
 338
 339 void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
 340 {
 341         i915_reg_t reg = gen6_pm_iir(dev_priv);
 342
 343         lockdep_assert_held(&dev_priv->irq_lock);
 344
 345         I915_WRITE(reg, reset_mask);
 346         I915_WRITE(reg, reset_mask);
 347         POSTING_READ(reg);
 348 }
 349
 350 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask)
 351 {
 352         lockdep_assert_held(&dev_priv->irq_lock);
 353
 354         dev_priv->pm_ier |= enable_mask;
 355         I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier);
 356         gen6_unmask_pm_irq(dev_priv, enable_mask);
 357         /* unmask_pm_irq provides an implicit barrier (POSTING_READ) */
 358 }
 359
 360 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask)
 361 {
 362         lockdep_assert_held(&dev_priv->irq_lock);
 363
 364         dev_priv->pm_ier &= ~disable_mask;
 365         __gen6_mask_pm_irq(dev_priv, disable_mask);
 366         I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier);
 367         /* though a barrier is missing here, but don't really need a one */
 368 }
 369
 370 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
 371 {
 372         spin_lock_irq(&dev_priv->irq_lock);
 373         gen6_reset_pm_iir(dev_priv, dev_priv->pm_rps_events);
 374         dev_priv->rps.pm_iir = 0;
 375         spin_unlock_irq(&dev_priv->irq_lock);
 376 }
 377
 378 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
 379 {
 380         if (READ_ONCE(dev_priv->rps.interrupts_enabled))
 381                 return;
 382
 383         spin_lock_irq(&dev_priv->irq_lock);
 384         WARN_ON_ONCE(dev_priv->rps.pm_iir);
 385         WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
 386         dev_priv->rps.interrupts_enabled = true;
 387         gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
 388
 389         spin_unlock_irq(&dev_priv->irq_lock);
 390 }
 391
 392 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
 393 {
 394         if (!READ_ONCE(dev_priv->rps.interrupts_enabled))
 395                 return;
 396
 397         spin_lock_irq(&dev_priv->irq_lock);
 398         dev_priv->rps.interrupts_enabled = false;
 399
 400         I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0u));
 401
 402         gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
 403
 404         spin_unlock_irq(&dev_priv->irq_lock);
 405         synchronize_irq(dev_priv->drm.irq);
 406
 407         /* Now that we will not be generating any more work, flush any
 408          * outsanding tasks. As we are called on the RPS idle path,
 409          * we will reset the GPU to minimum frequencies, so the current
 410          * state of the worker can be discarded.
 411          */
 412         cancel_work_sync(&dev_priv->rps.work);
 413         gen6_reset_rps_interrupts(dev_priv);
 414 }
 415
 416 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
 417 {
 418         spin_lock_irq(&dev_priv->irq_lock);
 419         gen6_reset_pm_iir(dev_priv, dev_priv->pm_guc_events);
 420         spin_unlock_irq(&dev_priv->irq_lock);
 421 }
 422
 423 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
 424 {
 425         spin_lock_irq(&dev_priv->irq_lock);
 426         if (!dev_priv->guc.interrupts_enabled) {
 427                 WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
 428                                        dev_priv->pm_guc_events);
 429                 dev_priv->guc.interrupts_enabled = true;
 430                 gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events);
 431         }
 432         spin_unlock_irq(&dev_priv->irq_lock);
 433 }
 434
 435 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
 436 {
 437         spin_lock_irq(&dev_priv->irq_lock);
 438         dev_priv->guc.interrupts_enabled = false;
 439
 440         gen6_disable_pm_irq(dev_priv, dev_priv->pm_guc_events);
 441
 442         spin_unlock_irq(&dev_priv->irq_lock);
 443         synchronize_irq(dev_priv->drm.irq);
 444
 445         gen9_reset_guc_interrupts(dev_priv);
 446 }
 447
 448 /**
 449  * bdw_update_port_irq - update DE port interrupt
 450  * @dev_priv: driver private
 451  * @interrupt_mask: mask of interrupt bits to update
 452  * @enabled_irq_mask: mask of interrupt bits to enable
 453  */
 454 static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
 455                                 uint32_t interrupt_mask,
 456                                 uint32_t enabled_irq_mask)
 457 {
 458         uint32_t new_val;
 459         uint32_t old_val;
 460
 461         lockdep_assert_held(&dev_priv->irq_lock);
 462
 463         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 464
 465         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 466                 return;
 467
 468         old_val = I915_READ(GEN8_DE_PORT_IMR);
 469
 470         new_val = old_val;
 471         new_val &= ~interrupt_mask;
 472         new_val |= (~enabled_irq_mask & interrupt_mask);
 473
 474         if (new_val != old_val) {
 475                 I915_WRITE(GEN8_DE_PORT_IMR, new_val);
 476                 POSTING_READ(GEN8_DE_PORT_IMR);
 477         }
 478 }
 479
 480 /**
 481  * bdw_update_pipe_irq - update DE pipe interrupt
 482  * @dev_priv: driver private
 483  * @pipe: pipe whose interrupt to update
 484  * @interrupt_mask: mask of interrupt bits to update
 485  * @enabled_irq_mask: mask of interrupt bits to enable
 486  */
 487 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
 488                          enum pipe pipe,
 489                          uint32_t interrupt_mask,
 490                          uint32_t enabled_irq_mask)
 491 {
 492         uint32_t new_val;
 493
 494         lockdep_assert_held(&dev_priv->irq_lock);
 495
 496         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 497
 498         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 499                 return;
 500
 501         new_val = dev_priv->de_irq_mask[pipe];
 502         new_val &= ~interrupt_mask;
 503         new_val |= (~enabled_irq_mask & interrupt_mask);
 504
 505         if (new_val != dev_priv->de_irq_mask[pipe]) {
 506                 dev_priv->de_irq_mask[pipe] = new_val;
 507                 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
 508                 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
 509         }
 510 }
 511
 512 /**
 513  * ibx_display_interrupt_update - update SDEIMR
 514  * @dev_priv: driver private
 515  * @interrupt_mask: mask of interrupt bits to update
 516  * @enabled_irq_mask: mask of interrupt bits to enable
 517  */
 518 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
 519                                   uint32_t interrupt_mask,
 520                                   uint32_t enabled_irq_mask)
 521 {
 522         uint32_t sdeimr = I915_READ(SDEIMR);
 523         sdeimr &= ~interrupt_mask;
 524         sdeimr |= (~enabled_irq_mask & interrupt_mask);
 525
 526         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 527
 528         lockdep_assert_held(&dev_priv->irq_lock);
 529
 530         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 531                 return;
 532
 533         I915_WRITE(SDEIMR, sdeimr);
 534         POSTING_READ(SDEIMR);
 535 }
 536
 537 static void
 538 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 539                        u32 enable_mask, u32 status_mask)
 540 {
 541         i915_reg_t reg = PIPESTAT(pipe);
 542         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 543
 544         lockdep_assert_held(&dev_priv->irq_lock);
 545         WARN_ON(!intel_irqs_enabled(dev_priv));
 546
 547         if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 548                       status_mask & ~PIPESTAT_INT_STATUS_MASK,
 549                       "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
 550                       pipe_name(pipe), enable_mask, status_mask))
 551                 return;
 552
 553         if ((pipestat & enable_mask) == enable_mask)
 554                 return;
 555
 556         dev_priv->pipestat_irq_mask[pipe] |= status_mask;
 557
 558         /* Enable the interrupt, clear any pending status */
 559         pipestat |= enable_mask | status_mask;
 560         I915_WRITE(reg, pipestat);
 561         POSTING_READ(reg);
 562 }
 563
 564 static void
 565 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 566                         u32 enable_mask, u32 status_mask)
 567 {
 568         i915_reg_t reg = PIPESTAT(pipe);
 569         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 570
 571         lockdep_assert_held(&dev_priv->irq_lock);
 572         WARN_ON(!intel_irqs_enabled(dev_priv));
 573
 574         if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 575                       status_mask & ~PIPESTAT_INT_STATUS_MASK,
 576                       "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
 577                       pipe_name(pipe), enable_mask, status_mask))
 578                 return;
 579
 580         if ((pipestat & enable_mask) == 0)
 581                 return;
 582
 583         dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
 584
 585         pipestat &= ~enable_mask;
 586         I915_WRITE(reg, pipestat);
 587         POSTING_READ(reg);
 588 }
 589
 590 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
 591 {
 592         u32 enable_mask = status_mask << 16;
 593
 594         /*
 595          * On pipe A we don't support the PSR interrupt yet,
 596          * on pipe B and C the same bit MBZ.
 597          */
 598         if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
 599                 return 0;
 600         /*
 601          * On pipe B and C we don't support the PSR interrupt yet, on pipe
 602          * A the same bit is for perf counters which we don't use either.
 603          */
 604         if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
 605                 return 0;
 606
 607         enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
 608                          SPRITE0_FLIP_DONE_INT_EN_VLV |
 609                          SPRITE1_FLIP_DONE_INT_EN_VLV);
 610         if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
 611                 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
 612         if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
 613                 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
 614
 615         return enable_mask;
 616 }
 617
 618 void
 619 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 620                      u32 status_mask)
 621 {
 622         u32 enable_mask;
 623
 624         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 625                 enable_mask = vlv_get_pipestat_enable_mask(&dev_priv->drm,
 626                                                            status_mask);
 627         else
 628                 enable_mask = status_mask << 16;
 629         __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 630 }
 631
 632 void
 633 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 634                       u32 status_mask)
 635 {
 636         u32 enable_mask;
 637
 638         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 639                 enable_mask = vlv_get_pipestat_enable_mask(&dev_priv->drm,
 640                                                            status_mask);
 641         else
 642                 enable_mask = status_mask << 16;
 643         __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 644 }
 645
 646 /**
 647  * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
 648  * @dev_priv: i915 device private
 649  */
 650 static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
 651 {
 652         if (!dev_priv->opregion.asle || !IS_MOBILE(dev_priv))
 653                 return;
 654
 655         spin_lock_irq(&dev_priv->irq_lock);
 656
 657         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
 658         if (INTEL_GEN(dev_priv) >= 4)
 659                 i915_enable_pipestat(dev_priv, PIPE_A,
 660                                      PIPE_LEGACY_BLC_EVENT_STATUS);
 661
 662         spin_unlock_irq(&dev_priv->irq_lock);
 663 }
 664
 665 /*
 666  * This timing diagram depicts the video signal in and
 667  * around the vertical blanking period.
 668  *
 669  * Assumptions about the fictitious mode used in this example:
 670  *  vblank_start >= 3
 671  *  vsync_start = vblank_start + 1
 672  *  vsync_end = vblank_start + 2
 673  *  vtotal = vblank_start + 3
 674  *
 675  *           start of vblank:
 676  *           latch double buffered registers
 677  *           increment frame counter (ctg+)
 678  *           generate start of vblank interrupt (gen4+)
 679  *           |
 680  *           |          frame start:
 681  *           |          generate frame start interrupt (aka. vblank interrupt) (gmch)
 682  *           |          may be shifted forward 1-3 extra lines via PIPECONF
 683  *           |          |
 684  *           |          |  start of vsync:
 685  *           |          |  generate vsync interrupt
 686  *           |          |  |
 687  * ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx
 688  *       .   \hs/   .      \hs/          \hs/          \hs/   .      \hs/
 689  * ----va---> <-----------------vb--------------------> <--------va-------------
 690  *       |          |       <----vs----->                     |
 691  * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
 692  * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
 693  * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
 694  *       |          |                                         |
 695  *       last visible pixel                                   first visible pixel
 696  *                  |                                         increment frame counter (gen3/4)
 697  *                  pixel counter = vblank_start * htotal     pixel counter = 0 (gen3/4)
 698  *
 699  * x  = horizontal active
 700  * _  = horizontal blanking
 701  * hs = horizontal sync
 702  * va = vertical active
 703  * vb = vertical blanking
 704  * vs = vertical sync
 705  * vbs = vblank_start (number)
 706  *
 707  * Summary:
 708  * - most events happen at the start of horizontal sync
 709  * - frame start happens at the start of horizontal blank, 1-4 lines
 710  *   (depending on PIPECONF settings) after the start of vblank
 711  * - gen3/4 pixel and frame counter are synchronized with the start
 712  *   of horizontal active on the first line of vertical active
 713  */
 714
 715 /* Called from drm generic code, passed a 'crtc', which
 716  * we use as a pipe index
 717  */
 718 static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
 719 {
 720         struct drm_i915_private *dev_priv = to_i915(dev);
 721         i915_reg_t high_frame, low_frame;
 722         u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
 723         struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
 724                                                                 pipe);
 725         const struct drm_display_mode *mode = &intel_crtc->base.hwmode;
 726         unsigned long irqflags;
 727
 728         htotal = mode->crtc_htotal;
 729         hsync_start = mode->crtc_hsync_start;
 730         vbl_start = mode->crtc_vblank_start;
 731         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 732                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 733
 734         /* Convert to pixel count */
 735         vbl_start *= htotal;
 736
 737         /* Start of vblank event occurs at start of hsync */
 738         vbl_start -= htotal - hsync_start;
 739
 740         high_frame = PIPEFRAME(pipe);
 741         low_frame = PIPEFRAMEPIXEL(pipe);
 742
 743         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 744
 745         /*
 746          * High & low register fields aren't synchronized, so make sure
 747          * we get a low value that's stable across two reads of the high
 748          * register.
 749          */
 750         do {
 751                 high1 = I915_READ_FW(high_frame) & PIPE_FRAME_HIGH_MASK;
 752                 low   = I915_READ_FW(low_frame);
 753                 high2 = I915_READ_FW(high_frame) & PIPE_FRAME_HIGH_MASK;
 754         } while (high1 != high2);
 755
 756         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 757
 758         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 759         pixel = low & PIPE_PIXEL_MASK;
 760         low >>= PIPE_FRAME_LOW_SHIFT;
 761
 762         /*
 763          * The frame counter increments at beginning of active.
 764          * Cook up a vblank counter by also checking the pixel
 765          * counter against vblank start.
 766          */
 767         return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
 768 }
 769
 770 static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
 771 {
 772         struct drm_i915_private *dev_priv = to_i915(dev);
 773
 774         return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
 775 }
 776
 777 /* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
 778 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
 779 {
 780         struct drm_device *dev = crtc->base.dev;
 781         struct drm_i915_private *dev_priv = to_i915(dev);
 782         const struct drm_display_mode *mode = &crtc->base.hwmode;
 783         enum pipe pipe = crtc->pipe;
 784         int position, vtotal;
 785
 786         if (!crtc->active)
 787                 return -1;
 788
 789         vtotal = mode->crtc_vtotal;
 790         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 791                 vtotal /= 2;
 792
 793         if (IS_GEN2(dev_priv))
 794                 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
 795         else
 796                 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
 797
 798         /*
 799          * On HSW, the DSL reg (0x70000) appears to return 0 if we
 800          * read it just before the start of vblank.  So try it again
 801          * so we don't accidentally end up spanning a vblank frame
 802          * increment, causing the pipe_update_end() code to squak at us.
 803          *
 804          * The nature of this problem means we can't simply check the ISR
 805          * bit and return the vblank start value; nor can we use the scanline
 806          * debug register in the transcoder as it appears to have the same
 807          * problem.  We may need to extend this to include other platforms,
 808          * but so far testing only shows the problem on HSW.
 809          */
 810         if (HAS_DDI(dev_priv) && !position) {
 811                 int i, temp;
 812
 813                 for (i = 0; i < 100; i++) {
 814                         udelay(1);
 815                         temp = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
 816                         if (temp != position) {
 817                                 position = temp;
 818                                 break;
 819                         }
 820                 }
 821         }
 822
 823         /*
 824          * See update_scanline_offset() for the details on the
 825          * scanline_offset adjustment.
 826          */
 827         return (position + crtc->scanline_offset) % vtotal;
 828 }
 829
 830 static int i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
 831                                     unsigned int flags, int *vpos, int *hpos,
 832                                     ktime_t *stime, ktime_t *etime,
 833                                     const struct drm_display_mode *mode)
 834 {
 835         struct drm_i915_private *dev_priv = to_i915(dev);
 836         struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
 837                                                                 pipe);
 838         int position;
 839         int vbl_start, vbl_end, hsync_start, htotal, vtotal;
 840         bool in_vbl = true;
 841         int ret = 0;
 842         unsigned long irqflags;
 843
 844         if (WARN_ON(!mode->crtc_clock)) {
 845                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 846                                  "pipe %c\n", pipe_name(pipe));
 847                 return 0;
 848         }
 849
 850         htotal = mode->crtc_htotal;
 851         hsync_start = mode->crtc_hsync_start;
 852         vtotal = mode->crtc_vtotal;
 853         vbl_start = mode->crtc_vblank_start;
 854         vbl_end = mode->crtc_vblank_end;
 855
 856         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 857                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 858                 vbl_end /= 2;
 859                 vtotal /= 2;
 860         }
 861
 862         ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 863
 864         /*
 865          * Lock uncore.lock, as we will do multiple timing critical raw
 866          * register reads, potentially with preemption disabled, so the
 867          * following code must not block on uncore.lock.
 868          */
 869         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 870
 871         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 872
 873         /* Get optional system timestamp before query. */
 874         if (stime)
 875                 *stime = ktime_get();
 876
 877         if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
 878                 /* No obvious pixelcount register. Only query vertical
 879                  * scanout position from Display scan line register.
 880                  */
 881                 position = __intel_get_crtc_scanline(intel_crtc);
 882         } else {
 883                 /* Have access to pixelcount since start of frame.
 884                  * We can split this into vertical and horizontal
 885                  * scanout position.
 886                  */
 887                 position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 888
 889                 /* convert to pixel counts */
 890                 vbl_start *= htotal;
 891                 vbl_end *= htotal;
 892                 vtotal *= htotal;
 893
 894                 /*
 895                  * In interlaced modes, the pixel counter counts all pixels,
 896                  * so one field will have htotal more pixels. In order to avoid
 897                  * the reported position from jumping backwards when the pixel
 898                  * counter is beyond the length of the shorter field, just
 899                  * clamp the position the length of the shorter field. This
 900                  * matches how the scanline counter based position works since
 901                  * the scanline counter doesn't count the two half lines.
 902                  */
 903                 if (position >= vtotal)
 904                         position = vtotal - 1;
 905
 906                 /*
 907                  * Start of vblank interrupt is triggered at start of hsync,
 908                  * just prior to the first active line of vblank. However we
 909                  * consider lines to start at the leading edge of horizontal
 910                  * active. So, should we get here before we've crossed into
 911                  * the horizontal active of the first line in vblank, we would
 912                  * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
 913                  * always add htotal-hsync_start to the current pixel position.
 914                  */
 915                 position = (position + htotal - hsync_start) % vtotal;
 916         }
 917
 918         /* Get optional system timestamp after query. */
 919         if (etime)
 920                 *etime = ktime_get();
 921
 922         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 923
 924         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 925
 926         in_vbl = position >= vbl_start && position < vbl_end;
 927
 928         /*
 929          * While in vblank, position will be negative
 930          * counting up towards 0 at vbl_end. And outside
 931          * vblank, position will be positive counting
 932          * up since vbl_end.
 933          */
 934         if (position >= vbl_start)
 935                 position -= vbl_end;
 936         else
 937                 position += vtotal - vbl_end;
 938
 939         if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
 940                 *vpos = position;
 941                 *hpos = 0;
 942         } else {
 943                 *vpos = position / htotal;
 944                 *hpos = position - (*vpos * htotal);
 945         }
 946
 947         /* In vblank? */
 948         if (in_vbl)
 949                 ret |= DRM_SCANOUTPOS_IN_VBLANK;
 950
 951         return ret;
 952 }
 953
 954 int intel_get_crtc_scanline(struct intel_crtc *crtc)
 955 {
 956         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 957         unsigned long irqflags;
 958         int position;
 959
 960         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 961         position = __intel_get_crtc_scanline(crtc);
 962         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 963
 964         return position;
 965 }
 966
 967 static int i915_get_vblank_timestamp(struct drm_device *dev, unsigned int pipe,
 968                               int *max_error,
 969                               struct timeval *vblank_time,
 970                               unsigned flags)
 971 {
 972         struct drm_i915_private *dev_priv = to_i915(dev);
 973         struct intel_crtc *crtc;
 974
 975         if (pipe >= INTEL_INFO(dev_priv)->num_pipes) {
 976                 DRM_ERROR("Invalid crtc %u\n", pipe);
 977                 return -EINVAL;
 978         }
 979
 980         /* Get drm_crtc to timestamp: */
 981         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
 982         if (crtc == NULL) {
 983                 DRM_ERROR("Invalid crtc %u\n", pipe);
 984                 return -EINVAL;
 985         }
 986
 987         if (!crtc->base.hwmode.crtc_clock) {
 988                 DRM_DEBUG_KMS("crtc %u is disabled\n", pipe);
 989                 return -EBUSY;
 990         }
 991
 992         /* Helper routine in DRM core does all the work: */
 993         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 994                                                      vblank_time, flags,
 995                                                      &crtc->base.hwmode);
 996 }
 997
 998 static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv)
 999 {
1000         u32 busy_up, busy_down, max_avg, min_avg;
1001         u8 new_delay;
1002
1003         spin_lock(&mchdev_lock);
1004
1005         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
1006
1007         new_delay = dev_priv->ips.cur_delay;
1008
1009         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
1010         busy_up = I915_READ(RCPREVBSYTUPAVG);
1011         busy_down = I915_READ(RCPREVBSYTDNAVG);
1012         max_avg = I915_READ(RCBMAXAVG);
1013         min_avg = I915_READ(RCBMINAVG);
1014
1015         /* Handle RCS change request from hw */
1016         if (busy_up > max_avg) {
1017                 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
1018                         new_delay = dev_priv->ips.cur_delay - 1;
1019                 if (new_delay < dev_priv->ips.max_delay)
1020                         new_delay = dev_priv->ips.max_delay;
1021         } else if (busy_down < min_avg) {
1022                 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
1023                         new_delay = dev_priv->ips.cur_delay + 1;
1024                 if (new_delay > dev_priv->ips.min_delay)
1025                         new_delay = dev_priv->ips.min_delay;
1026         }
1027
1028         if (ironlake_set_drps(dev_priv, new_delay))
1029                 dev_priv->ips.cur_delay = new_delay;
1030
1031         spin_unlock(&mchdev_lock);
1032
1033         return;
1034 }
1035
1036 static void notify_ring(struct intel_engine_cs *engine)
1037 {
1038         struct drm_i915_gem_request *rq = NULL;
1039         struct intel_wait *wait;
1040
1041         atomic_inc(&engine->irq_count);
1042         set_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted);
1043
1044         spin_lock(&engine->breadcrumbs.irq_lock);
1045         wait = engine->breadcrumbs.irq_wait;
1046         if (wait) {
1047                 /* We use a callback from the dma-fence to submit
1048                  * requests after waiting on our own requests. To
1049                  * ensure minimum delay in queuing the next request to
1050                  * hardware, signal the fence now rather than wait for
1051                  * the signaler to be woken up. We still wake up the
1052                  * waiter in order to handle the irq-seqno coherency
1053                  * issues (we may receive the interrupt before the
1054                  * seqno is written, see __i915_request_irq_complete())
1055                  * and to handle coalescing of multiple seqno updates
1056                  * and many waiters.
1057                  */
1058                 if (i915_seqno_passed(intel_engine_get_seqno(engine),
1059                                       wait->seqno))
1060                         rq = i915_gem_request_get(wait->request);
1061
1062                 wake_up_process(wait->tsk);
1063         } else {
1064                 __intel_engine_disarm_breadcrumbs(engine);
1065         }
1066         spin_unlock(&engine->breadcrumbs.irq_lock);
1067
1068         if (rq) {
1069                 dma_fence_signal(&rq->fence);
1070                 i915_gem_request_put(rq);
1071         }
1072
1073         trace_intel_engine_notify(engine, wait);
1074 }
1075
1076 static void vlv_c0_read(struct drm_i915_private *dev_priv,
1077                         struct intel_rps_ei *ei)
1078 {
1079         ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
1080         ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
1081         ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
1082 }
1083
1084 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
1085 {
1086         memset(&dev_priv->rps.ei, 0, sizeof(dev_priv->rps.ei));
1087 }
1088
1089 static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
1090 {
1091         const struct intel_rps_ei *prev = &dev_priv->rps.ei;
1092         struct intel_rps_ei now;
1093         u32 events = 0;
1094
1095         if ((pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) == 0)
1096                 return 0;
1097
1098         vlv_c0_read(dev_priv, &now);
1099         if (now.cz_clock == 0)
1100                 return 0;
1101
1102         if (prev->cz_clock) {
1103                 u64 time, c0;
1104                 u32 render, media;
1105                 unsigned int mul;
1106
1107                 mul = VLV_CZ_CLOCK_TO_MILLI_SEC * 100; /* scale to threshold% */
1108                 if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
1109                         mul <<= 8;
1110
1111                 time = now.cz_clock - prev->cz_clock;
1112                 time *= dev_priv->czclk_freq;
1113
1114                 /* Workload can be split between render + media,
1115                  * e.g. SwapBuffers being blitted in X after being rendered in
1116                  * mesa. To account for this we need to combine both engines
1117                  * into our activity counter.
1118                  */
1119                 render = now.render_c0 - prev->render_c0;
1120                 media = now.media_c0 - prev->media_c0;
1121                 c0 = max(render, media);
1122                 c0 *= mul;
1123
1124                 if (c0 > time * dev_priv->rps.up_threshold)
1125                         events = GEN6_PM_RP_UP_THRESHOLD;
1126                 else if (c0 < time * dev_priv->rps.down_threshold)
1127                         events = GEN6_PM_RP_DOWN_THRESHOLD;
1128         }
1129
1130         dev_priv->rps.ei = now;
1131         return events;
1132 }
1133
1134 static bool any_waiters(struct drm_i915_private *dev_priv)
1135 {
1136         struct intel_engine_cs *engine;
1137         enum intel_engine_id id;
1138
1139         for_each_engine(engine, dev_priv, id)
1140                 if (intel_engine_has_waiter(engine))
1141                         return true;
1142
1143         return false;
1144 }
1145
1146 static void gen6_pm_rps_work(struct work_struct *work)
1147 {
1148         struct drm_i915_private *dev_priv =
1149                 container_of(work, struct drm_i915_private, rps.work);
1150         bool client_boost = false;
1151         int new_delay, adj, min, max;
1152         u32 pm_iir = 0;
1153
1154         spin_lock_irq(&dev_priv->irq_lock);
1155         if (dev_priv->rps.interrupts_enabled) {
1156                 pm_iir = fetch_and_zero(&dev_priv->rps.pm_iir);
1157                 client_boost = fetch_and_zero(&dev_priv->rps.client_boost);
1158         }
1159         spin_unlock_irq(&dev_priv->irq_lock);
1160
1161         /* Make sure we didn't queue anything we're not going to process. */
1162         WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1163         if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
1164                 goto out;
1165
1166         mutex_lock(&dev_priv->rps.hw_lock);
1167
1168         pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
1169
1170         adj = dev_priv->rps.last_adj;
1171         new_delay = dev_priv->rps.cur_freq;
1172         min = dev_priv->rps.min_freq_softlimit;
1173         max = dev_priv->rps.max_freq_softlimit;
1174         if (client_boost || any_waiters(dev_priv))
1175                 max = dev_priv->rps.max_freq;
1176         if (client_boost && new_delay < dev_priv->rps.boost_freq) {
1177                 new_delay = dev_priv->rps.boost_freq;
1178                 adj = 0;
1179         } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1180                 if (adj > 0)
1181                         adj *= 2;
1182                 else /* CHV needs even encode values */
1183                         adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
1184
1185                 if (new_delay >= dev_priv->rps.max_freq_softlimit)
1186                         adj = 0;
1187         } else if (client_boost || any_waiters(dev_priv)) {
1188                 adj = 0;
1189         } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1190                 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1191                         new_delay = dev_priv->rps.efficient_freq;
1192                 else if (dev_priv->rps.cur_freq > dev_priv->rps.min_freq_softlimit)
1193                         new_delay = dev_priv->rps.min_freq_softlimit;
1194                 adj = 0;
1195         } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1196                 if (adj < 0)
1197                         adj *= 2;
1198                 else /* CHV needs even encode values */
1199                         adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
1200
1201                 if (new_delay <= dev_priv->rps.min_freq_softlimit)
1202                         adj = 0;
1203         } else { /* unknown event */
1204                 adj = 0;
1205         }
1206
1207         dev_priv->rps.last_adj = adj;
1208
1209         /* sysfs frequency interfaces may have snuck in while servicing the
1210          * interrupt
1211          */
1212         new_delay += adj;
1213         new_delay = clamp_t(int, new_delay, min, max);
1214
1215         if (intel_set_rps(dev_priv, new_delay)) {
1216                 DRM_DEBUG_DRIVER("Failed to set new GPU frequency\n");
1217                 dev_priv->rps.last_adj = 0;
1218         }
1219
1220         mutex_unlock(&dev_priv->rps.hw_lock);
1221
1222 out:
1223         /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1224         spin_lock_irq(&dev_priv->irq_lock);
1225         if (dev_priv->rps.interrupts_enabled)
1226                 gen6_unmask_pm_irq(dev_priv, dev_priv->pm_rps_events);
1227         spin_unlock_irq(&dev_priv->irq_lock);
1228 }
1229
1230
1231 /**
1232  * ivybridge_parity_work - Workqueue called when a parity error interrupt
1233  * occurred.
1234  * @work: workqueue struct
1235  *
1236  * Doesn't actually do anything except notify userspace. As a consequence of
1237  * this event, userspace should try to remap the bad rows since statistically
1238  * it is likely the same row is more likely to go bad again.
1239  */
1240 static void ivybridge_parity_work(struct work_struct *work)
1241 {
1242         struct drm_i915_private *dev_priv =
1243                 container_of(work, struct drm_i915_private, l3_parity.error_work);
1244         u32 error_status, row, bank, subbank;
1245         char *parity_event[6];
1246         uint32_t misccpctl;
1247         uint8_t slice = 0;
1248
1249         /* We must turn off DOP level clock gating to access the L3 registers.
1250          * In order to prevent a get/put style interface, acquire struct mutex
1251          * any time we access those registers.
1252          */
1253         mutex_lock(&dev_priv->drm.struct_mutex);
1254
1255         /* If we've screwed up tracking, just let the interrupt fire again */
1256         if (WARN_ON(!dev_priv->l3_parity.which_slice))
1257                 goto out;
1258
1259         misccpctl = I915_READ(GEN7_MISCCPCTL);
1260         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1261         POSTING_READ(GEN7_MISCCPCTL);
1262
1263         while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1264                 i915_reg_t reg;
1265
1266                 slice--;
1267                 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv)))
1268                         break;
1269
1270                 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1271
1272                 reg = GEN7_L3CDERRST1(slice);
1273
1274                 error_status = I915_READ(reg);
1275                 row = GEN7_PARITY_ERROR_ROW(error_status);
1276                 bank = GEN7_PARITY_ERROR_BANK(error_status);
1277                 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1278
1279                 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1280                 POSTING_READ(reg);
1281
1282                 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1283                 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1284                 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1285                 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1286                 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1287                 parity_event[5] = NULL;
1288
1289                 kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj,
1290                                    KOBJ_CHANGE, parity_event);
1291
1292                 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1293                           slice, row, bank, subbank);
1294
1295                 kfree(parity_event[4]);
1296                 kfree(parity_event[3]);
1297                 kfree(parity_event[2]);
1298                 kfree(parity_event[1]);
1299         }
1300
1301         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1302
1303 out:
1304         WARN_ON(dev_priv->l3_parity.which_slice);
1305         spin_lock_irq(&dev_priv->irq_lock);
1306         gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1307         spin_unlock_irq(&dev_priv->irq_lock);
1308
1309         mutex_unlock(&dev_priv->drm.struct_mutex);
1310 }
1311
1312 static void ivybridge_parity_error_irq_handler(struct drm_i915_private *dev_priv,
1313                                                u32 iir)
1314 {
1315         if (!HAS_L3_DPF(dev_priv))
1316                 return;
1317
1318         spin_lock(&dev_priv->irq_lock);
1319         gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1320         spin_unlock(&dev_priv->irq_lock);
1321
1322         iir &= GT_PARITY_ERROR(dev_priv);
1323         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1324                 dev_priv->l3_parity.which_slice |= 1 << 1;
1325
1326         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1327                 dev_priv->l3_parity.which_slice |= 1 << 0;
1328
1329         queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1330 }
1331
1332 static void ilk_gt_irq_handler(struct drm_i915_private *dev_priv,
1333                                u32 gt_iir)
1334 {
1335         if (gt_iir & GT_RENDER_USER_INTERRUPT)
1336                 notify_ring(dev_priv->engine[RCS]);
1337         if (gt_iir & ILK_BSD_USER_INTERRUPT)
1338                 notify_ring(dev_priv->engine[VCS]);
1339 }
1340
1341 static void snb_gt_irq_handler(struct drm_i915_private *dev_priv,
1342                                u32 gt_iir)
1343 {
1344         if (gt_iir & GT_RENDER_USER_INTERRUPT)
1345                 notify_ring(dev_priv->engine[RCS]);
1346         if (gt_iir & GT_BSD_USER_INTERRUPT)
1347                 notify_ring(dev_priv->engine[VCS]);
1348         if (gt_iir & GT_BLT_USER_INTERRUPT)
1349                 notify_ring(dev_priv->engine[BCS]);
1350
1351         if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1352                       GT_BSD_CS_ERROR_INTERRUPT |
1353                       GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1354                 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1355
1356         if (gt_iir & GT_PARITY_ERROR(dev_priv))
1357                 ivybridge_parity_error_irq_handler(dev_priv, gt_iir);
1358 }
1359
1360 static __always_inline void
1361 gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift)
1362 {
1363         if (iir & (GT_RENDER_USER_INTERRUPT << test_shift))
1364                 notify_ring(engine);
1365
1366         if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift)) {
1367                 set_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
1368                 tasklet_hi_schedule(&engine->irq_tasklet);
1369         }
1370 }
1371
1372 static irqreturn_t gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
1373                                    u32 master_ctl,
1374                                    u32 gt_iir[4])
1375 {
1376         irqreturn_t ret = IRQ_NONE;
1377
1378         if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1379                 gt_iir[0] = I915_READ_FW(GEN8_GT_IIR(0));
1380                 if (gt_iir[0]) {
1381                         I915_WRITE_FW(GEN8_GT_IIR(0), gt_iir[0]);
1382                         ret = IRQ_HANDLED;
1383                 } else
1384                         DRM_ERROR("The master control interrupt lied (GT0)!\n");
1385         }
1386
1387         if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1388                 gt_iir[1] = I915_READ_FW(GEN8_GT_IIR(1));
1389                 if (gt_iir[1]) {
1390                         I915_WRITE_FW(GEN8_GT_IIR(1), gt_iir[1]);
1391                         ret = IRQ_HANDLED;
1392                 } else
1393                         DRM_ERROR("The master control interrupt lied (GT1)!\n");
1394         }
1395
1396         if (master_ctl & GEN8_GT_VECS_IRQ) {
1397                 gt_iir[3] = I915_READ_FW(GEN8_GT_IIR(3));
1398                 if (gt_iir[3]) {
1399                         I915_WRITE_FW(GEN8_GT_IIR(3), gt_iir[3]);
1400                         ret = IRQ_HANDLED;
1401                 } else
1402                         DRM_ERROR("The master control interrupt lied (GT3)!\n");
1403         }
1404
1405         if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
1406                 gt_iir[2] = I915_READ_FW(GEN8_GT_IIR(2));
1407                 if (gt_iir[2] & (dev_priv->pm_rps_events |
1408                                  dev_priv->pm_guc_events)) {
1409                         I915_WRITE_FW(GEN8_GT_IIR(2),
1410                                       gt_iir[2] & (dev_priv->pm_rps_events |
1411                                                    dev_priv->pm_guc_events));
1412                         ret = IRQ_HANDLED;
1413                 } else
1414                         DRM_ERROR("The master control interrupt lied (PM)!\n");
1415         }
1416
1417         return ret;
1418 }
1419
1420 static void gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
1421                                 u32 gt_iir[4])
1422 {
1423         if (gt_iir[0]) {
1424                 gen8_cs_irq_handler(dev_priv->engine[RCS],
1425                                     gt_iir[0], GEN8_RCS_IRQ_SHIFT);
1426                 gen8_cs_irq_handler(dev_priv->engine[BCS],
1427                                     gt_iir[0], GEN8_BCS_IRQ_SHIFT);
1428         }
1429
1430         if (gt_iir[1]) {
1431                 gen8_cs_irq_handler(dev_priv->engine[VCS],
1432                                     gt_iir[1], GEN8_VCS1_IRQ_SHIFT);
1433                 gen8_cs_irq_handler(dev_priv->engine[VCS2],
1434                                     gt_iir[1], GEN8_VCS2_IRQ_SHIFT);
1435         }
1436
1437         if (gt_iir[3])
1438                 gen8_cs_irq_handler(dev_priv->engine[VECS],
1439                                     gt_iir[3], GEN8_VECS_IRQ_SHIFT);
1440
1441         if (gt_iir[2] & dev_priv->pm_rps_events)
1442                 gen6_rps_irq_handler(dev_priv, gt_iir[2]);
1443
1444         if (gt_iir[2] & dev_priv->pm_guc_events)
1445                 gen9_guc_irq_handler(dev_priv, gt_iir[2]);
1446 }
1447
1448 static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
1449 {
1450         switch (port) {
1451         case PORT_A:
1452                 return val & PORTA_HOTPLUG_LONG_DETECT;
1453         case PORT_B:
1454                 return val & PORTB_HOTPLUG_LONG_DETECT;
1455         case PORT_C:
1456                 return val & PORTC_HOTPLUG_LONG_DETECT;
1457         default:
1458                 return false;
1459         }
1460 }
1461
1462 static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
1463 {
1464         switch (port) {
1465         case PORT_E:
1466                 return val & PORTE_HOTPLUG_LONG_DETECT;
1467         default:
1468                 return false;
1469         }
1470 }
1471
1472 static bool spt_port_hotplug_long_detect(enum port port, u32 val)
1473 {
1474         switch (port) {
1475         case PORT_A:
1476                 return val & PORTA_HOTPLUG_LONG_DETECT;
1477         case PORT_B:
1478                 return val & PORTB_HOTPLUG_LONG_DETECT;
1479         case PORT_C:
1480                 return val & PORTC_HOTPLUG_LONG_DETECT;
1481         case PORT_D:
1482                 return val & PORTD_HOTPLUG_LONG_DETECT;
1483         default:
1484                 return false;
1485         }
1486 }
1487
1488 static bool ilk_port_hotplug_long_detect(enum port port, u32 val)
1489 {
1490         switch (port) {
1491         case PORT_A:
1492                 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
1493         default:
1494                 return false;
1495         }
1496 }
1497
1498 static bool pch_port_hotplug_long_detect(enum port port, u32 val)
1499 {
1500         switch (port) {
1501         case PORT_B:
1502                 return val & PORTB_HOTPLUG_LONG_DETECT;
1503         case PORT_C:
1504                 return val & PORTC_HOTPLUG_LONG_DETECT;
1505         case PORT_D:
1506                 return val & PORTD_HOTPLUG_LONG_DETECT;
1507         default:
1508                 return false;
1509         }
1510 }
1511
1512 static bool i9xx_port_hotplug_long_detect(enum port port, u32 val)
1513 {
1514         switch (port) {
1515         case PORT_B:
1516                 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1517         case PORT_C:
1518                 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1519         case PORT_D:
1520                 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1521         default:
1522                 return false;
1523         }
1524 }
1525
1526 /*
1527  * Get a bit mask of pins that have triggered, and which ones may be long.
1528  * This can be called multiple times with the same masks to accumulate
1529  * hotplug detection results from several registers.
1530  *
1531  * Note that the caller is expected to zero out the masks initially.
1532  */
1533 static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
1534                              u32 hotplug_trigger, u32 dig_hotplug_reg,
1535                              const u32 hpd[HPD_NUM_PINS],
1536                              bool long_pulse_detect(enum port port, u32 val))
1537 {
1538         enum port port;
1539         int i;
1540
1541         for_each_hpd_pin(i) {
1542                 if ((hpd[i] & hotplug_trigger) == 0)
1543                         continue;
1544
1545                 *pin_mask |= BIT(i);
1546
1547                 if (!intel_hpd_pin_to_port(i, &port))
1548                         continue;
1549
1550                 if (long_pulse_detect(port, dig_hotplug_reg))
1551                         *long_mask |= BIT(i);
1552         }
1553
1554         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
1555                          hotplug_trigger, dig_hotplug_reg, *pin_mask);
1556
1557 }
1558
1559 static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
1560 {
1561         wake_up_all(&dev_priv->gmbus_wait_queue);
1562 }
1563
1564 static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
1565 {
1566         wake_up_all(&dev_priv->gmbus_wait_queue);
1567 }
1568
1569 #if defined(CONFIG_DEBUG_FS)
1570 static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1571                                          enum pipe pipe,
1572                                          uint32_t crc0, uint32_t crc1,
1573                                          uint32_t crc2, uint32_t crc3,
1574                                          uint32_t crc4)
1575 {
1576         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1577         struct intel_pipe_crc_entry *entry;
1578         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1579         struct drm_driver *driver = dev_priv->drm.driver;
1580         uint32_t crcs[5];
1581         int head, tail;
1582
1583         spin_lock(&pipe_crc->lock);
1584         if (pipe_crc->source) {
1585                 if (!pipe_crc->entries) {
1586                         spin_unlock(&pipe_crc->lock);
1587                         DRM_DEBUG_KMS("spurious interrupt\n");
1588                         return;
1589                 }
1590
1591                 head = pipe_crc->head;
1592                 tail = pipe_crc->tail;
1593
1594                 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1595                         spin_unlock(&pipe_crc->lock);
1596                         DRM_ERROR("CRC buffer overflowing\n");
1597                         return;
1598                 }
1599
1600                 entry = &pipe_crc->entries[head];
1601
1602                 entry->frame = driver->get_vblank_counter(&dev_priv->drm, pipe);
1603                 entry->crc[0] = crc0;
1604                 entry->crc[1] = crc1;
1605                 entry->crc[2] = crc2;
1606                 entry->crc[3] = crc3;
1607                 entry->crc[4] = crc4;
1608
1609                 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1610                 pipe_crc->head = head;
1611
1612                 spin_unlock(&pipe_crc->lock);
1613
1614                 wake_up_interruptible(&pipe_crc->wq);
1615         } else {
1616                 /*
1617                  * For some not yet identified reason, the first CRC is
1618                  * bonkers. So let's just wait for the next vblank and read
1619                  * out the buggy result.
1620                  *
1621                  * On CHV sometimes the second CRC is bonkers as well, so
1622                  * don't trust that one either.
1623                  */
1624                 if (pipe_crc->skipped == 0 ||
1625                     (IS_CHERRYVIEW(dev_priv) && pipe_crc->skipped == 1)) {
1626                         pipe_crc->skipped++;
1627                         spin_unlock(&pipe_crc->lock);
1628                         return;
1629                 }
1630                 spin_unlock(&pipe_crc->lock);
1631                 crcs[0] = crc0;
1632                 crcs[1] = crc1;
1633                 crcs[2] = crc2;
1634                 crcs[3] = crc3;
1635                 crcs[4] = crc4;
1636                 drm_crtc_add_crc_entry(&crtc->base, true,
1637                                        drm_accurate_vblank_count(&crtc->base),
1638                                        crcs);
1639         }
1640 }
1641 #else
1642 static inline void
1643 display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1644                              enum pipe pipe,
1645                              uint32_t crc0, uint32_t crc1,
1646                              uint32_t crc2, uint32_t crc3,
1647                              uint32_t crc4) {}
1648 #endif
1649
1650
1651 static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1652                                      enum pipe pipe)
1653 {
1654         display_pipe_crc_irq_handler(dev_priv, pipe,
1655                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1656                                      0, 0, 0, 0);
1657 }
1658
1659 static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1660                                      enum pipe pipe)
1661 {
1662         display_pipe_crc_irq_handler(dev_priv, pipe,
1663                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1664                                      I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1665                                      I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1666                                      I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1667                                      I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1668 }
1669
1670 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1671                                       enum pipe pipe)
1672 {
1673         uint32_t res1, res2;
1674
1675         if (INTEL_GEN(dev_priv) >= 3)
1676                 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1677         else
1678                 res1 = 0;
1679
1680         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1681                 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1682         else
1683                 res2 = 0;
1684
1685         display_pipe_crc_irq_handler(dev_priv, pipe,
1686                                      I915_READ(PIPE_CRC_RES_RED(pipe)),
1687                                      I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1688                                      I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1689                                      res1, res2);
1690 }
1691
1692 /* The RPS events need forcewake, so we add them to a work queue and mask their
1693  * IMR bits until the work is done. Other interrupts can be processed without
1694  * the work queue. */
1695 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1696 {
1697         if (pm_iir & dev_priv->pm_rps_events) {
1698                 spin_lock(&dev_priv->irq_lock);
1699                 gen6_mask_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1700                 if (dev_priv->rps.interrupts_enabled) {
1701                         dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1702                         schedule_work(&dev_priv->rps.work);
1703                 }
1704                 spin_unlock(&dev_priv->irq_lock);
1705         }
1706
1707         if (INTEL_INFO(dev_priv)->gen >= 8)
1708                 return;
1709
1710         if (HAS_VEBOX(dev_priv)) {
1711                 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1712                         notify_ring(dev_priv->engine[VECS]);
1713
1714                 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1715                         DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
1716         }
1717 }
1718
1719 static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir)
1720 {
1721         if (gt_iir & GEN9_GUC_TO_HOST_INT_EVENT) {
1722                 /* Sample the log buffer flush related bits & clear them out now
1723                  * itself from the message identity register to minimize the
1724                  * probability of losing a flush interrupt, when there are back
1725                  * to back flush interrupts.
1726                  * There can be a new flush interrupt, for different log buffer
1727                  * type (like for ISR), whilst Host is handling one (for DPC).
1728                  * Since same bit is used in message register for ISR & DPC, it
1729                  * could happen that GuC sets the bit for 2nd interrupt but Host
1730                  * clears out the bit on handling the 1st interrupt.
1731                  */
1732                 u32 msg, flush;
1733
1734                 msg = I915_READ(SOFT_SCRATCH(15));
1735                 flush = msg & (INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED |
1736                                INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER);
1737                 if (flush) {
1738                         /* Clear the message bits that are handled */
1739                         I915_WRITE(SOFT_SCRATCH(15), msg & ~flush);
1740
1741                         /* Handle flush interrupt in bottom half */
1742                         queue_work(dev_priv->guc.log.flush_wq,
1743                                    &dev_priv->guc.log.flush_work);
1744
1745                         dev_priv->guc.log.flush_interrupt_count++;
1746                 } else {
1747                         /* Not clearing of unhandled event bits won't result in
1748                          * re-triggering of the interrupt.
1749                          */
1750                 }
1751         }
1752 }
1753
1754 static bool intel_pipe_handle_vblank(struct drm_i915_private *dev_priv,
1755                                      enum pipe pipe)
1756 {
1757         bool ret;
1758
1759         ret = drm_handle_vblank(&dev_priv->drm, pipe);
1760         if (ret)
1761                 intel_finish_page_flip_mmio(dev_priv, pipe);
1762
1763         return ret;
1764 }
1765
1766 static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv,
1767                                         u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1768 {
1769         int pipe;
1770
1771         spin_lock(&dev_priv->irq_lock);
1772
1773         if (!dev_priv->display_irqs_enabled) {
1774                 spin_unlock(&dev_priv->irq_lock);
1775                 return;
1776         }
1777
1778         for_each_pipe(dev_priv, pipe) {
1779                 i915_reg_t reg;
1780                 u32 mask, iir_bit = 0;
1781
1782                 /*
1783                  * PIPESTAT bits get signalled even when the interrupt is
1784                  * disabled with the mask bits, and some of the status bits do
1785                  * not generate interrupts at all (like the underrun bit). Hence
1786                  * we need to be careful that we only handle what we want to
1787                  * handle.
1788                  */
1789
1790                 /* fifo underruns are filterered in the underrun handler. */
1791                 mask = PIPE_FIFO_UNDERRUN_STATUS;
1792
1793                 switch (pipe) {
1794                 case PIPE_A:
1795                         iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1796                         break;
1797                 case PIPE_B:
1798                         iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1799                         break;
1800                 case PIPE_C:
1801                         iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1802                         break;
1803                 }
1804                 if (iir & iir_bit)
1805                         mask |= dev_priv->pipestat_irq_mask[pipe];
1806
1807                 if (!mask)
1808                         continue;
1809
1810                 reg = PIPESTAT(pipe);
1811                 mask |= PIPESTAT_INT_ENABLE_MASK;
1812                 pipe_stats[pipe] = I915_READ(reg) & mask;
1813
1814                 /*
1815                  * Clear the PIPE*STAT regs before the IIR
1816                  */
1817                 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1818                                         PIPESTAT_INT_STATUS_MASK))
1819                         I915_WRITE(reg, pipe_stats[pipe]);
1820         }
1821         spin_unlock(&dev_priv->irq_lock);
1822 }
1823
1824 static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1825                                             u32 pipe_stats[I915_MAX_PIPES])
1826 {
1827         enum pipe pipe;
1828
1829         for_each_pipe(dev_priv, pipe) {
1830                 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
1831                     intel_pipe_handle_vblank(dev_priv, pipe))
1832                         intel_check_page_flip(dev_priv, pipe);
1833
1834                 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV)
1835                         intel_finish_page_flip_cs(dev_priv, pipe);
1836
1837                 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1838                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1839
1840                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1841                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1842         }
1843
1844         if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1845                 gmbus_irq_handler(dev_priv);
1846 }
1847
1848 static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
1849 {
1850         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1851
1852         if (hotplug_status)
1853                 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1854
1855         return hotplug_status;
1856 }
1857
1858 static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1859                                  u32 hotplug_status)
1860 {
1861         u32 pin_mask = 0, long_mask = 0;
1862
1863         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
1864             IS_CHERRYVIEW(dev_priv)) {
1865                 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1866
1867                 if (hotplug_trigger) {
1868                         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1869                                            hotplug_trigger, hpd_status_g4x,
1870                                            i9xx_port_hotplug_long_detect);
1871
1872                         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1873                 }
1874
1875                 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1876                         dp_aux_irq_handler(dev_priv);
1877         } else {
1878                 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1879
1880                 if (hotplug_trigger) {
1881                         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1882                                            hotplug_trigger, hpd_status_i915,
1883                                            i9xx_port_hotplug_long_detect);
1884                         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1885                 }
1886         }
1887 }
1888
1889 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1890 {
1891         struct drm_device *dev = arg;
1892         struct drm_i915_private *dev_priv = to_i915(dev);
1893         irqreturn_t ret = IRQ_NONE;
1894
1895         if (!intel_irqs_enabled(dev_priv))
1896                 return IRQ_NONE;
1897
1898         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1899         disable_rpm_wakeref_asserts(dev_priv);
1900
1901         do {
1902                 u32 iir, gt_iir, pm_iir;
1903                 u32 pipe_stats[I915_MAX_PIPES] = {};
1904                 u32 hotplug_status = 0;
1905                 u32 ier = 0;
1906
1907                 gt_iir = I915_READ(GTIIR);
1908                 pm_iir = I915_READ(GEN6_PMIIR);
1909                 iir = I915_READ(VLV_IIR);
1910
1911                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1912                         break;
1913
1914                 ret = IRQ_HANDLED;
1915
1916                 /*
1917                  * Theory on interrupt generation, based on empirical evidence:
1918                  *
1919                  * x = ((VLV_IIR & VLV_IER) ||
1920                  *      (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
1921                  *       (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
1922                  *
1923                  * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1924                  * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
1925                  * guarantee the CPU interrupt will be raised again even if we
1926                  * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
1927                  * bits this time around.
1928                  */
1929                 I915_WRITE(VLV_MASTER_IER, 0);
1930                 ier = I915_READ(VLV_IER);
1931                 I915_WRITE(VLV_IER, 0);
1932
1933                 if (gt_iir)
1934                         I915_WRITE(GTIIR, gt_iir);
1935                 if (pm_iir)
1936                         I915_WRITE(GEN6_PMIIR, pm_iir);
1937
1938                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1939                         hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1940
1941                 /* Call regardless, as some status bits might not be
1942                  * signalled in iir */
1943                 valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1944
1945                 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
1946                            I915_LPE_PIPE_B_INTERRUPT))
1947                         intel_lpe_audio_irq_handler(dev_priv);
1948
1949                 /*
1950                  * VLV_IIR is single buffered, and reflects the level
1951                  * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1952                  */
1953                 if (iir)
1954                         I915_WRITE(VLV_IIR, iir);
1955
1956                 I915_WRITE(VLV_IER, ier);
1957                 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1958                 POSTING_READ(VLV_MASTER_IER);
1959
1960                 if (gt_iir)
1961                         snb_gt_irq_handler(dev_priv, gt_iir);
1962                 if (pm_iir)
1963                         gen6_rps_irq_handler(dev_priv, pm_iir);
1964
1965                 if (hotplug_status)
1966                         i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1967
1968                 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1969         } while (0);
1970
1971         enable_rpm_wakeref_asserts(dev_priv);
1972
1973         return ret;
1974 }
1975
1976 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1977 {
1978         struct drm_device *dev = arg;
1979         struct drm_i915_private *dev_priv = to_i915(dev);
1980         irqreturn_t ret = IRQ_NONE;
1981
1982         if (!intel_irqs_enabled(dev_priv))
1983                 return IRQ_NONE;
1984
1985         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1986         disable_rpm_wakeref_asserts(dev_priv);
1987
1988         do {
1989                 u32 master_ctl, iir;
1990                 u32 gt_iir[4] = {};
1991                 u32 pipe_stats[I915_MAX_PIPES] = {};
1992                 u32 hotplug_status = 0;
1993                 u32 ier = 0;
1994
1995                 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1996                 iir = I915_READ(VLV_IIR);
1997
1998                 if (master_ctl == 0 && iir == 0)
1999                         break;
2000
2001                 ret = IRQ_HANDLED;
2002
2003                 /*
2004                  * Theory on interrupt generation, based on empirical evidence:
2005                  *
2006                  * x = ((VLV_IIR & VLV_IER) ||
2007                  *      ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
2008                  *       (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
2009                  *
2010                  * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
2011                  * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
2012                  * guarantee the CPU interrupt will be raised again even if we
2013                  * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
2014                  * bits this time around.
2015                  */
2016                 I915_WRITE(GEN8_MASTER_IRQ, 0);
2017                 ier = I915_READ(VLV_IER);
2018                 I915_WRITE(VLV_IER, 0);
2019
2020                 gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
2021
2022                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
2023                         hotplug_status = i9xx_hpd_irq_ack(dev_priv);
2024
2025                 /* Call regardless, as some status bits might not be
2026                  * signalled in iir */
2027                 valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
2028
2029                 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
2030                            I915_LPE_PIPE_B_INTERRUPT |
2031                            I915_LPE_PIPE_C_INTERRUPT))
2032                         intel_lpe_audio_irq_handler(dev_priv);
2033
2034                 /*
2035                  * VLV_IIR is single buffered, and reflects the level
2036                  * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
2037                  */
2038                 if (iir)
2039                         I915_WRITE(VLV_IIR, iir);
2040
2041                 I915_WRITE(VLV_IER, ier);
2042                 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2043                 POSTING_READ(GEN8_MASTER_IRQ);
2044
2045                 gen8_gt_irq_handler(dev_priv, gt_iir);
2046
2047                 if (hotplug_status)
2048                         i9xx_hpd_irq_handler(dev_priv, hotplug_status);
2049
2050                 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
2051         } while (0);
2052
2053         enable_rpm_wakeref_asserts(dev_priv);
2054
2055         return ret;
2056 }
2057
2058 static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
2059                                 u32 hotplug_trigger,
2060                                 const u32 hpd[HPD_NUM_PINS])
2061 {
2062         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2063
2064         /*
2065          * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
2066          * unless we touch the hotplug register, even if hotplug_trigger is
2067          * zero. Not acking leads to "The master control interrupt lied (SDE)!"
2068          * errors.
2069          */
2070         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2071         if (!hotplug_trigger) {
2072                 u32 mask = PORTA_HOTPLUG_STATUS_MASK |
2073                         PORTD_HOTPLUG_STATUS_MASK |
2074                         PORTC_HOTPLUG_STATUS_MASK |
2075                         PORTB_HOTPLUG_STATUS_MASK;
2076                 dig_hotplug_reg &= ~mask;
2077         }
2078
2079         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2080         if (!hotplug_trigger)
2081                 return;
2082
2083         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2084                            dig_hotplug_reg, hpd,
2085                            pch_port_hotplug_long_detect);
2086
2087         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2088 }
2089
2090 static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2091 {
2092         int pipe;
2093         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
2094
2095         ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ibx);
2096
2097         if (pch_iir & SDE_AUDIO_POWER_MASK) {
2098                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
2099                                SDE_AUDIO_POWER_SHIFT);
2100                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
2101                                  port_name(port));
2102         }
2103
2104         if (pch_iir & SDE_AUX_MASK)
2105                 dp_aux_irq_handler(dev_priv);
2106
2107         if (pch_iir & SDE_GMBUS)
2108                 gmbus_irq_handler(dev_priv);
2109
2110         if (pch_iir & SDE_AUDIO_HDCP_MASK)
2111                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
2112
2113         if (pch_iir & SDE_AUDIO_TRANS_MASK)
2114                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
2115
2116         if (pch_iir & SDE_POISON)
2117                 DRM_ERROR("PCH poison interrupt\n");
2118
2119         if (pch_iir & SDE_FDI_MASK)
2120                 for_each_pipe(dev_priv, pipe)
2121                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
2122                                          pipe_name(pipe),
2123                                          I915_READ(FDI_RX_IIR(pipe)));
2124
2125         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
2126                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
2127
2128         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
2129                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
2130
2131         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
2132                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
2133
2134         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
2135                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2136 }
2137
2138 static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
2139 {
2140         u32 err_int = I915_READ(GEN7_ERR_INT);
2141         enum pipe pipe;
2142
2143         if (err_int & ERR_INT_POISON)
2144                 DRM_ERROR("Poison interrupt\n");
2145
2146         for_each_pipe(dev_priv, pipe) {
2147                 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
2148                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2149
2150                 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
2151                         if (IS_IVYBRIDGE(dev_priv))
2152                                 ivb_pipe_crc_irq_handler(dev_priv, pipe);
2153                         else
2154                                 hsw_pipe_crc_irq_handler(dev_priv, pipe);
2155                 }
2156         }
2157
2158         I915_WRITE(GEN7_ERR_INT, err_int);
2159 }
2160
2161 static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
2162 {
2163         u32 serr_int = I915_READ(SERR_INT);
2164
2165         if (serr_int & SERR_INT_POISON)
2166                 DRM_ERROR("PCH poison interrupt\n");
2167
2168         if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
2169                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
2170
2171         if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
2172                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2173
2174         if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
2175                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
2176
2177         I915_WRITE(SERR_INT, serr_int);
2178 }
2179
2180 static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2181 {
2182         int pipe;
2183         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2184
2185         ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_cpt);
2186
2187         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2188                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2189                                SDE_AUDIO_POWER_SHIFT_CPT);
2190                 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2191                                  port_name(port));
2192         }
2193
2194         if (pch_iir & SDE_AUX_MASK_CPT)
2195                 dp_aux_irq_handler(dev_priv);
2196
2197         if (pch_iir & SDE_GMBUS_CPT)
2198                 gmbus_irq_handler(dev_priv);
2199
2200         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2201                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2202
2203         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2204                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2205
2206         if (pch_iir & SDE_FDI_MASK_CPT)
2207                 for_each_pipe(dev_priv, pipe)
2208                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
2209                                          pipe_name(pipe),
2210                                          I915_READ(FDI_RX_IIR(pipe)));
2211
2212         if (pch_iir & SDE_ERROR_CPT)
2213                 cpt_serr_int_handler(dev_priv);
2214 }
2215
2216 static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2217 {
2218         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
2219                 ~SDE_PORTE_HOTPLUG_SPT;
2220         u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
2221         u32 pin_mask = 0, long_mask = 0;
2222
2223         if (hotplug_trigger) {
2224                 u32 dig_hotplug_reg;
2225
2226                 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2227                 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2228
2229                 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2230                                    dig_hotplug_reg, hpd_spt,
2231                                    spt_port_hotplug_long_detect);
2232         }
2233
2234         if (hotplug2_trigger) {
2235                 u32 dig_hotplug_reg;
2236
2237                 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
2238                 I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
2239
2240                 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger,
2241                                    dig_hotplug_reg, hpd_spt,
2242                                    spt_port_hotplug2_long_detect);
2243         }
2244
2245         if (pin_mask)
2246                 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2247
2248         if (pch_iir & SDE_GMBUS_CPT)
2249                 gmbus_irq_handler(dev_priv);
2250 }
2251
2252 static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
2253                                 u32 hotplug_trigger,
2254                                 const u32 hpd[HPD_NUM_PINS])
2255 {
2256         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2257
2258         dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
2259         I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
2260
2261         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2262                            dig_hotplug_reg, hpd,
2263                            ilk_port_hotplug_long_detect);
2264
2265         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2266 }
2267
2268 static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
2269                                     u32 de_iir)
2270 {
2271         enum pipe pipe;
2272         u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
2273
2274         if (hotplug_trigger)
2275                 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk);
2276
2277         if (de_iir & DE_AUX_CHANNEL_A)
2278                 dp_aux_irq_handler(dev_priv);
2279
2280         if (de_iir & DE_GSE)
2281                 intel_opregion_asle_intr(dev_priv);
2282
2283         if (de_iir & DE_POISON)
2284                 DRM_ERROR("Poison interrupt\n");
2285
2286         for_each_pipe(dev_priv, pipe) {
2287                 if (de_iir & DE_PIPE_VBLANK(pipe) &&
2288                     intel_pipe_handle_vblank(dev_priv, pipe))
2289                         intel_check_page_flip(dev_priv, pipe);
2290
2291                 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2292                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2293
2294                 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2295                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2296
2297                 /* plane/pipes map 1:1 on ilk+ */
2298                 if (de_iir & DE_PLANE_FLIP_DONE(pipe))
2299                         intel_finish_page_flip_cs(dev_priv, pipe);
2300         }
2301
2302         /* check event from PCH */
2303         if (de_iir & DE_PCH_EVENT) {
2304                 u32 pch_iir = I915_READ(SDEIIR);
2305
2306                 if (HAS_PCH_CPT(dev_priv))
2307                         cpt_irq_handler(dev_priv, pch_iir);
2308                 else
2309                         ibx_irq_handler(dev_priv, pch_iir);
2310
2311                 /* should clear PCH hotplug event before clear CPU irq */
2312                 I915_WRITE(SDEIIR, pch_iir);
2313         }
2314
2315         if (IS_GEN5(dev_priv) && de_iir & DE_PCU_EVENT)
2316                 ironlake_rps_change_irq_handler(dev_priv);
2317 }
2318
2319 static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
2320                                     u32 de_iir)
2321 {
2322         enum pipe pipe;
2323         u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2324
2325         if (hotplug_trigger)
2326                 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb);
2327
2328         if (de_iir & DE_ERR_INT_IVB)
2329                 ivb_err_int_handler(dev_priv);
2330
2331         if (de_iir & DE_AUX_CHANNEL_A_IVB)
2332                 dp_aux_irq_handler(dev_priv);
2333
2334         if (de_iir & DE_GSE_IVB)
2335                 intel_opregion_asle_intr(dev_priv);
2336
2337         for_each_pipe(dev_priv, pipe) {
2338                 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
2339                     intel_pipe_handle_vblank(dev_priv, pipe))
2340                         intel_check_page_flip(dev_priv, pipe);
2341
2342                 /* plane/pipes map 1:1 on ilk+ */
2343                 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe))
2344                         intel_finish_page_flip_cs(dev_priv, pipe);
2345         }
2346
2347         /* check event from PCH */
2348         if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
2349                 u32 pch_iir = I915_READ(SDEIIR);
2350
2351                 cpt_irq_handler(dev_priv, pch_iir);
2352
2353                 /* clear PCH hotplug event before clear CPU irq */
2354                 I915_WRITE(SDEIIR, pch_iir);
2355         }
2356 }
2357
2358 /*
2359  * To handle irqs with the minimum potential races with fresh interrupts, we:
2360  * 1 - Disable Master Interrupt Control.
2361  * 2 - Find the source(s) of the interrupt.
2362  * 3 - Clear the Interrupt Identity bits (IIR).
2363  * 4 - Process the interrupt(s) that had bits set in the IIRs.
2364  * 5 - Re-enable Master Interrupt Control.
2365  */
2366 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2367 {
2368         struct drm_device *dev = arg;
2369         struct drm_i915_private *dev_priv = to_i915(dev);
2370         u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2371         irqreturn_t ret = IRQ_NONE;
2372
2373         if (!intel_irqs_enabled(dev_priv))
2374                 return IRQ_NONE;
2375
2376         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2377         disable_rpm_wakeref_asserts(dev_priv);
2378
2379         /* disable master interrupt before clearing iir  */
2380         de_ier = I915_READ(DEIER);
2381         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2382         POSTING_READ(DEIER);
2383
2384         /* Disable south interrupts. We'll only write to SDEIIR once, so further
2385          * interrupts will will be stored on its back queue, and then we'll be
2386          * able to process them after we restore SDEIER (as soon as we restore
2387          * it, we'll get an interrupt if SDEIIR still has something to process
2388          * due to its back queue). */
2389         if (!HAS_PCH_NOP(dev_priv)) {
2390                 sde_ier = I915_READ(SDEIER);
2391                 I915_WRITE(SDEIER, 0);
2392                 POSTING_READ(SDEIER);
2393         }
2394
2395         /* Find, clear, then process each source of interrupt */
2396
2397         gt_iir = I915_READ(GTIIR);
2398         if (gt_iir) {
2399                 I915_WRITE(GTIIR, gt_iir);
2400                 ret = IRQ_HANDLED;
2401                 if (INTEL_GEN(dev_priv) >= 6)
2402                         snb_gt_irq_handler(dev_priv, gt_iir);
2403                 else
2404                         ilk_gt_irq_handler(dev_priv, gt_iir);
2405         }
2406
2407         de_iir = I915_READ(DEIIR);
2408         if (de_iir) {
2409                 I915_WRITE(DEIIR, de_iir);
2410                 ret = IRQ_HANDLED;
2411                 if (INTEL_GEN(dev_priv) >= 7)
2412                         ivb_display_irq_handler(dev_priv, de_iir);
2413                 else
2414                         ilk_display_irq_handler(dev_priv, de_iir);
2415         }
2416
2417         if (INTEL_GEN(dev_priv) >= 6) {
2418                 u32 pm_iir = I915_READ(GEN6_PMIIR);
2419                 if (pm_iir) {
2420                         I915_WRITE(GEN6_PMIIR, pm_iir);
2421                         ret = IRQ_HANDLED;
2422                         gen6_rps_irq_handler(dev_priv, pm_iir);
2423                 }
2424         }
2425
2426         I915_WRITE(DEIER, de_ier);
2427         POSTING_READ(DEIER);
2428         if (!HAS_PCH_NOP(dev_priv)) {
2429                 I915_WRITE(SDEIER, sde_ier);
2430                 POSTING_READ(SDEIER);
2431         }
2432
2433         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2434         enable_rpm_wakeref_asserts(dev_priv);
2435
2436         return ret;
2437 }
2438
2439 static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
2440                                 u32 hotplug_trigger,
2441                                 const u32 hpd[HPD_NUM_PINS])
2442 {
2443         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2444
2445         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2446         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2447
2448         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2449                            dig_hotplug_reg, hpd,
2450                            bxt_port_hotplug_long_detect);
2451
2452         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2453 }
2454
2455 static irqreturn_t
2456 gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2457 {
2458         irqreturn_t ret = IRQ_NONE;
2459         u32 iir;
2460         enum pipe pipe;
2461
2462         if (master_ctl & GEN8_DE_MISC_IRQ) {
2463                 iir = I915_READ(GEN8_DE_MISC_IIR);
2464                 if (iir) {
2465                         I915_WRITE(GEN8_DE_MISC_IIR, iir);
2466                         ret = IRQ_HANDLED;
2467                         if (iir & GEN8_DE_MISC_GSE)
2468                                 intel_opregion_asle_intr(dev_priv);
2469                         else
2470                                 DRM_ERROR("Unexpected DE Misc interrupt\n");
2471                 }
2472                 else
2473                         DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2474         }
2475
2476         if (master_ctl & GEN8_DE_PORT_IRQ) {
2477                 iir = I915_READ(GEN8_DE_PORT_IIR);
2478                 if (iir) {
2479                         u32 tmp_mask;
2480                         bool found = false;
2481
2482                         I915_WRITE(GEN8_DE_PORT_IIR, iir);
2483                         ret = IRQ_HANDLED;
2484
2485                         tmp_mask = GEN8_AUX_CHANNEL_A;
2486                         if (INTEL_INFO(dev_priv)->gen >= 9)
2487                                 tmp_mask |= GEN9_AUX_CHANNEL_B |
2488                                             GEN9_AUX_CHANNEL_C |
2489                                             GEN9_AUX_CHANNEL_D;
2490
2491                         if (iir & tmp_mask) {
2492                                 dp_aux_irq_handler(dev_priv);
2493                                 found = true;
2494                         }
2495
2496                         if (IS_GEN9_LP(dev_priv)) {
2497                                 tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
2498                                 if (tmp_mask) {
2499                                         bxt_hpd_irq_handler(dev_priv, tmp_mask,
2500                                                             hpd_bxt);
2501                                         found = true;
2502                                 }
2503                         } else if (IS_BROADWELL(dev_priv)) {
2504                                 tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
2505                                 if (tmp_mask) {
2506                                         ilk_hpd_irq_handler(dev_priv,
2507                                                             tmp_mask, hpd_bdw);
2508                                         found = true;
2509                                 }
2510                         }
2511
2512                         if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
2513                                 gmbus_irq_handler(dev_priv);
2514                                 found = true;
2515                         }
2516
2517                         if (!found)
2518                                 DRM_ERROR("Unexpected DE Port interrupt\n");
2519                 }
2520                 else
2521                         DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2522         }
2523
2524         for_each_pipe(dev_priv, pipe) {
2525                 u32 flip_done, fault_errors;
2526
2527                 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2528                         continue;
2529
2530                 iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2531                 if (!iir) {
2532                         DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2533                         continue;
2534                 }
2535
2536                 ret = IRQ_HANDLED;
2537                 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
2538
2539                 if (iir & GEN8_PIPE_VBLANK &&
2540                     intel_pipe_handle_vblank(dev_priv, pipe))
2541                         intel_check_page_flip(dev_priv, pipe);
2542
2543                 flip_done = iir;
2544                 if (INTEL_INFO(dev_priv)->gen >= 9)
2545                         flip_done &= GEN9_PIPE_PLANE1_FLIP_DONE;
2546                 else
2547                         flip_done &= GEN8_PIPE_PRIMARY_FLIP_DONE;
2548
2549                 if (flip_done)
2550                         intel_finish_page_flip_cs(dev_priv, pipe);
2551
2552                 if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
2553                         hsw_pipe_crc_irq_handler(dev_priv, pipe);
2554
2555                 if (iir & GEN8_PIPE_FIFO_UNDERRUN)
2556                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2557
2558                 fault_errors = iir;
2559                 if (INTEL_INFO(dev_priv)->gen >= 9)
2560                         fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2561                 else
2562                         fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2563
2564                 if (fault_errors)
2565                         DRM_ERROR("Fault errors on pipe %c: 0x%08x\n",
2566                                   pipe_name(pipe),
2567                                   fault_errors);
2568         }
2569
2570         if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
2571             master_ctl & GEN8_DE_PCH_IRQ) {
2572                 /*
2573                  * FIXME(BDW): Assume for now that the new interrupt handling
2574                  * scheme also closed the SDE interrupt handling race we've seen
2575                  * on older pch-split platforms. But this needs testing.
2576                  */
2577                 iir = I915_READ(SDEIIR);
2578                 if (iir) {
2579                         I915_WRITE(SDEIIR, iir);
2580                         ret = IRQ_HANDLED;
2581
2582                         if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
2583                                 spt_irq_handler(dev_priv, iir);
2584                         else
2585                                 cpt_irq_handler(dev_priv, iir);
2586                 } else {
2587                         /*
2588                          * Like on previous PCH there seems to be something
2589                          * fishy going on with forwarding PCH interrupts.
2590                          */
2591                         DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
2592                 }
2593         }
2594
2595         return ret;
2596 }
2597
2598 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2599 {
2600         struct drm_device *dev = arg;
2601         struct drm_i915_private *dev_priv = to_i915(dev);
2602         u32 master_ctl;
2603         u32 gt_iir[4] = {};
2604         irqreturn_t ret;
2605
2606         if (!intel_irqs_enabled(dev_priv))
2607                 return IRQ_NONE;
2608
2609         master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
2610         master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2611         if (!master_ctl)
2612                 return IRQ_NONE;
2613
2614         I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
2615
2616         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2617         disable_rpm_wakeref_asserts(dev_priv);
2618
2619         /* Find, clear, then process each source of interrupt */
2620         ret = gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
2621         gen8_gt_irq_handler(dev_priv, gt_iir);
2622         ret |= gen8_de_irq_handler(dev_priv, master_ctl);
2623
2624         I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2625         POSTING_READ_FW(GEN8_MASTER_IRQ);
2626
2627         enable_rpm_wakeref_asserts(dev_priv);
2628
2629         return ret;
2630 }
2631
2632 static void i915_error_wake_up(struct drm_i915_private *dev_priv)
2633 {
2634         /*
2635          * Notify all waiters for GPU completion events that reset state has
2636          * been changed, and that they need to restart their wait after
2637          * checking for potential errors (and bail out to drop locks if there is
2638          * a gpu reset pending so that i915_error_work_func can acquire them).
2639          */
2640
2641         /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2642         wake_up_all(&dev_priv->gpu_error.wait_queue);
2643
2644         /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2645         wake_up_all(&dev_priv->pending_flip_queue);
2646 }
2647
2648 /**
2649  * i915_reset_and_wakeup - do process context error handling work
2650  * @dev_priv: i915 device private
2651  *
2652  * Fire an error uevent so userspace can see that a hang or error
2653  * was detected.
2654  */
2655 static void i915_reset_and_wakeup(struct drm_i915_private *dev_priv)
2656 {
2657         struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj;
2658         char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2659         char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2660         char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2661
2662         kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
2663
2664         DRM_DEBUG_DRIVER("resetting chip\n");
2665         kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
2666
2667         /*
2668          * In most cases it's guaranteed that we get here with an RPM
2669          * reference held, for example because there is a pending GPU
2670          * request that won't finish until the reset is done. This
2671          * isn't the case at least when we get here by doing a
2672          * simulated reset via debugs, so get an RPM reference.
2673          */
2674         intel_runtime_pm_get(dev_priv);
2675         intel_prepare_reset(dev_priv);
2676
2677         do {
2678                 /*
2679                  * All state reset _must_ be completed before we update the
2680                  * reset counter, for otherwise waiters might miss the reset
2681                  * pending state and not properly drop locks, resulting in
2682                  * deadlocks with the reset work.
2683                  */
2684                 if (mutex_trylock(&dev_priv->drm.struct_mutex)) {
2685                         i915_reset(dev_priv);
2686                         mutex_unlock(&dev_priv->drm.struct_mutex);
2687                 }
2688
2689                 /* We need to wait for anyone holding the lock to wakeup */
2690         } while (wait_on_bit_timeout(&dev_priv->gpu_error.flags,
2691                                      I915_RESET_IN_PROGRESS,
2692                                      TASK_UNINTERRUPTIBLE,
2693                                      HZ));
2694
2695         intel_finish_reset(dev_priv);
2696         intel_runtime_pm_put(dev_priv);
2697
2698         if (!test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
2699                 kobject_uevent_env(kobj,
2700                                    KOBJ_CHANGE, reset_done_event);
2701
2702         /*
2703          * Note: The wake_up also serves as a memory barrier so that
2704          * waiters see the updated value of the dev_priv->gpu_error.
2705          */
2706         wake_up_all(&dev_priv->gpu_error.reset_queue);
2707 }
2708
2709 static inline void
2710 i915_err_print_instdone(struct drm_i915_private *dev_priv,
2711                         struct intel_instdone *instdone)
2712 {
2713         int slice;
2714         int subslice;
2715
2716         pr_err("  INSTDONE: 0x%08x\n", instdone->instdone);
2717
2718         if (INTEL_GEN(dev_priv) <= 3)
2719                 return;
2720
2721         pr_err("  SC_INSTDONE: 0x%08x\n", instdone->slice_common);
2722
2723         if (INTEL_GEN(dev_priv) <= 6)
2724                 return;
2725
2726         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
2727                 pr_err("  SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
2728                        slice, subslice, instdone->sampler[slice][subslice]);
2729
2730         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
2731                 pr_err("  ROW_INSTDONE[%d][%d]: 0x%08x\n",
2732                        slice, subslice, instdone->row[slice][subslice]);
2733 }
2734
2735 static void i915_clear_error_registers(struct drm_i915_private *dev_priv)
2736 {
2737         u32 eir;
2738
2739         if (!IS_GEN2(dev_priv))
2740                 I915_WRITE(PGTBL_ER, I915_READ(PGTBL_ER));
2741
2742         if (INTEL_GEN(dev_priv) < 4)
2743                 I915_WRITE(IPEIR, I915_READ(IPEIR));
2744         else
2745                 I915_WRITE(IPEIR_I965, I915_READ(IPEIR_I965));
2746
2747         I915_WRITE(EIR, I915_READ(EIR));
2748         eir = I915_READ(EIR);
2749         if (eir) {
2750                 /*
2751                  * some errors might have become stuck,
2752                  * mask them.
2753                  */
2754                 DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir);
2755                 I915_WRITE(EMR, I915_READ(EMR) | eir);
2756                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2757         }
2758 }
2759
2760 /**
2761  * i915_handle_error - handle a gpu error
2762  * @dev_priv: i915 device private
2763  * @engine_mask: mask representing engines that are hung
2764  * @fmt: Error message format string
2765  *
2766  * Do some basic checking of register state at error time and
2767  * dump it to the syslog.  Also call i915_capture_error_state() to make
2768  * sure we get a record and make it available in debugfs.  Fire a uevent
2769  * so userspace knows something bad happened (should trigger collection
2770  * of a ring dump etc.).
2771  */
2772 void i915_handle_error(struct drm_i915_private *dev_priv,
2773                        u32 engine_mask,
2774                        const char *fmt, ...)
2775 {
2776         va_list args;
2777         char error_msg[80];
2778
2779         va_start(args, fmt);
2780         vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2781         va_end(args);
2782
2783         i915_capture_error_state(dev_priv, engine_mask, error_msg);
2784         i915_clear_error_registers(dev_priv);
2785
2786         if (!engine_mask)
2787                 return;
2788
2789         if (test_and_set_bit(I915_RESET_IN_PROGRESS,
2790                              &dev_priv->gpu_error.flags))
2791                 return;
2792
2793         /*
2794          * Wakeup waiting processes so that the reset function
2795          * i915_reset_and_wakeup doesn't deadlock trying to grab
2796          * various locks. By bumping the reset counter first, the woken
2797          * processes will see a reset in progress and back off,
2798          * releasing their locks and then wait for the reset completion.
2799          * We must do this for _all_ gpu waiters that might hold locks
2800          * that the reset work needs to acquire.
2801          *
2802          * Note: The wake_up also provides a memory barrier to ensure that the
2803          * waiters see the updated value of the reset flags.
2804          */
2805         i915_error_wake_up(dev_priv);
2806
2807         i915_reset_and_wakeup(dev_priv);
2808 }
2809
2810 /* Called from drm generic code, passed 'crtc' which
2811  * we use as a pipe index
2812  */
2813 static int i8xx_enable_vblank(struct drm_device *dev, unsigned int pipe)
2814 {
2815         struct drm_i915_private *dev_priv = to_i915(dev);
2816         unsigned long irqflags;
2817
2818         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2819         i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
2820         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2821
2822         return 0;
2823 }
2824
2825 static int i965_enable_vblank(struct drm_device *dev, unsigned int pipe)
2826 {
2827         struct drm_i915_private *dev_priv = to_i915(dev);
2828         unsigned long irqflags;
2829
2830         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2831         i915_enable_pipestat(dev_priv, pipe,
2832                              PIPE_START_VBLANK_INTERRUPT_STATUS);
2833         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2834
2835         return 0;
2836 }
2837
2838 static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)
2839 {
2840         struct drm_i915_private *dev_priv = to_i915(dev);
2841         unsigned long irqflags;
2842         uint32_t bit = INTEL_GEN(dev_priv) >= 7 ?
2843                 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
2844
2845         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2846         ilk_enable_display_irq(dev_priv, bit);
2847         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2848
2849         return 0;
2850 }
2851
2852 static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe)
2853 {
2854         struct drm_i915_private *dev_priv = to_i915(dev);
2855         unsigned long irqflags;
2856
2857         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2858         bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2859         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2860
2861         return 0;
2862 }
2863
2864 /* Called from drm generic code, passed 'crtc' which
2865  * we use as a pipe index
2866  */
2867 static void i8xx_disable_vblank(struct drm_device *dev, unsigned int pipe)
2868 {
2869         struct drm_i915_private *dev_priv = to_i915(dev);
2870         unsigned long irqflags;
2871
2872         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2873         i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
2874         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2875 }
2876
2877 static void i965_disable_vblank(struct drm_device *dev, unsigned int pipe)
2878 {
2879         struct drm_i915_private *dev_priv = to_i915(dev);
2880         unsigned long irqflags;
2881
2882         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2883         i915_disable_pipestat(dev_priv, pipe,
2884                               PIPE_START_VBLANK_INTERRUPT_STATUS);
2885         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2886 }
2887
2888 static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)
2889 {
2890         struct drm_i915_private *dev_priv = to_i915(dev);
2891         unsigned long irqflags;
2892         uint32_t bit = INTEL_GEN(dev_priv) >= 7 ?
2893                 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
2894
2895         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2896         ilk_disable_display_irq(dev_priv, bit);
2897         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2898 }
2899
2900 static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe)
2901 {
2902         struct drm_i915_private *dev_priv = to_i915(dev);
2903         unsigned long irqflags;
2904
2905         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2906         bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2907         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2908 }
2909
2910 static void ibx_irq_reset(struct drm_i915_private *dev_priv)
2911 {
2912         if (HAS_PCH_NOP(dev_priv))
2913                 return;
2914
2915         GEN5_IRQ_RESET(SDE);
2916
2917         if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
2918                 I915_WRITE(SERR_INT, 0xffffffff);
2919 }
2920
2921 /*
2922  * SDEIER is also touched by the interrupt handler to work around missed PCH
2923  * interrupts. Hence we can't update it after the interrupt handler is enabled -
2924  * instead we unconditionally enable all PCH interrupt sources here, but then
2925  * only unmask them as needed with SDEIMR.
2926  *
2927  * This function needs to be called before interrupts are enabled.
2928  */
2929 static void ibx_irq_pre_postinstall(struct drm_device *dev)
2930 {
2931         struct drm_i915_private *dev_priv = to_i915(dev);
2932
2933         if (HAS_PCH_NOP(dev_priv))
2934                 return;
2935
2936         WARN_ON(I915_READ(SDEIER) != 0);
2937         I915_WRITE(SDEIER, 0xffffffff);
2938         POSTING_READ(SDEIER);
2939 }
2940
2941 static void gen5_gt_irq_reset(struct drm_i915_private *dev_priv)
2942 {
2943         GEN5_IRQ_RESET(GT);
2944         if (INTEL_GEN(dev_priv) >= 6)
2945                 GEN5_IRQ_RESET(GEN6_PM);
2946 }
2947
2948 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
2949 {
2950         enum pipe pipe;
2951
2952         if (IS_CHERRYVIEW(dev_priv))
2953                 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
2954         else
2955                 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2956
2957         i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
2958         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2959
2960         for_each_pipe(dev_priv, pipe) {
2961                 I915_WRITE(PIPESTAT(pipe),
2962                            PIPE_FIFO_UNDERRUN_STATUS |
2963                            PIPESTAT_INT_STATUS_MASK);
2964                 dev_priv->pipestat_irq_mask[pipe] = 0;
2965         }
2966
2967         GEN5_IRQ_RESET(VLV_);
2968         dev_priv->irq_mask = ~0;
2969 }
2970
2971 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
2972 {
2973         u32 pipestat_mask;
2974         u32 enable_mask;
2975         enum pipe pipe;
2976         u32 val;
2977
2978         pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
2979                         PIPE_CRC_DONE_INTERRUPT_STATUS;
2980
2981         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
2982         for_each_pipe(dev_priv, pipe)
2983                 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
2984
2985         enable_mask = I915_DISPLAY_PORT_INTERRUPT |
2986                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2987                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
2988         if (IS_CHERRYVIEW(dev_priv))
2989                 enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
2990
2991         WARN_ON(dev_priv->irq_mask != ~0);
2992
2993         val = (I915_LPE_PIPE_A_INTERRUPT |
2994                 I915_LPE_PIPE_B_INTERRUPT |
2995                 I915_LPE_PIPE_C_INTERRUPT);
2996
2997         enable_mask |= val;
2998
2999         dev_priv->irq_mask = ~enable_mask;
3000
3001         GEN5_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask);
3002 }
3003
3004 /* drm_dma.h hooks
3005 */
3006 static void ironlake_irq_reset(struct drm_device *dev)
3007 {
3008         struct drm_i915_private *dev_priv = to_i915(dev);
3009
3010         I915_WRITE(HWSTAM, 0xffffffff);
3011
3012         GEN5_IRQ_RESET(DE);
3013         if (IS_GEN7(dev_priv))
3014                 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
3015
3016         gen5_gt_irq_reset(dev_priv);
3017
3018         ibx_irq_reset(dev_priv);
3019 }
3020
3021 static void valleyview_irq_preinstall(struct drm_device *dev)
3022 {
3023         struct drm_i915_private *dev_priv = to_i915(dev);
3024
3025         I915_WRITE(VLV_MASTER_IER, 0);
3026         POSTING_READ(VLV_MASTER_IER);
3027
3028         gen5_gt_irq_reset(dev_priv);
3029
3030         spin_lock_irq(&dev_priv->irq_lock);
3031         if (dev_priv->display_irqs_enabled)
3032                 vlv_display_irq_reset(dev_priv);
3033         spin_unlock_irq(&dev_priv->irq_lock);
3034 }
3035
3036 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3037 {
3038         GEN8_IRQ_RESET_NDX(GT, 0);
3039         GEN8_IRQ_RESET_NDX(GT, 1);
3040         GEN8_IRQ_RESET_NDX(GT, 2);
3041         GEN8_IRQ_RESET_NDX(GT, 3);
3042 }
3043
3044 static void gen8_irq_reset(struct drm_device *dev)
3045 {
3046         struct drm_i915_private *dev_priv = to_i915(dev);
3047         int pipe;
3048
3049         I915_WRITE(GEN8_MASTER_IRQ, 0);
3050         POSTING_READ(GEN8_MASTER_IRQ);
3051
3052         gen8_gt_irq_reset(dev_priv);
3053
3054         for_each_pipe(dev_priv, pipe)
3055                 if (intel_display_power_is_enabled(dev_priv,
3056                                                    POWER_DOMAIN_PIPE(pipe)))
3057                         GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3058
3059         GEN5_IRQ_RESET(GEN8_DE_PORT_);
3060         GEN5_IRQ_RESET(GEN8_DE_MISC_);
3061         GEN5_IRQ_RESET(GEN8_PCU_);
3062
3063         if (HAS_PCH_SPLIT(dev_priv))
3064                 ibx_irq_reset(dev_priv);
3065 }
3066
3067 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
3068                                      unsigned int pipe_mask)
3069 {
3070         uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3071         enum pipe pipe;
3072
3073         spin_lock_irq(&dev_priv->irq_lock);
3074         for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3075                 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3076                                   dev_priv->de_irq_mask[pipe],
3077                                   ~dev_priv->de_irq_mask[pipe] | extra_ier);
3078         spin_unlock_irq(&dev_priv->irq_lock);
3079 }
3080
3081 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
3082                                      unsigned int pipe_mask)
3083 {
3084         enum pipe pipe;
3085
3086         spin_lock_irq(&dev_priv->irq_lock);
3087         for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3088                 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3089         spin_unlock_irq(&dev_priv->irq_lock);
3090
3091         /* make sure we're done processing display irqs */
3092         synchronize_irq(dev_priv->drm.irq);
3093 }
3094
3095 static void cherryview_irq_preinstall(struct drm_device *dev)
3096 {
3097         struct drm_i915_private *dev_priv = to_i915(dev);
3098
3099         I915_WRITE(GEN8_MASTER_IRQ, 0);
3100         POSTING_READ(GEN8_MASTER_IRQ);
3101
3102         gen8_gt_irq_reset(dev_priv);
3103
3104         GEN5_IRQ_RESET(GEN8_PCU_);
3105
3106         spin_lock_irq(&dev_priv->irq_lock);
3107         if (dev_priv->display_irqs_enabled)
3108                 vlv_display_irq_reset(dev_priv);
3109         spin_unlock_irq(&dev_priv->irq_lock);
3110 }
3111
3112 static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
3113                                   const u32 hpd[HPD_NUM_PINS])
3114 {
3115         struct intel_encoder *encoder;
3116         u32 enabled_irqs = 0;
3117
3118         for_each_intel_encoder(&dev_priv->drm, encoder)
3119                 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
3120                         enabled_irqs |= hpd[encoder->hpd_pin];
3121
3122         return enabled_irqs;
3123 }
3124
3125 static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
3126 {
3127         u32 hotplug;
3128
3129         /*
3130          * Enable digital hotplug on the PCH, and configure the DP short pulse
3131          * duration to 2ms (which is the minimum in the Display Port spec).
3132          * The pulse duration bits are reserved on LPT+.
3133          */
3134         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3135         hotplug &= ~(PORTB_PULSE_DURATION_MASK |
3136                      PORTC_PULSE_DURATION_MASK |
3137                      PORTD_PULSE_DURATION_MASK);
3138         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3139         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3140         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3141         /*
3142          * When CPU and PCH are on the same package, port A
3143          * HPD must be enabled in both north and south.
3144          */
3145         if (HAS_PCH_LPT_LP(dev_priv))
3146                 hotplug |= PORTA_HOTPLUG_ENABLE;
3147         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3148 }
3149
3150 static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
3151 {
3152         u32 hotplug_irqs, enabled_irqs;
3153
3154         if (HAS_PCH_IBX(dev_priv)) {
3155                 hotplug_irqs = SDE_HOTPLUG_MASK;
3156                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ibx);
3157         } else {
3158                 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3159                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_cpt);
3160         }
3161
3162         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3163
3164         ibx_hpd_detection_setup(dev_priv);
3165 }
3166
3167 static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3168 {
3169         u32 hotplug;
3170
3171         /* Enable digital hotplug on the PCH */
3172         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3173         hotplug |= PORTA_HOTPLUG_ENABLE |
3174                    PORTB_HOTPLUG_ENABLE |
3175                    PORTC_HOTPLUG_ENABLE |
3176                    PORTD_HOTPLUG_ENABLE;
3177         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3178
3179         hotplug = I915_READ(PCH_PORT_HOTPLUG2);
3180         hotplug |= PORTE_HOTPLUG_ENABLE;
3181         I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
3182 }
3183
3184 static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3185 {
3186         u32 hotplug_irqs, enabled_irqs;
3187
3188         hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
3189         enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt);
3190
3191         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3192
3193         spt_hpd_detection_setup(dev_priv);
3194 }
3195
3196 static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv)
3197 {
3198         u32 hotplug;
3199
3200         /*
3201          * Enable digital hotplug on the CPU, and configure the DP short pulse
3202          * duration to 2ms (which is the minimum in the Display Port spec)
3203          * The pulse duration bits are reserved on HSW+.
3204          */
3205         hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
3206         hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
3207         hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE |
3208                    DIGITAL_PORTA_PULSE_DURATION_2ms;
3209         I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
3210 }
3211
3212 static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
3213 {
3214         u32 hotplug_irqs, enabled_irqs;
3215
3216         if (INTEL_GEN(dev_priv) >= 8) {
3217                 hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
3218                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw);
3219
3220                 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3221         } else if (INTEL_GEN(dev_priv) >= 7) {
3222                 hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
3223                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ivb);
3224
3225                 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3226         } else {
3227                 hotplug_irqs = DE_DP_A_HOTPLUG;
3228                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ilk);
3229
3230                 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3231         }
3232
3233         ilk_hpd_detection_setup(dev_priv);
3234
3235         ibx_hpd_irq_setup(dev_priv);
3236 }
3237
3238 static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
3239                                       u32 enabled_irqs)
3240 {
3241         u32 hotplug;
3242
3243         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3244         hotplug |= PORTA_HOTPLUG_ENABLE |
3245                    PORTB_HOTPLUG_ENABLE |
3246                    PORTC_HOTPLUG_ENABLE;
3247
3248         DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x\n",
3249                       hotplug, enabled_irqs);
3250         hotplug &= ~BXT_DDI_HPD_INVERT_MASK;
3251
3252         /*
3253          * For BXT invert bit has to be set based on AOB design
3254          * for HPD detection logic, update it based on VBT fields.
3255          */
3256         if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) &&
3257             intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
3258                 hotplug |= BXT_DDIA_HPD_INVERT;
3259         if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) &&
3260             intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
3261                 hotplug |= BXT_DDIB_HPD_INVERT;
3262         if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) &&
3263             intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
3264                 hotplug |= BXT_DDIC_HPD_INVERT;
3265
3266         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3267 }
3268
3269 static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3270 {
3271         __bxt_hpd_detection_setup(dev_priv, BXT_DE_PORT_HOTPLUG_MASK);
3272 }
3273
3274 static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3275 {
3276         u32 hotplug_irqs, enabled_irqs;
3277
3278         enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bxt);
3279         hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK;
3280
3281         bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3282
3283         __bxt_hpd_detection_setup(dev_priv, enabled_irqs);
3284 }
3285
3286 static void ibx_irq_postinstall(struct drm_device *dev)
3287 {
3288         struct drm_i915_private *dev_priv = to_i915(dev);
3289         u32 mask;
3290
3291         if (HAS_PCH_NOP(dev_priv))
3292                 return;
3293
3294         if (HAS_PCH_IBX(dev_priv))
3295                 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3296         else
3297                 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3298
3299         gen5_assert_iir_is_zero(dev_priv, SDEIIR);
3300         I915_WRITE(SDEIMR, ~mask);
3301
3302         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
3303             HAS_PCH_LPT(dev_priv))
3304                 ibx_hpd_detection_setup(dev_priv);
3305         else
3306                 spt_hpd_detection_setup(dev_priv);
3307 }
3308
3309 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3310 {
3311         struct drm_i915_private *dev_priv = to_i915(dev);
3312         u32 pm_irqs, gt_irqs;
3313
3314         pm_irqs = gt_irqs = 0;
3315
3316         dev_priv->gt_irq_mask = ~0;
3317         if (HAS_L3_DPF(dev_priv)) {
3318                 /* L3 parity interrupt is always unmasked. */
3319                 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev_priv);
3320                 gt_irqs |= GT_PARITY_ERROR(dev_priv);
3321         }
3322
3323         gt_irqs |= GT_RENDER_USER_INTERRUPT;
3324         if (IS_GEN5(dev_priv)) {
3325                 gt_irqs |= ILK_BSD_USER_INTERRUPT;
3326         } else {
3327                 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3328         }
3329
3330         GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3331
3332         if (INTEL_GEN(dev_priv) >= 6) {
3333                 /*
3334                  * RPS interrupts will get enabled/disabled on demand when RPS
3335                  * itself is enabled/disabled.
3336                  */
3337                 if (HAS_VEBOX(dev_priv)) {
3338                         pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3339                         dev_priv->pm_ier |= PM_VEBOX_USER_INTERRUPT;
3340                 }
3341
3342                 dev_priv->pm_imr = 0xffffffff;
3343                 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_imr, pm_irqs);
3344         }
3345 }
3346
3347 static int ironlake_irq_postinstall(struct drm_device *dev)
3348 {
3349         struct drm_i915_private *dev_priv = to_i915(dev);
3350         u32 display_mask, extra_mask;
3351
3352         if (INTEL_GEN(dev_priv) >= 7) {
3353                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3354                                 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3355                                 DE_PLANEB_FLIP_DONE_IVB |
3356                                 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3357                 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3358                               DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
3359                               DE_DP_A_HOTPLUG_IVB);
3360         } else {
3361                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3362                                 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3363                                 DE_AUX_CHANNEL_A |
3364                                 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3365                                 DE_POISON);
3366                 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3367                               DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
3368                               DE_DP_A_HOTPLUG);
3369         }
3370
3371         dev_priv->irq_mask = ~display_mask;
3372
3373         I915_WRITE(HWSTAM, 0xeffe);
3374
3375         ibx_irq_pre_postinstall(dev);
3376
3377         GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3378
3379         gen5_gt_irq_postinstall(dev);
3380
3381         ilk_hpd_detection_setup(dev_priv);
3382
3383         ibx_irq_postinstall(dev);
3384
3385         if (IS_IRONLAKE_M(dev_priv)) {
3386                 /* Enable PCU event interrupts
3387                  *
3388                  * spinlocking not required here for correctness since interrupt
3389                  * setup is guaranteed to run in single-threaded context. But we
3390                  * need it to make the assert_spin_locked happy. */
3391                 spin_lock_irq(&dev_priv->irq_lock);
3392                 ilk_enable_display_irq(dev_priv, DE_PCU_EVENT);
3393                 spin_unlock_irq(&dev_priv->irq_lock);
3394         }
3395
3396         return 0;
3397 }
3398
3399 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3400 {
3401         lockdep_assert_held(&dev_priv->irq_lock);
3402
3403         if (dev_priv->display_irqs_enabled)
3404                 return;
3405
3406         dev_priv->display_irqs_enabled = true;
3407
3408         if (intel_irqs_enabled(dev_priv)) {
3409                 vlv_display_irq_reset(dev_priv);
3410                 vlv_display_irq_postinstall(dev_priv);
3411         }
3412 }
3413
3414 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3415 {
3416         lockdep_assert_held(&dev_priv->irq_lock);
3417
3418         if (!dev_priv->display_irqs_enabled)
3419                 return;
3420
3421         dev_priv->display_irqs_enabled = false;
3422
3423         if (intel_irqs_enabled(dev_priv))
3424                 vlv_display_irq_reset(dev_priv);
3425 }
3426
3427
3428 static int valleyview_irq_postinstall(struct drm_device *dev)
3429 {
3430         struct drm_i915_private *dev_priv = to_i915(dev);
3431
3432         gen5_gt_irq_postinstall(dev);
3433
3434         spin_lock_irq(&dev_priv->irq_lock);
3435         if (dev_priv->display_irqs_enabled)
3436                 vlv_display_irq_postinstall(dev_priv);
3437         spin_unlock_irq(&dev_priv->irq_lock);
3438
3439         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3440         POSTING_READ(VLV_MASTER_IER);
3441
3442         return 0;
3443 }
3444
3445 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3446 {
3447         /* These are interrupts we'll toggle with the ring mask register */
3448         uint32_t gt_interrupts[] = {
3449                 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3450                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3451                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3452                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3453                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3454                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3455                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3456                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3457                 0,
3458                 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3459                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3460                 };
3461
3462         if (HAS_L3_DPF(dev_priv))
3463                 gt_interrupts[0] |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
3464
3465         dev_priv->pm_ier = 0x0;
3466         dev_priv->pm_imr = ~dev_priv->pm_ier;
3467         GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3468         GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
3469         /*
3470          * RPS interrupts will get enabled/disabled on demand when RPS itself
3471          * is enabled/disabled. Same wil be the case for GuC interrupts.
3472          */
3473         GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_imr, dev_priv->pm_ier);
3474         GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
3475 }
3476
3477 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3478 {
3479         uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3480         uint32_t de_pipe_enables;
3481         u32 de_port_masked = GEN8_AUX_CHANNEL_A;
3482         u32 de_port_enables;
3483         u32 de_misc_masked = GEN8_DE_MISC_GSE;
3484         enum pipe pipe;
3485
3486         if (INTEL_INFO(dev_priv)->gen >= 9) {
3487                 de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
3488                                   GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3489                 de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
3490                                   GEN9_AUX_CHANNEL_D;
3491                 if (IS_GEN9_LP(dev_priv))
3492                         de_port_masked |= BXT_DE_PORT_GMBUS;
3493         } else {
3494                 de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
3495                                   GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3496         }
3497
3498         de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3499                                            GEN8_PIPE_FIFO_UNDERRUN;
3500
3501         de_port_enables = de_port_masked;
3502         if (IS_GEN9_LP(dev_priv))
3503                 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
3504         else if (IS_BROADWELL(dev_priv))
3505                 de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
3506
3507         dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3508         dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3509         dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3510
3511         for_each_pipe(dev_priv, pipe)
3512                 if (intel_display_power_is_enabled(dev_priv,
3513                                 POWER_DOMAIN_PIPE(pipe)))
3514                         GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3515                                           dev_priv->de_irq_mask[pipe],
3516                                           de_pipe_enables);
3517
3518         GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
3519         GEN5_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
3520
3521         if (IS_GEN9_LP(dev_priv))
3522                 bxt_hpd_detection_setup(dev_priv);
3523         else if (IS_BROADWELL(dev_priv))
3524                 ilk_hpd_detection_setup(dev_priv);
3525 }
3526
3527 static int gen8_irq_postinstall(struct drm_device *dev)
3528 {
3529         struct drm_i915_private *dev_priv = to_i915(dev);
3530
3531         if (HAS_PCH_SPLIT(dev_priv))
3532                 ibx_irq_pre_postinstall(dev);
3533
3534         gen8_gt_irq_postinstall(dev_priv);
3535         gen8_de_irq_postinstall(dev_priv);
3536
3537         if (HAS_PCH_SPLIT(dev_priv))
3538                 ibx_irq_postinstall(dev);
3539
3540         I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3541         POSTING_READ(GEN8_MASTER_IRQ);
3542
3543         return 0;
3544 }
3545
3546 static int cherryview_irq_postinstall(struct drm_device *dev)
3547 {
3548         struct drm_i915_private *dev_priv = to_i915(dev);
3549
3550         gen8_gt_irq_postinstall(dev_priv);
3551
3552         spin_lock_irq(&dev_priv->irq_lock);
3553         if (dev_priv->display_irqs_enabled)
3554                 vlv_display_irq_postinstall(dev_priv);
3555         spin_unlock_irq(&dev_priv->irq_lock);
3556
3557         I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3558         POSTING_READ(GEN8_MASTER_IRQ);
3559
3560         return 0;
3561 }
3562
3563 static void gen8_irq_uninstall(struct drm_device *dev)
3564 {
3565         struct drm_i915_private *dev_priv = to_i915(dev);
3566
3567         if (!dev_priv)
3568                 return;
3569
3570         gen8_irq_reset(dev);
3571 }
3572
3573 static void valleyview_irq_uninstall(struct drm_device *dev)
3574 {
3575         struct drm_i915_private *dev_priv = to_i915(dev);
3576
3577         if (!dev_priv)
3578                 return;
3579
3580         I915_WRITE(VLV_MASTER_IER, 0);
3581         POSTING_READ(VLV_MASTER_IER);
3582
3583         gen5_gt_irq_reset(dev_priv);
3584
3585         I915_WRITE(HWSTAM, 0xffffffff);
3586
3587         spin_lock_irq(&dev_priv->irq_lock);
3588         if (dev_priv->display_irqs_enabled)
3589                 vlv_display_irq_reset(dev_priv);
3590         spin_unlock_irq(&dev_priv->irq_lock);
3591 }
3592
3593 static void cherryview_irq_uninstall(struct drm_device *dev)
3594 {
3595         struct drm_i915_private *dev_priv = to_i915(dev);
3596
3597         if (!dev_priv)
3598                 return;
3599
3600         I915_WRITE(GEN8_MASTER_IRQ, 0);
3601         POSTING_READ(GEN8_MASTER_IRQ);
3602
3603         gen8_gt_irq_reset(dev_priv);
3604
3605         GEN5_IRQ_RESET(GEN8_PCU_);
3606
3607         spin_lock_irq(&dev_priv->irq_lock);
3608         if (dev_priv->display_irqs_enabled)
3609                 vlv_display_irq_reset(dev_priv);
3610         spin_unlock_irq(&dev_priv->irq_lock);
3611 }
3612
3613 static void ironlake_irq_uninstall(struct drm_device *dev)
3614 {
3615         struct drm_i915_private *dev_priv = to_i915(dev);
3616
3617         if (!dev_priv)
3618                 return;
3619
3620         ironlake_irq_reset(dev);
3621 }
3622
3623 static void i8xx_irq_preinstall(struct drm_device * dev)
3624 {
3625         struct drm_i915_private *dev_priv = to_i915(dev);
3626         int pipe;
3627
3628         for_each_pipe(dev_priv, pipe)
3629                 I915_WRITE(PIPESTAT(pipe), 0);
3630         I915_WRITE16(IMR, 0xffff);
3631         I915_WRITE16(IER, 0x0);
3632         POSTING_READ16(IER);
3633 }
3634
3635 static int i8xx_irq_postinstall(struct drm_device *dev)
3636 {
3637         struct drm_i915_private *dev_priv = to_i915(dev);
3638
3639         I915_WRITE16(EMR,
3640                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3641
3642         /* Unmask the interrupts that we always want on. */
3643         dev_priv->irq_mask =
3644                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3645                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3646                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3647                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3648         I915_WRITE16(IMR, dev_priv->irq_mask);
3649
3650         I915_WRITE16(IER,
3651                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3652                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3653                      I915_USER_INTERRUPT);
3654         POSTING_READ16(IER);
3655
3656         /* Interrupt setup is already guaranteed to be single-threaded, this is
3657          * just to make the assert_spin_locked check happy. */
3658         spin_lock_irq(&dev_priv->irq_lock);
3659         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3660         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3661         spin_unlock_irq(&dev_priv->irq_lock);
3662
3663         return 0;
3664 }
3665
3666 /*
3667  * Returns true when a page flip has completed.
3668  */
3669 static bool i8xx_handle_vblank(struct drm_i915_private *dev_priv,
3670                                int plane, int pipe, u32 iir)
3671 {
3672         u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3673
3674         if (!intel_pipe_handle_vblank(dev_priv, pipe))
3675                 return false;
3676
3677         if ((iir & flip_pending) == 0)
3678                 goto check_page_flip;
3679
3680         /* We detect FlipDone by looking for the change in PendingFlip from '1'
3681          * to '0' on the following vblank, i.e. IIR has the Pendingflip
3682          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3683          * the flip is completed (no longer pending). Since this doesn't raise
3684          * an interrupt per se, we watch for the change at vblank.
3685          */
3686         if (I915_READ16(ISR) & flip_pending)
3687                 goto check_page_flip;
3688
3689         intel_finish_page_flip_cs(dev_priv, pipe);
3690         return true;
3691
3692 check_page_flip:
3693         intel_check_page_flip(dev_priv, pipe);
3694         return false;
3695 }
3696
3697 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3698 {
3699         struct drm_device *dev = arg;
3700         struct drm_i915_private *dev_priv = to_i915(dev);
3701         u16 iir, new_iir;
3702         u32 pipe_stats[2];
3703         int pipe;
3704         u16 flip_mask =
3705                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3706                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3707         irqreturn_t ret;
3708
3709         if (!intel_irqs_enabled(dev_priv))
3710                 return IRQ_NONE;
3711
3712         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3713         disable_rpm_wakeref_asserts(dev_priv);
3714
3715         ret = IRQ_NONE;
3716         iir = I915_READ16(IIR);
3717         if (iir == 0)
3718                 goto out;
3719
3720         while (iir & ~flip_mask) {
3721                 /* Can't rely on pipestat interrupt bit in iir as it might
3722                  * have been cleared after the pipestat interrupt was received.
3723                  * It doesn't set the bit in iir again, but it still produces
3724                  * interrupts (for non-MSI).
3725                  */
3726                 spin_lock(&dev_priv->irq_lock);
3727                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3728                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3729
3730                 for_each_pipe(dev_priv, pipe) {
3731                         i915_reg_t reg = PIPESTAT(pipe);
3732                         pipe_stats[pipe] = I915_READ(reg);
3733
3734                         /*
3735                          * Clear the PIPE*STAT regs before the IIR
3736                          */
3737                         if (pipe_stats[pipe] & 0x8000ffff)
3738                                 I915_WRITE(reg, pipe_stats[pipe]);
3739                 }
3740                 spin_unlock(&dev_priv->irq_lock);
3741
3742                 I915_WRITE16(IIR, iir & ~flip_mask);
3743                 new_iir = I915_READ16(IIR); /* Flush posted writes */
3744
3745                 if (iir & I915_USER_INTERRUPT)
3746                         notify_ring(dev_priv->engine[RCS]);
3747
3748                 for_each_pipe(dev_priv, pipe) {
3749                         int plane = pipe;
3750                         if (HAS_FBC(dev_priv))
3751                                 plane = !plane;
3752
3753                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3754                             i8xx_handle_vblank(dev_priv, plane, pipe, iir))
3755                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3756
3757                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3758                                 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
3759
3760                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3761                                 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3762                                                                     pipe);
3763                 }
3764
3765                 iir = new_iir;
3766         }
3767         ret = IRQ_HANDLED;
3768
3769 out:
3770         enable_rpm_wakeref_asserts(dev_priv);
3771
3772         return ret;
3773 }
3774
3775 static void i8xx_irq_uninstall(struct drm_device * dev)
3776 {
3777         struct drm_i915_private *dev_priv = to_i915(dev);
3778         int pipe;
3779
3780         for_each_pipe(dev_priv, pipe) {
3781                 /* Clear enable bits; then clear status bits */
3782                 I915_WRITE(PIPESTAT(pipe), 0);
3783                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3784         }
3785         I915_WRITE16(IMR, 0xffff);
3786         I915_WRITE16(IER, 0x0);
3787         I915_WRITE16(IIR, I915_READ16(IIR));
3788 }
3789
3790 static void i915_irq_preinstall(struct drm_device * dev)
3791 {
3792         struct drm_i915_private *dev_priv = to_i915(dev);
3793         int pipe;
3794
3795         if (I915_HAS_HOTPLUG(dev_priv)) {
3796                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3797                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3798         }
3799
3800         I915_WRITE16(HWSTAM, 0xeffe);
3801         for_each_pipe(dev_priv, pipe)
3802                 I915_WRITE(PIPESTAT(pipe), 0);
3803         I915_WRITE(IMR, 0xffffffff);
3804         I915_WRITE(IER, 0x0);
3805         POSTING_READ(IER);
3806 }
3807
3808 static int i915_irq_postinstall(struct drm_device *dev)
3809 {
3810         struct drm_i915_private *dev_priv = to_i915(dev);
3811         u32 enable_mask;
3812
3813         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3814
3815         /* Unmask the interrupts that we always want on. */
3816         dev_priv->irq_mask =
3817                 ~(I915_ASLE_INTERRUPT |
3818                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3819                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3820                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3821                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3822
3823         enable_mask =
3824                 I915_ASLE_INTERRUPT |
3825                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3826                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3827                 I915_USER_INTERRUPT;
3828
3829         if (I915_HAS_HOTPLUG(dev_priv)) {
3830                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3831                 POSTING_READ(PORT_HOTPLUG_EN);
3832
3833                 /* Enable in IER... */
3834                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3835                 /* and unmask in IMR */
3836                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3837         }
3838
3839         I915_WRITE(IMR, dev_priv->irq_mask);
3840         I915_WRITE(IER, enable_mask);
3841         POSTING_READ(IER);
3842
3843         i915_enable_asle_pipestat(dev_priv);
3844
3845         /* Interrupt setup is already guaranteed to be single-threaded, this is
3846          * just to make the assert_spin_locked check happy. */
3847         spin_lock_irq(&dev_priv->irq_lock);
3848         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3849         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3850         spin_unlock_irq(&dev_priv->irq_lock);
3851
3852         return 0;
3853 }
3854
3855 /*
3856  * Returns true when a page flip has completed.
3857  */
3858 static bool i915_handle_vblank(struct drm_i915_private *dev_priv,
3859                                int plane, int pipe, u32 iir)
3860 {
3861         u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3862
3863         if (!intel_pipe_handle_vblank(dev_priv, pipe))
3864                 return false;
3865
3866         if ((iir & flip_pending) == 0)
3867                 goto check_page_flip;
3868
3869         /* We detect FlipDone by looking for the change in PendingFlip from '1'
3870          * to '0' on the following vblank, i.e. IIR has the Pendingflip
3871          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3872          * the flip is completed (no longer pending). Since this doesn't raise
3873          * an interrupt per se, we watch for the change at vblank.
3874          */
3875         if (I915_READ(ISR) & flip_pending)
3876                 goto check_page_flip;
3877
3878         intel_finish_page_flip_cs(dev_priv, pipe);
3879         return true;
3880
3881 check_page_flip:
3882         intel_check_page_flip(dev_priv, pipe);
3883         return false;
3884 }
3885
3886 static irqreturn_t i915_irq_handler(int irq, void *arg)
3887 {
3888         struct drm_device *dev = arg;
3889         struct drm_i915_private *dev_priv = to_i915(dev);
3890         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3891         u32 flip_mask =
3892                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3893                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3894         int pipe, ret = IRQ_NONE;
3895
3896         if (!intel_irqs_enabled(dev_priv))
3897                 return IRQ_NONE;
3898
3899         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3900         disable_rpm_wakeref_asserts(dev_priv);
3901
3902         iir = I915_READ(IIR);
3903         do {
3904                 bool irq_received = (iir & ~flip_mask) != 0;
3905                 bool blc_event = false;
3906
3907                 /* Can't rely on pipestat interrupt bit in iir as it might
3908                  * have been cleared after the pipestat interrupt was received.
3909                  * It doesn't set the bit in iir again, but it still produces
3910                  * interrupts (for non-MSI).
3911                  */
3912                 spin_lock(&dev_priv->irq_lock);
3913                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3914                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3915
3916                 for_each_pipe(dev_priv, pipe) {
3917                         i915_reg_t reg = PIPESTAT(pipe);
3918                         pipe_stats[pipe] = I915_READ(reg);
3919
3920                         /* Clear the PIPE*STAT regs before the IIR */
3921                         if (pipe_stats[pipe] & 0x8000ffff) {
3922                                 I915_WRITE(reg, pipe_stats[pipe]);
3923                                 irq_received = true;
3924                         }
3925                 }
3926                 spin_unlock(&dev_priv->irq_lock);
3927
3928                 if (!irq_received)
3929                         break;
3930
3931                 /* Consume port.  Then clear IIR or we'll miss events */
3932                 if (I915_HAS_HOTPLUG(dev_priv) &&
3933                     iir & I915_DISPLAY_PORT_INTERRUPT) {
3934                         u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
3935                         if (hotplug_status)
3936                                 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
3937                 }
3938
3939                 I915_WRITE(IIR, iir & ~flip_mask);
3940                 new_iir = I915_READ(IIR); /* Flush posted writes */
3941
3942                 if (iir & I915_USER_INTERRUPT)
3943                         notify_ring(dev_priv->engine[RCS]);
3944
3945                 for_each_pipe(dev_priv, pipe) {
3946                         int plane = pipe;
3947                         if (HAS_FBC(dev_priv))
3948                                 plane = !plane;
3949
3950                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3951                             i915_handle_vblank(dev_priv, plane, pipe, iir))
3952                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3953
3954                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3955                                 blc_event = true;
3956
3957                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3958                                 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
3959
3960                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3961                                 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3962                                                                     pipe);
3963                 }
3964
3965                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3966                         intel_opregion_asle_intr(dev_priv);
3967
3968                 /* With MSI, interrupts are only generated when iir
3969                  * transitions from zero to nonzero.  If another bit got
3970                  * set while we were handling the existing iir bits, then
3971                  * we would never get another interrupt.
3972                  *
3973                  * This is fine on non-MSI as well, as if we hit this path
3974                  * we avoid exiting the interrupt handler only to generate
3975                  * another one.
3976                  *
3977                  * Note that for MSI this could cause a stray interrupt report
3978                  * if an interrupt landed in the time between writing IIR and
3979                  * the posting read.  This should be rare enough to never
3980                  * trigger the 99% of 100,000 interrupts test for disabling
3981                  * stray interrupts.
3982                  */
3983                 ret = IRQ_HANDLED;
3984                 iir = new_iir;
3985         } while (iir & ~flip_mask);
3986
3987         enable_rpm_wakeref_asserts(dev_priv);
3988
3989         return ret;
3990 }
3991
3992 static void i915_irq_uninstall(struct drm_device * dev)
3993 {
3994         struct drm_i915_private *dev_priv = to_i915(dev);
3995         int pipe;
3996
3997         if (I915_HAS_HOTPLUG(dev_priv)) {
3998                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3999                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4000         }
4001
4002         I915_WRITE16(HWSTAM, 0xffff);
4003         for_each_pipe(dev_priv, pipe) {
4004                 /* Clear enable bits; then clear status bits */
4005                 I915_WRITE(PIPESTAT(pipe), 0);
4006                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4007         }
4008         I915_WRITE(IMR, 0xffffffff);
4009         I915_WRITE(IER, 0x0);
4010
4011         I915_WRITE(IIR, I915_READ(IIR));
4012 }
4013
4014 static void i965_irq_preinstall(struct drm_device * dev)
4015 {
4016         struct drm_i915_private *dev_priv = to_i915(dev);
4017         int pipe;
4018
4019         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4020         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4021
4022         I915_WRITE(HWSTAM, 0xeffe);
4023         for_each_pipe(dev_priv, pipe)
4024                 I915_WRITE(PIPESTAT(pipe), 0);
4025         I915_WRITE(IMR, 0xffffffff);
4026         I915_WRITE(IER, 0x0);
4027         POSTING_READ(IER);
4028 }
4029
4030 static int i965_irq_postinstall(struct drm_device *dev)
4031 {
4032         struct drm_i915_private *dev_priv = to_i915(dev);
4033         u32 enable_mask;
4034         u32 error_mask;
4035
4036         /* Unmask the interrupts that we always want on. */
4037         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
4038                                I915_DISPLAY_PORT_INTERRUPT |
4039                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4040                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4041                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4042                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4043                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4044
4045         enable_mask = ~dev_priv->irq_mask;
4046         enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4047                          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4048         enable_mask |= I915_USER_INTERRUPT;
4049
4050         if (IS_G4X(dev_priv))
4051                 enable_mask |= I915_BSD_USER_INTERRUPT;
4052
4053         /* Interrupt setup is already guaranteed to be single-threaded, this is
4054          * just to make the assert_spin_locked check happy. */
4055         spin_lock_irq(&dev_priv->irq_lock);
4056         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4057         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4058         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4059         spin_unlock_irq(&dev_priv->irq_lock);
4060
4061         /*
4062          * Enable some error detection, note the instruction error mask
4063          * bit is reserved, so we leave it masked.
4064          */
4065         if (IS_G4X(dev_priv)) {
4066                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4067                                GM45_ERROR_MEM_PRIV |
4068                                GM45_ERROR_CP_PRIV |
4069                                I915_ERROR_MEMORY_REFRESH);
4070         } else {
4071                 error_mask = ~(I915_ERROR_PAGE_TABLE |
4072                                I915_ERROR_MEMORY_REFRESH);
4073         }
4074         I915_WRITE(EMR, error_mask);
4075
4076         I915_WRITE(IMR, dev_priv->irq_mask);
4077         I915_WRITE(IER, enable_mask);
4078         POSTING_READ(IER);
4079
4080         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4081         POSTING_READ(PORT_HOTPLUG_EN);
4082
4083         i915_enable_asle_pipestat(dev_priv);
4084
4085         return 0;
4086 }
4087
4088 static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
4089 {
4090         u32 hotplug_en;
4091
4092         lockdep_assert_held(&dev_priv->irq_lock);
4093
4094         /* Note HDMI and DP share hotplug bits */
4095         /* enable bits are the same for all generations */
4096         hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);
4097         /* Programming the CRT detection parameters tends
4098            to generate a spurious hotplug event about three
4099            seconds later.  So just do it once.
4100         */
4101         if (IS_G4X(dev_priv))
4102                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4103         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4104
4105         /* Ignore TV since it's buggy */
4106         i915_hotplug_interrupt_update_locked(dev_priv,
4107                                              HOTPLUG_INT_EN_MASK |
4108                                              CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
4109                                              CRT_HOTPLUG_ACTIVATION_PERIOD_64,
4110                                              hotplug_en);
4111 }
4112
4113 static irqreturn_t i965_irq_handler(int irq, void *arg)
4114 {
4115         struct drm_device *dev = arg;
4116         struct drm_i915_private *dev_priv = to_i915(dev);
4117         u32 iir, new_iir;
4118         u32 pipe_stats[I915_MAX_PIPES];
4119         int ret = IRQ_NONE, pipe;
4120         u32 flip_mask =
4121                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4122                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4123
4124         if (!intel_irqs_enabled(dev_priv))
4125                 return IRQ_NONE;
4126
4127         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4128         disable_rpm_wakeref_asserts(dev_priv);
4129
4130         iir = I915_READ(IIR);
4131
4132         for (;;) {
4133                 bool irq_received = (iir & ~flip_mask) != 0;
4134                 bool blc_event = false;
4135
4136                 /* Can't rely on pipestat interrupt bit in iir as it might
4137                  * have been cleared after the pipestat interrupt was received.
4138                  * It doesn't set the bit in iir again, but it still produces
4139                  * interrupts (for non-MSI).
4140                  */
4141                 spin_lock(&dev_priv->irq_lock);
4142                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4143                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4144
4145                 for_each_pipe(dev_priv, pipe) {
4146                         i915_reg_t reg = PIPESTAT(pipe);
4147                         pipe_stats[pipe] = I915_READ(reg);
4148
4149                         /*
4150                          * Clear the PIPE*STAT regs before the IIR
4151                          */
4152                         if (pipe_stats[pipe] & 0x8000ffff) {
4153                                 I915_WRITE(reg, pipe_stats[pipe]);
4154                                 irq_received = true;
4155                         }
4156                 }
4157                 spin_unlock(&dev_priv->irq_lock);
4158
4159                 if (!irq_received)
4160                         break;
4161
4162                 ret = IRQ_HANDLED;
4163
4164                 /* Consume port.  Then clear IIR or we'll miss events */
4165                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
4166                         u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4167                         if (hotplug_status)
4168                                 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4169                 }
4170
4171                 I915_WRITE(IIR, iir & ~flip_mask);
4172                 new_iir = I915_READ(IIR); /* Flush posted writes */
4173
4174                 if (iir & I915_USER_INTERRUPT)
4175                         notify_ring(dev_priv->engine[RCS]);
4176                 if (iir & I915_BSD_USER_INTERRUPT)
4177                         notify_ring(dev_priv->engine[VCS]);
4178
4179                 for_each_pipe(dev_priv, pipe) {
4180                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4181                             i915_handle_vblank(dev_priv, pipe, pipe, iir))
4182                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4183
4184                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4185                                 blc_event = true;
4186
4187                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4188                                 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4189
4190                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4191                                 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
4192                 }
4193
4194                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4195                         intel_opregion_asle_intr(dev_priv);
4196
4197                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4198                         gmbus_irq_handler(dev_priv);
4199
4200                 /* With MSI, interrupts are only generated when iir
4201                  * transitions from zero to nonzero.  If another bit got
4202                  * set while we were handling the existing iir bits, then
4203                  * we would never get another interrupt.
4204                  *
4205                  * This is fine on non-MSI as well, as if we hit this path
4206                  * we avoid exiting the interrupt handler only to generate
4207                  * another one.
4208                  *
4209                  * Note that for MSI this could cause a stray interrupt report
4210                  * if an interrupt landed in the time between writing IIR and
4211                  * the posting read.  This should be rare enough to never
4212                  * trigger the 99% of 100,000 interrupts test for disabling
4213                  * stray interrupts.
4214                  */
4215                 iir = new_iir;
4216         }
4217
4218         enable_rpm_wakeref_asserts(dev_priv);
4219
4220         return ret;
4221 }
4222
4223 static void i965_irq_uninstall(struct drm_device * dev)
4224 {
4225         struct drm_i915_private *dev_priv = to_i915(dev);
4226         int pipe;
4227
4228         if (!dev_priv)
4229                 return;
4230
4231         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4232         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4233
4234         I915_WRITE(HWSTAM, 0xffffffff);
4235         for_each_pipe(dev_priv, pipe)
4236                 I915_WRITE(PIPESTAT(pipe), 0);
4237         I915_WRITE(IMR, 0xffffffff);
4238         I915_WRITE(IER, 0x0);
4239
4240         for_each_pipe(dev_priv, pipe)
4241                 I915_WRITE(PIPESTAT(pipe),
4242                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4243         I915_WRITE(IIR, I915_READ(IIR));
4244 }
4245
4246 /**
4247  * intel_irq_init - initializes irq support
4248  * @dev_priv: i915 device instance
4249  *
4250  * This function initializes all the irq support including work items, timers
4251  * and all the vtables. It does not setup the interrupt itself though.
4252  */
4253 void intel_irq_init(struct drm_i915_private *dev_priv)
4254 {
4255         struct drm_device *dev = &dev_priv->drm;
4256
4257         intel_hpd_init_work(dev_priv);
4258
4259         INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4260         INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4261
4262         if (HAS_GUC_SCHED(dev_priv))
4263                 dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT;
4264
4265         /* Let's track the enabled rps events */
4266         if (IS_VALLEYVIEW(dev_priv))
4267                 /* WaGsvRC0ResidencyMethod:vlv */
4268                 dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED;
4269         else
4270                 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4271
4272         dev_priv->rps.pm_intrmsk_mbz = 0;
4273
4274         /*
4275          * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
4276          * if GEN6_PM_UP_EI_EXPIRED is masked.
4277          *
4278          * TODO: verify if this can be reproduced on VLV,CHV.
4279          */
4280         if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
4281                 dev_priv->rps.pm_intrmsk_mbz |= GEN6_PM_RP_UP_EI_EXPIRED;
4282
4283         if (INTEL_INFO(dev_priv)->gen >= 8)
4284                 dev_priv->rps.pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
4285
4286         if (IS_GEN2(dev_priv)) {
4287                 /* Gen2 doesn't have a hardware frame counter */
4288                 dev->max_vblank_count = 0;
4289         } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
4290                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4291                 dev->driver->get_vblank_counter = g4x_get_vblank_counter;
4292         } else {
4293                 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4294                 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4295         }
4296
4297         /*
4298          * Opt out of the vblank disable timer on everything except gen2.
4299          * Gen2 doesn't have a hardware frame counter and so depends on
4300          * vblank interrupts to produce sane vblank seuquence numbers.
4301          */
4302         if (!IS_GEN2(dev_priv))
4303                 dev->vblank_disable_immediate = true;
4304
4305         /* Most platforms treat the display irq block as an always-on
4306          * power domain. vlv/chv can disable it at runtime and need
4307          * special care to avoid writing any of the display block registers
4308          * outside of the power domain. We defer setting up the display irqs
4309          * in this case to the runtime pm.
4310          */
4311         dev_priv->display_irqs_enabled = true;
4312         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4313                 dev_priv->display_irqs_enabled = false;
4314
4315         dev_priv->hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD;
4316
4317         dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4318         dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4319
4320         if (IS_CHERRYVIEW(dev_priv)) {
4321                 dev->driver->irq_handler = cherryview_irq_handler;
4322                 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4323                 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4324                 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4325                 dev->driver->enable_vblank = i965_enable_vblank;
4326                 dev->driver->disable_vblank = i965_disable_vblank;
4327                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4328         } else if (IS_VALLEYVIEW(dev_priv)) {
4329                 dev->driver->irq_handler = valleyview_irq_handler;
4330                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4331                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4332                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4333                 dev->driver->enable_vblank = i965_enable_vblank;
4334                 dev->driver->disable_vblank = i965_disable_vblank;
4335                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4336         } else if (INTEL_INFO(dev_priv)->gen >= 8) {
4337                 dev->driver->irq_handler = gen8_irq_handler;
4338                 dev->driver->irq_preinstall = gen8_irq_reset;
4339                 dev->driver->irq_postinstall = gen8_irq_postinstall;
4340                 dev->driver->irq_uninstall = gen8_irq_uninstall;
4341                 dev->driver->enable_vblank = gen8_enable_vblank;
4342                 dev->driver->disable_vblank = gen8_disable_vblank;
4343                 if (IS_GEN9_LP(dev_priv))
4344                         dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4345                 else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
4346                         dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4347                 else
4348                         dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4349         } else if (HAS_PCH_SPLIT(dev_priv)) {
4350                 dev->driver->irq_handler = ironlake_irq_handler;
4351                 dev->driver->irq_preinstall = ironlake_irq_reset;
4352                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4353                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4354                 dev->driver->enable_vblank = ironlake_enable_vblank;
4355                 dev->driver->disable_vblank = ironlake_disable_vblank;
4356                 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4357         } else {
4358                 if (IS_GEN2(dev_priv)) {
4359                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
4360                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
4361                         dev->driver->irq_handler = i8xx_irq_handler;
4362                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
4363                         dev->driver->enable_vblank = i8xx_enable_vblank;
4364                         dev->driver->disable_vblank = i8xx_disable_vblank;
4365                 } else if (IS_GEN3(dev_priv)) {
4366                         dev->driver->irq_preinstall = i915_irq_preinstall;
4367                         dev->driver->irq_postinstall = i915_irq_postinstall;
4368                         dev->driver->irq_uninstall = i915_irq_uninstall;
4369                         dev->driver->irq_handler = i915_irq_handler;
4370                         dev->driver->enable_vblank = i8xx_enable_vblank;
4371                         dev->driver->disable_vblank = i8xx_disable_vblank;
4372                 } else {
4373                         dev->driver->irq_preinstall = i965_irq_preinstall;
4374                         dev->driver->irq_postinstall = i965_irq_postinstall;
4375                         dev->driver->irq_uninstall = i965_irq_uninstall;
4376                         dev->driver->irq_handler = i965_irq_handler;
4377                         dev->driver->enable_vblank = i965_enable_vblank;
4378                         dev->driver->disable_vblank = i965_disable_vblank;
4379                 }
4380                 if (I915_HAS_HOTPLUG(dev_priv))
4381                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4382         }
4383 }
4384
4385 /**
4386  * intel_irq_install - enables the hardware interrupt
4387  * @dev_priv: i915 device instance
4388  *
4389  * This function enables the hardware interrupt handling, but leaves the hotplug
4390  * handling still disabled. It is called after intel_irq_init().
4391  *
4392  * In the driver load and resume code we need working interrupts in a few places
4393  * but don't want to deal with the hassle of concurrent probe and hotplug
4394  * workers. Hence the split into this two-stage approach.
4395  */
4396 int intel_irq_install(struct drm_i915_private *dev_priv)
4397 {
4398         /*
4399          * We enable some interrupt sources in our postinstall hooks, so mark
4400          * interrupts as enabled _before_ actually enabling them to avoid
4401          * special cases in our ordering checks.
4402          */
4403         dev_priv->pm.irqs_enabled = true;
4404
4405         return drm_irq_install(&dev_priv->drm, dev_priv->drm.pdev->irq);
4406 }
4407
4408 /**
4409  * intel_irq_uninstall - finilizes all irq handling
4410  * @dev_priv: i915 device instance
4411  *
4412  * This stops interrupt and hotplug handling and unregisters and frees all
4413  * resources acquired in the init functions.
4414  */
4415 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4416 {
4417         drm_irq_uninstall(&dev_priv->drm);
4418         intel_hpd_cancel_work(dev_priv);
4419         dev_priv->pm.irqs_enabled = false;
4420 }
4421
4422 /**
4423  * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4424  * @dev_priv: i915 device instance
4425  *
4426  * This function is used to disable interrupts at runtime, both in the runtime
4427  * pm and the system suspend/resume code.
4428  */
4429 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4430 {
4431         dev_priv->drm.driver->irq_uninstall(&dev_priv->drm);
4432         dev_priv->pm.irqs_enabled = false;
4433         synchronize_irq(dev_priv->drm.irq);
4434 }
4435
4436 /**
4437  * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4438  * @dev_priv: i915 device instance
4439  *
4440  * This function is used to enable interrupts at runtime, both in the runtime
4441  * pm and the system suspend/resume code.
4442  */
4443 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4444 {
4445         dev_priv->pm.irqs_enabled = true;
4446         dev_priv->drm.driver->irq_preinstall(&dev_priv->drm);
4447         dev_priv->drm.driver->irq_postinstall(&dev_priv->drm);
4448 }