drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/circ_buf.h>
  32 #include <linux/slab.h>
  33 #include <linux/sysrq.h>
  34
  35 #include <drm/drm_drv.h>
  36 #include <drm/drm_irq.h>
  37
  38 #include "display/intel_display_types.h"
  39 #include "display/intel_fifo_underrun.h"
  40 #include "display/intel_hotplug.h"
  41 #include "display/intel_lpe_audio.h"
  42 #include "display/intel_psr.h"
  43
  44 #include "gt/intel_gt.h"
  45 #include "gt/intel_gt_irq.h"
  46 #include "gt/intel_gt_pm_irq.h"
  47 #include "gt/intel_rps.h"
  48
  49 #include "i915_drv.h"
  50 #include "i915_irq.h"
  51 #include "i915_trace.h"
  52 #include "intel_pm.h"
  53
  54 /**
  55  * DOC: interrupt handling
  56  *
  57  * These functions provide the basic support for enabling and disabling the
  58  * interrupt handling support. There's a lot more functionality in i915_irq.c
  59  * and related files, but that will be described in separate chapters.
  60  */
  61
  62 typedef bool (*long_pulse_detect_func)(enum hpd_pin pin, u32 val);
  63
  64 static const u32 hpd_ilk[HPD_NUM_PINS] = {
  65         [HPD_PORT_A] = DE_DP_A_HOTPLUG,
  66 };
  67
  68 static const u32 hpd_ivb[HPD_NUM_PINS] = {
  69         [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
  70 };
  71
  72 static const u32 hpd_bdw[HPD_NUM_PINS] = {
  73         [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
  74 };
  75
  76 static const u32 hpd_ibx[HPD_NUM_PINS] = {
  77         [HPD_CRT] = SDE_CRT_HOTPLUG,
  78         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
  79         [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
  80         [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
  81         [HPD_PORT_D] = SDE_PORTD_HOTPLUG,
  82 };
  83
  84 static const u32 hpd_cpt[HPD_NUM_PINS] = {
  85         [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
  86         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
  87         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  88         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  89         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
  90 };
  91
  92 static const u32 hpd_spt[HPD_NUM_PINS] = {
  93         [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
  94         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  95         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  96         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
  97         [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT,
  98 };
  99
 100 static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
 101         [HPD_CRT] = CRT_HOTPLUG_INT_EN,
 102         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
 103         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
 104         [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
 105         [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
 106         [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN,
 107 };
 108
 109 static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
 110         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
 111         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
 112         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
 113         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
 114         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
 115         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS,
 116 };
 117
 118 static const u32 hpd_status_i915[HPD_NUM_PINS] = {
 119         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
 120         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
 121         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
 122         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
 123         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
 124         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS,
 125 };
 126
 127 static const u32 hpd_bxt[HPD_NUM_PINS] = {
 128         [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
 129         [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
 130         [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC,
 131 };
 132
 133 static const u32 hpd_gen11[HPD_NUM_PINS] = {
 134         [HPD_PORT_C] = GEN11_TC1_HOTPLUG | GEN11_TBT1_HOTPLUG,
 135         [HPD_PORT_D] = GEN11_TC2_HOTPLUG | GEN11_TBT2_HOTPLUG,
 136         [HPD_PORT_E] = GEN11_TC3_HOTPLUG | GEN11_TBT3_HOTPLUG,
 137         [HPD_PORT_F] = GEN11_TC4_HOTPLUG | GEN11_TBT4_HOTPLUG,
 138 };
 139
 140 static const u32 hpd_gen12[HPD_NUM_PINS] = {
 141         [HPD_PORT_D] = GEN11_TC1_HOTPLUG | GEN11_TBT1_HOTPLUG,
 142         [HPD_PORT_E] = GEN11_TC2_HOTPLUG | GEN11_TBT2_HOTPLUG,
 143         [HPD_PORT_F] = GEN11_TC3_HOTPLUG | GEN11_TBT3_HOTPLUG,
 144         [HPD_PORT_G] = GEN11_TC4_HOTPLUG | GEN11_TBT4_HOTPLUG,
 145         [HPD_PORT_H] = GEN12_TC5_HOTPLUG | GEN12_TBT5_HOTPLUG,
 146         [HPD_PORT_I] = GEN12_TC6_HOTPLUG | GEN12_TBT6_HOTPLUG,
 147 };
 148
 149 static const u32 hpd_icp[HPD_NUM_PINS] = {
 150         [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A),
 151         [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B),
 152         [HPD_PORT_C] = SDE_TC_HOTPLUG_ICP(PORT_TC1),
 153         [HPD_PORT_D] = SDE_TC_HOTPLUG_ICP(PORT_TC2),
 154         [HPD_PORT_E] = SDE_TC_HOTPLUG_ICP(PORT_TC3),
 155         [HPD_PORT_F] = SDE_TC_HOTPLUG_ICP(PORT_TC4),
 156 };
 157
 158 static const u32 hpd_tgp[HPD_NUM_PINS] = {
 159         [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A),
 160         [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B),
 161         [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(PORT_C),
 162         [HPD_PORT_D] = SDE_TC_HOTPLUG_ICP(PORT_TC1),
 163         [HPD_PORT_E] = SDE_TC_HOTPLUG_ICP(PORT_TC2),
 164         [HPD_PORT_F] = SDE_TC_HOTPLUG_ICP(PORT_TC3),
 165         [HPD_PORT_G] = SDE_TC_HOTPLUG_ICP(PORT_TC4),
 166         [HPD_PORT_H] = SDE_TC_HOTPLUG_ICP(PORT_TC5),
 167         [HPD_PORT_I] = SDE_TC_HOTPLUG_ICP(PORT_TC6),
 168 };
 169
 170 static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
 171 {
 172         struct i915_hotplug *hpd = &dev_priv->hotplug;
 173
 174         if (HAS_GMCH(dev_priv)) {
 175                 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
 176                     IS_CHERRYVIEW(dev_priv))
 177                         hpd->hpd = hpd_status_g4x;
 178                 else
 179                         hpd->hpd = hpd_status_i915;
 180                 return;
 181         }
 182
 183         if (INTEL_GEN(dev_priv) >= 12)
 184                 hpd->hpd = hpd_gen12;
 185         else if (INTEL_GEN(dev_priv) >= 11)
 186                 hpd->hpd = hpd_gen11;
 187         else if (IS_GEN9_LP(dev_priv))
 188                 hpd->hpd = hpd_bxt;
 189         else if (INTEL_GEN(dev_priv) >= 8)
 190                 hpd->hpd = hpd_bdw;
 191         else if (INTEL_GEN(dev_priv) >= 7)
 192                 hpd->hpd = hpd_ivb;
 193         else
 194                 hpd->hpd = hpd_ilk;
 195
 196         if (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))
 197                 return;
 198
 199         if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv))
 200                 hpd->pch_hpd = hpd_tgp;
 201         else if (HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
 202                 hpd->pch_hpd = hpd_icp;
 203         else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv))
 204                 hpd->pch_hpd = hpd_spt;
 205         else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_CPT(dev_priv))
 206                 hpd->pch_hpd = hpd_cpt;
 207         else if (HAS_PCH_IBX(dev_priv))
 208                 hpd->pch_hpd = hpd_ibx;
 209         else
 210                 MISSING_CASE(INTEL_PCH_TYPE(dev_priv));
 211 }
 212
 213 static void
 214 intel_handle_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
 215 {
 216         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
 217
 218         drm_crtc_handle_vblank(&crtc->base);
 219 }
 220
 221 void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
 222                     i915_reg_t iir, i915_reg_t ier)
 223 {
 224         intel_uncore_write(uncore, imr, 0xffffffff);
 225         intel_uncore_posting_read(uncore, imr);
 226
 227         intel_uncore_write(uncore, ier, 0);
 228
 229         /* IIR can theoretically queue up two events. Be paranoid. */
 230         intel_uncore_write(uncore, iir, 0xffffffff);
 231         intel_uncore_posting_read(uncore, iir);
 232         intel_uncore_write(uncore, iir, 0xffffffff);
 233         intel_uncore_posting_read(uncore, iir);
 234 }
 235
 236 void gen2_irq_reset(struct intel_uncore *uncore)
 237 {
 238         intel_uncore_write16(uncore, GEN2_IMR, 0xffff);
 239         intel_uncore_posting_read16(uncore, GEN2_IMR);
 240
 241         intel_uncore_write16(uncore, GEN2_IER, 0);
 242
 243         /* IIR can theoretically queue up two events. Be paranoid. */
 244         intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
 245         intel_uncore_posting_read16(uncore, GEN2_IIR);
 246         intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
 247         intel_uncore_posting_read16(uncore, GEN2_IIR);
 248 }
 249
 250 /*
 251  * We should clear IMR at preinstall/uninstall, and just check at postinstall.
 252  */
 253 static void gen3_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg)
 254 {
 255         u32 val = intel_uncore_read(uncore, reg);
 256
 257         if (val == 0)
 258                 return;
 259
 260         drm_WARN(&uncore->i915->drm, 1,
 261                  "Interrupt register 0x%x is not zero: 0x%08x\n",
 262                  i915_mmio_reg_offset(reg), val);
 263         intel_uncore_write(uncore, reg, 0xffffffff);
 264         intel_uncore_posting_read(uncore, reg);
 265         intel_uncore_write(uncore, reg, 0xffffffff);
 266         intel_uncore_posting_read(uncore, reg);
 267 }
 268
 269 static void gen2_assert_iir_is_zero(struct intel_uncore *uncore)
 270 {
 271         u16 val = intel_uncore_read16(uncore, GEN2_IIR);
 272
 273         if (val == 0)
 274                 return;
 275
 276         drm_WARN(&uncore->i915->drm, 1,
 277                  "Interrupt register 0x%x is not zero: 0x%08x\n",
 278                  i915_mmio_reg_offset(GEN2_IIR), val);
 279         intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
 280         intel_uncore_posting_read16(uncore, GEN2_IIR);
 281         intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
 282         intel_uncore_posting_read16(uncore, GEN2_IIR);
 283 }
 284
 285 void gen3_irq_init(struct intel_uncore *uncore,
 286                    i915_reg_t imr, u32 imr_val,
 287                    i915_reg_t ier, u32 ier_val,
 288                    i915_reg_t iir)
 289 {
 290         gen3_assert_iir_is_zero(uncore, iir);
 291
 292         intel_uncore_write(uncore, ier, ier_val);
 293         intel_uncore_write(uncore, imr, imr_val);
 294         intel_uncore_posting_read(uncore, imr);
 295 }
 296
 297 void gen2_irq_init(struct intel_uncore *uncore,
 298                    u32 imr_val, u32 ier_val)
 299 {
 300         gen2_assert_iir_is_zero(uncore);
 301
 302         intel_uncore_write16(uncore, GEN2_IER, ier_val);
 303         intel_uncore_write16(uncore, GEN2_IMR, imr_val);
 304         intel_uncore_posting_read16(uncore, GEN2_IMR);
 305 }
 306
 307 /* For display hotplug interrupt */
 308 static inline void
 309 i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
 310                                      u32 mask,
 311                                      u32 bits)
 312 {
 313         u32 val;
 314
 315         lockdep_assert_held(&dev_priv->irq_lock);
 316         drm_WARN_ON(&dev_priv->drm, bits & ~mask);
 317
 318         val = I915_READ(PORT_HOTPLUG_EN);
 319         val &= ~mask;
 320         val |= bits;
 321         I915_WRITE(PORT_HOTPLUG_EN, val);
 322 }
 323
 324 /**
 325  * i915_hotplug_interrupt_update - update hotplug interrupt enable
 326  * @dev_priv: driver private
 327  * @mask: bits to update
 328  * @bits: bits to enable
 329  * NOTE: the HPD enable bits are modified both inside and outside
 330  * of an interrupt context. To avoid that read-modify-write cycles
 331  * interfer, these bits are protected by a spinlock. Since this
 332  * function is usually not called from a context where the lock is
 333  * held already, this function acquires the lock itself. A non-locking
 334  * version is also available.
 335  */
 336 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
 337                                    u32 mask,
 338                                    u32 bits)
 339 {
 340         spin_lock_irq(&dev_priv->irq_lock);
 341         i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
 342         spin_unlock_irq(&dev_priv->irq_lock);
 343 }
 344
 345 /**
 346  * ilk_update_display_irq - update DEIMR
 347  * @dev_priv: driver private
 348  * @interrupt_mask: mask of interrupt bits to update
 349  * @enabled_irq_mask: mask of interrupt bits to enable
 350  */
 351 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
 352                             u32 interrupt_mask,
 353                             u32 enabled_irq_mask)
 354 {
 355         u32 new_val;
 356
 357         lockdep_assert_held(&dev_priv->irq_lock);
 358
 359         drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
 360
 361         if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
 362                 return;
 363
 364         new_val = dev_priv->irq_mask;
 365         new_val &= ~interrupt_mask;
 366         new_val |= (~enabled_irq_mask & interrupt_mask);
 367
 368         if (new_val != dev_priv->irq_mask) {
 369                 dev_priv->irq_mask = new_val;
 370                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 371                 POSTING_READ(DEIMR);
 372         }
 373 }
 374
 375 /**
 376  * bdw_update_port_irq - update DE port interrupt
 377  * @dev_priv: driver private
 378  * @interrupt_mask: mask of interrupt bits to update
 379  * @enabled_irq_mask: mask of interrupt bits to enable
 380  */
 381 static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
 382                                 u32 interrupt_mask,
 383                                 u32 enabled_irq_mask)
 384 {
 385         u32 new_val;
 386         u32 old_val;
 387
 388         lockdep_assert_held(&dev_priv->irq_lock);
 389
 390         drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
 391
 392         if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
 393                 return;
 394
 395         old_val = I915_READ(GEN8_DE_PORT_IMR);
 396
 397         new_val = old_val;
 398         new_val &= ~interrupt_mask;
 399         new_val |= (~enabled_irq_mask & interrupt_mask);
 400
 401         if (new_val != old_val) {
 402                 I915_WRITE(GEN8_DE_PORT_IMR, new_val);
 403                 POSTING_READ(GEN8_DE_PORT_IMR);
 404         }
 405 }
 406
 407 /**
 408  * bdw_update_pipe_irq - update DE pipe interrupt
 409  * @dev_priv: driver private
 410  * @pipe: pipe whose interrupt to update
 411  * @interrupt_mask: mask of interrupt bits to update
 412  * @enabled_irq_mask: mask of interrupt bits to enable
 413  */
 414 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
 415                          enum pipe pipe,
 416                          u32 interrupt_mask,
 417                          u32 enabled_irq_mask)
 418 {
 419         u32 new_val;
 420
 421         lockdep_assert_held(&dev_priv->irq_lock);
 422
 423         drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
 424
 425         if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
 426                 return;
 427
 428         new_val = dev_priv->de_irq_mask[pipe];
 429         new_val &= ~interrupt_mask;
 430         new_val |= (~enabled_irq_mask & interrupt_mask);
 431
 432         if (new_val != dev_priv->de_irq_mask[pipe]) {
 433                 dev_priv->de_irq_mask[pipe] = new_val;
 434                 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
 435                 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
 436         }
 437 }
 438
 439 /**
 440  * ibx_display_interrupt_update - update SDEIMR
 441  * @dev_priv: driver private
 442  * @interrupt_mask: mask of interrupt bits to update
 443  * @enabled_irq_mask: mask of interrupt bits to enable
 444  */
 445 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
 446                                   u32 interrupt_mask,
 447                                   u32 enabled_irq_mask)
 448 {
 449         u32 sdeimr = I915_READ(SDEIMR);
 450         sdeimr &= ~interrupt_mask;
 451         sdeimr |= (~enabled_irq_mask & interrupt_mask);
 452
 453         drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
 454
 455         lockdep_assert_held(&dev_priv->irq_lock);
 456
 457         if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
 458                 return;
 459
 460         I915_WRITE(SDEIMR, sdeimr);
 461         POSTING_READ(SDEIMR);
 462 }
 463
 464 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
 465                               enum pipe pipe)
 466 {
 467         u32 status_mask = dev_priv->pipestat_irq_mask[pipe];
 468         u32 enable_mask = status_mask << 16;
 469
 470         lockdep_assert_held(&dev_priv->irq_lock);
 471
 472         if (INTEL_GEN(dev_priv) < 5)
 473                 goto out;
 474
 475         /*
 476          * On pipe A we don't support the PSR interrupt yet,
 477          * on pipe B and C the same bit MBZ.
 478          */
 479         if (drm_WARN_ON_ONCE(&dev_priv->drm,
 480                              status_mask & PIPE_A_PSR_STATUS_VLV))
 481                 return 0;
 482         /*
 483          * On pipe B and C we don't support the PSR interrupt yet, on pipe
 484          * A the same bit is for perf counters which we don't use either.
 485          */
 486         if (drm_WARN_ON_ONCE(&dev_priv->drm,
 487                              status_mask & PIPE_B_PSR_STATUS_VLV))
 488                 return 0;
 489
 490         enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
 491                          SPRITE0_FLIP_DONE_INT_EN_VLV |
 492                          SPRITE1_FLIP_DONE_INT_EN_VLV);
 493         if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
 494                 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
 495         if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
 496                 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
 497
 498 out:
 499         drm_WARN_ONCE(&dev_priv->drm,
 500                       enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 501                       status_mask & ~PIPESTAT_INT_STATUS_MASK,
 502                       "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
 503                       pipe_name(pipe), enable_mask, status_mask);
 504
 505         return enable_mask;
 506 }
 507
 508 void i915_enable_pipestat(struct drm_i915_private *dev_priv,
 509                           enum pipe pipe, u32 status_mask)
 510 {
 511         i915_reg_t reg = PIPESTAT(pipe);
 512         u32 enable_mask;
 513
 514         drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,
 515                       "pipe %c: status_mask=0x%x\n",
 516                       pipe_name(pipe), status_mask);
 517
 518         lockdep_assert_held(&dev_priv->irq_lock);
 519         drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv));
 520
 521         if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == status_mask)
 522                 return;
 523
 524         dev_priv->pipestat_irq_mask[pipe] |= status_mask;
 525         enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
 526
 527         I915_WRITE(reg, enable_mask | status_mask);
 528         POSTING_READ(reg);
 529 }
 530
 531 void i915_disable_pipestat(struct drm_i915_private *dev_priv,
 532                            enum pipe pipe, u32 status_mask)
 533 {
 534         i915_reg_t reg = PIPESTAT(pipe);
 535         u32 enable_mask;
 536
 537         drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,
 538                       "pipe %c: status_mask=0x%x\n",
 539                       pipe_name(pipe), status_mask);
 540
 541         lockdep_assert_held(&dev_priv->irq_lock);
 542         drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv));
 543
 544         if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == 0)
 545                 return;
 546
 547         dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
 548         enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
 549
 550         I915_WRITE(reg, enable_mask | status_mask);
 551         POSTING_READ(reg);
 552 }
 553
 554 static bool i915_has_asle(struct drm_i915_private *dev_priv)
 555 {
 556         if (!dev_priv->opregion.asle)
 557                 return false;
 558
 559         return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
 560 }
 561
 562 /**
 563  * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
 564  * @dev_priv: i915 device private
 565  */
 566 static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
 567 {
 568         if (!i915_has_asle(dev_priv))
 569                 return;
 570
 571         spin_lock_irq(&dev_priv->irq_lock);
 572
 573         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
 574         if (INTEL_GEN(dev_priv) >= 4)
 575                 i915_enable_pipestat(dev_priv, PIPE_A,
 576                                      PIPE_LEGACY_BLC_EVENT_STATUS);
 577
 578         spin_unlock_irq(&dev_priv->irq_lock);
 579 }
 580
 581 /*
 582  * This timing diagram depicts the video signal in and
 583  * around the vertical blanking period.
 584  *
 585  * Assumptions about the fictitious mode used in this example:
 586  *  vblank_start >= 3
 587  *  vsync_start = vblank_start + 1
 588  *  vsync_end = vblank_start + 2
 589  *  vtotal = vblank_start + 3
 590  *
 591  *           start of vblank:
 592  *           latch double buffered registers
 593  *           increment frame counter (ctg+)
 594  *           generate start of vblank interrupt (gen4+)
 595  *           |
 596  *           |          frame start:
 597  *           |          generate frame start interrupt (aka. vblank interrupt) (gmch)
 598  *           |          may be shifted forward 1-3 extra lines via PIPECONF
 599  *           |          |
 600  *           |          |  start of vsync:
 601  *           |          |  generate vsync interrupt
 602  *           |          |  |
 603  * ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx
 604  *       .   \hs/   .      \hs/          \hs/          \hs/   .      \hs/
 605  * ----va---> <-----------------vb--------------------> <--------va-------------
 606  *       |          |       <----vs----->                     |
 607  * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
 608  * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
 609  * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
 610  *       |          |                                         |
 611  *       last visible pixel                                   first visible pixel
 612  *                  |                                         increment frame counter (gen3/4)
 613  *                  pixel counter = vblank_start * htotal     pixel counter = 0 (gen3/4)
 614  *
 615  * x  = horizontal active
 616  * _  = horizontal blanking
 617  * hs = horizontal sync
 618  * va = vertical active
 619  * vb = vertical blanking
 620  * vs = vertical sync
 621  * vbs = vblank_start (number)
 622  *
 623  * Summary:
 624  * - most events happen at the start of horizontal sync
 625  * - frame start happens at the start of horizontal blank, 1-4 lines
 626  *   (depending on PIPECONF settings) after the start of vblank
 627  * - gen3/4 pixel and frame counter are synchronized with the start
 628  *   of horizontal active on the first line of vertical active
 629  */
 630
 631 /* Called from drm generic code, passed a 'crtc', which
 632  * we use as a pipe index
 633  */
 634 u32 i915_get_vblank_counter(struct drm_crtc *crtc)
 635 {
 636         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 637         struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)];
 638         const struct drm_display_mode *mode = &vblank->hwmode;
 639         enum pipe pipe = to_intel_crtc(crtc)->pipe;
 640         i915_reg_t high_frame, low_frame;
 641         u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
 642         unsigned long irqflags;
 643
 644         /*
 645          * On i965gm TV output the frame counter only works up to
 646          * the point when we enable the TV encoder. After that the
 647          * frame counter ceases to work and reads zero. We need a
 648          * vblank wait before enabling the TV encoder and so we
 649          * have to enable vblank interrupts while the frame counter
 650          * is still in a working state. However the core vblank code
 651          * does not like us returning non-zero frame counter values
 652          * when we've told it that we don't have a working frame
 653          * counter. Thus we must stop non-zero values leaking out.
 654          */
 655         if (!vblank->max_vblank_count)
 656                 return 0;
 657
 658         htotal = mode->crtc_htotal;
 659         hsync_start = mode->crtc_hsync_start;
 660         vbl_start = mode->crtc_vblank_start;
 661         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 662                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 663
 664         /* Convert to pixel count */
 665         vbl_start *= htotal;
 666
 667         /* Start of vblank event occurs at start of hsync */
 668         vbl_start -= htotal - hsync_start;
 669
 670         high_frame = PIPEFRAME(pipe);
 671         low_frame = PIPEFRAMEPIXEL(pipe);
 672
 673         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 674
 675         /*
 676          * High & low register fields aren't synchronized, so make sure
 677          * we get a low value that's stable across two reads of the high
 678          * register.
 679          */
 680         do {
 681                 high1 = intel_de_read_fw(dev_priv, high_frame) & PIPE_FRAME_HIGH_MASK;
 682                 low   = intel_de_read_fw(dev_priv, low_frame);
 683                 high2 = intel_de_read_fw(dev_priv, high_frame) & PIPE_FRAME_HIGH_MASK;
 684         } while (high1 != high2);
 685
 686         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 687
 688         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 689         pixel = low & PIPE_PIXEL_MASK;
 690         low >>= PIPE_FRAME_LOW_SHIFT;
 691
 692         /*
 693          * The frame counter increments at beginning of active.
 694          * Cook up a vblank counter by also checking the pixel
 695          * counter against vblank start.
 696          */
 697         return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
 698 }
 699
 700 u32 g4x_get_vblank_counter(struct drm_crtc *crtc)
 701 {
 702         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 703         enum pipe pipe = to_intel_crtc(crtc)->pipe;
 704
 705         return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
 706 }
 707
 708 /*
 709  * On certain encoders on certain platforms, pipe
 710  * scanline register will not work to get the scanline,
 711  * since the timings are driven from the PORT or issues
 712  * with scanline register updates.
 713  * This function will use Framestamp and current
 714  * timestamp registers to calculate the scanline.
 715  */
 716 static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)
 717 {
 718         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 719         struct drm_vblank_crtc *vblank =
 720                 &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
 721         const struct drm_display_mode *mode = &vblank->hwmode;
 722         u32 vblank_start = mode->crtc_vblank_start;
 723         u32 vtotal = mode->crtc_vtotal;
 724         u32 htotal = mode->crtc_htotal;
 725         u32 clock = mode->crtc_clock;
 726         u32 scanline, scan_prev_time, scan_curr_time, scan_post_time;
 727
 728         /*
 729          * To avoid the race condition where we might cross into the
 730          * next vblank just between the PIPE_FRMTMSTMP and TIMESTAMP_CTR
 731          * reads. We make sure we read PIPE_FRMTMSTMP and TIMESTAMP_CTR
 732          * during the same frame.
 733          */
 734         do {
 735                 /*
 736                  * This field provides read back of the display
 737                  * pipe frame time stamp. The time stamp value
 738                  * is sampled at every start of vertical blank.
 739                  */
 740                 scan_prev_time = intel_de_read_fw(dev_priv,
 741                                                   PIPE_FRMTMSTMP(crtc->pipe));
 742
 743                 /*
 744                  * The TIMESTAMP_CTR register has the current
 745                  * time stamp value.
 746                  */
 747                 scan_curr_time = intel_de_read_fw(dev_priv, IVB_TIMESTAMP_CTR);
 748
 749                 scan_post_time = intel_de_read_fw(dev_priv,
 750                                                   PIPE_FRMTMSTMP(crtc->pipe));
 751         } while (scan_post_time != scan_prev_time);
 752
 753         scanline = div_u64(mul_u32_u32(scan_curr_time - scan_prev_time,
 754                                         clock), 1000 * htotal);
 755         scanline = min(scanline, vtotal - 1);
 756         scanline = (scanline + vblank_start) % vtotal;
 757
 758         return scanline;
 759 }
 760
 761 /*
 762  * intel_de_read_fw(), only for fast reads of display block, no need for
 763  * forcewake etc.
 764  */
 765 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
 766 {
 767         struct drm_device *dev = crtc->base.dev;
 768         struct drm_i915_private *dev_priv = to_i915(dev);
 769         const struct drm_display_mode *mode;
 770         struct drm_vblank_crtc *vblank;
 771         enum pipe pipe = crtc->pipe;
 772         int position, vtotal;
 773
 774         if (!crtc->active)
 775                 return -1;
 776
 777         vblank = &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
 778         mode = &vblank->hwmode;
 779
 780         if (crtc->mode_flags & I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP)
 781                 return __intel_get_crtc_scanline_from_timestamp(crtc);
 782
 783         vtotal = mode->crtc_vtotal;
 784         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 785                 vtotal /= 2;
 786
 787         if (IS_GEN(dev_priv, 2))
 788                 position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
 789         else
 790                 position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
 791
 792         /*
 793          * On HSW, the DSL reg (0x70000) appears to return 0 if we
 794          * read it just before the start of vblank.  So try it again
 795          * so we don't accidentally end up spanning a vblank frame
 796          * increment, causing the pipe_update_end() code to squak at us.
 797          *
 798          * The nature of this problem means we can't simply check the ISR
 799          * bit and return the vblank start value; nor can we use the scanline
 800          * debug register in the transcoder as it appears to have the same
 801          * problem.  We may need to extend this to include other platforms,
 802          * but so far testing only shows the problem on HSW.
 803          */
 804         if (HAS_DDI(dev_priv) && !position) {
 805                 int i, temp;
 806
 807                 for (i = 0; i < 100; i++) {
 808                         udelay(1);
 809                         temp = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
 810                         if (temp != position) {
 811                                 position = temp;
 812                                 break;
 813                         }
 814                 }
 815         }
 816
 817         /*
 818          * See update_scanline_offset() for the details on the
 819          * scanline_offset adjustment.
 820          */
 821         return (position + crtc->scanline_offset) % vtotal;
 822 }
 823
 824 static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
 825                                      bool in_vblank_irq,
 826                                      int *vpos, int *hpos,
 827                                      ktime_t *stime, ktime_t *etime,
 828                                      const struct drm_display_mode *mode)
 829 {
 830         struct drm_device *dev = _crtc->dev;
 831         struct drm_i915_private *dev_priv = to_i915(dev);
 832         struct intel_crtc *crtc = to_intel_crtc(_crtc);
 833         enum pipe pipe = crtc->pipe;
 834         int position;
 835         int vbl_start, vbl_end, hsync_start, htotal, vtotal;
 836         unsigned long irqflags;
 837         bool use_scanline_counter = INTEL_GEN(dev_priv) >= 5 ||
 838                 IS_G4X(dev_priv) || IS_GEN(dev_priv, 2) ||
 839                 crtc->mode_flags & I915_MODE_FLAG_USE_SCANLINE_COUNTER;
 840
 841         if (drm_WARN_ON(&dev_priv->drm, !mode->crtc_clock)) {
 842                 drm_dbg(&dev_priv->drm,
 843                         "trying to get scanoutpos for disabled "
 844                         "pipe %c\n", pipe_name(pipe));
 845                 return false;
 846         }
 847
 848         htotal = mode->crtc_htotal;
 849         hsync_start = mode->crtc_hsync_start;
 850         vtotal = mode->crtc_vtotal;
 851         vbl_start = mode->crtc_vblank_start;
 852         vbl_end = mode->crtc_vblank_end;
 853
 854         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 855                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 856                 vbl_end /= 2;
 857                 vtotal /= 2;
 858         }
 859
 860         /*
 861          * Lock uncore.lock, as we will do multiple timing critical raw
 862          * register reads, potentially with preemption disabled, so the
 863          * following code must not block on uncore.lock.
 864          */
 865         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 866
 867         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 868
 869         /* Get optional system timestamp before query. */
 870         if (stime)
 871                 *stime = ktime_get();
 872
 873         if (use_scanline_counter) {
 874                 /* No obvious pixelcount register. Only query vertical
 875                  * scanout position from Display scan line register.
 876                  */
 877                 position = __intel_get_crtc_scanline(crtc);
 878         } else {
 879                 /* Have access to pixelcount since start of frame.
 880                  * We can split this into vertical and horizontal
 881                  * scanout position.
 882                  */
 883                 position = (intel_de_read_fw(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 884
 885                 /* convert to pixel counts */
 886                 vbl_start *= htotal;
 887                 vbl_end *= htotal;
 888                 vtotal *= htotal;
 889
 890                 /*
 891                  * In interlaced modes, the pixel counter counts all pixels,
 892                  * so one field will have htotal more pixels. In order to avoid
 893                  * the reported position from jumping backwards when the pixel
 894                  * counter is beyond the length of the shorter field, just
 895                  * clamp the position the length of the shorter field. This
 896                  * matches how the scanline counter based position works since
 897                  * the scanline counter doesn't count the two half lines.
 898                  */
 899                 if (position >= vtotal)
 900                         position = vtotal - 1;
 901
 902                 /*
 903                  * Start of vblank interrupt is triggered at start of hsync,
 904                  * just prior to the first active line of vblank. However we
 905                  * consider lines to start at the leading edge of horizontal
 906                  * active. So, should we get here before we've crossed into
 907                  * the horizontal active of the first line in vblank, we would
 908                  * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
 909                  * always add htotal-hsync_start to the current pixel position.
 910                  */
 911                 position = (position + htotal - hsync_start) % vtotal;
 912         }
 913
 914         /* Get optional system timestamp after query. */
 915         if (etime)
 916                 *etime = ktime_get();
 917
 918         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 919
 920         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 921
 922         /*
 923          * While in vblank, position will be negative
 924          * counting up towards 0 at vbl_end. And outside
 925          * vblank, position will be positive counting
 926          * up since vbl_end.
 927          */
 928         if (position >= vbl_start)
 929                 position -= vbl_end;
 930         else
 931                 position += vtotal - vbl_end;
 932
 933         if (use_scanline_counter) {
 934                 *vpos = position;
 935                 *hpos = 0;
 936         } else {
 937                 *vpos = position / htotal;
 938                 *hpos = position - (*vpos * htotal);
 939         }
 940
 941         return true;
 942 }
 943
 944 bool intel_crtc_get_vblank_timestamp(struct drm_crtc *crtc, int *max_error,
 945                                      ktime_t *vblank_time, bool in_vblank_irq)
 946 {
 947         return drm_crtc_vblank_helper_get_vblank_timestamp_internal(
 948                 crtc, max_error, vblank_time, in_vblank_irq,
 949                 i915_get_crtc_scanoutpos);
 950 }
 951
 952 int intel_get_crtc_scanline(struct intel_crtc *crtc)
 953 {
 954         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 955         unsigned long irqflags;
 956         int position;
 957
 958         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 959         position = __intel_get_crtc_scanline(crtc);
 960         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 961
 962         return position;
 963 }
 964
 965 /**
 966  * ivb_parity_work - Workqueue called when a parity error interrupt
 967  * occurred.
 968  * @work: workqueue struct
 969  *
 970  * Doesn't actually do anything except notify userspace. As a consequence of
 971  * this event, userspace should try to remap the bad rows since statistically
 972  * it is likely the same row is more likely to go bad again.
 973  */
 974 static void ivb_parity_work(struct work_struct *work)
 975 {
 976         struct drm_i915_private *dev_priv =
 977                 container_of(work, typeof(*dev_priv), l3_parity.error_work);
 978         struct intel_gt *gt = &dev_priv->gt;
 979         u32 error_status, row, bank, subbank;
 980         char *parity_event[6];
 981         u32 misccpctl;
 982         u8 slice = 0;
 983
 984         /* We must turn off DOP level clock gating to access the L3 registers.
 985          * In order to prevent a get/put style interface, acquire struct mutex
 986          * any time we access those registers.
 987          */
 988         mutex_lock(&dev_priv->drm.struct_mutex);
 989
 990         /* If we've screwed up tracking, just let the interrupt fire again */
 991         if (drm_WARN_ON(&dev_priv->drm, !dev_priv->l3_parity.which_slice))
 992                 goto out;
 993
 994         misccpctl = I915_READ(GEN7_MISCCPCTL);
 995         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
 996         POSTING_READ(GEN7_MISCCPCTL);
 997
 998         while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
 999                 i915_reg_t reg;
1000
1001                 slice--;
1002                 if (drm_WARN_ON_ONCE(&dev_priv->drm,
1003                                      slice >= NUM_L3_SLICES(dev_priv)))
1004                         break;
1005
1006                 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1007
1008                 reg = GEN7_L3CDERRST1(slice);
1009
1010                 error_status = I915_READ(reg);
1011                 row = GEN7_PARITY_ERROR_ROW(error_status);
1012                 bank = GEN7_PARITY_ERROR_BANK(error_status);
1013                 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1014
1015                 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1016                 POSTING_READ(reg);
1017
1018                 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1019                 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1020                 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1021                 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1022                 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1023                 parity_event[5] = NULL;
1024
1025                 kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj,
1026                                    KOBJ_CHANGE, parity_event);
1027
1028                 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1029                           slice, row, bank, subbank);
1030
1031                 kfree(parity_event[4]);
1032                 kfree(parity_event[3]);
1033                 kfree(parity_event[2]);
1034                 kfree(parity_event[1]);
1035         }
1036
1037         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1038
1039 out:
1040         drm_WARN_ON(&dev_priv->drm, dev_priv->l3_parity.which_slice);
1041         spin_lock_irq(&gt->irq_lock);
1042         gen5_gt_enable_irq(gt, GT_PARITY_ERROR(dev_priv));
1043         spin_unlock_irq(&gt->irq_lock);
1044
1045         mutex_unlock(&dev_priv->drm.struct_mutex);
1046 }
1047
1048 static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1049 {
1050         switch (pin) {
1051         case HPD_PORT_C:
1052                 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC1);
1053         case HPD_PORT_D:
1054                 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC2);
1055         case HPD_PORT_E:
1056                 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC3);
1057         case HPD_PORT_F:
1058                 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC4);
1059         default:
1060                 return false;
1061         }
1062 }
1063
1064 static bool gen12_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1065 {
1066         switch (pin) {
1067         case HPD_PORT_D:
1068                 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC1);
1069         case HPD_PORT_E:
1070                 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC2);
1071         case HPD_PORT_F:
1072                 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC3);
1073         case HPD_PORT_G:
1074                 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC4);
1075         case HPD_PORT_H:
1076                 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC5);
1077         case HPD_PORT_I:
1078                 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC6);
1079         default:
1080                 return false;
1081         }
1082 }
1083
1084 static bool bxt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1085 {
1086         switch (pin) {
1087         case HPD_PORT_A:
1088                 return val & PORTA_HOTPLUG_LONG_DETECT;
1089         case HPD_PORT_B:
1090                 return val & PORTB_HOTPLUG_LONG_DETECT;
1091         case HPD_PORT_C:
1092                 return val & PORTC_HOTPLUG_LONG_DETECT;
1093         default:
1094                 return false;
1095         }
1096 }
1097
1098 static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1099 {
1100         switch (pin) {
1101         case HPD_PORT_A:
1102                 return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_A);
1103         case HPD_PORT_B:
1104                 return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_B);
1105         case HPD_PORT_C:
1106                 return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_C);
1107         default:
1108                 return false;
1109         }
1110 }
1111
1112 static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1113 {
1114         switch (pin) {
1115         case HPD_PORT_C:
1116                 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
1117         case HPD_PORT_D:
1118                 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
1119         case HPD_PORT_E:
1120                 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
1121         case HPD_PORT_F:
1122                 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
1123         default:
1124                 return false;
1125         }
1126 }
1127
1128 static bool tgp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1129 {
1130         switch (pin) {
1131         case HPD_PORT_D:
1132                 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
1133         case HPD_PORT_E:
1134                 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
1135         case HPD_PORT_F:
1136                 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
1137         case HPD_PORT_G:
1138                 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
1139         case HPD_PORT_H:
1140                 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC5);
1141         case HPD_PORT_I:
1142                 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC6);
1143         default:
1144                 return false;
1145         }
1146 }
1147
1148 static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val)
1149 {
1150         switch (pin) {
1151         case HPD_PORT_E:
1152                 return val & PORTE_HOTPLUG_LONG_DETECT;
1153         default:
1154                 return false;
1155         }
1156 }
1157
1158 static bool spt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1159 {
1160         switch (pin) {
1161         case HPD_PORT_A:
1162                 return val & PORTA_HOTPLUG_LONG_DETECT;
1163         case HPD_PORT_B:
1164                 return val & PORTB_HOTPLUG_LONG_DETECT;
1165         case HPD_PORT_C:
1166                 return val & PORTC_HOTPLUG_LONG_DETECT;
1167         case HPD_PORT_D:
1168                 return val & PORTD_HOTPLUG_LONG_DETECT;
1169         default:
1170                 return false;
1171         }
1172 }
1173
1174 static bool ilk_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1175 {
1176         switch (pin) {
1177         case HPD_PORT_A:
1178                 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
1179         default:
1180                 return false;
1181         }
1182 }
1183
1184 static bool pch_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1185 {
1186         switch (pin) {
1187         case HPD_PORT_B:
1188                 return val & PORTB_HOTPLUG_LONG_DETECT;
1189         case HPD_PORT_C:
1190                 return val & PORTC_HOTPLUG_LONG_DETECT;
1191         case HPD_PORT_D:
1192                 return val & PORTD_HOTPLUG_LONG_DETECT;
1193         default:
1194                 return false;
1195         }
1196 }
1197
1198 static bool i9xx_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1199 {
1200         switch (pin) {
1201         case HPD_PORT_B:
1202                 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1203         case HPD_PORT_C:
1204                 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1205         case HPD_PORT_D:
1206                 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1207         default:
1208                 return false;
1209         }
1210 }
1211
1212 /*
1213  * Get a bit mask of pins that have triggered, and which ones may be long.
1214  * This can be called multiple times with the same masks to accumulate
1215  * hotplug detection results from several registers.
1216  *
1217  * Note that the caller is expected to zero out the masks initially.
1218  */
1219 static void intel_get_hpd_pins(struct drm_i915_private *dev_priv,
1220                                u32 *pin_mask, u32 *long_mask,
1221                                u32 hotplug_trigger, u32 dig_hotplug_reg,
1222                                const u32 hpd[HPD_NUM_PINS],
1223                                bool long_pulse_detect(enum hpd_pin pin, u32 val))
1224 {
1225         enum hpd_pin pin;
1226
1227         BUILD_BUG_ON(BITS_PER_TYPE(*pin_mask) < HPD_NUM_PINS);
1228
1229         for_each_hpd_pin(pin) {
1230                 if ((hpd[pin] & hotplug_trigger) == 0)
1231                         continue;
1232
1233                 *pin_mask |= BIT(pin);
1234
1235                 if (long_pulse_detect(pin, dig_hotplug_reg))
1236                         *long_mask |= BIT(pin);
1237         }
1238
1239         drm_dbg(&dev_priv->drm,
1240                 "hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x, long 0x%08x\n",
1241                 hotplug_trigger, dig_hotplug_reg, *pin_mask, *long_mask);
1242
1243 }
1244
1245 static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
1246 {
1247         wake_up_all(&dev_priv->gmbus_wait_queue);
1248 }
1249
1250 static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
1251 {
1252         wake_up_all(&dev_priv->gmbus_wait_queue);
1253 }
1254
1255 #if defined(CONFIG_DEBUG_FS)
1256 static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1257                                          enum pipe pipe,
1258                                          u32 crc0, u32 crc1,
1259                                          u32 crc2, u32 crc3,
1260                                          u32 crc4)
1261 {
1262         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1263         struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
1264         u32 crcs[5] = { crc0, crc1, crc2, crc3, crc4 };
1265
1266         trace_intel_pipe_crc(crtc, crcs);
1267
1268         spin_lock(&pipe_crc->lock);
1269         /*
1270          * For some not yet identified reason, the first CRC is
1271          * bonkers. So let's just wait for the next vblank and read
1272          * out the buggy result.
1273          *
1274          * On GEN8+ sometimes the second CRC is bonkers as well, so
1275          * don't trust that one either.
1276          */
1277         if (pipe_crc->skipped <= 0 ||
1278             (INTEL_GEN(dev_priv) >= 8 && pipe_crc->skipped == 1)) {
1279                 pipe_crc->skipped++;
1280                 spin_unlock(&pipe_crc->lock);
1281                 return;
1282         }
1283         spin_unlock(&pipe_crc->lock);
1284
1285         drm_crtc_add_crc_entry(&crtc->base, true,
1286                                 drm_crtc_accurate_vblank_count(&crtc->base),
1287                                 crcs);
1288 }
1289 #else
1290 static inline void
1291 display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1292                              enum pipe pipe,
1293                              u32 crc0, u32 crc1,
1294                              u32 crc2, u32 crc3,
1295                              u32 crc4) {}
1296 #endif
1297
1298
1299 static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1300                                      enum pipe pipe)
1301 {
1302         display_pipe_crc_irq_handler(dev_priv, pipe,
1303                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1304                                      0, 0, 0, 0);
1305 }
1306
1307 static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1308                                      enum pipe pipe)
1309 {
1310         display_pipe_crc_irq_handler(dev_priv, pipe,
1311                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1312                                      I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1313                                      I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1314                                      I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1315                                      I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1316 }
1317
1318 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1319                                       enum pipe pipe)
1320 {
1321         u32 res1, res2;
1322
1323         if (INTEL_GEN(dev_priv) >= 3)
1324                 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1325         else
1326                 res1 = 0;
1327
1328         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1329                 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1330         else
1331                 res2 = 0;
1332
1333         display_pipe_crc_irq_handler(dev_priv, pipe,
1334                                      I915_READ(PIPE_CRC_RES_RED(pipe)),
1335                                      I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1336                                      I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1337                                      res1, res2);
1338 }
1339
1340 static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
1341 {
1342         enum pipe pipe;
1343
1344         for_each_pipe(dev_priv, pipe) {
1345                 I915_WRITE(PIPESTAT(pipe),
1346                            PIPESTAT_INT_STATUS_MASK |
1347                            PIPE_FIFO_UNDERRUN_STATUS);
1348
1349                 dev_priv->pipestat_irq_mask[pipe] = 0;
1350         }
1351 }
1352
1353 static void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,
1354                                   u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1355 {
1356         enum pipe pipe;
1357
1358         spin_lock(&dev_priv->irq_lock);
1359
1360         if (!dev_priv->display_irqs_enabled) {
1361                 spin_unlock(&dev_priv->irq_lock);
1362                 return;
1363         }
1364
1365         for_each_pipe(dev_priv, pipe) {
1366                 i915_reg_t reg;
1367                 u32 status_mask, enable_mask, iir_bit = 0;
1368
1369                 /*
1370                  * PIPESTAT bits get signalled even when the interrupt is
1371                  * disabled with the mask bits, and some of the status bits do
1372                  * not generate interrupts at all (like the underrun bit). Hence
1373                  * we need to be careful that we only handle what we want to
1374                  * handle.
1375                  */
1376
1377                 /* fifo underruns are filterered in the underrun handler. */
1378                 status_mask = PIPE_FIFO_UNDERRUN_STATUS;
1379
1380                 switch (pipe) {
1381                 default:
1382                 case PIPE_A:
1383                         iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1384                         break;
1385                 case PIPE_B:
1386                         iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1387                         break;
1388                 case PIPE_C:
1389                         iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1390                         break;
1391                 }
1392                 if (iir & iir_bit)
1393                         status_mask |= dev_priv->pipestat_irq_mask[pipe];
1394
1395                 if (!status_mask)
1396                         continue;
1397
1398                 reg = PIPESTAT(pipe);
1399                 pipe_stats[pipe] = I915_READ(reg) & status_mask;
1400                 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
1401
1402                 /*
1403                  * Clear the PIPE*STAT regs before the IIR
1404                  *
1405                  * Toggle the enable bits to make sure we get an
1406                  * edge in the ISR pipe event bit if we don't clear
1407                  * all the enabled status bits. Otherwise the edge
1408                  * triggered IIR on i965/g4x wouldn't notice that
1409                  * an interrupt is still pending.
1410                  */
1411                 if (pipe_stats[pipe]) {
1412                         I915_WRITE(reg, pipe_stats[pipe]);
1413                         I915_WRITE(reg, enable_mask);
1414                 }
1415         }
1416         spin_unlock(&dev_priv->irq_lock);
1417 }
1418
1419 static void i8xx_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1420                                       u16 iir, u32 pipe_stats[I915_MAX_PIPES])
1421 {
1422         enum pipe pipe;
1423
1424         for_each_pipe(dev_priv, pipe) {
1425                 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1426                         intel_handle_vblank(dev_priv, pipe);
1427
1428                 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1429                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1430
1431                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1432                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1433         }
1434 }
1435
1436 static void i915_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1437                                       u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1438 {
1439         bool blc_event = false;
1440         enum pipe pipe;
1441
1442         for_each_pipe(dev_priv, pipe) {
1443                 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1444                         intel_handle_vblank(dev_priv, pipe);
1445
1446                 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1447                         blc_event = true;
1448
1449                 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1450                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1451
1452                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1453                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1454         }
1455
1456         if (blc_event || (iir & I915_ASLE_INTERRUPT))
1457                 intel_opregion_asle_intr(dev_priv);
1458 }
1459
1460 static void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1461                                       u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1462 {
1463         bool blc_event = false;
1464         enum pipe pipe;
1465
1466         for_each_pipe(dev_priv, pipe) {
1467                 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1468                         intel_handle_vblank(dev_priv, pipe);
1469
1470                 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1471                         blc_event = true;
1472
1473                 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1474                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1475
1476                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1477                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1478         }
1479
1480         if (blc_event || (iir & I915_ASLE_INTERRUPT))
1481                 intel_opregion_asle_intr(dev_priv);
1482
1483         if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1484                 gmbus_irq_handler(dev_priv);
1485 }
1486
1487 static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1488                                             u32 pipe_stats[I915_MAX_PIPES])
1489 {
1490         enum pipe pipe;
1491
1492         for_each_pipe(dev_priv, pipe) {
1493                 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1494                         intel_handle_vblank(dev_priv, pipe);
1495
1496                 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1497                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1498
1499                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1500                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1501         }
1502
1503         if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1504                 gmbus_irq_handler(dev_priv);
1505 }
1506
1507 static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
1508 {
1509         u32 hotplug_status = 0, hotplug_status_mask;
1510         int i;
1511
1512         if (IS_G4X(dev_priv) ||
1513             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1514                 hotplug_status_mask = HOTPLUG_INT_STATUS_G4X |
1515                         DP_AUX_CHANNEL_MASK_INT_STATUS_G4X;
1516         else
1517                 hotplug_status_mask = HOTPLUG_INT_STATUS_I915;
1518
1519         /*
1520          * We absolutely have to clear all the pending interrupt
1521          * bits in PORT_HOTPLUG_STAT. Otherwise the ISR port
1522          * interrupt bit won't have an edge, and the i965/g4x
1523          * edge triggered IIR will not notice that an interrupt
1524          * is still pending. We can't use PORT_HOTPLUG_EN to
1525          * guarantee the edge as the act of toggling the enable
1526          * bits can itself generate a new hotplug interrupt :(
1527          */
1528         for (i = 0; i < 10; i++) {
1529                 u32 tmp = I915_READ(PORT_HOTPLUG_STAT) & hotplug_status_mask;
1530
1531                 if (tmp == 0)
1532                         return hotplug_status;
1533
1534                 hotplug_status |= tmp;
1535                 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1536         }
1537
1538         drm_WARN_ONCE(&dev_priv->drm, 1,
1539                       "PORT_HOTPLUG_STAT did not clear (0x%08x)\n",
1540                       I915_READ(PORT_HOTPLUG_STAT));
1541
1542         return hotplug_status;
1543 }
1544
1545 static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1546                                  u32 hotplug_status)
1547 {
1548         u32 pin_mask = 0, long_mask = 0;
1549         u32 hotplug_trigger;
1550
1551         if (IS_G4X(dev_priv) ||
1552             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1553                 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1554         else
1555                 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1556
1557         if (hotplug_trigger) {
1558                 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1559                                    hotplug_trigger, hotplug_trigger,
1560                                    dev_priv->hotplug.hpd,
1561                                    i9xx_port_hotplug_long_detect);
1562
1563                 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1564         }
1565
1566         if ((IS_G4X(dev_priv) ||
1567              IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1568             hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1569                 dp_aux_irq_handler(dev_priv);
1570 }
1571
1572 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1573 {
1574         struct drm_i915_private *dev_priv = arg;
1575         irqreturn_t ret = IRQ_NONE;
1576
1577         if (!intel_irqs_enabled(dev_priv))
1578                 return IRQ_NONE;
1579
1580         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1581         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1582
1583         do {
1584                 u32 iir, gt_iir, pm_iir;
1585                 u32 pipe_stats[I915_MAX_PIPES] = {};
1586                 u32 hotplug_status = 0;
1587                 u32 ier = 0;
1588
1589                 gt_iir = I915_READ(GTIIR);
1590                 pm_iir = I915_READ(GEN6_PMIIR);
1591                 iir = I915_READ(VLV_IIR);
1592
1593                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1594                         break;
1595
1596                 ret = IRQ_HANDLED;
1597
1598                 /*
1599                  * Theory on interrupt generation, based on empirical evidence:
1600                  *
1601                  * x = ((VLV_IIR & VLV_IER) ||
1602                  *      (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
1603                  *       (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
1604                  *
1605                  * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1606                  * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
1607                  * guarantee the CPU interrupt will be raised again even if we
1608                  * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
1609                  * bits this time around.
1610                  */
1611                 I915_WRITE(VLV_MASTER_IER, 0);
1612                 ier = I915_READ(VLV_IER);
1613                 I915_WRITE(VLV_IER, 0);
1614
1615                 if (gt_iir)
1616                         I915_WRITE(GTIIR, gt_iir);
1617                 if (pm_iir)
1618                         I915_WRITE(GEN6_PMIIR, pm_iir);
1619
1620                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1621                         hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1622
1623                 /* Call regardless, as some status bits might not be
1624                  * signalled in iir */
1625                 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1626
1627                 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
1628                            I915_LPE_PIPE_B_INTERRUPT))
1629                         intel_lpe_audio_irq_handler(dev_priv);
1630
1631                 /*
1632                  * VLV_IIR is single buffered, and reflects the level
1633                  * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1634                  */
1635                 if (iir)
1636                         I915_WRITE(VLV_IIR, iir);
1637
1638                 I915_WRITE(VLV_IER, ier);
1639                 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1640
1641                 if (gt_iir)
1642                         gen6_gt_irq_handler(&dev_priv->gt, gt_iir);
1643                 if (pm_iir)
1644                         gen6_rps_irq_handler(&dev_priv->gt.rps, pm_iir);
1645
1646                 if (hotplug_status)
1647                         i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1648
1649                 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1650         } while (0);
1651
1652         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1653
1654         return ret;
1655 }
1656
1657 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1658 {
1659         struct drm_i915_private *dev_priv = arg;
1660         irqreturn_t ret = IRQ_NONE;
1661
1662         if (!intel_irqs_enabled(dev_priv))
1663                 return IRQ_NONE;
1664
1665         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1666         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1667
1668         do {
1669                 u32 master_ctl, iir;
1670                 u32 pipe_stats[I915_MAX_PIPES] = {};
1671                 u32 hotplug_status = 0;
1672                 u32 ier = 0;
1673
1674                 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1675                 iir = I915_READ(VLV_IIR);
1676
1677                 if (master_ctl == 0 && iir == 0)
1678                         break;
1679
1680                 ret = IRQ_HANDLED;
1681
1682                 /*
1683                  * Theory on interrupt generation, based on empirical evidence:
1684                  *
1685                  * x = ((VLV_IIR & VLV_IER) ||
1686                  *      ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
1687                  *       (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
1688                  *
1689                  * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1690                  * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
1691                  * guarantee the CPU interrupt will be raised again even if we
1692                  * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
1693                  * bits this time around.
1694                  */
1695                 I915_WRITE(GEN8_MASTER_IRQ, 0);
1696                 ier = I915_READ(VLV_IER);
1697                 I915_WRITE(VLV_IER, 0);
1698
1699                 gen8_gt_irq_handler(&dev_priv->gt, master_ctl);
1700
1701                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1702                         hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1703
1704                 /* Call regardless, as some status bits might not be
1705                  * signalled in iir */
1706                 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1707
1708                 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
1709                            I915_LPE_PIPE_B_INTERRUPT |
1710                            I915_LPE_PIPE_C_INTERRUPT))
1711                         intel_lpe_audio_irq_handler(dev_priv);
1712
1713                 /*
1714                  * VLV_IIR is single buffered, and reflects the level
1715                  * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1716                  */
1717                 if (iir)
1718                         I915_WRITE(VLV_IIR, iir);
1719
1720                 I915_WRITE(VLV_IER, ier);
1721                 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
1722
1723                 if (hotplug_status)
1724                         i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1725
1726                 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1727         } while (0);
1728
1729         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1730
1731         return ret;
1732 }
1733
1734 static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1735                                 u32 hotplug_trigger)
1736 {
1737         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
1738
1739         /*
1740          * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
1741          * unless we touch the hotplug register, even if hotplug_trigger is
1742          * zero. Not acking leads to "The master control interrupt lied (SDE)!"
1743          * errors.
1744          */
1745         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1746         if (!hotplug_trigger) {
1747                 u32 mask = PORTA_HOTPLUG_STATUS_MASK |
1748                         PORTD_HOTPLUG_STATUS_MASK |
1749                         PORTC_HOTPLUG_STATUS_MASK |
1750                         PORTB_HOTPLUG_STATUS_MASK;
1751                 dig_hotplug_reg &= ~mask;
1752         }
1753
1754         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1755         if (!hotplug_trigger)
1756                 return;
1757
1758         intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1759                            hotplug_trigger, dig_hotplug_reg,
1760                            dev_priv->hotplug.pch_hpd,
1761                            pch_port_hotplug_long_detect);
1762
1763         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1764 }
1765
1766 static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1767 {
1768         enum pipe pipe;
1769         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1770
1771         ibx_hpd_irq_handler(dev_priv, hotplug_trigger);
1772
1773         if (pch_iir & SDE_AUDIO_POWER_MASK) {
1774                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1775                                SDE_AUDIO_POWER_SHIFT);
1776                 drm_dbg(&dev_priv->drm, "PCH audio power change on port %d\n",
1777                         port_name(port));
1778         }
1779
1780         if (pch_iir & SDE_AUX_MASK)
1781                 dp_aux_irq_handler(dev_priv);
1782
1783         if (pch_iir & SDE_GMBUS)
1784                 gmbus_irq_handler(dev_priv);
1785
1786         if (pch_iir & SDE_AUDIO_HDCP_MASK)
1787                 drm_dbg(&dev_priv->drm, "PCH HDCP audio interrupt\n");
1788
1789         if (pch_iir & SDE_AUDIO_TRANS_MASK)
1790                 drm_dbg(&dev_priv->drm, "PCH transcoder audio interrupt\n");
1791
1792         if (pch_iir & SDE_POISON)
1793                 drm_err(&dev_priv->drm, "PCH poison interrupt\n");
1794
1795         if (pch_iir & SDE_FDI_MASK) {
1796                 for_each_pipe(dev_priv, pipe)
1797                         drm_dbg(&dev_priv->drm, "  pipe %c FDI IIR: 0x%08x\n",
1798                                 pipe_name(pipe),
1799                                 I915_READ(FDI_RX_IIR(pipe)));
1800         }
1801
1802         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1803                 drm_dbg(&dev_priv->drm, "PCH transcoder CRC done interrupt\n");
1804
1805         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1806                 drm_dbg(&dev_priv->drm,
1807                         "PCH transcoder CRC error interrupt\n");
1808
1809         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1810                 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A);
1811
1812         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1813                 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B);
1814 }
1815
1816 static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
1817 {
1818         u32 err_int = I915_READ(GEN7_ERR_INT);
1819         enum pipe pipe;
1820
1821         if (err_int & ERR_INT_POISON)
1822                 drm_err(&dev_priv->drm, "Poison interrupt\n");
1823
1824         for_each_pipe(dev_priv, pipe) {
1825                 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
1826                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1827
1828                 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1829                         if (IS_IVYBRIDGE(dev_priv))
1830                                 ivb_pipe_crc_irq_handler(dev_priv, pipe);
1831                         else
1832                                 hsw_pipe_crc_irq_handler(dev_priv, pipe);
1833                 }
1834         }
1835
1836         I915_WRITE(GEN7_ERR_INT, err_int);
1837 }
1838
1839 static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
1840 {
1841         u32 serr_int = I915_READ(SERR_INT);
1842         enum pipe pipe;
1843
1844         if (serr_int & SERR_INT_POISON)
1845                 drm_err(&dev_priv->drm, "PCH poison interrupt\n");
1846
1847         for_each_pipe(dev_priv, pipe)
1848                 if (serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pipe))
1849                         intel_pch_fifo_underrun_irq_handler(dev_priv, pipe);
1850
1851         I915_WRITE(SERR_INT, serr_int);
1852 }
1853
1854 static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1855 {
1856         enum pipe pipe;
1857         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1858
1859         ibx_hpd_irq_handler(dev_priv, hotplug_trigger);
1860
1861         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1862                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1863                                SDE_AUDIO_POWER_SHIFT_CPT);
1864                 drm_dbg(&dev_priv->drm, "PCH audio power change on port %c\n",
1865                         port_name(port));
1866         }
1867
1868         if (pch_iir & SDE_AUX_MASK_CPT)
1869                 dp_aux_irq_handler(dev_priv);
1870
1871         if (pch_iir & SDE_GMBUS_CPT)
1872                 gmbus_irq_handler(dev_priv);
1873
1874         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1875                 drm_dbg(&dev_priv->drm, "Audio CP request interrupt\n");
1876
1877         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1878                 drm_dbg(&dev_priv->drm, "Audio CP change interrupt\n");
1879
1880         if (pch_iir & SDE_FDI_MASK_CPT) {
1881                 for_each_pipe(dev_priv, pipe)
1882                         drm_dbg(&dev_priv->drm, "  pipe %c FDI IIR: 0x%08x\n",
1883                                 pipe_name(pipe),
1884                                 I915_READ(FDI_RX_IIR(pipe)));
1885         }
1886
1887         if (pch_iir & SDE_ERROR_CPT)
1888                 cpt_serr_int_handler(dev_priv);
1889 }
1890
1891 static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1892 {
1893         u32 ddi_hotplug_trigger, tc_hotplug_trigger;
1894         u32 pin_mask = 0, long_mask = 0;
1895         bool (*tc_port_hotplug_long_detect)(enum hpd_pin pin, u32 val);
1896
1897         if (HAS_PCH_TGP(dev_priv)) {
1898                 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
1899                 tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
1900                 tc_port_hotplug_long_detect = tgp_tc_port_hotplug_long_detect;
1901         } else if (HAS_PCH_JSP(dev_priv)) {
1902                 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
1903                 tc_hotplug_trigger = 0;
1904         } else if (HAS_PCH_MCC(dev_priv)) {
1905                 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
1906                 tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(PORT_TC1);
1907                 tc_port_hotplug_long_detect = icp_tc_port_hotplug_long_detect;
1908         } else {
1909                 drm_WARN(&dev_priv->drm, !HAS_PCH_ICP(dev_priv),
1910                          "Unrecognized PCH type 0x%x\n",
1911                          INTEL_PCH_TYPE(dev_priv));
1912
1913                 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
1914                 tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
1915                 tc_port_hotplug_long_detect = icp_tc_port_hotplug_long_detect;
1916         }
1917
1918         if (ddi_hotplug_trigger) {
1919                 u32 dig_hotplug_reg;
1920
1921                 dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI);
1922                 I915_WRITE(SHOTPLUG_CTL_DDI, dig_hotplug_reg);
1923
1924                 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1925                                    ddi_hotplug_trigger, dig_hotplug_reg,
1926                                    dev_priv->hotplug.pch_hpd,
1927                                    icp_ddi_port_hotplug_long_detect);
1928         }
1929
1930         if (tc_hotplug_trigger) {
1931                 u32 dig_hotplug_reg;
1932
1933                 dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC);
1934                 I915_WRITE(SHOTPLUG_CTL_TC, dig_hotplug_reg);
1935
1936                 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1937                                    tc_hotplug_trigger, dig_hotplug_reg,
1938                                    dev_priv->hotplug.pch_hpd,
1939                                    tc_port_hotplug_long_detect);
1940         }
1941
1942         if (pin_mask)
1943                 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1944
1945         if (pch_iir & SDE_GMBUS_ICP)
1946                 gmbus_irq_handler(dev_priv);
1947 }
1948
1949 static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1950 {
1951         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
1952                 ~SDE_PORTE_HOTPLUG_SPT;
1953         u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
1954         u32 pin_mask = 0, long_mask = 0;
1955
1956         if (hotplug_trigger) {
1957                 u32 dig_hotplug_reg;
1958
1959                 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1960                 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1961
1962                 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1963                                    hotplug_trigger, dig_hotplug_reg,
1964                                    dev_priv->hotplug.pch_hpd,
1965                                    spt_port_hotplug_long_detect);
1966         }
1967
1968         if (hotplug2_trigger) {
1969                 u32 dig_hotplug_reg;
1970
1971                 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
1972                 I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
1973
1974                 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1975                                    hotplug2_trigger, dig_hotplug_reg,
1976                                    dev_priv->hotplug.pch_hpd,
1977                                    spt_port_hotplug2_long_detect);
1978         }
1979
1980         if (pin_mask)
1981                 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1982
1983         if (pch_iir & SDE_GMBUS_CPT)
1984                 gmbus_irq_handler(dev_priv);
1985 }
1986
1987 static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
1988                                 u32 hotplug_trigger)
1989 {
1990         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
1991
1992         dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
1993         I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
1994
1995         intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1996                            hotplug_trigger, dig_hotplug_reg,
1997                            dev_priv->hotplug.hpd,
1998                            ilk_port_hotplug_long_detect);
1999
2000         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2001 }
2002
2003 static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
2004                                     u32 de_iir)
2005 {
2006         enum pipe pipe;
2007         u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
2008
2009         if (hotplug_trigger)
2010                 ilk_hpd_irq_handler(dev_priv, hotplug_trigger);
2011
2012         if (de_iir & DE_AUX_CHANNEL_A)
2013                 dp_aux_irq_handler(dev_priv);
2014
2015         if (de_iir & DE_GSE)
2016                 intel_opregion_asle_intr(dev_priv);
2017
2018         if (de_iir & DE_POISON)
2019                 drm_err(&dev_priv->drm, "Poison interrupt\n");
2020
2021         for_each_pipe(dev_priv, pipe) {
2022                 if (de_iir & DE_PIPE_VBLANK(pipe))
2023                         intel_handle_vblank(dev_priv, pipe);
2024
2025                 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2026                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2027
2028                 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2029                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2030         }
2031
2032         /* check event from PCH */
2033         if (de_iir & DE_PCH_EVENT) {
2034                 u32 pch_iir = I915_READ(SDEIIR);
2035
2036                 if (HAS_PCH_CPT(dev_priv))
2037                         cpt_irq_handler(dev_priv, pch_iir);
2038                 else
2039                         ibx_irq_handler(dev_priv, pch_iir);
2040
2041                 /* should clear PCH hotplug event before clear CPU irq */
2042                 I915_WRITE(SDEIIR, pch_iir);
2043         }
2044
2045         if (IS_GEN(dev_priv, 5) && de_iir & DE_PCU_EVENT)
2046                 gen5_rps_irq_handler(&dev_priv->gt.rps);
2047 }
2048
2049 static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
2050                                     u32 de_iir)
2051 {
2052         enum pipe pipe;
2053         u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2054
2055         if (hotplug_trigger)
2056                 ilk_hpd_irq_handler(dev_priv, hotplug_trigger);
2057
2058         if (de_iir & DE_ERR_INT_IVB)
2059                 ivb_err_int_handler(dev_priv);
2060
2061         if (de_iir & DE_EDP_PSR_INT_HSW) {
2062                 u32 psr_iir = I915_READ(EDP_PSR_IIR);
2063
2064                 intel_psr_irq_handler(dev_priv, psr_iir);
2065                 I915_WRITE(EDP_PSR_IIR, psr_iir);
2066         }
2067
2068         if (de_iir & DE_AUX_CHANNEL_A_IVB)
2069                 dp_aux_irq_handler(dev_priv);
2070
2071         if (de_iir & DE_GSE_IVB)
2072                 intel_opregion_asle_intr(dev_priv);
2073
2074         for_each_pipe(dev_priv, pipe) {
2075                 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
2076                         intel_handle_vblank(dev_priv, pipe);
2077         }
2078
2079         /* check event from PCH */
2080         if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
2081                 u32 pch_iir = I915_READ(SDEIIR);
2082
2083                 cpt_irq_handler(dev_priv, pch_iir);
2084
2085                 /* clear PCH hotplug event before clear CPU irq */
2086                 I915_WRITE(SDEIIR, pch_iir);
2087         }
2088 }
2089
2090 /*
2091  * To handle irqs with the minimum potential races with fresh interrupts, we:
2092  * 1 - Disable Master Interrupt Control.
2093  * 2 - Find the source(s) of the interrupt.
2094  * 3 - Clear the Interrupt Identity bits (IIR).
2095  * 4 - Process the interrupt(s) that had bits set in the IIRs.
2096  * 5 - Re-enable Master Interrupt Control.
2097  */
2098 static irqreturn_t ilk_irq_handler(int irq, void *arg)
2099 {
2100         struct drm_i915_private *i915 = arg;
2101         void __iomem * const regs = i915->uncore.regs;
2102         u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2103         irqreturn_t ret = IRQ_NONE;
2104
2105         if (unlikely(!intel_irqs_enabled(i915)))
2106                 return IRQ_NONE;
2107
2108         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2109         disable_rpm_wakeref_asserts(&i915->runtime_pm);
2110
2111         /* disable master interrupt before clearing iir  */
2112         de_ier = raw_reg_read(regs, DEIER);
2113         raw_reg_write(regs, DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2114
2115         /* Disable south interrupts. We'll only write to SDEIIR once, so further
2116          * interrupts will will be stored on its back queue, and then we'll be
2117          * able to process them after we restore SDEIER (as soon as we restore
2118          * it, we'll get an interrupt if SDEIIR still has something to process
2119          * due to its back queue). */
2120         if (!HAS_PCH_NOP(i915)) {
2121                 sde_ier = raw_reg_read(regs, SDEIER);
2122                 raw_reg_write(regs, SDEIER, 0);
2123         }
2124
2125         /* Find, clear, then process each source of interrupt */
2126
2127         gt_iir = raw_reg_read(regs, GTIIR);
2128         if (gt_iir) {
2129                 raw_reg_write(regs, GTIIR, gt_iir);
2130                 if (INTEL_GEN(i915) >= 6)
2131                         gen6_gt_irq_handler(&i915->gt, gt_iir);
2132                 else
2133                         gen5_gt_irq_handler(&i915->gt, gt_iir);
2134                 ret = IRQ_HANDLED;
2135         }
2136
2137         de_iir = raw_reg_read(regs, DEIIR);
2138         if (de_iir) {
2139                 raw_reg_write(regs, DEIIR, de_iir);
2140                 if (INTEL_GEN(i915) >= 7)
2141                         ivb_display_irq_handler(i915, de_iir);
2142                 else
2143                         ilk_display_irq_handler(i915, de_iir);
2144                 ret = IRQ_HANDLED;
2145         }
2146
2147         if (INTEL_GEN(i915) >= 6) {
2148                 u32 pm_iir = raw_reg_read(regs, GEN6_PMIIR);
2149                 if (pm_iir) {
2150                         raw_reg_write(regs, GEN6_PMIIR, pm_iir);
2151                         gen6_rps_irq_handler(&i915->gt.rps, pm_iir);
2152                         ret = IRQ_HANDLED;
2153                 }
2154         }
2155
2156         raw_reg_write(regs, DEIER, de_ier);
2157         if (sde_ier)
2158                 raw_reg_write(regs, SDEIER, sde_ier);
2159
2160         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2161         enable_rpm_wakeref_asserts(&i915->runtime_pm);
2162
2163         return ret;
2164 }
2165
2166 static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
2167                                 u32 hotplug_trigger)
2168 {
2169         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2170
2171         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2172         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2173
2174         intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2175                            hotplug_trigger, dig_hotplug_reg,
2176                            dev_priv->hotplug.hpd,
2177                            bxt_port_hotplug_long_detect);
2178
2179         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2180 }
2181
2182 static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
2183 {
2184         u32 pin_mask = 0, long_mask = 0;
2185         u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK;
2186         u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK;
2187         long_pulse_detect_func long_pulse_detect;
2188
2189         if (INTEL_GEN(dev_priv) >= 12)
2190                 long_pulse_detect = gen12_port_hotplug_long_detect;
2191         else
2192                 long_pulse_detect = gen11_port_hotplug_long_detect;
2193
2194         if (trigger_tc) {
2195                 u32 dig_hotplug_reg;
2196
2197                 dig_hotplug_reg = I915_READ(GEN11_TC_HOTPLUG_CTL);
2198                 I915_WRITE(GEN11_TC_HOTPLUG_CTL, dig_hotplug_reg);
2199
2200                 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2201                                    trigger_tc, dig_hotplug_reg,
2202                                    dev_priv->hotplug.hpd,
2203                                    long_pulse_detect);
2204         }
2205
2206         if (trigger_tbt) {
2207                 u32 dig_hotplug_reg;
2208
2209                 dig_hotplug_reg = I915_READ(GEN11_TBT_HOTPLUG_CTL);
2210                 I915_WRITE(GEN11_TBT_HOTPLUG_CTL, dig_hotplug_reg);
2211
2212                 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2213                                    trigger_tbt, dig_hotplug_reg,
2214                                    dev_priv->hotplug.hpd,
2215                                    long_pulse_detect);
2216         }
2217
2218         if (pin_mask)
2219                 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2220         else
2221                 drm_err(&dev_priv->drm,
2222                         "Unexpected DE HPD interrupt 0x%08x\n", iir);
2223 }
2224
2225 static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
2226 {
2227         u32 mask;
2228
2229         if (INTEL_GEN(dev_priv) >= 12)
2230                 return TGL_DE_PORT_AUX_DDIA |
2231                         TGL_DE_PORT_AUX_DDIB |
2232                         TGL_DE_PORT_AUX_DDIC |
2233                         TGL_DE_PORT_AUX_USBC1 |
2234                         TGL_DE_PORT_AUX_USBC2 |
2235                         TGL_DE_PORT_AUX_USBC3 |
2236                         TGL_DE_PORT_AUX_USBC4 |
2237                         TGL_DE_PORT_AUX_USBC5 |
2238                         TGL_DE_PORT_AUX_USBC6;
2239
2240
2241         mask = GEN8_AUX_CHANNEL_A;
2242         if (INTEL_GEN(dev_priv) >= 9)
2243                 mask |= GEN9_AUX_CHANNEL_B |
2244                         GEN9_AUX_CHANNEL_C |
2245                         GEN9_AUX_CHANNEL_D;
2246
2247         if (IS_CNL_WITH_PORT_F(dev_priv) || IS_GEN(dev_priv, 11))
2248                 mask |= CNL_AUX_CHANNEL_F;
2249
2250         if (IS_GEN(dev_priv, 11))
2251                 mask |= ICL_AUX_CHANNEL_E;
2252
2253         return mask;
2254 }
2255
2256 static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
2257 {
2258         if (IS_ROCKETLAKE(dev_priv))
2259                 return RKL_DE_PIPE_IRQ_FAULT_ERRORS;
2260         else if (INTEL_GEN(dev_priv) >= 11)
2261                 return GEN11_DE_PIPE_IRQ_FAULT_ERRORS;
2262         else if (INTEL_GEN(dev_priv) >= 9)
2263                 return GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2264         else
2265                 return GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2266 }
2267
2268 static void
2269 gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
2270 {
2271         bool found = false;
2272
2273         if (iir & GEN8_DE_MISC_GSE) {
2274                 intel_opregion_asle_intr(dev_priv);
2275                 found = true;
2276         }
2277
2278         if (iir & GEN8_DE_EDP_PSR) {
2279                 u32 psr_iir;
2280                 i915_reg_t iir_reg;
2281
2282                 if (INTEL_GEN(dev_priv) >= 12)
2283                         iir_reg = TRANS_PSR_IIR(dev_priv->psr.transcoder);
2284                 else
2285                         iir_reg = EDP_PSR_IIR;
2286
2287                 psr_iir = I915_READ(iir_reg);
2288                 I915_WRITE(iir_reg, psr_iir);
2289
2290                 if (psr_iir)
2291                         found = true;
2292
2293                 intel_psr_irq_handler(dev_priv, psr_iir);
2294         }
2295
2296         if (!found)
2297                 drm_err(&dev_priv->drm, "Unexpected DE Misc interrupt\n");
2298 }
2299
2300 static irqreturn_t
2301 gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2302 {
2303         irqreturn_t ret = IRQ_NONE;
2304         u32 iir;
2305         enum pipe pipe;
2306
2307         if (master_ctl & GEN8_DE_MISC_IRQ) {
2308                 iir = I915_READ(GEN8_DE_MISC_IIR);
2309                 if (iir) {
2310                         I915_WRITE(GEN8_DE_MISC_IIR, iir);
2311                         ret = IRQ_HANDLED;
2312                         gen8_de_misc_irq_handler(dev_priv, iir);
2313                 } else {
2314                         drm_err(&dev_priv->drm,
2315                                 "The master control interrupt lied (DE MISC)!\n");
2316                 }
2317         }
2318
2319         if (INTEL_GEN(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) {
2320                 iir = I915_READ(GEN11_DE_HPD_IIR);
2321                 if (iir) {
2322                         I915_WRITE(GEN11_DE_HPD_IIR, iir);
2323                         ret = IRQ_HANDLED;
2324                         gen11_hpd_irq_handler(dev_priv, iir);
2325                 } else {
2326                         drm_err(&dev_priv->drm,
2327                                 "The master control interrupt lied, (DE HPD)!\n");
2328                 }
2329         }
2330
2331         if (master_ctl & GEN8_DE_PORT_IRQ) {
2332                 iir = I915_READ(GEN8_DE_PORT_IIR);
2333                 if (iir) {
2334                         u32 tmp_mask;
2335                         bool found = false;
2336
2337                         I915_WRITE(GEN8_DE_PORT_IIR, iir);
2338                         ret = IRQ_HANDLED;
2339
2340                         if (iir & gen8_de_port_aux_mask(dev_priv)) {
2341                                 dp_aux_irq_handler(dev_priv);
2342                                 found = true;
2343                         }
2344
2345                         if (IS_GEN9_LP(dev_priv)) {
2346                                 tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
2347                                 if (tmp_mask) {
2348                                         bxt_hpd_irq_handler(dev_priv, tmp_mask);
2349                                         found = true;
2350                                 }
2351                         } else if (IS_BROADWELL(dev_priv)) {
2352                                 tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
2353                                 if (tmp_mask) {
2354                                         ilk_hpd_irq_handler(dev_priv, tmp_mask);
2355                                         found = true;
2356                                 }
2357                         }
2358
2359                         if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
2360                                 gmbus_irq_handler(dev_priv);
2361                                 found = true;
2362                         }
2363
2364                         if (!found)
2365                                 drm_err(&dev_priv->drm,
2366                                         "Unexpected DE Port interrupt\n");
2367                 }
2368                 else
2369                         drm_err(&dev_priv->drm,
2370                                 "The master control interrupt lied (DE PORT)!\n");
2371         }
2372
2373         for_each_pipe(dev_priv, pipe) {
2374                 u32 fault_errors;
2375
2376                 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2377                         continue;
2378
2379                 iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2380                 if (!iir) {
2381                         drm_err(&dev_priv->drm,
2382                                 "The master control interrupt lied (DE PIPE)!\n");
2383                         continue;
2384                 }
2385
2386                 ret = IRQ_HANDLED;
2387                 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
2388
2389                 if (iir & GEN8_PIPE_VBLANK)
2390                         intel_handle_vblank(dev_priv, pipe);
2391
2392                 if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
2393                         hsw_pipe_crc_irq_handler(dev_priv, pipe);
2394
2395                 if (iir & GEN8_PIPE_FIFO_UNDERRUN)
2396                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2397
2398                 fault_errors = iir & gen8_de_pipe_fault_mask(dev_priv);
2399                 if (fault_errors)
2400                         drm_err(&dev_priv->drm,
2401                                 "Fault errors on pipe %c: 0x%08x\n",
2402                                 pipe_name(pipe),
2403                                 fault_errors);
2404         }
2405
2406         if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
2407             master_ctl & GEN8_DE_PCH_IRQ) {
2408                 /*
2409                  * FIXME(BDW): Assume for now that the new interrupt handling
2410                  * scheme also closed the SDE interrupt handling race we've seen
2411                  * on older pch-split platforms. But this needs testing.
2412                  */
2413                 iir = I915_READ(SDEIIR);
2414                 if (iir) {
2415                         I915_WRITE(SDEIIR, iir);
2416                         ret = IRQ_HANDLED;
2417
2418                         if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2419                                 icp_irq_handler(dev_priv, iir);
2420                         else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
2421                                 spt_irq_handler(dev_priv, iir);
2422                         else
2423                                 cpt_irq_handler(dev_priv, iir);
2424                 } else {
2425                         /*
2426                          * Like on previous PCH there seems to be something
2427                          * fishy going on with forwarding PCH interrupts.
2428                          */
2429                         drm_dbg(&dev_priv->drm,
2430                                 "The master control interrupt lied (SDE)!\n");
2431                 }
2432         }
2433
2434         return ret;
2435 }
2436
2437 static inline u32 gen8_master_intr_disable(void __iomem * const regs)
2438 {
2439         raw_reg_write(regs, GEN8_MASTER_IRQ, 0);
2440
2441         /*
2442          * Now with master disabled, get a sample of level indications
2443          * for this interrupt. Indications will be cleared on related acks.
2444          * New indications can and will light up during processing,
2445          * and will generate new interrupt after enabling master.
2446          */
2447         return raw_reg_read(regs, GEN8_MASTER_IRQ);
2448 }
2449
2450 static inline void gen8_master_intr_enable(void __iomem * const regs)
2451 {
2452         raw_reg_write(regs, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2453 }
2454
2455 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2456 {
2457         struct drm_i915_private *dev_priv = arg;
2458         void __iomem * const regs = dev_priv->uncore.regs;
2459         u32 master_ctl;
2460
2461         if (!intel_irqs_enabled(dev_priv))
2462                 return IRQ_NONE;
2463
2464         master_ctl = gen8_master_intr_disable(regs);
2465         if (!master_ctl) {
2466                 gen8_master_intr_enable(regs);
2467                 return IRQ_NONE;
2468         }
2469
2470         /* Find, queue (onto bottom-halves), then clear each source */
2471         gen8_gt_irq_handler(&dev_priv->gt, master_ctl);
2472
2473         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2474         if (master_ctl & ~GEN8_GT_IRQS) {
2475                 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2476                 gen8_de_irq_handler(dev_priv, master_ctl);
2477                 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2478         }
2479
2480         gen8_master_intr_enable(regs);
2481
2482         return IRQ_HANDLED;
2483 }
2484
2485 static u32
2486 gen11_gu_misc_irq_ack(struct intel_gt *gt, const u32 master_ctl)
2487 {
2488         void __iomem * const regs = gt->uncore->regs;
2489         u32 iir;
2490
2491         if (!(master_ctl & GEN11_GU_MISC_IRQ))
2492                 return 0;
2493
2494         iir = raw_reg_read(regs, GEN11_GU_MISC_IIR);
2495         if (likely(iir))
2496                 raw_reg_write(regs, GEN11_GU_MISC_IIR, iir);
2497
2498         return iir;
2499 }
2500
2501 static void
2502 gen11_gu_misc_irq_handler(struct intel_gt *gt, const u32 iir)
2503 {
2504         if (iir & GEN11_GU_MISC_GSE)
2505                 intel_opregion_asle_intr(gt->i915);
2506 }
2507
2508 static inline u32 gen11_master_intr_disable(void __iomem * const regs)
2509 {
2510         raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, 0);
2511
2512         /*
2513          * Now with master disabled, get a sample of level indications
2514          * for this interrupt. Indications will be cleared on related acks.
2515          * New indications can and will light up during processing,
2516          * and will generate new interrupt after enabling master.
2517          */
2518         return raw_reg_read(regs, GEN11_GFX_MSTR_IRQ);
2519 }
2520
2521 static inline void gen11_master_intr_enable(void __iomem * const regs)
2522 {
2523         raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
2524 }
2525
2526 static void
2527 gen11_display_irq_handler(struct drm_i915_private *i915)
2528 {
2529         void __iomem * const regs = i915->uncore.regs;
2530         const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL);
2531
2532         disable_rpm_wakeref_asserts(&i915->runtime_pm);
2533         /*
2534          * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ
2535          * for the display related bits.
2536          */
2537         raw_reg_write(regs, GEN11_DISPLAY_INT_CTL, 0x0);
2538         gen8_de_irq_handler(i915, disp_ctl);
2539         raw_reg_write(regs, GEN11_DISPLAY_INT_CTL,
2540                       GEN11_DISPLAY_IRQ_ENABLE);
2541
2542         enable_rpm_wakeref_asserts(&i915->runtime_pm);
2543 }
2544
2545 static __always_inline irqreturn_t
2546 __gen11_irq_handler(struct drm_i915_private * const i915,
2547                     u32 (*intr_disable)(void __iomem * const regs),
2548                     void (*intr_enable)(void __iomem * const regs))
2549 {
2550         void __iomem * const regs = i915->uncore.regs;
2551         struct intel_gt *gt = &i915->gt;
2552         u32 master_ctl;
2553         u32 gu_misc_iir;
2554
2555         if (!intel_irqs_enabled(i915))
2556                 return IRQ_NONE;
2557
2558         master_ctl = intr_disable(regs);
2559         if (!master_ctl) {
2560                 intr_enable(regs);
2561                 return IRQ_NONE;
2562         }
2563
2564         /* Find, queue (onto bottom-halves), then clear each source */
2565         gen11_gt_irq_handler(gt, master_ctl);
2566
2567         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2568         if (master_ctl & GEN11_DISPLAY_IRQ)
2569                 gen11_display_irq_handler(i915);
2570
2571         gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
2572
2573         intr_enable(regs);
2574
2575         gen11_gu_misc_irq_handler(gt, gu_misc_iir);
2576
2577         return IRQ_HANDLED;
2578 }
2579
2580 static irqreturn_t gen11_irq_handler(int irq, void *arg)
2581 {
2582         return __gen11_irq_handler(arg,
2583                                    gen11_master_intr_disable,
2584                                    gen11_master_intr_enable);
2585 }
2586
2587 static u32 dg1_master_intr_disable_and_ack(void __iomem * const regs)
2588 {
2589         u32 val;
2590
2591         /* First disable interrupts */
2592         raw_reg_write(regs, DG1_MSTR_UNIT_INTR, 0);
2593
2594         /* Get the indication levels and ack the master unit */
2595         val = raw_reg_read(regs, DG1_MSTR_UNIT_INTR);
2596         if (unlikely(!val))
2597                 return 0;
2598
2599         raw_reg_write(regs, DG1_MSTR_UNIT_INTR, val);
2600
2601         /*
2602          * Now with master disabled, get a sample of level indications
2603          * for this interrupt and ack them right away - we keep GEN11_MASTER_IRQ
2604          * out as this bit doesn't exist anymore for DG1
2605          */
2606         val = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ) & ~GEN11_MASTER_IRQ;
2607         if (unlikely(!val))
2608                 return 0;
2609
2610         raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, val);
2611
2612         return val;
2613 }
2614
2615 static inline void dg1_master_intr_enable(void __iomem * const regs)
2616 {
2617         raw_reg_write(regs, DG1_MSTR_UNIT_INTR, DG1_MSTR_IRQ);
2618 }
2619
2620 static irqreturn_t dg1_irq_handler(int irq, void *arg)
2621 {
2622         return __gen11_irq_handler(arg,
2623                                    dg1_master_intr_disable_and_ack,
2624                                    dg1_master_intr_enable);
2625 }
2626
2627 /* Called from drm generic code, passed 'crtc' which
2628  * we use as a pipe index
2629  */
2630 int i8xx_enable_vblank(struct drm_crtc *crtc)
2631 {
2632         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2633         enum pipe pipe = to_intel_crtc(crtc)->pipe;
2634         unsigned long irqflags;
2635
2636         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2637         i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
2638         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2639
2640         return 0;
2641 }
2642
2643 int i915gm_enable_vblank(struct drm_crtc *crtc)
2644 {
2645         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2646
2647         /*
2648          * Vblank interrupts fail to wake the device up from C2+.
2649          * Disabling render clock gating during C-states avoids
2650          * the problem. There is a small power cost so we do this
2651          * only when vblank interrupts are actually enabled.
2652          */
2653         if (dev_priv->vblank_enabled++ == 0)
2654                 I915_WRITE(SCPD0, _MASKED_BIT_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));
2655
2656         return i8xx_enable_vblank(crtc);
2657 }
2658
2659 int i965_enable_vblank(struct drm_crtc *crtc)
2660 {
2661         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2662         enum pipe pipe = to_intel_crtc(crtc)->pipe;
2663         unsigned long irqflags;
2664
2665         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2666         i915_enable_pipestat(dev_priv, pipe,
2667                              PIPE_START_VBLANK_INTERRUPT_STATUS);
2668         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2669
2670         return 0;
2671 }
2672
2673 int ilk_enable_vblank(struct drm_crtc *crtc)
2674 {
2675         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2676         enum pipe pipe = to_intel_crtc(crtc)->pipe;
2677         unsigned long irqflags;
2678         u32 bit = INTEL_GEN(dev_priv) >= 7 ?
2679                 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
2680
2681         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2682         ilk_enable_display_irq(dev_priv, bit);
2683         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2684
2685         /* Even though there is no DMC, frame counter can get stuck when
2686          * PSR is active as no frames are generated.
2687          */
2688         if (HAS_PSR(dev_priv))
2689                 drm_crtc_vblank_restore(crtc);
2690
2691         return 0;
2692 }
2693
2694 int bdw_enable_vblank(struct drm_crtc *crtc)
2695 {
2696         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2697         enum pipe pipe = to_intel_crtc(crtc)->pipe;
2698         unsigned long irqflags;
2699
2700         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2701         bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2702         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2703
2704         /* Even if there is no DMC, frame counter can get stuck when
2705          * PSR is active as no frames are generated, so check only for PSR.
2706          */
2707         if (HAS_PSR(dev_priv))
2708                 drm_crtc_vblank_restore(crtc);
2709
2710         return 0;
2711 }
2712
2713 /* Called from drm generic code, passed 'crtc' which
2714  * we use as a pipe index
2715  */
2716 void i8xx_disable_vblank(struct drm_crtc *crtc)
2717 {
2718         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2719         enum pipe pipe = to_intel_crtc(crtc)->pipe;
2720         unsigned long irqflags;
2721
2722         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2723         i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
2724         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2725 }
2726
2727 void i915gm_disable_vblank(struct drm_crtc *crtc)
2728 {
2729         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2730
2731         i8xx_disable_vblank(crtc);
2732
2733         if (--dev_priv->vblank_enabled == 0)
2734                 I915_WRITE(SCPD0, _MASKED_BIT_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));
2735 }
2736
2737 void i965_disable_vblank(struct drm_crtc *crtc)
2738 {
2739         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2740         enum pipe pipe = to_intel_crtc(crtc)->pipe;
2741         unsigned long irqflags;
2742
2743         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2744         i915_disable_pipestat(dev_priv, pipe,
2745                               PIPE_START_VBLANK_INTERRUPT_STATUS);
2746         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2747 }
2748
2749 void ilk_disable_vblank(struct drm_crtc *crtc)
2750 {
2751         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2752         enum pipe pipe = to_intel_crtc(crtc)->pipe;
2753         unsigned long irqflags;
2754         u32 bit = INTEL_GEN(dev_priv) >= 7 ?
2755                 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
2756
2757         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2758         ilk_disable_display_irq(dev_priv, bit);
2759         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2760 }
2761
2762 void bdw_disable_vblank(struct drm_crtc *crtc)
2763 {
2764         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2765         enum pipe pipe = to_intel_crtc(crtc)->pipe;
2766         unsigned long irqflags;
2767
2768         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2769         bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2770         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2771 }
2772
2773 static void ibx_irq_reset(struct drm_i915_private *dev_priv)
2774 {
2775         struct intel_uncore *uncore = &dev_priv->uncore;
2776
2777         if (HAS_PCH_NOP(dev_priv))
2778                 return;
2779
2780         GEN3_IRQ_RESET(uncore, SDE);
2781
2782         if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
2783                 I915_WRITE(SERR_INT, 0xffffffff);
2784 }
2785
2786 /*
2787  * SDEIER is also touched by the interrupt handler to work around missed PCH
2788  * interrupts. Hence we can't update it after the interrupt handler is enabled -
2789  * instead we unconditionally enable all PCH interrupt sources here, but then
2790  * only unmask them as needed with SDEIMR.
2791  *
2792  * This function needs to be called before interrupts are enabled.
2793  */
2794 static void ibx_irq_pre_postinstall(struct drm_i915_private *dev_priv)
2795 {
2796         if (HAS_PCH_NOP(dev_priv))
2797                 return;
2798
2799         drm_WARN_ON(&dev_priv->drm, I915_READ(SDEIER) != 0);
2800         I915_WRITE(SDEIER, 0xffffffff);
2801         POSTING_READ(SDEIER);
2802 }
2803
2804 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
2805 {
2806         struct intel_uncore *uncore = &dev_priv->uncore;
2807
2808         if (IS_CHERRYVIEW(dev_priv))
2809                 intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
2810         else
2811                 intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK);
2812
2813         i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
2814         intel_uncore_write(uncore, PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2815
2816         i9xx_pipestat_irq_reset(dev_priv);
2817
2818         GEN3_IRQ_RESET(uncore, VLV_);
2819         dev_priv->irq_mask = ~0u;
2820 }
2821
2822 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
2823 {
2824         struct intel_uncore *uncore = &dev_priv->uncore;
2825
2826         u32 pipestat_mask;
2827         u32 enable_mask;
2828         enum pipe pipe;
2829
2830         pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS;
2831
2832         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
2833         for_each_pipe(dev_priv, pipe)
2834                 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
2835
2836         enable_mask = I915_DISPLAY_PORT_INTERRUPT |
2837                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2838                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2839                 I915_LPE_PIPE_A_INTERRUPT |
2840                 I915_LPE_PIPE_B_INTERRUPT;
2841
2842         if (IS_CHERRYVIEW(dev_priv))
2843                 enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT |
2844                         I915_LPE_PIPE_C_INTERRUPT;
2845
2846         drm_WARN_ON(&dev_priv->drm, dev_priv->irq_mask != ~0u);
2847
2848         dev_priv->irq_mask = ~enable_mask;
2849
2850         GEN3_IRQ_INIT(uncore, VLV_, dev_priv->irq_mask, enable_mask);
2851 }
2852
2853 /* drm_dma.h hooks
2854 */
2855 static void ilk_irq_reset(struct drm_i915_private *dev_priv)
2856 {
2857         struct intel_uncore *uncore = &dev_priv->uncore;
2858
2859         GEN3_IRQ_RESET(uncore, DE);
2860         if (IS_GEN(dev_priv, 7))
2861                 intel_uncore_write(uncore, GEN7_ERR_INT, 0xffffffff);
2862
2863         if (IS_HASWELL(dev_priv)) {
2864                 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
2865                 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
2866         }
2867
2868         gen5_gt_irq_reset(&dev_priv->gt);
2869
2870         ibx_irq_reset(dev_priv);
2871 }
2872
2873 static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
2874 {
2875         I915_WRITE(VLV_MASTER_IER, 0);
2876         POSTING_READ(VLV_MASTER_IER);
2877
2878         gen5_gt_irq_reset(&dev_priv->gt);
2879
2880         spin_lock_irq(&dev_priv->irq_lock);
2881         if (dev_priv->display_irqs_enabled)
2882                 vlv_display_irq_reset(dev_priv);
2883         spin_unlock_irq(&dev_priv->irq_lock);
2884 }
2885
2886 static void gen8_irq_reset(struct drm_i915_private *dev_priv)
2887 {
2888         struct intel_uncore *uncore = &dev_priv->uncore;
2889         enum pipe pipe;
2890
2891         gen8_master_intr_disable(dev_priv->uncore.regs);
2892
2893         gen8_gt_irq_reset(&dev_priv->gt);
2894
2895         intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
2896         intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
2897
2898         for_each_pipe(dev_priv, pipe)
2899                 if (intel_display_power_is_enabled(dev_priv,
2900                                                    POWER_DOMAIN_PIPE(pipe)))
2901                         GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
2902
2903         GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);
2904         GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
2905         GEN3_IRQ_RESET(uncore, GEN8_PCU_);
2906
2907         if (HAS_PCH_SPLIT(dev_priv))
2908                 ibx_irq_reset(dev_priv);
2909 }
2910
2911 static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
2912 {
2913         struct intel_uncore *uncore = &dev_priv->uncore;
2914         enum pipe pipe;
2915         u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
2916                 BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
2917
2918         intel_uncore_write(uncore, GEN11_DISPLAY_INT_CTL, 0);
2919
2920         if (INTEL_GEN(dev_priv) >= 12) {
2921                 enum transcoder trans;
2922
2923                 for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {
2924                         enum intel_display_power_domain domain;
2925
2926                         domain = POWER_DOMAIN_TRANSCODER(trans);
2927                         if (!intel_display_power_is_enabled(dev_priv, domain))
2928                                 continue;
2929
2930                         intel_uncore_write(uncore, TRANS_PSR_IMR(trans), 0xffffffff);
2931                         intel_uncore_write(uncore, TRANS_PSR_IIR(trans), 0xffffffff);
2932                 }
2933         } else {
2934                 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
2935                 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
2936         }
2937
2938         for_each_pipe(dev_priv, pipe)
2939                 if (intel_display_power_is_enabled(dev_priv,
2940                                                    POWER_DOMAIN_PIPE(pipe)))
2941                         GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
2942
2943         GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);
2944         GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
2945         GEN3_IRQ_RESET(uncore, GEN11_DE_HPD_);
2946
2947         if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2948                 GEN3_IRQ_RESET(uncore, SDE);
2949
2950         /* Wa_14010685332:icl,jsl,ehl,tgl,rkl */
2951         if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
2952                 intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
2953                                  SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
2954                 intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
2955                                  SBCLK_RUN_REFCLK_DIS, 0);
2956         }
2957 }
2958
2959 static void gen11_irq_reset(struct drm_i915_private *dev_priv)
2960 {
2961         struct intel_uncore *uncore = &dev_priv->uncore;
2962
2963         if (HAS_MASTER_UNIT_IRQ(dev_priv))
2964                 dg1_master_intr_disable_and_ack(dev_priv->uncore.regs);
2965         else
2966                 gen11_master_intr_disable(dev_priv->uncore.regs);
2967
2968         gen11_gt_irq_reset(&dev_priv->gt);
2969         gen11_display_irq_reset(dev_priv);
2970
2971         GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
2972         GEN3_IRQ_RESET(uncore, GEN8_PCU_);
2973 }
2974
2975 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
2976                                      u8 pipe_mask)
2977 {
2978         struct intel_uncore *uncore = &dev_priv->uncore;
2979
2980         u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
2981         enum pipe pipe;
2982
2983         spin_lock_irq(&dev_priv->irq_lock);
2984
2985         if (!intel_irqs_enabled(dev_priv)) {
2986                 spin_unlock_irq(&dev_priv->irq_lock);
2987                 return;
2988         }
2989
2990         for_each_pipe_masked(dev_priv, pipe, pipe_mask)
2991                 GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,
2992                                   dev_priv->de_irq_mask[pipe],
2993                                   ~dev_priv->de_irq_mask[pipe] | extra_ier);
2994
2995         spin_unlock_irq(&dev_priv->irq_lock);
2996 }
2997
2998 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
2999                                      u8 pipe_mask)
3000 {
3001         struct intel_uncore *uncore = &dev_priv->uncore;
3002         enum pipe pipe;
3003
3004         spin_lock_irq(&dev_priv->irq_lock);
3005
3006         if (!intel_irqs_enabled(dev_priv)) {
3007                 spin_unlock_irq(&dev_priv->irq_lock);
3008                 return;
3009         }
3010
3011         for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3012                 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
3013
3014         spin_unlock_irq(&dev_priv->irq_lock);
3015
3016         /* make sure we're done processing display irqs */
3017         intel_synchronize_irq(dev_priv);
3018 }
3019
3020 static void cherryview_irq_reset(struct drm_i915_private *dev_priv)
3021 {
3022         struct intel_uncore *uncore = &dev_priv->uncore;
3023
3024         I915_WRITE(GEN8_MASTER_IRQ, 0);
3025         POSTING_READ(GEN8_MASTER_IRQ);
3026
3027         gen8_gt_irq_reset(&dev_priv->gt);
3028
3029         GEN3_IRQ_RESET(uncore, GEN8_PCU_);
3030
3031         spin_lock_irq(&dev_priv->irq_lock);
3032         if (dev_priv->display_irqs_enabled)
3033                 vlv_display_irq_reset(dev_priv);
3034         spin_unlock_irq(&dev_priv->irq_lock);
3035 }
3036
3037 static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
3038                                   const u32 hpd[HPD_NUM_PINS])
3039 {
3040         struct intel_encoder *encoder;
3041         u32 enabled_irqs = 0;
3042
3043         for_each_intel_encoder(&dev_priv->drm, encoder)
3044                 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
3045                         enabled_irqs |= hpd[encoder->hpd_pin];
3046
3047         return enabled_irqs;
3048 }
3049
3050 static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
3051 {
3052         u32 hotplug;
3053
3054         /*
3055          * Enable digital hotplug on the PCH, and configure the DP short pulse
3056          * duration to 2ms (which is the minimum in the Display Port spec).
3057          * The pulse duration bits are reserved on LPT+.
3058          */
3059         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3060         hotplug &= ~(PORTB_PULSE_DURATION_MASK |
3061                      PORTC_PULSE_DURATION_MASK |
3062                      PORTD_PULSE_DURATION_MASK);
3063         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3064         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3065         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3066         /*
3067          * When CPU and PCH are on the same package, port A
3068          * HPD must be enabled in both north and south.
3069          */
3070         if (HAS_PCH_LPT_LP(dev_priv))
3071                 hotplug |= PORTA_HOTPLUG_ENABLE;
3072         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3073 }
3074
3075 static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
3076 {
3077         u32 hotplug_irqs, enabled_irqs;
3078
3079         if (HAS_PCH_IBX(dev_priv))
3080                 hotplug_irqs = SDE_HOTPLUG_MASK;
3081         else
3082                 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3083
3084         enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3085
3086         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3087
3088         ibx_hpd_detection_setup(dev_priv);
3089 }
3090
3091 static void icp_hpd_detection_setup(struct drm_i915_private *dev_priv,
3092                                     u32 ddi_hotplug_enable_mask,
3093                                     u32 tc_hotplug_enable_mask)
3094 {
3095         u32 hotplug;
3096
3097         hotplug = I915_READ(SHOTPLUG_CTL_DDI);
3098         hotplug |= ddi_hotplug_enable_mask;
3099         I915_WRITE(SHOTPLUG_CTL_DDI, hotplug);
3100
3101         if (tc_hotplug_enable_mask) {
3102                 hotplug = I915_READ(SHOTPLUG_CTL_TC);
3103                 hotplug |= tc_hotplug_enable_mask;
3104                 I915_WRITE(SHOTPLUG_CTL_TC, hotplug);
3105         }
3106 }
3107
3108 static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv,
3109                               u32 sde_ddi_mask, u32 sde_tc_mask,
3110                               u32 ddi_enable_mask, u32 tc_enable_mask)
3111 {
3112         u32 hotplug_irqs, enabled_irqs;
3113
3114         hotplug_irqs = sde_ddi_mask | sde_tc_mask;
3115         enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3116
3117         if (INTEL_PCH_TYPE(dev_priv) <= PCH_TGP)
3118                 I915_WRITE(SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
3119
3120         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3121
3122         icp_hpd_detection_setup(dev_priv, ddi_enable_mask, tc_enable_mask);
3123 }
3124
3125 /*
3126  * EHL doesn't need most of gen11_hpd_irq_setup, it's handling only the
3127  * equivalent of SDE.
3128  */
3129 static void mcc_hpd_irq_setup(struct drm_i915_private *dev_priv)
3130 {
3131         icp_hpd_irq_setup(dev_priv,
3132                           SDE_DDI_MASK_ICP, SDE_TC_HOTPLUG_ICP(PORT_TC1),
3133                           ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE(PORT_TC1));
3134 }
3135
3136 /*
3137  * JSP behaves exactly the same as MCC above except that port C is mapped to
3138  * the DDI-C pins instead of the TC1 pins.  This means we should follow TGP's
3139  * masks & tables rather than ICP's masks & tables.
3140  */
3141 static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv)
3142 {
3143         icp_hpd_irq_setup(dev_priv,
3144                           SDE_DDI_MASK_TGP, 0,
3145                           TGP_DDI_HPD_ENABLE_MASK, 0);
3146 }
3147
3148 static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
3149 {
3150         u32 hotplug;
3151
3152         hotplug = I915_READ(GEN11_TC_HOTPLUG_CTL);
3153         hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) |
3154                    GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) |
3155                    GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) |
3156                    GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4);
3157         I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug);
3158
3159         hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL);
3160         hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) |
3161                    GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) |
3162                    GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) |
3163                    GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4);
3164         I915_WRITE(GEN11_TBT_HOTPLUG_CTL, hotplug);
3165 }
3166
3167 static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
3168 {
3169         u32 hotplug_irqs, enabled_irqs;
3170         u32 val;
3171
3172         enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
3173         hotplug_irqs = GEN11_DE_TC_HOTPLUG_MASK | GEN11_DE_TBT_HOTPLUG_MASK;
3174
3175         val = I915_READ(GEN11_DE_HPD_IMR);
3176         val &= ~hotplug_irqs;
3177         val |= ~enabled_irqs & hotplug_irqs;
3178         I915_WRITE(GEN11_DE_HPD_IMR, val);
3179         POSTING_READ(GEN11_DE_HPD_IMR);
3180
3181         gen11_hpd_detection_setup(dev_priv);
3182
3183         if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP)
3184                 icp_hpd_irq_setup(dev_priv, SDE_DDI_MASK_TGP, SDE_TC_MASK_TGP,
3185                                   TGP_DDI_HPD_ENABLE_MASK, TGP_TC_HPD_ENABLE_MASK);
3186         else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3187                 icp_hpd_irq_setup(dev_priv, SDE_DDI_MASK_ICP, SDE_TC_MASK_ICP,
3188                                   ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE_MASK);
3189 }
3190
3191 static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3192 {
3193         u32 val, hotplug;
3194
3195         /* Display WA #1179 WaHardHangonHotPlug: cnp */
3196         if (HAS_PCH_CNP(dev_priv)) {
3197                 val = I915_READ(SOUTH_CHICKEN1);
3198                 val &= ~CHASSIS_CLK_REQ_DURATION_MASK;
3199                 val |= CHASSIS_CLK_REQ_DURATION(0xf);
3200                 I915_WRITE(SOUTH_CHICKEN1, val);
3201         }
3202
3203         /* Enable digital hotplug on the PCH */
3204         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3205         hotplug |= PORTA_HOTPLUG_ENABLE |
3206                    PORTB_HOTPLUG_ENABLE |
3207                    PORTC_HOTPLUG_ENABLE |
3208                    PORTD_HOTPLUG_ENABLE;
3209         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3210
3211         hotplug = I915_READ(PCH_PORT_HOTPLUG2);
3212         hotplug |= PORTE_HOTPLUG_ENABLE;
3213         I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
3214 }
3215
3216 static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3217 {
3218         u32 hotplug_irqs, enabled_irqs;
3219
3220         if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
3221                 I915_WRITE(SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
3222
3223         hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
3224         enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3225
3226         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3227
3228         spt_hpd_detection_setup(dev_priv);
3229 }
3230
3231 static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv)
3232 {
3233         u32 hotplug;
3234
3235         /*
3236          * Enable digital hotplug on the CPU, and configure the DP short pulse
3237          * duration to 2ms (which is the minimum in the Display Port spec)
3238          * The pulse duration bits are reserved on HSW+.
3239          */
3240         hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
3241         hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
3242         hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE |
3243                    DIGITAL_PORTA_PULSE_DURATION_2ms;
3244         I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
3245 }
3246
3247 static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
3248 {
3249         u32 hotplug_irqs, enabled_irqs;
3250
3251         if (INTEL_GEN(dev_priv) >= 8) {
3252                 hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
3253                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
3254
3255                 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3256         } else if (INTEL_GEN(dev_priv) >= 7) {
3257                 hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
3258                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
3259
3260                 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3261         } else {
3262                 hotplug_irqs = DE_DP_A_HOTPLUG;
3263                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
3264
3265                 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3266         }
3267
3268         ilk_hpd_detection_setup(dev_priv);
3269
3270         ibx_hpd_irq_setup(dev_priv);
3271 }
3272
3273 static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
3274                                       u32 enabled_irqs)
3275 {
3276         u32 hotplug;
3277
3278         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3279         hotplug |= PORTA_HOTPLUG_ENABLE |
3280                    PORTB_HOTPLUG_ENABLE |
3281                    PORTC_HOTPLUG_ENABLE;
3282
3283         drm_dbg_kms(&dev_priv->drm,
3284                     "Invert bit setting: hp_ctl:%x hp_port:%x\n",
3285                     hotplug, enabled_irqs);
3286         hotplug &= ~BXT_DDI_HPD_INVERT_MASK;
3287
3288         /*
3289          * For BXT invert bit has to be set based on AOB design
3290          * for HPD detection logic, update it based on VBT fields.
3291          */
3292         if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) &&
3293             intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
3294                 hotplug |= BXT_DDIA_HPD_INVERT;
3295         if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) &&
3296             intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
3297                 hotplug |= BXT_DDIB_HPD_INVERT;
3298         if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) &&
3299             intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
3300                 hotplug |= BXT_DDIC_HPD_INVERT;
3301
3302         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3303 }
3304
3305 static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3306 {
3307         __bxt_hpd_detection_setup(dev_priv, BXT_DE_PORT_HOTPLUG_MASK);
3308 }
3309
3310 static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3311 {
3312         u32 hotplug_irqs, enabled_irqs;
3313
3314         enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
3315         hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK;
3316
3317         bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3318
3319         __bxt_hpd_detection_setup(dev_priv, enabled_irqs);
3320 }
3321
3322 static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
3323 {
3324         u32 mask;
3325
3326         if (HAS_PCH_NOP(dev_priv))
3327                 return;
3328
3329         if (HAS_PCH_IBX(dev_priv))
3330                 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3331         else if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
3332                 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3333         else
3334                 mask = SDE_GMBUS_CPT;
3335
3336         gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
3337         I915_WRITE(SDEIMR, ~mask);
3338
3339         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
3340             HAS_PCH_LPT(dev_priv))
3341                 ibx_hpd_detection_setup(dev_priv);
3342         else
3343                 spt_hpd_detection_setup(dev_priv);
3344 }
3345
3346 static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
3347 {
3348         struct intel_uncore *uncore = &dev_priv->uncore;
3349         u32 display_mask, extra_mask;
3350
3351         if (INTEL_GEN(dev_priv) >= 7) {
3352                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3353                                 DE_PCH_EVENT_IVB | DE_AUX_CHANNEL_A_IVB);
3354                 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3355                               DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
3356                               DE_DP_A_HOTPLUG_IVB);
3357         } else {
3358                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3359                                 DE_AUX_CHANNEL_A | DE_PIPEB_CRC_DONE |
3360                                 DE_PIPEA_CRC_DONE | DE_POISON);
3361                 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3362                               DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
3363                               DE_DP_A_HOTPLUG);
3364         }
3365
3366         if (IS_HASWELL(dev_priv)) {
3367                 gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
3368                 display_mask |= DE_EDP_PSR_INT_HSW;
3369         }
3370
3371         dev_priv->irq_mask = ~display_mask;
3372
3373         ibx_irq_pre_postinstall(dev_priv);
3374
3375         GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask,
3376                       display_mask | extra_mask);
3377
3378         gen5_gt_irq_postinstall(&dev_priv->gt);
3379
3380         ilk_hpd_detection_setup(dev_priv);
3381
3382         ibx_irq_postinstall(dev_priv);
3383
3384         if (IS_IRONLAKE_M(dev_priv)) {
3385                 /* Enable PCU event interrupts
3386                  *
3387                  * spinlocking not required here for correctness since interrupt
3388                  * setup is guaranteed to run in single-threaded context. But we
3389                  * need it to make the assert_spin_locked happy. */
3390                 spin_lock_irq(&dev_priv->irq_lock);
3391                 ilk_enable_display_irq(dev_priv, DE_PCU_EVENT);
3392                 spin_unlock_irq(&dev_priv->irq_lock);
3393         }
3394 }
3395
3396 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3397 {
3398         lockdep_assert_held(&dev_priv->irq_lock);
3399
3400         if (dev_priv->display_irqs_enabled)
3401                 return;
3402
3403         dev_priv->display_irqs_enabled = true;
3404
3405         if (intel_irqs_enabled(dev_priv)) {
3406                 vlv_display_irq_reset(dev_priv);
3407                 vlv_display_irq_postinstall(dev_priv);
3408         }
3409 }
3410
3411 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3412 {
3413         lockdep_assert_held(&dev_priv->irq_lock);
3414
3415         if (!dev_priv->display_irqs_enabled)
3416                 return;
3417
3418         dev_priv->display_irqs_enabled = false;
3419
3420         if (intel_irqs_enabled(dev_priv))
3421                 vlv_display_irq_reset(dev_priv);
3422 }
3423
3424
3425 static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv)
3426 {
3427         gen5_gt_irq_postinstall(&dev_priv->gt);
3428
3429         spin_lock_irq(&dev_priv->irq_lock);
3430         if (dev_priv->display_irqs_enabled)
3431                 vlv_display_irq_postinstall(dev_priv);
3432         spin_unlock_irq(&dev_priv->irq_lock);
3433
3434         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3435         POSTING_READ(VLV_MASTER_IER);
3436 }
3437
3438 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3439 {
3440         struct intel_uncore *uncore = &dev_priv->uncore;
3441
3442         u32 de_pipe_masked = gen8_de_pipe_fault_mask(dev_priv) |
3443                 GEN8_PIPE_CDCLK_CRC_DONE;
3444         u32 de_pipe_enables;
3445         u32 de_port_masked = gen8_de_port_aux_mask(dev_priv);
3446         u32 de_port_enables;
3447         u32 de_misc_masked = GEN8_DE_EDP_PSR;
3448         u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
3449                 BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
3450         enum pipe pipe;
3451
3452         if (INTEL_GEN(dev_priv) <= 10)
3453                 de_misc_masked |= GEN8_DE_MISC_GSE;
3454
3455         if (IS_GEN9_LP(dev_priv))
3456                 de_port_masked |= BXT_DE_PORT_GMBUS;
3457
3458         de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3459                                            GEN8_PIPE_FIFO_UNDERRUN;
3460
3461         de_port_enables = de_port_masked;
3462         if (IS_GEN9_LP(dev_priv))
3463                 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
3464         else if (IS_BROADWELL(dev_priv))
3465                 de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
3466
3467         if (INTEL_GEN(dev_priv) >= 12) {
3468                 enum transcoder trans;
3469
3470                 for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {
3471                         enum intel_display_power_domain domain;
3472
3473                         domain = POWER_DOMAIN_TRANSCODER(trans);
3474                         if (!intel_display_power_is_enabled(dev_priv, domain))
3475                                 continue;
3476
3477                         gen3_assert_iir_is_zero(uncore, TRANS_PSR_IIR(trans));
3478                 }
3479         } else {
3480                 gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
3481         }
3482
3483         for_each_pipe(dev_priv, pipe) {
3484                 dev_priv->de_irq_mask[pipe] = ~de_pipe_masked;
3485
3486                 if (intel_display_power_is_enabled(dev_priv,
3487                                 POWER_DOMAIN_PIPE(pipe)))
3488                         GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,
3489                                           dev_priv->de_irq_mask[pipe],
3490                                           de_pipe_enables);
3491         }
3492
3493         GEN3_IRQ_INIT(uncore, GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
3494         GEN3_IRQ_INIT(uncore, GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
3495
3496         if (INTEL_GEN(dev_priv) >= 11) {
3497                 u32 de_hpd_masked = 0;
3498                 u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK |
3499                                      GEN11_DE_TBT_HOTPLUG_MASK;
3500
3501                 GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked,
3502                               de_hpd_enables);
3503                 gen11_hpd_detection_setup(dev_priv);
3504         } else if (IS_GEN9_LP(dev_priv)) {
3505                 bxt_hpd_detection_setup(dev_priv);
3506         } else if (IS_BROADWELL(dev_priv)) {
3507                 ilk_hpd_detection_setup(dev_priv);
3508         }
3509 }
3510
3511 static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
3512 {
3513         if (HAS_PCH_SPLIT(dev_priv))
3514                 ibx_irq_pre_postinstall(dev_priv);
3515
3516         gen8_gt_irq_postinstall(&dev_priv->gt);
3517         gen8_de_irq_postinstall(dev_priv);
3518
3519         if (HAS_PCH_SPLIT(dev_priv))
3520                 ibx_irq_postinstall(dev_priv);
3521
3522         gen8_master_intr_enable(dev_priv->uncore.regs);
3523 }
3524
3525 static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
3526 {
3527         u32 mask = SDE_GMBUS_ICP;
3528
3529         drm_WARN_ON(&dev_priv->drm, I915_READ(SDEIER) != 0);
3530         I915_WRITE(SDEIER, 0xffffffff);
3531         POSTING_READ(SDEIER);
3532
3533         gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
3534         I915_WRITE(SDEIMR, ~mask);
3535
3536         if (HAS_PCH_TGP(dev_priv))
3537                 icp_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK,
3538                                         TGP_TC_HPD_ENABLE_MASK);
3539         else if (HAS_PCH_JSP(dev_priv))
3540                 icp_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK, 0);
3541         else if (HAS_PCH_MCC(dev_priv))
3542                 icp_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK,
3543                                         ICP_TC_HPD_ENABLE(PORT_TC1));
3544         else
3545                 icp_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK,
3546                                         ICP_TC_HPD_ENABLE_MASK);
3547 }
3548
3549 static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
3550 {
3551         struct intel_uncore *uncore = &dev_priv->uncore;
3552         u32 gu_misc_masked = GEN11_GU_MISC_GSE;
3553
3554         if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3555                 icp_irq_postinstall(dev_priv);
3556
3557         gen11_gt_irq_postinstall(&dev_priv->gt);
3558         gen8_de_irq_postinstall(dev_priv);
3559
3560         GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
3561
3562         I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
3563
3564         if (HAS_MASTER_UNIT_IRQ(dev_priv)) {
3565                 dg1_master_intr_enable(uncore->regs);
3566                 POSTING_READ(DG1_MSTR_UNIT_INTR);
3567         } else {
3568                 gen11_master_intr_enable(uncore->regs);
3569                 POSTING_READ(GEN11_GFX_MSTR_IRQ);
3570         }
3571 }
3572
3573 static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
3574 {
3575         gen8_gt_irq_postinstall(&dev_priv->gt);
3576
3577         spin_lock_irq(&dev_priv->irq_lock);
3578         if (dev_priv->display_irqs_enabled)
3579                 vlv_display_irq_postinstall(dev_priv);
3580         spin_unlock_irq(&dev_priv->irq_lock);
3581
3582         I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3583         POSTING_READ(GEN8_MASTER_IRQ);
3584 }
3585
3586 static void i8xx_irq_reset(struct drm_i915_private *dev_priv)
3587 {
3588         struct intel_uncore *uncore = &dev_priv->uncore;
3589
3590         i9xx_pipestat_irq_reset(dev_priv);
3591
3592         GEN2_IRQ_RESET(uncore);
3593 }
3594
3595 static void i8xx_irq_postinstall(struct drm_i915_private *dev_priv)
3596 {
3597         struct intel_uncore *uncore = &dev_priv->uncore;
3598         u16 enable_mask;
3599
3600         intel_uncore_write16(uncore,
3601                              EMR,
3602                              ~(I915_ERROR_PAGE_TABLE |
3603                                I915_ERROR_MEMORY_REFRESH));
3604
3605         /* Unmask the interrupts that we always want on. */
3606         dev_priv->irq_mask =
3607                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3608                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3609                   I915_MASTER_ERROR_INTERRUPT);
3610
3611         enable_mask =
3612                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3613                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3614                 I915_MASTER_ERROR_INTERRUPT |
3615                 I915_USER_INTERRUPT;
3616
3617         GEN2_IRQ_INIT(uncore, dev_priv->irq_mask, enable_mask);
3618
3619         /* Interrupt setup is already guaranteed to be single-threaded, this is
3620          * just to make the assert_spin_locked check happy. */
3621         spin_lock_irq(&dev_priv->irq_lock);
3622         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3623         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3624         spin_unlock_irq(&dev_priv->irq_lock);
3625 }
3626
3627 static void i8xx_error_irq_ack(struct drm_i915_private *i915,
3628                                u16 *eir, u16 *eir_stuck)
3629 {
3630         struct intel_uncore *uncore = &i915->uncore;
3631         u16 emr;
3632
3633         *eir = intel_uncore_read16(uncore, EIR);
3634
3635         if (*eir)
3636                 intel_uncore_write16(uncore, EIR, *eir);
3637
3638         *eir_stuck = intel_uncore_read16(uncore, EIR);
3639         if (*eir_stuck == 0)
3640                 return;
3641
3642         /*
3643          * Toggle all EMR bits to make sure we get an edge
3644          * in the ISR master error bit if we don't clear
3645          * all the EIR bits. Otherwise the edge triggered
3646          * IIR on i965/g4x wouldn't notice that an interrupt
3647          * is still pending. Also some EIR bits can't be
3648          * cleared except by handling the underlying error
3649          * (or by a GPU reset) so we mask any bit that
3650          * remains set.
3651          */
3652         emr = intel_uncore_read16(uncore, EMR);
3653         intel_uncore_write16(uncore, EMR, 0xffff);
3654         intel_uncore_write16(uncore, EMR, emr | *eir_stuck);
3655 }
3656
3657 static void i8xx_error_irq_handler(struct drm_i915_private *dev_priv,
3658                                    u16 eir, u16 eir_stuck)
3659 {
3660         DRM_DEBUG("Master Error: EIR 0x%04x\n", eir);
3661
3662         if (eir_stuck)
3663                 drm_dbg(&dev_priv->drm, "EIR stuck: 0x%04x, masked\n",
3664                         eir_stuck);
3665 }
3666
3667 static void i9xx_error_irq_ack(struct drm_i915_private *dev_priv,
3668                                u32 *eir, u32 *eir_stuck)
3669 {
3670         u32 emr;
3671
3672         *eir = I915_READ(EIR);
3673
3674         I915_WRITE(EIR, *eir);
3675
3676         *eir_stuck = I915_READ(EIR);
3677         if (*eir_stuck == 0)
3678                 return;
3679
3680         /*
3681          * Toggle all EMR bits to make sure we get an edge
3682          * in the ISR master error bit if we don't clear
3683          * all the EIR bits. Otherwise the edge triggered
3684          * IIR on i965/g4x wouldn't notice that an interrupt
3685          * is still pending. Also some EIR bits can't be
3686          * cleared except by handling the underlying error
3687          * (or by a GPU reset) so we mask any bit that
3688          * remains set.
3689          */
3690         emr = I915_READ(EMR);
3691         I915_WRITE(EMR, 0xffffffff);
3692         I915_WRITE(EMR, emr | *eir_stuck);
3693 }
3694
3695 static void i9xx_error_irq_handler(struct drm_i915_private *dev_priv,
3696                                    u32 eir, u32 eir_stuck)
3697 {
3698         DRM_DEBUG("Master Error, EIR 0x%08x\n", eir);
3699
3700         if (eir_stuck)
3701                 drm_dbg(&dev_priv->drm, "EIR stuck: 0x%08x, masked\n",
3702                         eir_stuck);
3703 }
3704
3705 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3706 {
3707         struct drm_i915_private *dev_priv = arg;
3708         irqreturn_t ret = IRQ_NONE;
3709
3710         if (!intel_irqs_enabled(dev_priv))
3711                 return IRQ_NONE;
3712
3713         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3714         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
3715
3716         do {
3717                 u32 pipe_stats[I915_MAX_PIPES] = {};
3718                 u16 eir = 0, eir_stuck = 0;
3719                 u16 iir;
3720
3721                 iir = intel_uncore_read16(&dev_priv->uncore, GEN2_IIR);
3722                 if (iir == 0)
3723                         break;
3724
3725                 ret = IRQ_HANDLED;
3726
3727                 /* Call regardless, as some status bits might not be
3728                  * signalled in iir */
3729                 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
3730
3731                 if (iir & I915_MASTER_ERROR_INTERRUPT)
3732                         i8xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
3733
3734                 intel_uncore_write16(&dev_priv->uncore, GEN2_IIR, iir);
3735
3736                 if (iir & I915_USER_INTERRUPT)
3737                         intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]);
3738
3739                 if (iir & I915_MASTER_ERROR_INTERRUPT)
3740                         i8xx_error_irq_handler(dev_priv, eir, eir_stuck);
3741
3742                 i8xx_pipestat_irq_handler(dev_priv, iir, pipe_stats);
3743         } while (0);
3744
3745         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
3746
3747         return ret;
3748 }
3749
3750 static void i915_irq_reset(struct drm_i915_private *dev_priv)
3751 {
3752         struct intel_uncore *uncore = &dev_priv->uncore;
3753
3754         if (I915_HAS_HOTPLUG(dev_priv)) {
3755                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3756                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3757         }
3758
3759         i9xx_pipestat_irq_reset(dev_priv);
3760
3761         GEN3_IRQ_RESET(uncore, GEN2_);
3762 }
3763
3764 static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
3765 {
3766         struct intel_uncore *uncore = &dev_priv->uncore;
3767         u32 enable_mask;
3768
3769         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE |
3770                           I915_ERROR_MEMORY_REFRESH));
3771
3772         /* Unmask the interrupts that we always want on. */
3773         dev_priv->irq_mask =
3774                 ~(I915_ASLE_INTERRUPT |
3775                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3776                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3777                   I915_MASTER_ERROR_INTERRUPT);
3778
3779         enable_mask =
3780                 I915_ASLE_INTERRUPT |
3781                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3782                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3783                 I915_MASTER_ERROR_INTERRUPT |
3784                 I915_USER_INTERRUPT;
3785
3786         if (I915_HAS_HOTPLUG(dev_priv)) {
3787                 /* Enable in IER... */
3788                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3789                 /* and unmask in IMR */
3790                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3791         }
3792
3793         GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);
3794
3795         /* Interrupt setup is already guaranteed to be single-threaded, this is
3796          * just to make the assert_spin_locked check happy. */
3797         spin_lock_irq(&dev_priv->irq_lock);
3798         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3799         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3800         spin_unlock_irq(&dev_priv->irq_lock);
3801
3802         i915_enable_asle_pipestat(dev_priv);
3803 }
3804
3805 static irqreturn_t i915_irq_handler(int irq, void *arg)
3806 {
3807         struct drm_i915_private *dev_priv = arg;
3808         irqreturn_t ret = IRQ_NONE;
3809
3810         if (!intel_irqs_enabled(dev_priv))
3811                 return IRQ_NONE;
3812
3813         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3814         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
3815
3816         do {
3817                 u32 pipe_stats[I915_MAX_PIPES] = {};
3818                 u32 eir = 0, eir_stuck = 0;
3819                 u32 hotplug_status = 0;
3820                 u32 iir;
3821
3822                 iir = I915_READ(GEN2_IIR);
3823                 if (iir == 0)
3824                         break;
3825
3826                 ret = IRQ_HANDLED;
3827
3828                 if (I915_HAS_HOTPLUG(dev_priv) &&
3829                     iir & I915_DISPLAY_PORT_INTERRUPT)
3830                         hotplug_status = i9xx_hpd_irq_ack(dev_priv);
3831
3832                 /* Call regardless, as some status bits might not be
3833                  * signalled in iir */
3834                 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
3835
3836                 if (iir & I915_MASTER_ERROR_INTERRUPT)
3837                         i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
3838
3839                 I915_WRITE(GEN2_IIR, iir);
3840
3841                 if (iir & I915_USER_INTERRUPT)
3842                         intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]);
3843
3844                 if (iir & I915_MASTER_ERROR_INTERRUPT)
3845                         i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
3846
3847                 if (hotplug_status)
3848                         i9xx_hpd_irq_handler(dev_priv, hotplug_status);
3849
3850                 i915_pipestat_irq_handler(dev_priv, iir, pipe_stats);
3851         } while (0);
3852
3853         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
3854
3855         return ret;
3856 }
3857
3858 static void i965_irq_reset(struct drm_i915_private *dev_priv)
3859 {
3860         struct intel_uncore *uncore = &dev_priv->uncore;
3861
3862         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3863         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3864
3865         i9xx_pipestat_irq_reset(dev_priv);
3866
3867         GEN3_IRQ_RESET(uncore, GEN2_);
3868 }
3869
3870 static void i965_irq_postinstall(struct drm_i915_private *dev_priv)
3871 {
3872         struct intel_uncore *uncore = &dev_priv->uncore;
3873         u32 enable_mask;
3874         u32 error_mask;
3875
3876         /*
3877          * Enable some error detection, note the instruction error mask
3878          * bit is reserved, so we leave it masked.
3879          */
3880         if (IS_G4X(dev_priv)) {
3881                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3882                                GM45_ERROR_MEM_PRIV |
3883                                GM45_ERROR_CP_PRIV |
3884                                I915_ERROR_MEMORY_REFRESH);
3885         } else {
3886                 error_mask = ~(I915_ERROR_PAGE_TABLE |
3887                                I915_ERROR_MEMORY_REFRESH);
3888         }
3889         I915_WRITE(EMR, error_mask);
3890
3891         /* Unmask the interrupts that we always want on. */
3892         dev_priv->irq_mask =
3893                 ~(I915_ASLE_INTERRUPT |
3894                   I915_DISPLAY_PORT_INTERRUPT |
3895                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3896                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3897                   I915_MASTER_ERROR_INTERRUPT);
3898
3899         enable_mask =
3900                 I915_ASLE_INTERRUPT |
3901                 I915_DISPLAY_PORT_INTERRUPT |
3902                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3903                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3904                 I915_MASTER_ERROR_INTERRUPT |
3905                 I915_USER_INTERRUPT;
3906
3907         if (IS_G4X(dev_priv))
3908                 enable_mask |= I915_BSD_USER_INTERRUPT;
3909
3910         GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);
3911
3912         /* Interrupt setup is already guaranteed to be single-threaded, this is
3913          * just to make the assert_spin_locked check happy. */
3914         spin_lock_irq(&dev_priv->irq_lock);
3915         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3916         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3917         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3918         spin_unlock_irq(&dev_priv->irq_lock);
3919
3920         i915_enable_asle_pipestat(dev_priv);
3921 }
3922
3923 static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
3924 {
3925         u32 hotplug_en;
3926
3927         lockdep_assert_held(&dev_priv->irq_lock);
3928
3929         /* Note HDMI and DP share hotplug bits */
3930         /* enable bits are the same for all generations */
3931         hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);
3932         /* Programming the CRT detection parameters tends
3933            to generate a spurious hotplug event about three
3934            seconds later.  So just do it once.
3935         */
3936         if (IS_G4X(dev_priv))
3937                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
3938         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
3939
3940         /* Ignore TV since it's buggy */
3941         i915_hotplug_interrupt_update_locked(dev_priv,
3942                                              HOTPLUG_INT_EN_MASK |
3943                                              CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
3944                                              CRT_HOTPLUG_ACTIVATION_PERIOD_64,
3945                                              hotplug_en);
3946 }
3947
3948 static irqreturn_t i965_irq_handler(int irq, void *arg)
3949 {
3950         struct drm_i915_private *dev_priv = arg;
3951         irqreturn_t ret = IRQ_NONE;
3952
3953         if (!intel_irqs_enabled(dev_priv))
3954                 return IRQ_NONE;
3955
3956         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3957         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
3958
3959         do {
3960                 u32 pipe_stats[I915_MAX_PIPES] = {};
3961                 u32 eir = 0, eir_stuck = 0;
3962                 u32 hotplug_status = 0;
3963                 u32 iir;
3964
3965                 iir = I915_READ(GEN2_IIR);
3966                 if (iir == 0)
3967                         break;
3968
3969                 ret = IRQ_HANDLED;
3970
3971                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
3972                         hotplug_status = i9xx_hpd_irq_ack(dev_priv);
3973
3974                 /* Call regardless, as some status bits might not be
3975                  * signalled in iir */
3976                 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
3977
3978                 if (iir & I915_MASTER_ERROR_INTERRUPT)
3979                         i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
3980
3981                 I915_WRITE(GEN2_IIR, iir);
3982
3983                 if (iir & I915_USER_INTERRUPT)
3984                         intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]);
3985
3986                 if (iir & I915_BSD_USER_INTERRUPT)
3987                         intel_engine_signal_breadcrumbs(dev_priv->gt.engine[VCS0]);
3988
3989                 if (iir & I915_MASTER_ERROR_INTERRUPT)
3990                         i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
3991
3992                 if (hotplug_status)
3993                         i9xx_hpd_irq_handler(dev_priv, hotplug_status);
3994
3995                 i965_pipestat_irq_handler(dev_priv, iir, pipe_stats);
3996         } while (0);
3997
3998         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
3999
4000         return ret;
4001 }
4002
4003 /**
4004  * intel_irq_init - initializes irq support
4005  * @dev_priv: i915 device instance
4006  *
4007  * This function initializes all the irq support including work items, timers
4008  * and all the vtables. It does not setup the interrupt itself though.
4009  */
4010 void intel_irq_init(struct drm_i915_private *dev_priv)
4011 {
4012         struct drm_device *dev = &dev_priv->drm;
4013         int i;
4014
4015         intel_hpd_init_pins(dev_priv);
4016
4017         intel_hpd_init_work(dev_priv);
4018
4019         INIT_WORK(&dev_priv->l3_parity.error_work, ivb_parity_work);
4020         for (i = 0; i < MAX_L3_SLICES; ++i)
4021                 dev_priv->l3_parity.remap_info[i] = NULL;
4022
4023         /* pre-gen11 the guc irqs bits are in the upper 16 bits of the pm reg */
4024         if (HAS_GT_UC(dev_priv) && INTEL_GEN(dev_priv) < 11)
4025                 dev_priv->gt.pm_guc_events = GUC_INTR_GUC2HOST << 16;
4026
4027         dev->vblank_disable_immediate = true;
4028
4029         /* Most platforms treat the display irq block as an always-on
4030          * power domain. vlv/chv can disable it at runtime and need
4031          * special care to avoid writing any of the display block registers
4032          * outside of the power domain. We defer setting up the display irqs
4033          * in this case to the runtime pm.
4034          */
4035         dev_priv->display_irqs_enabled = true;
4036         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4037                 dev_priv->display_irqs_enabled = false;
4038
4039         dev_priv->hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD;
4040         /* If we have MST support, we want to avoid doing short HPD IRQ storm
4041          * detection, as short HPD storms will occur as a natural part of
4042          * sideband messaging with MST.
4043          * On older platforms however, IRQ storms can occur with both long and
4044          * short pulses, as seen on some G4x systems.
4045          */
4046         dev_priv->hotplug.hpd_short_storm_enabled = !HAS_DP_MST(dev_priv);
4047
4048         if (HAS_GMCH(dev_priv)) {
4049                 if (I915_HAS_HOTPLUG(dev_priv))
4050                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4051         } else {
4052                 if (HAS_PCH_JSP(dev_priv))
4053                         dev_priv->display.hpd_irq_setup = jsp_hpd_irq_setup;
4054                 else if (HAS_PCH_MCC(dev_priv))
4055                         dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup;
4056                 else if (INTEL_GEN(dev_priv) >= 11)
4057                         dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
4058                 else if (IS_GEN9_LP(dev_priv))
4059                         dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4060                 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
4061                         dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4062                 else
4063                         dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4064         }
4065 }
4066
4067 /**
4068  * intel_irq_fini - deinitializes IRQ support
4069  * @i915: i915 device instance
4070  *
4071  * This function deinitializes all the IRQ support.
4072  */
4073 void intel_irq_fini(struct drm_i915_private *i915)
4074 {
4075         int i;
4076
4077         for (i = 0; i < MAX_L3_SLICES; ++i)
4078                 kfree(i915->l3_parity.remap_info[i]);
4079 }
4080
4081 static irq_handler_t intel_irq_handler(struct drm_i915_private *dev_priv)
4082 {
4083         if (HAS_GMCH(dev_priv)) {
4084                 if (IS_CHERRYVIEW(dev_priv))
4085                         return cherryview_irq_handler;
4086                 else if (IS_VALLEYVIEW(dev_priv))
4087                         return valleyview_irq_handler;
4088                 else if (IS_GEN(dev_priv, 4))
4089                         return i965_irq_handler;
4090                 else if (IS_GEN(dev_priv, 3))
4091                         return i915_irq_handler;
4092                 else
4093                         return i8xx_irq_handler;
4094         } else {
4095                 if (HAS_MASTER_UNIT_IRQ(dev_priv))
4096                         return dg1_irq_handler;
4097                 if (INTEL_GEN(dev_priv) >= 11)
4098                         return gen11_irq_handler;
4099                 else if (INTEL_GEN(dev_priv) >= 8)
4100                         return gen8_irq_handler;
4101                 else
4102                         return ilk_irq_handler;
4103         }
4104 }
4105
4106 static void intel_irq_reset(struct drm_i915_private *dev_priv)
4107 {
4108         if (HAS_GMCH(dev_priv)) {
4109                 if (IS_CHERRYVIEW(dev_priv))
4110                         cherryview_irq_reset(dev_priv);
4111                 else if (IS_VALLEYVIEW(dev_priv))
4112                         valleyview_irq_reset(dev_priv);
4113                 else if (IS_GEN(dev_priv, 4))
4114                         i965_irq_reset(dev_priv);
4115                 else if (IS_GEN(dev_priv, 3))
4116                         i915_irq_reset(dev_priv);
4117                 else
4118                         i8xx_irq_reset(dev_priv);
4119         } else {
4120                 if (INTEL_GEN(dev_priv) >= 11)
4121                         gen11_irq_reset(dev_priv);
4122                 else if (INTEL_GEN(dev_priv) >= 8)
4123                         gen8_irq_reset(dev_priv);
4124                 else
4125                         ilk_irq_reset(dev_priv);
4126         }
4127 }
4128
4129 static void intel_irq_postinstall(struct drm_i915_private *dev_priv)
4130 {
4131         if (HAS_GMCH(dev_priv)) {
4132                 if (IS_CHERRYVIEW(dev_priv))
4133                         cherryview_irq_postinstall(dev_priv);
4134                 else if (IS_VALLEYVIEW(dev_priv))
4135                         valleyview_irq_postinstall(dev_priv);
4136                 else if (IS_GEN(dev_priv, 4))
4137                         i965_irq_postinstall(dev_priv);
4138                 else if (IS_GEN(dev_priv, 3))
4139                         i915_irq_postinstall(dev_priv);
4140                 else
4141                         i8xx_irq_postinstall(dev_priv);
4142         } else {
4143                 if (INTEL_GEN(dev_priv) >= 11)
4144                         gen11_irq_postinstall(dev_priv);
4145                 else if (INTEL_GEN(dev_priv) >= 8)
4146                         gen8_irq_postinstall(dev_priv);
4147                 else
4148                         ilk_irq_postinstall(dev_priv);
4149         }
4150 }
4151
4152 /**
4153  * intel_irq_install - enables the hardware interrupt
4154  * @dev_priv: i915 device instance
4155  *
4156  * This function enables the hardware interrupt handling, but leaves the hotplug
4157  * handling still disabled. It is called after intel_irq_init().
4158  *
4159  * In the driver load and resume code we need working interrupts in a few places
4160  * but don't want to deal with the hassle of concurrent probe and hotplug
4161  * workers. Hence the split into this two-stage approach.
4162  */
4163 int intel_irq_install(struct drm_i915_private *dev_priv)
4164 {
4165         int irq = dev_priv->drm.pdev->irq;
4166         int ret;
4167
4168         /*
4169          * We enable some interrupt sources in our postinstall hooks, so mark
4170          * interrupts as enabled _before_ actually enabling them to avoid
4171          * special cases in our ordering checks.
4172          */
4173         dev_priv->runtime_pm.irqs_enabled = true;
4174
4175         dev_priv->drm.irq_enabled = true;
4176
4177         intel_irq_reset(dev_priv);
4178
4179         ret = request_irq(irq, intel_irq_handler(dev_priv),
4180                           IRQF_SHARED, DRIVER_NAME, dev_priv);
4181         if (ret < 0) {
4182                 dev_priv->drm.irq_enabled = false;
4183                 return ret;
4184         }
4185
4186         intel_irq_postinstall(dev_priv);
4187
4188         return ret;
4189 }
4190
4191 /**
4192  * intel_irq_uninstall - finilizes all irq handling
4193  * @dev_priv: i915 device instance
4194  *
4195  * This stops interrupt and hotplug handling and unregisters and frees all
4196  * resources acquired in the init functions.
4197  */
4198 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4199 {
4200         int irq = dev_priv->drm.pdev->irq;
4201
4202         /*
4203          * FIXME we can get called twice during driver probe
4204          * error handling as well as during driver remove due to
4205          * intel_modeset_driver_remove() calling us out of sequence.
4206          * Would be nice if it didn't do that...
4207          */
4208         if (!dev_priv->drm.irq_enabled)
4209                 return;
4210
4211         dev_priv->drm.irq_enabled = false;
4212
4213         intel_irq_reset(dev_priv);
4214
4215         free_irq(irq, dev_priv);
4216
4217         intel_hpd_cancel_work(dev_priv);
4218         dev_priv->runtime_pm.irqs_enabled = false;
4219 }
4220
4221 /**
4222  * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4223  * @dev_priv: i915 device instance
4224  *
4225  * This function is used to disable interrupts at runtime, both in the runtime
4226  * pm and the system suspend/resume code.
4227  */
4228 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4229 {
4230         intel_irq_reset(dev_priv);
4231         dev_priv->runtime_pm.irqs_enabled = false;
4232         intel_synchronize_irq(dev_priv);
4233 }
4234
4235 /**
4236  * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4237  * @dev_priv: i915 device instance
4238  *
4239  * This function is used to enable interrupts at runtime, both in the runtime
4240  * pm and the system suspend/resume code.
4241  */
4242 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4243 {
4244         dev_priv->runtime_pm.irqs_enabled = true;
4245         intel_irq_reset(dev_priv);
4246         intel_irq_postinstall(dev_priv);
4247 }
4248
4249 bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
4250 {
4251         /*
4252          * We only use drm_irq_uninstall() at unload and VT switch, so
4253          * this is the only thing we need to check.
4254          */
4255         return dev_priv->runtime_pm.irqs_enabled;
4256 }
4257
4258 void intel_synchronize_irq(struct drm_i915_private *i915)
4259 {
4260         synchronize_irq(i915->drm.pdev->irq);
4261 }