drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include "drmP.h"
  34 #include "drm.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "intel_drv.h"
  39
  40 /* For display hotplug interrupt */
  41 static void
  42 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  43 {
  44         if ((dev_priv->irq_mask & mask) != 0) {
  45                 dev_priv->irq_mask &= ~mask;
  46                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  47                 POSTING_READ(DEIMR);
  48         }
  49 }
  50
  51 static inline void
  52 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  53 {
  54         if ((dev_priv->irq_mask & mask) != mask) {
  55                 dev_priv->irq_mask |= mask;
  56                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  57                 POSTING_READ(DEIMR);
  58         }
  59 }
  60
  61 void
  62 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  63 {
  64         if ((dev_priv->pipestat[pipe] & mask) != mask) {
  65                 u32 reg = PIPESTAT(pipe);
  66
  67                 dev_priv->pipestat[pipe] |= mask;
  68                 /* Enable the interrupt, clear any pending status */
  69                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
  70                 POSTING_READ(reg);
  71         }
  72 }
  73
  74 void
  75 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  76 {
  77         if ((dev_priv->pipestat[pipe] & mask) != 0) {
  78                 u32 reg = PIPESTAT(pipe);
  79
  80                 dev_priv->pipestat[pipe] &= ~mask;
  81                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
  82                 POSTING_READ(reg);
  83         }
  84 }
  85
  86 /**
  87  * intel_enable_asle - enable ASLE interrupt for OpRegion
  88  */
  89 void intel_enable_asle(struct drm_device *dev)
  90 {
  91         drm_i915_private_t *dev_priv = dev->dev_private;
  92         unsigned long irqflags;
  93
  94         /* FIXME: opregion/asle for VLV */
  95         if (IS_VALLEYVIEW(dev))
  96                 return;
  97
  98         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  99
 100         if (HAS_PCH_SPLIT(dev))
 101                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 102         else {
 103                 i915_enable_pipestat(dev_priv, 1,
 104                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
 105                 if (INTEL_INFO(dev)->gen >= 4)
 106                         i915_enable_pipestat(dev_priv, 0,
 107                                              PIPE_LEGACY_BLC_EVENT_ENABLE);
 108         }
 109
 110         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 111 }
 112
 113 /**
 114  * i915_pipe_enabled - check if a pipe is enabled
 115  * @dev: DRM device
 116  * @pipe: pipe to check
 117  *
 118  * Reading certain registers when the pipe is disabled can hang the chip.
 119  * Use this routine to make sure the PLL is running and the pipe is active
 120  * before reading such registers if unsure.
 121  */
 122 static int
 123 i915_pipe_enabled(struct drm_device *dev, int pipe)
 124 {
 125         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 126         return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
 127 }
 128
 129 /* Called from drm generic code, passed a 'crtc', which
 130  * we use as a pipe index
 131  */
 132 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 133 {
 134         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 135         unsigned long high_frame;
 136         unsigned long low_frame;
 137         u32 high1, high2, low;
 138
 139         if (!i915_pipe_enabled(dev, pipe)) {
 140                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 141                                 "pipe %c\n", pipe_name(pipe));
 142                 return 0;
 143         }
 144
 145         high_frame = PIPEFRAME(pipe);
 146         low_frame = PIPEFRAMEPIXEL(pipe);
 147
 148         /*
 149          * High & low register fields aren't synchronized, so make sure
 150          * we get a low value that's stable across two reads of the high
 151          * register.
 152          */
 153         do {
 154                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 155                 low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
 156                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 157         } while (high1 != high2);
 158
 159         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 160         low >>= PIPE_FRAME_LOW_SHIFT;
 161         return (high1 << 8) | low;
 162 }
 163
 164 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 165 {
 166         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 167         int reg = PIPE_FRMCOUNT_GM45(pipe);
 168
 169         if (!i915_pipe_enabled(dev, pipe)) {
 170                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 171                                  "pipe %c\n", pipe_name(pipe));
 172                 return 0;
 173         }
 174
 175         return I915_READ(reg);
 176 }
 177
 178 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 179                              int *vpos, int *hpos)
 180 {
 181         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 182         u32 vbl = 0, position = 0;
 183         int vbl_start, vbl_end, htotal, vtotal;
 184         bool in_vbl = true;
 185         int ret = 0;
 186
 187         if (!i915_pipe_enabled(dev, pipe)) {
 188                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 189                                  "pipe %c\n", pipe_name(pipe));
 190                 return 0;
 191         }
 192
 193         /* Get vtotal. */
 194         vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
 195
 196         if (INTEL_INFO(dev)->gen >= 4) {
 197                 /* No obvious pixelcount register. Only query vertical
 198                  * scanout position from Display scan line register.
 199                  */
 200                 position = I915_READ(PIPEDSL(pipe));
 201
 202                 /* Decode into vertical scanout position. Don't have
 203                  * horizontal scanout position.
 204                  */
 205                 *vpos = position & 0x1fff;
 206                 *hpos = 0;
 207         } else {
 208                 /* Have access to pixelcount since start of frame.
 209                  * We can split this into vertical and horizontal
 210                  * scanout position.
 211                  */
 212                 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 213
 214                 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
 215                 *vpos = position / htotal;
 216                 *hpos = position - (*vpos * htotal);
 217         }
 218
 219         /* Query vblank area. */
 220         vbl = I915_READ(VBLANK(pipe));
 221
 222         /* Test position against vblank region. */
 223         vbl_start = vbl & 0x1fff;
 224         vbl_end = (vbl >> 16) & 0x1fff;
 225
 226         if ((*vpos < vbl_start) || (*vpos > vbl_end))
 227                 in_vbl = false;
 228
 229         /* Inside "upper part" of vblank area? Apply corrective offset: */
 230         if (in_vbl && (*vpos >= vbl_start))
 231                 *vpos = *vpos - vtotal;
 232
 233         /* Readouts valid? */
 234         if (vbl > 0)
 235                 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 236
 237         /* In vblank? */
 238         if (in_vbl)
 239                 ret |= DRM_SCANOUTPOS_INVBL;
 240
 241         return ret;
 242 }
 243
 244 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
 245                               int *max_error,
 246                               struct timeval *vblank_time,
 247                               unsigned flags)
 248 {
 249         struct drm_i915_private *dev_priv = dev->dev_private;
 250         struct drm_crtc *crtc;
 251
 252         if (pipe < 0 || pipe >= dev_priv->num_pipe) {
 253                 DRM_ERROR("Invalid crtc %d\n", pipe);
 254                 return -EINVAL;
 255         }
 256
 257         /* Get drm_crtc to timestamp: */
 258         crtc = intel_get_crtc_for_pipe(dev, pipe);
 259         if (crtc == NULL) {
 260                 DRM_ERROR("Invalid crtc %d\n", pipe);
 261                 return -EINVAL;
 262         }
 263
 264         if (!crtc->enabled) {
 265                 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
 266                 return -EBUSY;
 267         }
 268
 269         /* Helper routine in DRM core does all the work: */
 270         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 271                                                      vblank_time, flags,
 272                                                      crtc);
 273 }
 274
 275 /*
 276  * Handle hotplug events outside the interrupt handler proper.
 277  */
 278 static void i915_hotplug_work_func(struct work_struct *work)
 279 {
 280         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 281                                                     hotplug_work);
 282         struct drm_device *dev = dev_priv->dev;
 283         struct drm_mode_config *mode_config = &dev->mode_config;
 284         struct intel_encoder *encoder;
 285
 286         mutex_lock(&mode_config->mutex);
 287         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 288
 289         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 290                 if (encoder->hot_plug)
 291                         encoder->hot_plug(encoder);
 292
 293         mutex_unlock(&mode_config->mutex);
 294
 295         /* Just fire off a uevent and let userspace tell us what to do */
 296         drm_helper_hpd_irq_event(dev);
 297 }
 298
 299 /* defined intel_pm.c */
 300 extern spinlock_t mchdev_lock;
 301
 302 static void ironlake_handle_rps_change(struct drm_device *dev)
 303 {
 304         drm_i915_private_t *dev_priv = dev->dev_private;
 305         u32 busy_up, busy_down, max_avg, min_avg;
 306         u8 new_delay;
 307         unsigned long flags;
 308
 309         spin_lock_irqsave(&mchdev_lock, flags);
 310
 311         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 312
 313         new_delay = dev_priv->cur_delay;
 314
 315         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 316         busy_up = I915_READ(RCPREVBSYTUPAVG);
 317         busy_down = I915_READ(RCPREVBSYTDNAVG);
 318         max_avg = I915_READ(RCBMAXAVG);
 319         min_avg = I915_READ(RCBMINAVG);
 320
 321         /* Handle RCS change request from hw */
 322         if (busy_up > max_avg) {
 323                 if (dev_priv->cur_delay != dev_priv->max_delay)
 324                         new_delay = dev_priv->cur_delay - 1;
 325                 if (new_delay < dev_priv->max_delay)
 326                         new_delay = dev_priv->max_delay;
 327         } else if (busy_down < min_avg) {
 328                 if (dev_priv->cur_delay != dev_priv->min_delay)
 329                         new_delay = dev_priv->cur_delay + 1;
 330                 if (new_delay > dev_priv->min_delay)
 331                         new_delay = dev_priv->min_delay;
 332         }
 333
 334         if (ironlake_set_drps(dev, new_delay))
 335                 dev_priv->cur_delay = new_delay;
 336
 337         spin_unlock_irqrestore(&mchdev_lock, flags);
 338
 339         return;
 340 }
 341
 342 static void notify_ring(struct drm_device *dev,
 343                         struct intel_ring_buffer *ring)
 344 {
 345         struct drm_i915_private *dev_priv = dev->dev_private;
 346
 347         if (ring->obj == NULL)
 348                 return;
 349
 350         trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
 351
 352         wake_up_all(&ring->irq_queue);
 353         if (i915_enable_hangcheck) {
 354                 dev_priv->hangcheck_count = 0;
 355                 mod_timer(&dev_priv->hangcheck_timer,
 356                           jiffies +
 357                           msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
 358         }
 359 }
 360
 361 static void gen6_pm_rps_work(struct work_struct *work)
 362 {
 363         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 364                                                     rps.work);
 365         u32 pm_iir, pm_imr;
 366         u8 new_delay;
 367
 368         spin_lock_irq(&dev_priv->rps.lock);
 369         pm_iir = dev_priv->rps.pm_iir;
 370         dev_priv->rps.pm_iir = 0;
 371         pm_imr = I915_READ(GEN6_PMIMR);
 372         I915_WRITE(GEN6_PMIMR, 0);
 373         spin_unlock_irq(&dev_priv->rps.lock);
 374
 375         if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
 376                 return;
 377
 378         mutex_lock(&dev_priv->dev->struct_mutex);
 379
 380         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
 381                 new_delay = dev_priv->rps.cur_delay + 1;
 382         else
 383                 new_delay = dev_priv->rps.cur_delay - 1;
 384
 385         gen6_set_rps(dev_priv->dev, new_delay);
 386
 387         mutex_unlock(&dev_priv->dev->struct_mutex);
 388 }
 389
 390
 391 /**
 392  * ivybridge_parity_work - Workqueue called when a parity error interrupt
 393  * occurred.
 394  * @work: workqueue struct
 395  *
 396  * Doesn't actually do anything except notify userspace. As a consequence of
 397  * this event, userspace should try to remap the bad rows since statistically
 398  * it is likely the same row is more likely to go bad again.
 399  */
 400 static void ivybridge_parity_work(struct work_struct *work)
 401 {
 402         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 403                                                     parity_error_work);
 404         u32 error_status, row, bank, subbank;
 405         char *parity_event[5];
 406         uint32_t misccpctl;
 407         unsigned long flags;
 408
 409         /* We must turn off DOP level clock gating to access the L3 registers.
 410          * In order to prevent a get/put style interface, acquire struct mutex
 411          * any time we access those registers.
 412          */
 413         mutex_lock(&dev_priv->dev->struct_mutex);
 414
 415         misccpctl = I915_READ(GEN7_MISCCPCTL);
 416         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
 417         POSTING_READ(GEN7_MISCCPCTL);
 418
 419         error_status = I915_READ(GEN7_L3CDERRST1);
 420         row = GEN7_PARITY_ERROR_ROW(error_status);
 421         bank = GEN7_PARITY_ERROR_BANK(error_status);
 422         subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
 423
 424         I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
 425                                     GEN7_L3CDERRST1_ENABLE);
 426         POSTING_READ(GEN7_L3CDERRST1);
 427
 428         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
 429
 430         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 431         dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
 432         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 433         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 434
 435         mutex_unlock(&dev_priv->dev->struct_mutex);
 436
 437         parity_event[0] = "L3_PARITY_ERROR=1";
 438         parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
 439         parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
 440         parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
 441         parity_event[4] = NULL;
 442
 443         kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
 444                            KOBJ_CHANGE, parity_event);
 445
 446         DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
 447                   row, bank, subbank);
 448
 449         kfree(parity_event[3]);
 450         kfree(parity_event[2]);
 451         kfree(parity_event[1]);
 452 }
 453
 454 static void ivybridge_handle_parity_error(struct drm_device *dev)
 455 {
 456         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 457         unsigned long flags;
 458
 459         if (!HAS_L3_GPU_CACHE(dev))
 460                 return;
 461
 462         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 463         dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
 464         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 465         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 466
 467         queue_work(dev_priv->wq, &dev_priv->parity_error_work);
 468 }
 469
 470 static void snb_gt_irq_handler(struct drm_device *dev,
 471                                struct drm_i915_private *dev_priv,
 472                                u32 gt_iir)
 473 {
 474
 475         if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
 476                       GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
 477                 notify_ring(dev, &dev_priv->ring[RCS]);
 478         if (gt_iir & GEN6_BSD_USER_INTERRUPT)
 479                 notify_ring(dev, &dev_priv->ring[VCS]);
 480         if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
 481                 notify_ring(dev, &dev_priv->ring[BCS]);
 482
 483         if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
 484                       GT_GEN6_BSD_CS_ERROR_INTERRUPT |
 485                       GT_RENDER_CS_ERROR_INTERRUPT)) {
 486                 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
 487                 i915_handle_error(dev, false);
 488         }
 489
 490         if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
 491                 ivybridge_handle_parity_error(dev);
 492 }
 493
 494 static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
 495                                 u32 pm_iir)
 496 {
 497         unsigned long flags;
 498
 499         /*
 500          * IIR bits should never already be set because IMR should
 501          * prevent an interrupt from being shown in IIR. The warning
 502          * displays a case where we've unsafely cleared
 503          * dev_priv->rps.pm_iir. Although missing an interrupt of the same
 504          * type is not a problem, it displays a problem in the logic.
 505          *
 506          * The mask bit in IMR is cleared by dev_priv->rps.work.
 507          */
 508
 509         spin_lock_irqsave(&dev_priv->rps.lock, flags);
 510         WARN(dev_priv->rps.pm_iir & pm_iir, "Missed a PM interrupt\n");
 511         dev_priv->rps.pm_iir |= pm_iir;
 512         I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
 513         POSTING_READ(GEN6_PMIMR);
 514         spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
 515
 516         queue_work(dev_priv->wq, &dev_priv->rps.work);
 517 }
 518
 519 static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS)
 520 {
 521         struct drm_device *dev = (struct drm_device *) arg;
 522         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 523         u32 iir, gt_iir, pm_iir;
 524         irqreturn_t ret = IRQ_NONE;
 525         unsigned long irqflags;
 526         int pipe;
 527         u32 pipe_stats[I915_MAX_PIPES];
 528         bool blc_event;
 529
 530         atomic_inc(&dev_priv->irq_received);
 531
 532         while (true) {
 533                 iir = I915_READ(VLV_IIR);
 534                 gt_iir = I915_READ(GTIIR);
 535                 pm_iir = I915_READ(GEN6_PMIIR);
 536
 537                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
 538                         goto out;
 539
 540                 ret = IRQ_HANDLED;
 541
 542                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 543
 544                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 545                 for_each_pipe(pipe) {
 546                         int reg = PIPESTAT(pipe);
 547                         pipe_stats[pipe] = I915_READ(reg);
 548
 549                         /*
 550                          * Clear the PIPE*STAT regs before the IIR
 551                          */
 552                         if (pipe_stats[pipe] & 0x8000ffff) {
 553                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
 554                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
 555                                                          pipe_name(pipe));
 556                                 I915_WRITE(reg, pipe_stats[pipe]);
 557                         }
 558                 }
 559                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 560
 561                 for_each_pipe(pipe) {
 562                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
 563                                 drm_handle_vblank(dev, pipe);
 564
 565                         if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
 566                                 intel_prepare_page_flip(dev, pipe);
 567                                 intel_finish_page_flip(dev, pipe);
 568                         }
 569                 }
 570
 571                 /* Consume port.  Then clear IIR or we'll miss events */
 572                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
 573                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
 574
 575                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
 576                                          hotplug_status);
 577                         if (hotplug_status & dev_priv->hotplug_supported_mask)
 578                                 queue_work(dev_priv->wq,
 579                                            &dev_priv->hotplug_work);
 580
 581                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
 582                         I915_READ(PORT_HOTPLUG_STAT);
 583                 }
 584
 585                 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
 586                         blc_event = true;
 587
 588                 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
 589                         gen6_queue_rps_work(dev_priv, pm_iir);
 590
 591                 I915_WRITE(GTIIR, gt_iir);
 592                 I915_WRITE(GEN6_PMIIR, pm_iir);
 593                 I915_WRITE(VLV_IIR, iir);
 594         }
 595
 596 out:
 597         return ret;
 598 }
 599
 600 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
 601 {
 602         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 603         int pipe;
 604
 605         if (pch_iir & SDE_AUDIO_POWER_MASK)
 606                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
 607                                  (pch_iir & SDE_AUDIO_POWER_MASK) >>
 608                                  SDE_AUDIO_POWER_SHIFT);
 609
 610         if (pch_iir & SDE_GMBUS)
 611                 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
 612
 613         if (pch_iir & SDE_AUDIO_HDCP_MASK)
 614                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
 615
 616         if (pch_iir & SDE_AUDIO_TRANS_MASK)
 617                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
 618
 619         if (pch_iir & SDE_POISON)
 620                 DRM_ERROR("PCH poison interrupt\n");
 621
 622         if (pch_iir & SDE_FDI_MASK)
 623                 for_each_pipe(pipe)
 624                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
 625                                          pipe_name(pipe),
 626                                          I915_READ(FDI_RX_IIR(pipe)));
 627
 628         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
 629                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
 630
 631         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
 632                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
 633
 634         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
 635                 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
 636         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
 637                 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
 638 }
 639
 640 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
 641 {
 642         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 643         int pipe;
 644
 645         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
 646                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
 647                                  (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
 648                                  SDE_AUDIO_POWER_SHIFT_CPT);
 649
 650         if (pch_iir & SDE_AUX_MASK_CPT)
 651                 DRM_DEBUG_DRIVER("AUX channel interrupt\n");
 652
 653         if (pch_iir & SDE_GMBUS_CPT)
 654                 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
 655
 656         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
 657                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
 658
 659         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
 660                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
 661
 662         if (pch_iir & SDE_FDI_MASK_CPT)
 663                 for_each_pipe(pipe)
 664                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
 665                                          pipe_name(pipe),
 666                                          I915_READ(FDI_RX_IIR(pipe)));
 667 }
 668
 669 static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
 670 {
 671         struct drm_device *dev = (struct drm_device *) arg;
 672         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 673         u32 de_iir, gt_iir, de_ier, pm_iir;
 674         irqreturn_t ret = IRQ_NONE;
 675         int i;
 676
 677         atomic_inc(&dev_priv->irq_received);
 678
 679         /* disable master interrupt before clearing iir  */
 680         de_ier = I915_READ(DEIER);
 681         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 682
 683         gt_iir = I915_READ(GTIIR);
 684         if (gt_iir) {
 685                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 686                 I915_WRITE(GTIIR, gt_iir);
 687                 ret = IRQ_HANDLED;
 688         }
 689
 690         de_iir = I915_READ(DEIIR);
 691         if (de_iir) {
 692                 if (de_iir & DE_GSE_IVB)
 693                         intel_opregion_gse_intr(dev);
 694
 695                 for (i = 0; i < 3; i++) {
 696                         if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
 697                                 intel_prepare_page_flip(dev, i);
 698                                 intel_finish_page_flip_plane(dev, i);
 699                         }
 700                         if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
 701                                 drm_handle_vblank(dev, i);
 702                 }
 703
 704                 /* check event from PCH */
 705                 if (de_iir & DE_PCH_EVENT_IVB) {
 706                         u32 pch_iir = I915_READ(SDEIIR);
 707
 708                         if (pch_iir & SDE_HOTPLUG_MASK_CPT)
 709                                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 710                         cpt_irq_handler(dev, pch_iir);
 711
 712                         /* clear PCH hotplug event before clear CPU irq */
 713                         I915_WRITE(SDEIIR, pch_iir);
 714                 }
 715
 716                 I915_WRITE(DEIIR, de_iir);
 717                 ret = IRQ_HANDLED;
 718         }
 719
 720         pm_iir = I915_READ(GEN6_PMIIR);
 721         if (pm_iir) {
 722                 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
 723                         gen6_queue_rps_work(dev_priv, pm_iir);
 724                 I915_WRITE(GEN6_PMIIR, pm_iir);
 725                 ret = IRQ_HANDLED;
 726         }
 727
 728         I915_WRITE(DEIER, de_ier);
 729         POSTING_READ(DEIER);
 730
 731         return ret;
 732 }
 733
 734 static void ilk_gt_irq_handler(struct drm_device *dev,
 735                                struct drm_i915_private *dev_priv,
 736                                u32 gt_iir)
 737 {
 738         if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
 739                 notify_ring(dev, &dev_priv->ring[RCS]);
 740         if (gt_iir & GT_BSD_USER_INTERRUPT)
 741                 notify_ring(dev, &dev_priv->ring[VCS]);
 742 }
 743
 744 static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
 745 {
 746         struct drm_device *dev = (struct drm_device *) arg;
 747         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 748         int ret = IRQ_NONE;
 749         u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
 750         u32 hotplug_mask;
 751
 752         atomic_inc(&dev_priv->irq_received);
 753
 754         /* disable master interrupt before clearing iir  */
 755         de_ier = I915_READ(DEIER);
 756         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 757         POSTING_READ(DEIER);
 758
 759         de_iir = I915_READ(DEIIR);
 760         gt_iir = I915_READ(GTIIR);
 761         pch_iir = I915_READ(SDEIIR);
 762         pm_iir = I915_READ(GEN6_PMIIR);
 763
 764         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
 765             (!IS_GEN6(dev) || pm_iir == 0))
 766                 goto done;
 767
 768         if (HAS_PCH_CPT(dev))
 769                 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
 770         else
 771                 hotplug_mask = SDE_HOTPLUG_MASK;
 772
 773         ret = IRQ_HANDLED;
 774
 775         if (IS_GEN5(dev))
 776                 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
 777         else
 778                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 779
 780         if (de_iir & DE_GSE)
 781                 intel_opregion_gse_intr(dev);
 782
 783         if (de_iir & DE_PLANEA_FLIP_DONE) {
 784                 intel_prepare_page_flip(dev, 0);
 785                 intel_finish_page_flip_plane(dev, 0);
 786         }
 787
 788         if (de_iir & DE_PLANEB_FLIP_DONE) {
 789                 intel_prepare_page_flip(dev, 1);
 790                 intel_finish_page_flip_plane(dev, 1);
 791         }
 792
 793         if (de_iir & DE_PIPEA_VBLANK)
 794                 drm_handle_vblank(dev, 0);
 795
 796         if (de_iir & DE_PIPEB_VBLANK)
 797                 drm_handle_vblank(dev, 1);
 798
 799         /* check event from PCH */
 800         if (de_iir & DE_PCH_EVENT) {
 801                 if (pch_iir & hotplug_mask)
 802                         queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 803                 if (HAS_PCH_CPT(dev))
 804                         cpt_irq_handler(dev, pch_iir);
 805                 else
 806                         ibx_irq_handler(dev, pch_iir);
 807         }
 808
 809         if (IS_GEN5(dev) &&  de_iir & DE_PCU_EVENT)
 810                 ironlake_handle_rps_change(dev);
 811
 812         if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
 813                 gen6_queue_rps_work(dev_priv, pm_iir);
 814
 815         /* should clear PCH hotplug event before clear CPU irq */
 816         I915_WRITE(SDEIIR, pch_iir);
 817         I915_WRITE(GTIIR, gt_iir);
 818         I915_WRITE(DEIIR, de_iir);
 819         I915_WRITE(GEN6_PMIIR, pm_iir);
 820
 821 done:
 822         I915_WRITE(DEIER, de_ier);
 823         POSTING_READ(DEIER);
 824
 825         return ret;
 826 }
 827
 828 /**
 829  * i915_error_work_func - do process context error handling work
 830  * @work: work struct
 831  *
 832  * Fire an error uevent so userspace can see that a hang or error
 833  * was detected.
 834  */
 835 static void i915_error_work_func(struct work_struct *work)
 836 {
 837         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 838                                                     error_work);
 839         struct drm_device *dev = dev_priv->dev;
 840         char *error_event[] = { "ERROR=1", NULL };
 841         char *reset_event[] = { "RESET=1", NULL };
 842         char *reset_done_event[] = { "ERROR=0", NULL };
 843
 844         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 845
 846         if (atomic_read(&dev_priv->mm.wedged)) {
 847                 DRM_DEBUG_DRIVER("resetting chip\n");
 848                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
 849                 if (!i915_reset(dev)) {
 850                         atomic_set(&dev_priv->mm.wedged, 0);
 851                         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
 852                 }
 853                 complete_all(&dev_priv->error_completion);
 854         }
 855 }
 856
 857 #ifdef CONFIG_DEBUG_FS
 858 static struct drm_i915_error_object *
 859 i915_error_object_create(struct drm_i915_private *dev_priv,
 860                          struct drm_i915_gem_object *src)
 861 {
 862         struct drm_i915_error_object *dst;
 863         int page, page_count;
 864         u32 reloc_offset;
 865
 866         if (src == NULL || src->pages == NULL)
 867                 return NULL;
 868
 869         page_count = src->base.size / PAGE_SIZE;
 870
 871         dst = kmalloc(sizeof(*dst) + page_count * sizeof(u32 *), GFP_ATOMIC);
 872         if (dst == NULL)
 873                 return NULL;
 874
 875         reloc_offset = src->gtt_offset;
 876         for (page = 0; page < page_count; page++) {
 877                 unsigned long flags;
 878                 void *d;
 879
 880                 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
 881                 if (d == NULL)
 882                         goto unwind;
 883
 884                 local_irq_save(flags);
 885                 if (reloc_offset < dev_priv->mm.gtt_mappable_end &&
 886                     src->has_global_gtt_mapping) {
 887                         void __iomem *s;
 888
 889                         /* Simply ignore tiling or any overlapping fence.
 890                          * It's part of the error state, and this hopefully
 891                          * captures what the GPU read.
 892                          */
 893
 894                         s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
 895                                                      reloc_offset);
 896                         memcpy_fromio(d, s, PAGE_SIZE);
 897                         io_mapping_unmap_atomic(s);
 898                 } else {
 899                         void *s;
 900
 901                         drm_clflush_pages(&src->pages[page], 1);
 902
 903                         s = kmap_atomic(src->pages[page]);
 904                         memcpy(d, s, PAGE_SIZE);
 905                         kunmap_atomic(s);
 906
 907                         drm_clflush_pages(&src->pages[page], 1);
 908                 }
 909                 local_irq_restore(flags);
 910
 911                 dst->pages[page] = d;
 912
 913                 reloc_offset += PAGE_SIZE;
 914         }
 915         dst->page_count = page_count;
 916         dst->gtt_offset = src->gtt_offset;
 917
 918         return dst;
 919
 920 unwind:
 921         while (page--)
 922                 kfree(dst->pages[page]);
 923         kfree(dst);
 924         return NULL;
 925 }
 926
 927 static void
 928 i915_error_object_free(struct drm_i915_error_object *obj)
 929 {
 930         int page;
 931
 932         if (obj == NULL)
 933                 return;
 934
 935         for (page = 0; page < obj->page_count; page++)
 936                 kfree(obj->pages[page]);
 937
 938         kfree(obj);
 939 }
 940
 941 void
 942 i915_error_state_free(struct kref *error_ref)
 943 {
 944         struct drm_i915_error_state *error = container_of(error_ref,
 945                                                           typeof(*error), ref);
 946         int i;
 947
 948         for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
 949                 i915_error_object_free(error->ring[i].batchbuffer);
 950                 i915_error_object_free(error->ring[i].ringbuffer);
 951                 kfree(error->ring[i].requests);
 952         }
 953
 954         kfree(error->active_bo);
 955         kfree(error->overlay);
 956         kfree(error);
 957 }
 958 static void capture_bo(struct drm_i915_error_buffer *err,
 959                        struct drm_i915_gem_object *obj)
 960 {
 961         err->size = obj->base.size;
 962         err->name = obj->base.name;
 963         err->rseqno = obj->last_read_seqno;
 964         err->wseqno = obj->last_write_seqno;
 965         err->gtt_offset = obj->gtt_offset;
 966         err->read_domains = obj->base.read_domains;
 967         err->write_domain = obj->base.write_domain;
 968         err->fence_reg = obj->fence_reg;
 969         err->pinned = 0;
 970         if (obj->pin_count > 0)
 971                 err->pinned = 1;
 972         if (obj->user_pin_count > 0)
 973                 err->pinned = -1;
 974         err->tiling = obj->tiling_mode;
 975         err->dirty = obj->dirty;
 976         err->purgeable = obj->madv != I915_MADV_WILLNEED;
 977         err->ring = obj->ring ? obj->ring->id : -1;
 978         err->cache_level = obj->cache_level;
 979 }
 980
 981 static u32 capture_active_bo(struct drm_i915_error_buffer *err,
 982                              int count, struct list_head *head)
 983 {
 984         struct drm_i915_gem_object *obj;
 985         int i = 0;
 986
 987         list_for_each_entry(obj, head, mm_list) {
 988                 capture_bo(err++, obj);
 989                 if (++i == count)
 990                         break;
 991         }
 992
 993         return i;
 994 }
 995
 996 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
 997                              int count, struct list_head *head)
 998 {
 999         struct drm_i915_gem_object *obj;
1000         int i = 0;
1001
1002         list_for_each_entry(obj, head, gtt_list) {
1003                 if (obj->pin_count == 0)
1004                         continue;
1005
1006                 capture_bo(err++, obj);
1007                 if (++i == count)
1008                         break;
1009         }
1010
1011         return i;
1012 }
1013
1014 static void i915_gem_record_fences(struct drm_device *dev,
1015                                    struct drm_i915_error_state *error)
1016 {
1017         struct drm_i915_private *dev_priv = dev->dev_private;
1018         int i;
1019
1020         /* Fences */
1021         switch (INTEL_INFO(dev)->gen) {
1022         case 7:
1023         case 6:
1024                 for (i = 0; i < 16; i++)
1025                         error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
1026                 break;
1027         case 5:
1028         case 4:
1029                 for (i = 0; i < 16; i++)
1030                         error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
1031                 break;
1032         case 3:
1033                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
1034                         for (i = 0; i < 8; i++)
1035                                 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1036         case 2:
1037                 for (i = 0; i < 8; i++)
1038                         error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1039                 break;
1040
1041         }
1042 }
1043
1044 static struct drm_i915_error_object *
1045 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1046                              struct intel_ring_buffer *ring)
1047 {
1048         struct drm_i915_gem_object *obj;
1049         u32 seqno;
1050
1051         if (!ring->get_seqno)
1052                 return NULL;
1053
1054         seqno = ring->get_seqno(ring, false);
1055         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1056                 if (obj->ring != ring)
1057                         continue;
1058
1059                 if (i915_seqno_passed(seqno, obj->last_read_seqno))
1060                         continue;
1061
1062                 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1063                         continue;
1064
1065                 /* We need to copy these to an anonymous buffer as the simplest
1066                  * method to avoid being overwritten by userspace.
1067                  */
1068                 return i915_error_object_create(dev_priv, obj);
1069         }
1070
1071         return NULL;
1072 }
1073
1074 static void i915_record_ring_state(struct drm_device *dev,
1075                                    struct drm_i915_error_state *error,
1076                                    struct intel_ring_buffer *ring)
1077 {
1078         struct drm_i915_private *dev_priv = dev->dev_private;
1079
1080         if (INTEL_INFO(dev)->gen >= 6) {
1081                 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
1082                 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
1083                 error->semaphore_mboxes[ring->id][0]
1084                         = I915_READ(RING_SYNC_0(ring->mmio_base));
1085                 error->semaphore_mboxes[ring->id][1]
1086                         = I915_READ(RING_SYNC_1(ring->mmio_base));
1087         }
1088
1089         if (INTEL_INFO(dev)->gen >= 4) {
1090                 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
1091                 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1092                 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1093                 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
1094                 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
1095                 if (ring->id == RCS) {
1096                         error->instdone1 = I915_READ(INSTDONE1);
1097                         error->bbaddr = I915_READ64(BB_ADDR);
1098                 }
1099         } else {
1100                 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
1101                 error->ipeir[ring->id] = I915_READ(IPEIR);
1102                 error->ipehr[ring->id] = I915_READ(IPEHR);
1103                 error->instdone[ring->id] = I915_READ(INSTDONE);
1104         }
1105
1106         error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
1107         error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
1108         error->seqno[ring->id] = ring->get_seqno(ring, false);
1109         error->acthd[ring->id] = intel_ring_get_active_head(ring);
1110         error->head[ring->id] = I915_READ_HEAD(ring);
1111         error->tail[ring->id] = I915_READ_TAIL(ring);
1112
1113         error->cpu_ring_head[ring->id] = ring->head;
1114         error->cpu_ring_tail[ring->id] = ring->tail;
1115 }
1116
1117 static void i915_gem_record_rings(struct drm_device *dev,
1118                                   struct drm_i915_error_state *error)
1119 {
1120         struct drm_i915_private *dev_priv = dev->dev_private;
1121         struct intel_ring_buffer *ring;
1122         struct drm_i915_gem_request *request;
1123         int i, count;
1124
1125         for_each_ring(ring, dev_priv, i) {
1126                 i915_record_ring_state(dev, error, ring);
1127
1128                 error->ring[i].batchbuffer =
1129                         i915_error_first_batchbuffer(dev_priv, ring);
1130
1131                 error->ring[i].ringbuffer =
1132                         i915_error_object_create(dev_priv, ring->obj);
1133
1134                 count = 0;
1135                 list_for_each_entry(request, &ring->request_list, list)
1136                         count++;
1137
1138                 error->ring[i].num_requests = count;
1139                 error->ring[i].requests =
1140                         kmalloc(count*sizeof(struct drm_i915_error_request),
1141                                 GFP_ATOMIC);
1142                 if (error->ring[i].requests == NULL) {
1143                         error->ring[i].num_requests = 0;
1144                         continue;
1145                 }
1146
1147                 count = 0;
1148                 list_for_each_entry(request, &ring->request_list, list) {
1149                         struct drm_i915_error_request *erq;
1150
1151                         erq = &error->ring[i].requests[count++];
1152                         erq->seqno = request->seqno;
1153                         erq->jiffies = request->emitted_jiffies;
1154                         erq->tail = request->tail;
1155                 }
1156         }
1157 }
1158
1159 /**
1160  * i915_capture_error_state - capture an error record for later analysis
1161  * @dev: drm device
1162  *
1163  * Should be called when an error is detected (either a hang or an error
1164  * interrupt) to capture error state from the time of the error.  Fills
1165  * out a structure which becomes available in debugfs for user level tools
1166  * to pick up.
1167  */
1168 static void i915_capture_error_state(struct drm_device *dev)
1169 {
1170         struct drm_i915_private *dev_priv = dev->dev_private;
1171         struct drm_i915_gem_object *obj;
1172         struct drm_i915_error_state *error;
1173         unsigned long flags;
1174         int i, pipe;
1175
1176         spin_lock_irqsave(&dev_priv->error_lock, flags);
1177         error = dev_priv->first_error;
1178         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1179         if (error)
1180                 return;
1181
1182         /* Account for pipe specific data like PIPE*STAT */
1183         error = kzalloc(sizeof(*error), GFP_ATOMIC);
1184         if (!error) {
1185                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1186                 return;
1187         }
1188
1189         DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
1190                  dev->primary->index);
1191
1192         kref_init(&error->ref);
1193         error->eir = I915_READ(EIR);
1194         error->pgtbl_er = I915_READ(PGTBL_ER);
1195         error->ccid = I915_READ(CCID);
1196
1197         if (HAS_PCH_SPLIT(dev))
1198                 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1199         else if (IS_VALLEYVIEW(dev))
1200                 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1201         else if (IS_GEN2(dev))
1202                 error->ier = I915_READ16(IER);
1203         else
1204                 error->ier = I915_READ(IER);
1205
1206         for_each_pipe(pipe)
1207                 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
1208
1209         if (INTEL_INFO(dev)->gen >= 6) {
1210                 error->error = I915_READ(ERROR_GEN6);
1211                 error->done_reg = I915_READ(DONE_REG);
1212         }
1213
1214         i915_gem_record_fences(dev, error);
1215         i915_gem_record_rings(dev, error);
1216
1217         /* Record buffers on the active and pinned lists. */
1218         error->active_bo = NULL;
1219         error->pinned_bo = NULL;
1220
1221         i = 0;
1222         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1223                 i++;
1224         error->active_bo_count = i;
1225         list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list)
1226                 if (obj->pin_count)
1227                         i++;
1228         error->pinned_bo_count = i - error->active_bo_count;
1229
1230         error->active_bo = NULL;
1231         error->pinned_bo = NULL;
1232         if (i) {
1233                 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
1234                                            GFP_ATOMIC);
1235                 if (error->active_bo)
1236                         error->pinned_bo =
1237                                 error->active_bo + error->active_bo_count;
1238         }
1239
1240         if (error->active_bo)
1241                 error->active_bo_count =
1242                         capture_active_bo(error->active_bo,
1243                                           error->active_bo_count,
1244                                           &dev_priv->mm.active_list);
1245
1246         if (error->pinned_bo)
1247                 error->pinned_bo_count =
1248                         capture_pinned_bo(error->pinned_bo,
1249                                           error->pinned_bo_count,
1250                                           &dev_priv->mm.gtt_list);
1251
1252         do_gettimeofday(&error->time);
1253
1254         error->overlay = intel_overlay_capture_error_state(dev);
1255         error->display = intel_display_capture_error_state(dev);
1256
1257         spin_lock_irqsave(&dev_priv->error_lock, flags);
1258         if (dev_priv->first_error == NULL) {
1259                 dev_priv->first_error = error;
1260                 error = NULL;
1261         }
1262         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1263
1264         if (error)
1265                 i915_error_state_free(&error->ref);
1266 }
1267
1268 void i915_destroy_error_state(struct drm_device *dev)
1269 {
1270         struct drm_i915_private *dev_priv = dev->dev_private;
1271         struct drm_i915_error_state *error;
1272         unsigned long flags;
1273
1274         spin_lock_irqsave(&dev_priv->error_lock, flags);
1275         error = dev_priv->first_error;
1276         dev_priv->first_error = NULL;
1277         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1278
1279         if (error)
1280                 kref_put(&error->ref, i915_error_state_free);
1281 }
1282 #else
1283 #define i915_capture_error_state(x)
1284 #endif
1285
1286 static void i915_report_and_clear_eir(struct drm_device *dev)
1287 {
1288         struct drm_i915_private *dev_priv = dev->dev_private;
1289         u32 eir = I915_READ(EIR);
1290         int pipe;
1291
1292         if (!eir)
1293                 return;
1294
1295         pr_err("render error detected, EIR: 0x%08x\n", eir);
1296
1297         if (IS_G4X(dev)) {
1298                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1299                         u32 ipeir = I915_READ(IPEIR_I965);
1300
1301                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1302                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1303                         pr_err("  INSTDONE: 0x%08x\n",
1304                                I915_READ(INSTDONE_I965));
1305                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
1306                         pr_err("  INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1307                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1308                         I915_WRITE(IPEIR_I965, ipeir);
1309                         POSTING_READ(IPEIR_I965);
1310                 }
1311                 if (eir & GM45_ERROR_PAGE_TABLE) {
1312                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1313                         pr_err("page table error\n");
1314                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
1315                         I915_WRITE(PGTBL_ER, pgtbl_err);
1316                         POSTING_READ(PGTBL_ER);
1317                 }
1318         }
1319
1320         if (!IS_GEN2(dev)) {
1321                 if (eir & I915_ERROR_PAGE_TABLE) {
1322                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1323                         pr_err("page table error\n");
1324                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
1325                         I915_WRITE(PGTBL_ER, pgtbl_err);
1326                         POSTING_READ(PGTBL_ER);
1327                 }
1328         }
1329
1330         if (eir & I915_ERROR_MEMORY_REFRESH) {
1331                 pr_err("memory refresh error:\n");
1332                 for_each_pipe(pipe)
1333                         pr_err("pipe %c stat: 0x%08x\n",
1334                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
1335                 /* pipestat has already been acked */
1336         }
1337         if (eir & I915_ERROR_INSTRUCTION) {
1338                 pr_err("instruction error\n");
1339                 pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
1340                 if (INTEL_INFO(dev)->gen < 4) {
1341                         u32 ipeir = I915_READ(IPEIR);
1342
1343                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
1344                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
1345                         pr_err("  INSTDONE: 0x%08x\n", I915_READ(INSTDONE));
1346                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
1347                         I915_WRITE(IPEIR, ipeir);
1348                         POSTING_READ(IPEIR);
1349                 } else {
1350                         u32 ipeir = I915_READ(IPEIR_I965);
1351
1352                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1353                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1354                         pr_err("  INSTDONE: 0x%08x\n",
1355                                I915_READ(INSTDONE_I965));
1356                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
1357                         pr_err("  INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1358                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1359                         I915_WRITE(IPEIR_I965, ipeir);
1360                         POSTING_READ(IPEIR_I965);
1361                 }
1362         }
1363
1364         I915_WRITE(EIR, eir);
1365         POSTING_READ(EIR);
1366         eir = I915_READ(EIR);
1367         if (eir) {
1368                 /*
1369                  * some errors might have become stuck,
1370                  * mask them.
1371                  */
1372                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1373                 I915_WRITE(EMR, I915_READ(EMR) | eir);
1374                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1375         }
1376 }
1377
1378 /**
1379  * i915_handle_error - handle an error interrupt
1380  * @dev: drm device
1381  *
1382  * Do some basic checking of regsiter state at error interrupt time and
1383  * dump it to the syslog.  Also call i915_capture_error_state() to make
1384  * sure we get a record and make it available in debugfs.  Fire a uevent
1385  * so userspace knows something bad happened (should trigger collection
1386  * of a ring dump etc.).
1387  */
1388 void i915_handle_error(struct drm_device *dev, bool wedged)
1389 {
1390         struct drm_i915_private *dev_priv = dev->dev_private;
1391         struct intel_ring_buffer *ring;
1392         int i;
1393
1394         i915_capture_error_state(dev);
1395         i915_report_and_clear_eir(dev);
1396
1397         if (wedged) {
1398                 INIT_COMPLETION(dev_priv->error_completion);
1399                 atomic_set(&dev_priv->mm.wedged, 1);
1400
1401                 /*
1402                  * Wakeup waiting processes so they don't hang
1403                  */
1404                 for_each_ring(ring, dev_priv, i)
1405                         wake_up_all(&ring->irq_queue);
1406         }
1407
1408         queue_work(dev_priv->wq, &dev_priv->error_work);
1409 }
1410
1411 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1412 {
1413         drm_i915_private_t *dev_priv = dev->dev_private;
1414         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1415         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1416         struct drm_i915_gem_object *obj;
1417         struct intel_unpin_work *work;
1418         unsigned long flags;
1419         bool stall_detected;
1420
1421         /* Ignore early vblank irqs */
1422         if (intel_crtc == NULL)
1423                 return;
1424
1425         spin_lock_irqsave(&dev->event_lock, flags);
1426         work = intel_crtc->unpin_work;
1427
1428         if (work == NULL || work->pending || !work->enable_stall_check) {
1429                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1430                 spin_unlock_irqrestore(&dev->event_lock, flags);
1431                 return;
1432         }
1433
1434         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1435         obj = work->pending_flip_obj;
1436         if (INTEL_INFO(dev)->gen >= 4) {
1437                 int dspsurf = DSPSURF(intel_crtc->plane);
1438                 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1439                                         obj->gtt_offset;
1440         } else {
1441                 int dspaddr = DSPADDR(intel_crtc->plane);
1442                 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
1443                                                         crtc->y * crtc->fb->pitches[0] +
1444                                                         crtc->x * crtc->fb->bits_per_pixel/8);
1445         }
1446
1447         spin_unlock_irqrestore(&dev->event_lock, flags);
1448
1449         if (stall_detected) {
1450                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1451                 intel_prepare_page_flip(dev, intel_crtc->plane);
1452         }
1453 }
1454
1455 /* Called from drm generic code, passed 'crtc' which
1456  * we use as a pipe index
1457  */
1458 static int i915_enable_vblank(struct drm_device *dev, int pipe)
1459 {
1460         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1461         unsigned long irqflags;
1462
1463         if (!i915_pipe_enabled(dev, pipe))
1464                 return -EINVAL;
1465
1466         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1467         if (INTEL_INFO(dev)->gen >= 4)
1468                 i915_enable_pipestat(dev_priv, pipe,
1469                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1470         else
1471                 i915_enable_pipestat(dev_priv, pipe,
1472                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1473
1474         /* maintain vblank delivery even in deep C-states */
1475         if (dev_priv->info->gen == 3)
1476                 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1477         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1478
1479         return 0;
1480 }
1481
1482 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1483 {
1484         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1485         unsigned long irqflags;
1486
1487         if (!i915_pipe_enabled(dev, pipe))
1488                 return -EINVAL;
1489
1490         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1491         ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1492                                     DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1493         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1494
1495         return 0;
1496 }
1497
1498 static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
1499 {
1500         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1501         unsigned long irqflags;
1502
1503         if (!i915_pipe_enabled(dev, pipe))
1504                 return -EINVAL;
1505
1506         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1507         ironlake_enable_display_irq(dev_priv,
1508                                     DE_PIPEA_VBLANK_IVB << (5 * pipe));
1509         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1510
1511         return 0;
1512 }
1513
1514 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1515 {
1516         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1517         unsigned long irqflags;
1518         u32 imr;
1519
1520         if (!i915_pipe_enabled(dev, pipe))
1521                 return -EINVAL;
1522
1523         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1524         imr = I915_READ(VLV_IMR);
1525         if (pipe == 0)
1526                 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1527         else
1528                 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1529         I915_WRITE(VLV_IMR, imr);
1530         i915_enable_pipestat(dev_priv, pipe,
1531                              PIPE_START_VBLANK_INTERRUPT_ENABLE);
1532         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1533
1534         return 0;
1535 }
1536
1537 /* Called from drm generic code, passed 'crtc' which
1538  * we use as a pipe index
1539  */
1540 static void i915_disable_vblank(struct drm_device *dev, int pipe)
1541 {
1542         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1543         unsigned long irqflags;
1544
1545         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1546         if (dev_priv->info->gen == 3)
1547                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
1548
1549         i915_disable_pipestat(dev_priv, pipe,
1550                               PIPE_VBLANK_INTERRUPT_ENABLE |
1551                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
1552         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1553 }
1554
1555 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1556 {
1557         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1558         unsigned long irqflags;
1559
1560         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1561         ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1562                                      DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1563         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1564 }
1565
1566 static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
1567 {
1568         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1569         unsigned long irqflags;
1570
1571         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1572         ironlake_disable_display_irq(dev_priv,
1573                                      DE_PIPEA_VBLANK_IVB << (pipe * 5));
1574         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1575 }
1576
1577 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1578 {
1579         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1580         unsigned long irqflags;
1581         u32 imr;
1582
1583         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1584         i915_disable_pipestat(dev_priv, pipe,
1585                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
1586         imr = I915_READ(VLV_IMR);
1587         if (pipe == 0)
1588                 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1589         else
1590                 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1591         I915_WRITE(VLV_IMR, imr);
1592         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1593 }
1594
1595 static u32
1596 ring_last_seqno(struct intel_ring_buffer *ring)
1597 {
1598         return list_entry(ring->request_list.prev,
1599                           struct drm_i915_gem_request, list)->seqno;
1600 }
1601
1602 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1603 {
1604         if (list_empty(&ring->request_list) ||
1605             i915_seqno_passed(ring->get_seqno(ring, false),
1606                               ring_last_seqno(ring))) {
1607                 /* Issue a wake-up to catch stuck h/w. */
1608                 if (waitqueue_active(&ring->irq_queue)) {
1609                         DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1610                                   ring->name);
1611                         wake_up_all(&ring->irq_queue);
1612                         *err = true;
1613                 }
1614                 return true;
1615         }
1616         return false;
1617 }
1618
1619 static bool kick_ring(struct intel_ring_buffer *ring)
1620 {
1621         struct drm_device *dev = ring->dev;
1622         struct drm_i915_private *dev_priv = dev->dev_private;
1623         u32 tmp = I915_READ_CTL(ring);
1624         if (tmp & RING_WAIT) {
1625                 DRM_ERROR("Kicking stuck wait on %s\n",
1626                           ring->name);
1627                 I915_WRITE_CTL(ring, tmp);
1628                 return true;
1629         }
1630         return false;
1631 }
1632
1633 static bool i915_hangcheck_hung(struct drm_device *dev)
1634 {
1635         drm_i915_private_t *dev_priv = dev->dev_private;
1636
1637         if (dev_priv->hangcheck_count++ > 1) {
1638                 bool hung = true;
1639
1640                 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1641                 i915_handle_error(dev, true);
1642
1643                 if (!IS_GEN2(dev)) {
1644                         struct intel_ring_buffer *ring;
1645                         int i;
1646
1647                         /* Is the chip hanging on a WAIT_FOR_EVENT?
1648                          * If so we can simply poke the RB_WAIT bit
1649                          * and break the hang. This should work on
1650                          * all but the second generation chipsets.
1651                          */
1652                         for_each_ring(ring, dev_priv, i)
1653                                 hung &= !kick_ring(ring);
1654                 }
1655
1656                 return hung;
1657         }
1658
1659         return false;
1660 }
1661
1662 /**
1663  * This is called when the chip hasn't reported back with completed
1664  * batchbuffers in a long time. The first time this is called we simply record
1665  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1666  * again, we assume the chip is wedged and try to fix it.
1667  */
1668 void i915_hangcheck_elapsed(unsigned long data)
1669 {
1670         struct drm_device *dev = (struct drm_device *)data;
1671         drm_i915_private_t *dev_priv = dev->dev_private;
1672         uint32_t acthd[I915_NUM_RINGS], instdone, instdone1;
1673         struct intel_ring_buffer *ring;
1674         bool err = false, idle;
1675         int i;
1676
1677         if (!i915_enable_hangcheck)
1678                 return;
1679
1680         memset(acthd, 0, sizeof(acthd));
1681         idle = true;
1682         for_each_ring(ring, dev_priv, i) {
1683             idle &= i915_hangcheck_ring_idle(ring, &err);
1684             acthd[i] = intel_ring_get_active_head(ring);
1685         }
1686
1687         /* If all work is done then ACTHD clearly hasn't advanced. */
1688         if (idle) {
1689                 if (err) {
1690                         if (i915_hangcheck_hung(dev))
1691                                 return;
1692
1693                         goto repeat;
1694                 }
1695
1696                 dev_priv->hangcheck_count = 0;
1697                 return;
1698         }
1699
1700         if (INTEL_INFO(dev)->gen < 4) {
1701                 instdone = I915_READ(INSTDONE);
1702                 instdone1 = 0;
1703         } else {
1704                 instdone = I915_READ(INSTDONE_I965);
1705                 instdone1 = I915_READ(INSTDONE1);
1706         }
1707
1708         if (memcmp(dev_priv->last_acthd, acthd, sizeof(acthd)) == 0 &&
1709             dev_priv->last_instdone == instdone &&
1710             dev_priv->last_instdone1 == instdone1) {
1711                 if (i915_hangcheck_hung(dev))
1712                         return;
1713         } else {
1714                 dev_priv->hangcheck_count = 0;
1715
1716                 memcpy(dev_priv->last_acthd, acthd, sizeof(acthd));
1717                 dev_priv->last_instdone = instdone;
1718                 dev_priv->last_instdone1 = instdone1;
1719         }
1720
1721 repeat:
1722         /* Reset timer case chip hangs without another request being added */
1723         mod_timer(&dev_priv->hangcheck_timer,
1724                   jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1725 }
1726
1727 /* drm_dma.h hooks
1728 */
1729 static void ironlake_irq_preinstall(struct drm_device *dev)
1730 {
1731         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1732
1733         atomic_set(&dev_priv->irq_received, 0);
1734
1735         I915_WRITE(HWSTAM, 0xeffe);
1736
1737         /* XXX hotplug from PCH */
1738
1739         I915_WRITE(DEIMR, 0xffffffff);
1740         I915_WRITE(DEIER, 0x0);
1741         POSTING_READ(DEIER);
1742
1743         /* and GT */
1744         I915_WRITE(GTIMR, 0xffffffff);
1745         I915_WRITE(GTIER, 0x0);
1746         POSTING_READ(GTIER);
1747
1748         /* south display irq */
1749         I915_WRITE(SDEIMR, 0xffffffff);
1750         I915_WRITE(SDEIER, 0x0);
1751         POSTING_READ(SDEIER);
1752 }
1753
1754 static void valleyview_irq_preinstall(struct drm_device *dev)
1755 {
1756         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1757         int pipe;
1758
1759         atomic_set(&dev_priv->irq_received, 0);
1760
1761         /* VLV magic */
1762         I915_WRITE(VLV_IMR, 0);
1763         I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
1764         I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
1765         I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
1766
1767         /* and GT */
1768         I915_WRITE(GTIIR, I915_READ(GTIIR));
1769         I915_WRITE(GTIIR, I915_READ(GTIIR));
1770         I915_WRITE(GTIMR, 0xffffffff);
1771         I915_WRITE(GTIER, 0x0);
1772         POSTING_READ(GTIER);
1773
1774         I915_WRITE(DPINVGTT, 0xff);
1775
1776         I915_WRITE(PORT_HOTPLUG_EN, 0);
1777         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1778         for_each_pipe(pipe)
1779                 I915_WRITE(PIPESTAT(pipe), 0xffff);
1780         I915_WRITE(VLV_IIR, 0xffffffff);
1781         I915_WRITE(VLV_IMR, 0xffffffff);
1782         I915_WRITE(VLV_IER, 0x0);
1783         POSTING_READ(VLV_IER);
1784 }
1785
1786 /*
1787  * Enable digital hotplug on the PCH, and configure the DP short pulse
1788  * duration to 2ms (which is the minimum in the Display Port spec)
1789  *
1790  * This register is the same on all known PCH chips.
1791  */
1792
1793 static void ironlake_enable_pch_hotplug(struct drm_device *dev)
1794 {
1795         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1796         u32     hotplug;
1797
1798         hotplug = I915_READ(PCH_PORT_HOTPLUG);
1799         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1800         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1801         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1802         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1803         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1804 }
1805
1806 static int ironlake_irq_postinstall(struct drm_device *dev)
1807 {
1808         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1809         /* enable kind of interrupts always enabled */
1810         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1811                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1812         u32 render_irqs;
1813         u32 hotplug_mask;
1814
1815         dev_priv->irq_mask = ~display_mask;
1816
1817         /* should always can generate irq */
1818         I915_WRITE(DEIIR, I915_READ(DEIIR));
1819         I915_WRITE(DEIMR, dev_priv->irq_mask);
1820         I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
1821         POSTING_READ(DEIER);
1822
1823         dev_priv->gt_irq_mask = ~0;
1824
1825         I915_WRITE(GTIIR, I915_READ(GTIIR));
1826         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1827
1828         if (IS_GEN6(dev))
1829                 render_irqs =
1830                         GT_USER_INTERRUPT |
1831                         GEN6_BSD_USER_INTERRUPT |
1832                         GEN6_BLITTER_USER_INTERRUPT;
1833         else
1834                 render_irqs =
1835                         GT_USER_INTERRUPT |
1836                         GT_PIPE_NOTIFY |
1837                         GT_BSD_USER_INTERRUPT;
1838         I915_WRITE(GTIER, render_irqs);
1839         POSTING_READ(GTIER);
1840
1841         if (HAS_PCH_CPT(dev)) {
1842                 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1843                                 SDE_PORTB_HOTPLUG_CPT |
1844                                 SDE_PORTC_HOTPLUG_CPT |
1845                                 SDE_PORTD_HOTPLUG_CPT);
1846         } else {
1847                 hotplug_mask = (SDE_CRT_HOTPLUG |
1848                                 SDE_PORTB_HOTPLUG |
1849                                 SDE_PORTC_HOTPLUG |
1850                                 SDE_PORTD_HOTPLUG |
1851                                 SDE_AUX_MASK);
1852         }
1853
1854         dev_priv->pch_irq_mask = ~hotplug_mask;
1855
1856         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1857         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1858         I915_WRITE(SDEIER, hotplug_mask);
1859         POSTING_READ(SDEIER);
1860
1861         ironlake_enable_pch_hotplug(dev);
1862
1863         if (IS_IRONLAKE_M(dev)) {
1864                 /* Clear & enable PCU event interrupts */
1865                 I915_WRITE(DEIIR, DE_PCU_EVENT);
1866                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1867                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1868         }
1869
1870         return 0;
1871 }
1872
1873 static int ivybridge_irq_postinstall(struct drm_device *dev)
1874 {
1875         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1876         /* enable kind of interrupts always enabled */
1877         u32 display_mask =
1878                 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
1879                 DE_PLANEC_FLIP_DONE_IVB |
1880                 DE_PLANEB_FLIP_DONE_IVB |
1881                 DE_PLANEA_FLIP_DONE_IVB;
1882         u32 render_irqs;
1883         u32 hotplug_mask;
1884
1885         dev_priv->irq_mask = ~display_mask;
1886
1887         /* should always can generate irq */
1888         I915_WRITE(DEIIR, I915_READ(DEIIR));
1889         I915_WRITE(DEIMR, dev_priv->irq_mask);
1890         I915_WRITE(DEIER,
1891                    display_mask |
1892                    DE_PIPEC_VBLANK_IVB |
1893                    DE_PIPEB_VBLANK_IVB |
1894                    DE_PIPEA_VBLANK_IVB);
1895         POSTING_READ(DEIER);
1896
1897         dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
1898
1899         I915_WRITE(GTIIR, I915_READ(GTIIR));
1900         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1901
1902         render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
1903                 GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
1904         I915_WRITE(GTIER, render_irqs);
1905         POSTING_READ(GTIER);
1906
1907         hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1908                         SDE_PORTB_HOTPLUG_CPT |
1909                         SDE_PORTC_HOTPLUG_CPT |
1910                         SDE_PORTD_HOTPLUG_CPT);
1911         dev_priv->pch_irq_mask = ~hotplug_mask;
1912
1913         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1914         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1915         I915_WRITE(SDEIER, hotplug_mask);
1916         POSTING_READ(SDEIER);
1917
1918         ironlake_enable_pch_hotplug(dev);
1919
1920         return 0;
1921 }
1922
1923 static int valleyview_irq_postinstall(struct drm_device *dev)
1924 {
1925         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1926         u32 enable_mask;
1927         u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1928         u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
1929         u16 msid;
1930
1931         enable_mask = I915_DISPLAY_PORT_INTERRUPT;
1932         enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
1933                 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1934                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
1935                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1936
1937         /*
1938          *Leave vblank interrupts masked initially.  enable/disable will
1939          * toggle them based on usage.
1940          */
1941         dev_priv->irq_mask = (~enable_mask) |
1942                 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1943                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1944
1945         dev_priv->pipestat[0] = 0;
1946         dev_priv->pipestat[1] = 0;
1947
1948         /* Hack for broken MSIs on VLV */
1949         pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
1950         pci_read_config_word(dev->pdev, 0x98, &msid);
1951         msid &= 0xff; /* mask out delivery bits */
1952         msid |= (1<<14);
1953         pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
1954
1955         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
1956         I915_WRITE(VLV_IER, enable_mask);
1957         I915_WRITE(VLV_IIR, 0xffffffff);
1958         I915_WRITE(PIPESTAT(0), 0xffff);
1959         I915_WRITE(PIPESTAT(1), 0xffff);
1960         POSTING_READ(VLV_IER);
1961
1962         i915_enable_pipestat(dev_priv, 0, pipestat_enable);
1963         i915_enable_pipestat(dev_priv, 1, pipestat_enable);
1964
1965         I915_WRITE(VLV_IIR, 0xffffffff);
1966         I915_WRITE(VLV_IIR, 0xffffffff);
1967
1968         dev_priv->gt_irq_mask = ~0;
1969
1970         I915_WRITE(GTIIR, I915_READ(GTIIR));
1971         I915_WRITE(GTIIR, I915_READ(GTIIR));
1972         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1973         I915_WRITE(GTIER, GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT |
1974                    GT_GEN6_BLT_CS_ERROR_INTERRUPT |
1975                    GT_GEN6_BLT_USER_INTERRUPT |
1976                    GT_GEN6_BSD_USER_INTERRUPT |
1977                    GT_GEN6_BSD_CS_ERROR_INTERRUPT |
1978                    GT_GEN7_L3_PARITY_ERROR_INTERRUPT |
1979                    GT_PIPE_NOTIFY |
1980                    GT_RENDER_CS_ERROR_INTERRUPT |
1981                    GT_SYNC_STATUS |
1982                    GT_USER_INTERRUPT);
1983         POSTING_READ(GTIER);
1984
1985         /* ack & enable invalid PTE error interrupts */
1986 #if 0 /* FIXME: add support to irq handler for checking these bits */
1987         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
1988         I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
1989 #endif
1990
1991         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1992 #if 0 /* FIXME: check register definitions; some have moved */
1993         /* Note HDMI and DP share bits */
1994         if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1995                 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1996         if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1997                 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1998         if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1999                 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2000         if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
2001                 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2002         if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
2003                 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2004         if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2005                 hotplug_en |= CRT_HOTPLUG_INT_EN;
2006                 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2007         }
2008 #endif
2009
2010         I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2011
2012         return 0;
2013 }
2014
2015 static void valleyview_irq_uninstall(struct drm_device *dev)
2016 {
2017         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2018         int pipe;
2019
2020         if (!dev_priv)
2021                 return;
2022
2023         for_each_pipe(pipe)
2024                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2025
2026         I915_WRITE(HWSTAM, 0xffffffff);
2027         I915_WRITE(PORT_HOTPLUG_EN, 0);
2028         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2029         for_each_pipe(pipe)
2030                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2031         I915_WRITE(VLV_IIR, 0xffffffff);
2032         I915_WRITE(VLV_IMR, 0xffffffff);
2033         I915_WRITE(VLV_IER, 0x0);
2034         POSTING_READ(VLV_IER);
2035 }
2036
2037 static void ironlake_irq_uninstall(struct drm_device *dev)
2038 {
2039         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2040
2041         if (!dev_priv)
2042                 return;
2043
2044         I915_WRITE(HWSTAM, 0xffffffff);
2045
2046         I915_WRITE(DEIMR, 0xffffffff);
2047         I915_WRITE(DEIER, 0x0);
2048         I915_WRITE(DEIIR, I915_READ(DEIIR));
2049
2050         I915_WRITE(GTIMR, 0xffffffff);
2051         I915_WRITE(GTIER, 0x0);
2052         I915_WRITE(GTIIR, I915_READ(GTIIR));
2053
2054         I915_WRITE(SDEIMR, 0xffffffff);
2055         I915_WRITE(SDEIER, 0x0);
2056         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2057 }
2058
2059 static void i8xx_irq_preinstall(struct drm_device * dev)
2060 {
2061         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2062         int pipe;
2063
2064         atomic_set(&dev_priv->irq_received, 0);
2065
2066         for_each_pipe(pipe)
2067                 I915_WRITE(PIPESTAT(pipe), 0);
2068         I915_WRITE16(IMR, 0xffff);
2069         I915_WRITE16(IER, 0x0);
2070         POSTING_READ16(IER);
2071 }
2072
2073 static int i8xx_irq_postinstall(struct drm_device *dev)
2074 {
2075         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2076
2077         dev_priv->pipestat[0] = 0;
2078         dev_priv->pipestat[1] = 0;
2079
2080         I915_WRITE16(EMR,
2081                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2082
2083         /* Unmask the interrupts that we always want on. */
2084         dev_priv->irq_mask =
2085                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2086                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2087                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2088                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2089                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2090         I915_WRITE16(IMR, dev_priv->irq_mask);
2091
2092         I915_WRITE16(IER,
2093                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2094                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2095                      I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2096                      I915_USER_INTERRUPT);
2097         POSTING_READ16(IER);
2098
2099         return 0;
2100 }
2101
2102 static irqreturn_t i8xx_irq_handler(DRM_IRQ_ARGS)
2103 {
2104         struct drm_device *dev = (struct drm_device *) arg;
2105         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2106         u16 iir, new_iir;
2107         u32 pipe_stats[2];
2108         unsigned long irqflags;
2109         int irq_received;
2110         int pipe;
2111         u16 flip_mask =
2112                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2113                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2114
2115         atomic_inc(&dev_priv->irq_received);
2116
2117         iir = I915_READ16(IIR);
2118         if (iir == 0)
2119                 return IRQ_NONE;
2120
2121         while (iir & ~flip_mask) {
2122                 /* Can't rely on pipestat interrupt bit in iir as it might
2123                  * have been cleared after the pipestat interrupt was received.
2124                  * It doesn't set the bit in iir again, but it still produces
2125                  * interrupts (for non-MSI).
2126                  */
2127                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2128                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2129                         i915_handle_error(dev, false);
2130
2131                 for_each_pipe(pipe) {
2132                         int reg = PIPESTAT(pipe);
2133                         pipe_stats[pipe] = I915_READ(reg);
2134
2135                         /*
2136                          * Clear the PIPE*STAT regs before the IIR
2137                          */
2138                         if (pipe_stats[pipe] & 0x8000ffff) {
2139                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2140                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2141                                                          pipe_name(pipe));
2142                                 I915_WRITE(reg, pipe_stats[pipe]);
2143                                 irq_received = 1;
2144                         }
2145                 }
2146                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2147
2148                 I915_WRITE16(IIR, iir & ~flip_mask);
2149                 new_iir = I915_READ16(IIR); /* Flush posted writes */
2150
2151                 i915_update_dri1_breadcrumb(dev);
2152
2153                 if (iir & I915_USER_INTERRUPT)
2154                         notify_ring(dev, &dev_priv->ring[RCS]);
2155
2156                 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2157                     drm_handle_vblank(dev, 0)) {
2158                         if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
2159                                 intel_prepare_page_flip(dev, 0);
2160                                 intel_finish_page_flip(dev, 0);
2161                                 flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
2162                         }
2163                 }
2164
2165                 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2166                     drm_handle_vblank(dev, 1)) {
2167                         if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
2168                                 intel_prepare_page_flip(dev, 1);
2169                                 intel_finish_page_flip(dev, 1);
2170                                 flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2171                         }
2172                 }
2173
2174                 iir = new_iir;
2175         }
2176
2177         return IRQ_HANDLED;
2178 }
2179
2180 static void i8xx_irq_uninstall(struct drm_device * dev)
2181 {
2182         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2183         int pipe;
2184
2185         for_each_pipe(pipe) {
2186                 /* Clear enable bits; then clear status bits */
2187                 I915_WRITE(PIPESTAT(pipe), 0);
2188                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2189         }
2190         I915_WRITE16(IMR, 0xffff);
2191         I915_WRITE16(IER, 0x0);
2192         I915_WRITE16(IIR, I915_READ16(IIR));
2193 }
2194
2195 static void i915_irq_preinstall(struct drm_device * dev)
2196 {
2197         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2198         int pipe;
2199
2200         atomic_set(&dev_priv->irq_received, 0);
2201
2202         if (I915_HAS_HOTPLUG(dev)) {
2203                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2204                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2205         }
2206
2207         I915_WRITE16(HWSTAM, 0xeffe);
2208         for_each_pipe(pipe)
2209                 I915_WRITE(PIPESTAT(pipe), 0);
2210         I915_WRITE(IMR, 0xffffffff);
2211         I915_WRITE(IER, 0x0);
2212         POSTING_READ(IER);
2213 }
2214
2215 static int i915_irq_postinstall(struct drm_device *dev)
2216 {
2217         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2218         u32 enable_mask;
2219
2220         dev_priv->pipestat[0] = 0;
2221         dev_priv->pipestat[1] = 0;
2222
2223         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2224
2225         /* Unmask the interrupts that we always want on. */
2226         dev_priv->irq_mask =
2227                 ~(I915_ASLE_INTERRUPT |
2228                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2229                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2230                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2231                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2232                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2233
2234         enable_mask =
2235                 I915_ASLE_INTERRUPT |
2236                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2237                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2238                 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2239                 I915_USER_INTERRUPT;
2240
2241         if (I915_HAS_HOTPLUG(dev)) {
2242                 /* Enable in IER... */
2243                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2244                 /* and unmask in IMR */
2245                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2246         }
2247
2248         I915_WRITE(IMR, dev_priv->irq_mask);
2249         I915_WRITE(IER, enable_mask);
2250         POSTING_READ(IER);
2251
2252         if (I915_HAS_HOTPLUG(dev)) {
2253                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2254
2255                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2256                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2257                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2258                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2259                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2260                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
2261                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
2262                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2263                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
2264                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2265                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2266                         hotplug_en |= CRT_HOTPLUG_INT_EN;
2267                         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2268                 }
2269
2270                 /* Ignore TV since it's buggy */
2271
2272                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2273         }
2274
2275         intel_opregion_enable_asle(dev);
2276
2277         return 0;
2278 }
2279
2280 static irqreturn_t i915_irq_handler(DRM_IRQ_ARGS)
2281 {
2282         struct drm_device *dev = (struct drm_device *) arg;
2283         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2284         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
2285         unsigned long irqflags;
2286         u32 flip_mask =
2287                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2288                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2289         u32 flip[2] = {
2290                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT,
2291                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
2292         };
2293         int pipe, ret = IRQ_NONE;
2294
2295         atomic_inc(&dev_priv->irq_received);
2296
2297         iir = I915_READ(IIR);
2298         do {
2299                 bool irq_received = (iir & ~flip_mask) != 0;
2300                 bool blc_event = false;
2301
2302                 /* Can't rely on pipestat interrupt bit in iir as it might
2303                  * have been cleared after the pipestat interrupt was received.
2304                  * It doesn't set the bit in iir again, but it still produces
2305                  * interrupts (for non-MSI).
2306                  */
2307                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2308                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2309                         i915_handle_error(dev, false);
2310
2311                 for_each_pipe(pipe) {
2312                         int reg = PIPESTAT(pipe);
2313                         pipe_stats[pipe] = I915_READ(reg);
2314
2315                         /* Clear the PIPE*STAT regs before the IIR */
2316                         if (pipe_stats[pipe] & 0x8000ffff) {
2317                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2318                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2319                                                          pipe_name(pipe));
2320                                 I915_WRITE(reg, pipe_stats[pipe]);
2321                                 irq_received = true;
2322                         }
2323                 }
2324                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2325
2326                 if (!irq_received)
2327                         break;
2328
2329                 /* Consume port.  Then clear IIR or we'll miss events */
2330                 if ((I915_HAS_HOTPLUG(dev)) &&
2331                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2332                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2333
2334                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2335                                   hotplug_status);
2336                         if (hotplug_status & dev_priv->hotplug_supported_mask)
2337                                 queue_work(dev_priv->wq,
2338                                            &dev_priv->hotplug_work);
2339
2340                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2341                         POSTING_READ(PORT_HOTPLUG_STAT);
2342                 }
2343
2344                 I915_WRITE(IIR, iir & ~flip_mask);
2345                 new_iir = I915_READ(IIR); /* Flush posted writes */
2346
2347                 if (iir & I915_USER_INTERRUPT)
2348                         notify_ring(dev, &dev_priv->ring[RCS]);
2349
2350                 for_each_pipe(pipe) {
2351                         int plane = pipe;
2352                         if (IS_MOBILE(dev))
2353                                 plane = !plane;
2354                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
2355                             drm_handle_vblank(dev, pipe)) {
2356                                 if (iir & flip[plane]) {
2357                                         intel_prepare_page_flip(dev, plane);
2358                                         intel_finish_page_flip(dev, pipe);
2359                                         flip_mask &= ~flip[plane];
2360                                 }
2361                         }
2362
2363                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2364                                 blc_event = true;
2365                 }
2366
2367                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2368                         intel_opregion_asle_intr(dev);
2369
2370                 /* With MSI, interrupts are only generated when iir
2371                  * transitions from zero to nonzero.  If another bit got
2372                  * set while we were handling the existing iir bits, then
2373                  * we would never get another interrupt.
2374                  *
2375                  * This is fine on non-MSI as well, as if we hit this path
2376                  * we avoid exiting the interrupt handler only to generate
2377                  * another one.
2378                  *
2379                  * Note that for MSI this could cause a stray interrupt report
2380                  * if an interrupt landed in the time between writing IIR and
2381                  * the posting read.  This should be rare enough to never
2382                  * trigger the 99% of 100,000 interrupts test for disabling
2383                  * stray interrupts.
2384                  */
2385                 ret = IRQ_HANDLED;
2386                 iir = new_iir;
2387         } while (iir & ~flip_mask);
2388
2389         i915_update_dri1_breadcrumb(dev);
2390
2391         return ret;
2392 }
2393
2394 static void i915_irq_uninstall(struct drm_device * dev)
2395 {
2396         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2397         int pipe;
2398
2399         if (I915_HAS_HOTPLUG(dev)) {
2400                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2401                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2402         }
2403
2404         I915_WRITE16(HWSTAM, 0xffff);
2405         for_each_pipe(pipe) {
2406                 /* Clear enable bits; then clear status bits */
2407                 I915_WRITE(PIPESTAT(pipe), 0);
2408                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2409         }
2410         I915_WRITE(IMR, 0xffffffff);
2411         I915_WRITE(IER, 0x0);
2412
2413         I915_WRITE(IIR, I915_READ(IIR));
2414 }
2415
2416 static void i965_irq_preinstall(struct drm_device * dev)
2417 {
2418         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2419         int pipe;
2420
2421         atomic_set(&dev_priv->irq_received, 0);
2422
2423         I915_WRITE(PORT_HOTPLUG_EN, 0);
2424         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2425
2426         I915_WRITE(HWSTAM, 0xeffe);
2427         for_each_pipe(pipe)
2428                 I915_WRITE(PIPESTAT(pipe), 0);
2429         I915_WRITE(IMR, 0xffffffff);
2430         I915_WRITE(IER, 0x0);
2431         POSTING_READ(IER);
2432 }
2433
2434 static int i965_irq_postinstall(struct drm_device *dev)
2435 {
2436         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2437         u32 hotplug_en;
2438         u32 enable_mask;
2439         u32 error_mask;
2440
2441         /* Unmask the interrupts that we always want on. */
2442         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
2443                                I915_DISPLAY_PORT_INTERRUPT |
2444                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2445                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2446                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2447                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2448                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2449
2450         enable_mask = ~dev_priv->irq_mask;
2451         enable_mask |= I915_USER_INTERRUPT;
2452
2453         if (IS_G4X(dev))
2454                 enable_mask |= I915_BSD_USER_INTERRUPT;
2455
2456         dev_priv->pipestat[0] = 0;
2457         dev_priv->pipestat[1] = 0;
2458
2459         /*
2460          * Enable some error detection, note the instruction error mask
2461          * bit is reserved, so we leave it masked.
2462          */
2463         if (IS_G4X(dev)) {
2464                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2465                                GM45_ERROR_MEM_PRIV |
2466                                GM45_ERROR_CP_PRIV |
2467                                I915_ERROR_MEMORY_REFRESH);
2468         } else {
2469                 error_mask = ~(I915_ERROR_PAGE_TABLE |
2470                                I915_ERROR_MEMORY_REFRESH);
2471         }
2472         I915_WRITE(EMR, error_mask);
2473
2474         I915_WRITE(IMR, dev_priv->irq_mask);
2475         I915_WRITE(IER, enable_mask);
2476         POSTING_READ(IER);
2477
2478         /* Note HDMI and DP share hotplug bits */
2479         hotplug_en = 0;
2480         if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2481                 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2482         if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2483                 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2484         if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2485                 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2486         if (IS_G4X(dev)) {
2487                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_G4X)
2488                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2489                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_G4X)
2490                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2491         } else {
2492                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I965)
2493                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2494                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I965)
2495                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2496         }
2497         if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2498                 hotplug_en |= CRT_HOTPLUG_INT_EN;
2499
2500                 /* Programming the CRT detection parameters tends
2501                    to generate a spurious hotplug event about three
2502                    seconds later.  So just do it once.
2503                    */
2504                 if (IS_G4X(dev))
2505                         hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2506                 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2507         }
2508
2509         /* Ignore TV since it's buggy */
2510
2511         I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2512
2513         intel_opregion_enable_asle(dev);
2514
2515         return 0;
2516 }
2517
2518 static irqreturn_t i965_irq_handler(DRM_IRQ_ARGS)
2519 {
2520         struct drm_device *dev = (struct drm_device *) arg;
2521         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2522         u32 iir, new_iir;
2523         u32 pipe_stats[I915_MAX_PIPES];
2524         unsigned long irqflags;
2525         int irq_received;
2526         int ret = IRQ_NONE, pipe;
2527
2528         atomic_inc(&dev_priv->irq_received);
2529
2530         iir = I915_READ(IIR);
2531
2532         for (;;) {
2533                 bool blc_event = false;
2534
2535                 irq_received = iir != 0;
2536
2537                 /* Can't rely on pipestat interrupt bit in iir as it might
2538                  * have been cleared after the pipestat interrupt was received.
2539                  * It doesn't set the bit in iir again, but it still produces
2540                  * interrupts (for non-MSI).
2541                  */
2542                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2543                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2544                         i915_handle_error(dev, false);
2545
2546                 for_each_pipe(pipe) {
2547                         int reg = PIPESTAT(pipe);
2548                         pipe_stats[pipe] = I915_READ(reg);
2549
2550                         /*
2551                          * Clear the PIPE*STAT regs before the IIR
2552                          */
2553                         if (pipe_stats[pipe] & 0x8000ffff) {
2554                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2555                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2556                                                          pipe_name(pipe));
2557                                 I915_WRITE(reg, pipe_stats[pipe]);
2558                                 irq_received = 1;
2559                         }
2560                 }
2561                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2562
2563                 if (!irq_received)
2564                         break;
2565
2566                 ret = IRQ_HANDLED;
2567
2568                 /* Consume port.  Then clear IIR or we'll miss events */
2569                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
2570                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2571
2572                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2573                                   hotplug_status);
2574                         if (hotplug_status & dev_priv->hotplug_supported_mask)
2575                                 queue_work(dev_priv->wq,
2576                                            &dev_priv->hotplug_work);
2577
2578                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2579                         I915_READ(PORT_HOTPLUG_STAT);
2580                 }
2581
2582                 I915_WRITE(IIR, iir);
2583                 new_iir = I915_READ(IIR); /* Flush posted writes */
2584
2585                 if (iir & I915_USER_INTERRUPT)
2586                         notify_ring(dev, &dev_priv->ring[RCS]);
2587                 if (iir & I915_BSD_USER_INTERRUPT)
2588                         notify_ring(dev, &dev_priv->ring[VCS]);
2589
2590                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
2591                         intel_prepare_page_flip(dev, 0);
2592
2593                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
2594                         intel_prepare_page_flip(dev, 1);
2595
2596                 for_each_pipe(pipe) {
2597                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
2598                             drm_handle_vblank(dev, pipe)) {
2599                                 i915_pageflip_stall_check(dev, pipe);
2600                                 intel_finish_page_flip(dev, pipe);
2601                         }
2602
2603                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2604                                 blc_event = true;
2605                 }
2606
2607
2608                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2609                         intel_opregion_asle_intr(dev);
2610
2611                 /* With MSI, interrupts are only generated when iir
2612                  * transitions from zero to nonzero.  If another bit got
2613                  * set while we were handling the existing iir bits, then
2614                  * we would never get another interrupt.
2615                  *
2616                  * This is fine on non-MSI as well, as if we hit this path
2617                  * we avoid exiting the interrupt handler only to generate
2618                  * another one.
2619                  *
2620                  * Note that for MSI this could cause a stray interrupt report
2621                  * if an interrupt landed in the time between writing IIR and
2622                  * the posting read.  This should be rare enough to never
2623                  * trigger the 99% of 100,000 interrupts test for disabling
2624                  * stray interrupts.
2625                  */
2626                 iir = new_iir;
2627         }
2628
2629         i915_update_dri1_breadcrumb(dev);
2630
2631         return ret;
2632 }
2633
2634 static void i965_irq_uninstall(struct drm_device * dev)
2635 {
2636         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2637         int pipe;
2638
2639         if (!dev_priv)
2640                 return;
2641
2642         I915_WRITE(PORT_HOTPLUG_EN, 0);
2643         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2644
2645         I915_WRITE(HWSTAM, 0xffffffff);
2646         for_each_pipe(pipe)
2647                 I915_WRITE(PIPESTAT(pipe), 0);
2648         I915_WRITE(IMR, 0xffffffff);
2649         I915_WRITE(IER, 0x0);
2650
2651         for_each_pipe(pipe)
2652                 I915_WRITE(PIPESTAT(pipe),
2653                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2654         I915_WRITE(IIR, I915_READ(IIR));
2655 }
2656
2657 void intel_irq_init(struct drm_device *dev)
2658 {
2659         struct drm_i915_private *dev_priv = dev->dev_private;
2660
2661         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2662         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
2663         INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
2664         INIT_WORK(&dev_priv->parity_error_work, ivybridge_parity_work);
2665
2666         dev->driver->get_vblank_counter = i915_get_vblank_counter;
2667         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2668         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
2669                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2670                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2671         }
2672
2673         if (drm_core_check_feature(dev, DRIVER_MODESET))
2674                 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2675         else
2676                 dev->driver->get_vblank_timestamp = NULL;
2677         dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2678
2679         if (IS_VALLEYVIEW(dev)) {
2680                 dev->driver->irq_handler = valleyview_irq_handler;
2681                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2682                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2683                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2684                 dev->driver->enable_vblank = valleyview_enable_vblank;
2685                 dev->driver->disable_vblank = valleyview_disable_vblank;
2686         } else if (IS_IVYBRIDGE(dev)) {
2687                 /* Share pre & uninstall handlers with ILK/SNB */
2688                 dev->driver->irq_handler = ivybridge_irq_handler;
2689                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2690                 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2691                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2692                 dev->driver->enable_vblank = ivybridge_enable_vblank;
2693                 dev->driver->disable_vblank = ivybridge_disable_vblank;
2694         } else if (IS_HASWELL(dev)) {
2695                 /* Share interrupts handling with IVB */
2696                 dev->driver->irq_handler = ivybridge_irq_handler;
2697                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2698                 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2699                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2700                 dev->driver->enable_vblank = ivybridge_enable_vblank;
2701                 dev->driver->disable_vblank = ivybridge_disable_vblank;
2702         } else if (HAS_PCH_SPLIT(dev)) {
2703                 dev->driver->irq_handler = ironlake_irq_handler;
2704                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2705                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2706                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2707                 dev->driver->enable_vblank = ironlake_enable_vblank;
2708                 dev->driver->disable_vblank = ironlake_disable_vblank;
2709         } else {
2710                 if (INTEL_INFO(dev)->gen == 2) {
2711                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
2712                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
2713                         dev->driver->irq_handler = i8xx_irq_handler;
2714                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
2715                 } else if (INTEL_INFO(dev)->gen == 3) {
2716                         /* IIR "flip pending" means done if this bit is set */
2717                         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
2718
2719                         dev->driver->irq_preinstall = i915_irq_preinstall;
2720                         dev->driver->irq_postinstall = i915_irq_postinstall;
2721                         dev->driver->irq_uninstall = i915_irq_uninstall;
2722                         dev->driver->irq_handler = i915_irq_handler;
2723                 } else {
2724                         dev->driver->irq_preinstall = i965_irq_preinstall;
2725                         dev->driver->irq_postinstall = i965_irq_postinstall;
2726                         dev->driver->irq_uninstall = i965_irq_uninstall;
2727                         dev->driver->irq_handler = i965_irq_handler;
2728                 }
2729                 dev->driver->enable_vblank = i915_enable_vblank;
2730                 dev->driver->disable_vblank = i915_disable_vblank;
2731         }
2732 }