1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/circ_buf.h>
32 #include <linux/cpuidle.h>
33 #include <linux/slab.h>
34 #include <linux/sysrq.h>
36 #include <drm/drm_drv.h>
37 #include <drm/drm_irq.h>
38 #include <drm/i915_drm.h>
40 #include "display/intel_fifo_underrun.h"
41 #include "display/intel_hotplug.h"
42 #include "display/intel_lpe_audio.h"
43 #include "display/intel_psr.h"
47 #include "i915_trace.h"
48 #include "intel_drv.h"
52 * DOC: interrupt handling
54 * These functions provide the basic support for enabling and disabling the
55 * interrupt handling support. There's a lot more functionality in i915_irq.c
56 * and related files, but that will be described in separate chapters.
59 static const u32 hpd_ilk[HPD_NUM_PINS] = {
60 [HPD_PORT_A] = DE_DP_A_HOTPLUG,
63 static const u32 hpd_ivb[HPD_NUM_PINS] = {
64 [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
67 static const u32 hpd_bdw[HPD_NUM_PINS] = {
68 [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
71 static const u32 hpd_ibx[HPD_NUM_PINS] = {
72 [HPD_CRT] = SDE_CRT_HOTPLUG,
73 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
74 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
75 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
76 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
79 static const u32 hpd_cpt[HPD_NUM_PINS] = {
80 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
81 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
82 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
83 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
84 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
87 static const u32 hpd_spt[HPD_NUM_PINS] = {
88 [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
89 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
90 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
91 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
92 [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT
95 static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
96 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
97 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
98 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
99 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
100 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
101 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
104 static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
105 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
106 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
107 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
108 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
109 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
110 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
113 static const u32 hpd_status_i915[HPD_NUM_PINS] = {
114 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
115 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
116 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
117 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
118 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
119 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
123 static const u32 hpd_bxt[HPD_NUM_PINS] = {
124 [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
125 [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
126 [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
129 static const u32 hpd_gen11[HPD_NUM_PINS] = {
130 [HPD_PORT_C] = GEN11_TC1_HOTPLUG | GEN11_TBT1_HOTPLUG,
131 [HPD_PORT_D] = GEN11_TC2_HOTPLUG | GEN11_TBT2_HOTPLUG,
132 [HPD_PORT_E] = GEN11_TC3_HOTPLUG | GEN11_TBT3_HOTPLUG,
133 [HPD_PORT_F] = GEN11_TC4_HOTPLUG | GEN11_TBT4_HOTPLUG
136 static const u32 hpd_icp[HPD_NUM_PINS] = {
137 [HPD_PORT_A] = SDE_DDIA_HOTPLUG_ICP,
138 [HPD_PORT_B] = SDE_DDIB_HOTPLUG_ICP,
139 [HPD_PORT_C] = SDE_TC1_HOTPLUG_ICP,
140 [HPD_PORT_D] = SDE_TC2_HOTPLUG_ICP,
141 [HPD_PORT_E] = SDE_TC3_HOTPLUG_ICP,
142 [HPD_PORT_F] = SDE_TC4_HOTPLUG_ICP
145 static const u32 hpd_mcc[HPD_NUM_PINS] = {
146 [HPD_PORT_A] = SDE_DDIA_HOTPLUG_ICP,
147 [HPD_PORT_B] = SDE_DDIB_HOTPLUG_ICP,
148 [HPD_PORT_C] = SDE_TC1_HOTPLUG_ICP
151 static void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
152 i915_reg_t iir, i915_reg_t ier)
154 intel_uncore_write(uncore, imr, 0xffffffff);
155 intel_uncore_posting_read(uncore, imr);
157 intel_uncore_write(uncore, ier, 0);
159 /* IIR can theoretically queue up two events. Be paranoid. */
160 intel_uncore_write(uncore, iir, 0xffffffff);
161 intel_uncore_posting_read(uncore, iir);
162 intel_uncore_write(uncore, iir, 0xffffffff);
163 intel_uncore_posting_read(uncore, iir);
166 static void gen2_irq_reset(struct intel_uncore *uncore)
168 intel_uncore_write16(uncore, GEN2_IMR, 0xffff);
169 intel_uncore_posting_read16(uncore, GEN2_IMR);
171 intel_uncore_write16(uncore, GEN2_IER, 0);
173 /* IIR can theoretically queue up two events. Be paranoid. */
174 intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
175 intel_uncore_posting_read16(uncore, GEN2_IIR);
176 intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
177 intel_uncore_posting_read16(uncore, GEN2_IIR);
180 #define GEN8_IRQ_RESET_NDX(uncore, type, which) \
182 unsigned int which_ = which; \
183 gen3_irq_reset((uncore), GEN8_##type##_IMR(which_), \
184 GEN8_##type##_IIR(which_), GEN8_##type##_IER(which_)); \
187 #define GEN3_IRQ_RESET(uncore, type) \
188 gen3_irq_reset((uncore), type##IMR, type##IIR, type##IER)
190 #define GEN2_IRQ_RESET(uncore) \
191 gen2_irq_reset(uncore)
194 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
196 static void gen3_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg)
198 u32 val = intel_uncore_read(uncore, reg);
203 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
204 i915_mmio_reg_offset(reg), val);
205 intel_uncore_write(uncore, reg, 0xffffffff);
206 intel_uncore_posting_read(uncore, reg);
207 intel_uncore_write(uncore, reg, 0xffffffff);
208 intel_uncore_posting_read(uncore, reg);
211 static void gen2_assert_iir_is_zero(struct intel_uncore *uncore)
213 u16 val = intel_uncore_read16(uncore, GEN2_IIR);
218 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
219 i915_mmio_reg_offset(GEN2_IIR), val);
220 intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
221 intel_uncore_posting_read16(uncore, GEN2_IIR);
222 intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
223 intel_uncore_posting_read16(uncore, GEN2_IIR);
226 static void gen3_irq_init(struct intel_uncore *uncore,
227 i915_reg_t imr, u32 imr_val,
228 i915_reg_t ier, u32 ier_val,
231 gen3_assert_iir_is_zero(uncore, iir);
233 intel_uncore_write(uncore, ier, ier_val);
234 intel_uncore_write(uncore, imr, imr_val);
235 intel_uncore_posting_read(uncore, imr);
238 static void gen2_irq_init(struct intel_uncore *uncore,
239 u32 imr_val, u32 ier_val)
241 gen2_assert_iir_is_zero(uncore);
243 intel_uncore_write16(uncore, GEN2_IER, ier_val);
244 intel_uncore_write16(uncore, GEN2_IMR, imr_val);
245 intel_uncore_posting_read16(uncore, GEN2_IMR);
248 #define GEN8_IRQ_INIT_NDX(uncore, type, which, imr_val, ier_val) \
250 unsigned int which_ = which; \
251 gen3_irq_init((uncore), \
252 GEN8_##type##_IMR(which_), imr_val, \
253 GEN8_##type##_IER(which_), ier_val, \
254 GEN8_##type##_IIR(which_)); \
257 #define GEN3_IRQ_INIT(uncore, type, imr_val, ier_val) \
258 gen3_irq_init((uncore), \
259 type##IMR, imr_val, \
260 type##IER, ier_val, \
263 #define GEN2_IRQ_INIT(uncore, imr_val, ier_val) \
264 gen2_irq_init((uncore), imr_val, ier_val)
266 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
267 static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
269 /* For display hotplug interrupt */
271 i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
277 lockdep_assert_held(&dev_priv->irq_lock);
278 WARN_ON(bits & ~mask);
280 val = I915_READ(PORT_HOTPLUG_EN);
283 I915_WRITE(PORT_HOTPLUG_EN, val);
287 * i915_hotplug_interrupt_update - update hotplug interrupt enable
288 * @dev_priv: driver private
289 * @mask: bits to update
290 * @bits: bits to enable
291 * NOTE: the HPD enable bits are modified both inside and outside
292 * of an interrupt context. To avoid that read-modify-write cycles
293 * interfer, these bits are protected by a spinlock. Since this
294 * function is usually not called from a context where the lock is
295 * held already, this function acquires the lock itself. A non-locking
296 * version is also available.
298 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
302 spin_lock_irq(&dev_priv->irq_lock);
303 i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
304 spin_unlock_irq(&dev_priv->irq_lock);
308 gen11_gt_engine_identity(struct intel_gt *gt,
309 const unsigned int bank, const unsigned int bit);
311 static bool gen11_reset_one_iir(struct intel_gt *gt,
312 const unsigned int bank,
313 const unsigned int bit)
315 void __iomem * const regs = gt->uncore->regs;
318 lockdep_assert_held(>->i915->irq_lock);
320 dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));
323 * According to the BSpec, DW_IIR bits cannot be cleared without
324 * first servicing the Selector & Shared IIR registers.
326 gen11_gt_engine_identity(gt, bank, bit);
329 * We locked GT INT DW by reading it. If we want to (try
330 * to) recover from this succesfully, we need to clear
331 * our bit, otherwise we are locking the register for
334 raw_reg_write(regs, GEN11_GT_INTR_DW(bank), BIT(bit));
343 * ilk_update_display_irq - update DEIMR
344 * @dev_priv: driver private
345 * @interrupt_mask: mask of interrupt bits to update
346 * @enabled_irq_mask: mask of interrupt bits to enable
348 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
350 u32 enabled_irq_mask)
354 lockdep_assert_held(&dev_priv->irq_lock);
356 WARN_ON(enabled_irq_mask & ~interrupt_mask);
358 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
361 new_val = dev_priv->irq_mask;
362 new_val &= ~interrupt_mask;
363 new_val |= (~enabled_irq_mask & interrupt_mask);
365 if (new_val != dev_priv->irq_mask) {
366 dev_priv->irq_mask = new_val;
367 I915_WRITE(DEIMR, dev_priv->irq_mask);
373 * ilk_update_gt_irq - update GTIMR
374 * @dev_priv: driver private
375 * @interrupt_mask: mask of interrupt bits to update
376 * @enabled_irq_mask: mask of interrupt bits to enable
378 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
380 u32 enabled_irq_mask)
382 lockdep_assert_held(&dev_priv->irq_lock);
384 WARN_ON(enabled_irq_mask & ~interrupt_mask);
386 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
389 dev_priv->gt_irq_mask &= ~interrupt_mask;
390 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
391 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
394 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, u32 mask)
396 ilk_update_gt_irq(dev_priv, mask, mask);
397 intel_uncore_posting_read_fw(&dev_priv->uncore, GTIMR);
400 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, u32 mask)
402 ilk_update_gt_irq(dev_priv, mask, 0);
405 static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
407 WARN_ON_ONCE(INTEL_GEN(dev_priv) >= 11);
409 return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
412 static void write_pm_imr(struct drm_i915_private *dev_priv)
415 u32 mask = dev_priv->pm_imr;
417 if (INTEL_GEN(dev_priv) >= 11) {
418 reg = GEN11_GPM_WGBOXPERF_INTR_MASK;
419 /* pm is in upper half */
421 } else if (INTEL_GEN(dev_priv) >= 8) {
422 reg = GEN8_GT_IMR(2);
427 I915_WRITE(reg, mask);
431 static void write_pm_ier(struct drm_i915_private *dev_priv)
434 u32 mask = dev_priv->pm_ier;
436 if (INTEL_GEN(dev_priv) >= 11) {
437 reg = GEN11_GPM_WGBOXPERF_INTR_ENABLE;
438 /* pm is in upper half */
440 } else if (INTEL_GEN(dev_priv) >= 8) {
441 reg = GEN8_GT_IER(2);
446 I915_WRITE(reg, mask);
450 * snb_update_pm_irq - update GEN6_PMIMR
451 * @dev_priv: driver private
452 * @interrupt_mask: mask of interrupt bits to update
453 * @enabled_irq_mask: mask of interrupt bits to enable
455 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
457 u32 enabled_irq_mask)
461 WARN_ON(enabled_irq_mask & ~interrupt_mask);
463 lockdep_assert_held(&dev_priv->irq_lock);
465 new_val = dev_priv->pm_imr;
466 new_val &= ~interrupt_mask;
467 new_val |= (~enabled_irq_mask & interrupt_mask);
469 if (new_val != dev_priv->pm_imr) {
470 dev_priv->pm_imr = new_val;
471 write_pm_imr(dev_priv);
475 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
477 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
480 snb_update_pm_irq(dev_priv, mask, mask);
483 static void __gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
485 snb_update_pm_irq(dev_priv, mask, 0);
488 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
490 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
493 __gen6_mask_pm_irq(dev_priv, mask);
496 static void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
498 i915_reg_t reg = gen6_pm_iir(dev_priv);
500 lockdep_assert_held(&dev_priv->irq_lock);
502 I915_WRITE(reg, reset_mask);
503 I915_WRITE(reg, reset_mask);
507 static void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask)
509 lockdep_assert_held(&dev_priv->irq_lock);
511 dev_priv->pm_ier |= enable_mask;
512 write_pm_ier(dev_priv);
513 gen6_unmask_pm_irq(dev_priv, enable_mask);
514 /* unmask_pm_irq provides an implicit barrier (POSTING_READ) */
517 static void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask)
519 lockdep_assert_held(&dev_priv->irq_lock);
521 dev_priv->pm_ier &= ~disable_mask;
522 __gen6_mask_pm_irq(dev_priv, disable_mask);
523 write_pm_ier(dev_priv);
524 /* though a barrier is missing here, but don't really need a one */
527 void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv)
529 spin_lock_irq(&dev_priv->irq_lock);
531 while (gen11_reset_one_iir(&dev_priv->gt, 0, GEN11_GTPM))
534 dev_priv->gt_pm.rps.pm_iir = 0;
536 spin_unlock_irq(&dev_priv->irq_lock);
539 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
541 spin_lock_irq(&dev_priv->irq_lock);
542 gen6_reset_pm_iir(dev_priv, GEN6_PM_RPS_EVENTS);
543 dev_priv->gt_pm.rps.pm_iir = 0;
544 spin_unlock_irq(&dev_priv->irq_lock);
547 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
549 struct intel_rps *rps = &dev_priv->gt_pm.rps;
551 if (READ_ONCE(rps->interrupts_enabled))
554 spin_lock_irq(&dev_priv->irq_lock);
555 WARN_ON_ONCE(rps->pm_iir);
557 if (INTEL_GEN(dev_priv) >= 11)
558 WARN_ON_ONCE(gen11_reset_one_iir(&dev_priv->gt, 0, GEN11_GTPM));
560 WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
562 rps->interrupts_enabled = true;
563 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
565 spin_unlock_irq(&dev_priv->irq_lock);
568 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
570 struct intel_rps *rps = &dev_priv->gt_pm.rps;
572 if (!READ_ONCE(rps->interrupts_enabled))
575 spin_lock_irq(&dev_priv->irq_lock);
576 rps->interrupts_enabled = false;
578 I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0u));
580 gen6_disable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
582 spin_unlock_irq(&dev_priv->irq_lock);
583 intel_synchronize_irq(dev_priv);
585 /* Now that we will not be generating any more work, flush any
586 * outstanding tasks. As we are called on the RPS idle path,
587 * we will reset the GPU to minimum frequencies, so the current
588 * state of the worker can be discarded.
590 cancel_work_sync(&rps->work);
591 if (INTEL_GEN(dev_priv) >= 11)
592 gen11_reset_rps_interrupts(dev_priv);
594 gen6_reset_rps_interrupts(dev_priv);
597 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
599 assert_rpm_wakelock_held(&dev_priv->runtime_pm);
601 spin_lock_irq(&dev_priv->irq_lock);
602 gen6_reset_pm_iir(dev_priv, dev_priv->pm_guc_events);
603 spin_unlock_irq(&dev_priv->irq_lock);
606 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
608 assert_rpm_wakelock_held(&dev_priv->runtime_pm);
610 spin_lock_irq(&dev_priv->irq_lock);
611 if (!dev_priv->guc.interrupts.enabled) {
612 WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
613 dev_priv->pm_guc_events);
614 dev_priv->guc.interrupts.enabled = true;
615 gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events);
617 spin_unlock_irq(&dev_priv->irq_lock);
620 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
622 assert_rpm_wakelock_held(&dev_priv->runtime_pm);
624 spin_lock_irq(&dev_priv->irq_lock);
625 dev_priv->guc.interrupts.enabled = false;
627 gen6_disable_pm_irq(dev_priv, dev_priv->pm_guc_events);
629 spin_unlock_irq(&dev_priv->irq_lock);
630 intel_synchronize_irq(dev_priv);
632 gen9_reset_guc_interrupts(dev_priv);
635 void gen11_reset_guc_interrupts(struct drm_i915_private *i915)
637 spin_lock_irq(&i915->irq_lock);
638 gen11_reset_one_iir(&i915->gt, 0, GEN11_GUC);
639 spin_unlock_irq(&i915->irq_lock);
642 void gen11_enable_guc_interrupts(struct drm_i915_private *dev_priv)
644 spin_lock_irq(&dev_priv->irq_lock);
645 if (!dev_priv->guc.interrupts.enabled) {
646 u32 events = REG_FIELD_PREP(ENGINE1_MASK,
647 GEN11_GUC_INTR_GUC2HOST);
649 WARN_ON_ONCE(gen11_reset_one_iir(&dev_priv->gt, 0, GEN11_GUC));
650 I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, events);
651 I915_WRITE(GEN11_GUC_SG_INTR_MASK, ~events);
652 dev_priv->guc.interrupts.enabled = true;
654 spin_unlock_irq(&dev_priv->irq_lock);
657 void gen11_disable_guc_interrupts(struct drm_i915_private *dev_priv)
659 spin_lock_irq(&dev_priv->irq_lock);
660 dev_priv->guc.interrupts.enabled = false;
662 I915_WRITE(GEN11_GUC_SG_INTR_MASK, ~0);
663 I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, 0);
665 spin_unlock_irq(&dev_priv->irq_lock);
666 intel_synchronize_irq(dev_priv);
668 gen11_reset_guc_interrupts(dev_priv);
672 * bdw_update_port_irq - update DE port interrupt
673 * @dev_priv: driver private
674 * @interrupt_mask: mask of interrupt bits to update
675 * @enabled_irq_mask: mask of interrupt bits to enable
677 static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
679 u32 enabled_irq_mask)
684 lockdep_assert_held(&dev_priv->irq_lock);
686 WARN_ON(enabled_irq_mask & ~interrupt_mask);
688 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
691 old_val = I915_READ(GEN8_DE_PORT_IMR);
694 new_val &= ~interrupt_mask;
695 new_val |= (~enabled_irq_mask & interrupt_mask);
697 if (new_val != old_val) {
698 I915_WRITE(GEN8_DE_PORT_IMR, new_val);
699 POSTING_READ(GEN8_DE_PORT_IMR);
704 * bdw_update_pipe_irq - update DE pipe interrupt
705 * @dev_priv: driver private
706 * @pipe: pipe whose interrupt to update
707 * @interrupt_mask: mask of interrupt bits to update
708 * @enabled_irq_mask: mask of interrupt bits to enable
710 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
713 u32 enabled_irq_mask)
717 lockdep_assert_held(&dev_priv->irq_lock);
719 WARN_ON(enabled_irq_mask & ~interrupt_mask);
721 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
724 new_val = dev_priv->de_irq_mask[pipe];
725 new_val &= ~interrupt_mask;
726 new_val |= (~enabled_irq_mask & interrupt_mask);
728 if (new_val != dev_priv->de_irq_mask[pipe]) {
729 dev_priv->de_irq_mask[pipe] = new_val;
730 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
731 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
736 * ibx_display_interrupt_update - update SDEIMR
737 * @dev_priv: driver private
738 * @interrupt_mask: mask of interrupt bits to update
739 * @enabled_irq_mask: mask of interrupt bits to enable
741 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
743 u32 enabled_irq_mask)
745 u32 sdeimr = I915_READ(SDEIMR);
746 sdeimr &= ~interrupt_mask;
747 sdeimr |= (~enabled_irq_mask & interrupt_mask);
749 WARN_ON(enabled_irq_mask & ~interrupt_mask);
751 lockdep_assert_held(&dev_priv->irq_lock);
753 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
756 I915_WRITE(SDEIMR, sdeimr);
757 POSTING_READ(SDEIMR);
760 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
763 u32 status_mask = dev_priv->pipestat_irq_mask[pipe];
764 u32 enable_mask = status_mask << 16;
766 lockdep_assert_held(&dev_priv->irq_lock);
768 if (INTEL_GEN(dev_priv) < 5)
772 * On pipe A we don't support the PSR interrupt yet,
773 * on pipe B and C the same bit MBZ.
775 if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
778 * On pipe B and C we don't support the PSR interrupt yet, on pipe
779 * A the same bit is for perf counters which we don't use either.
781 if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
784 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
785 SPRITE0_FLIP_DONE_INT_EN_VLV |
786 SPRITE1_FLIP_DONE_INT_EN_VLV);
787 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
788 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
789 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
790 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
793 WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
794 status_mask & ~PIPESTAT_INT_STATUS_MASK,
795 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
796 pipe_name(pipe), enable_mask, status_mask);
801 void i915_enable_pipestat(struct drm_i915_private *dev_priv,
802 enum pipe pipe, u32 status_mask)
804 i915_reg_t reg = PIPESTAT(pipe);
807 WARN_ONCE(status_mask & ~PIPESTAT_INT_STATUS_MASK,
808 "pipe %c: status_mask=0x%x\n",
809 pipe_name(pipe), status_mask);
811 lockdep_assert_held(&dev_priv->irq_lock);
812 WARN_ON(!intel_irqs_enabled(dev_priv));
814 if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == status_mask)
817 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
818 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
820 I915_WRITE(reg, enable_mask | status_mask);
824 void i915_disable_pipestat(struct drm_i915_private *dev_priv,
825 enum pipe pipe, u32 status_mask)
827 i915_reg_t reg = PIPESTAT(pipe);
830 WARN_ONCE(status_mask & ~PIPESTAT_INT_STATUS_MASK,
831 "pipe %c: status_mask=0x%x\n",
832 pipe_name(pipe), status_mask);
834 lockdep_assert_held(&dev_priv->irq_lock);
835 WARN_ON(!intel_irqs_enabled(dev_priv));
837 if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == 0)
840 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
841 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
843 I915_WRITE(reg, enable_mask | status_mask);
847 static bool i915_has_asle(struct drm_i915_private *dev_priv)
849 if (!dev_priv->opregion.asle)
852 return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
856 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
857 * @dev_priv: i915 device private
859 static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
861 if (!i915_has_asle(dev_priv))
864 spin_lock_irq(&dev_priv->irq_lock);
866 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
867 if (INTEL_GEN(dev_priv) >= 4)
868 i915_enable_pipestat(dev_priv, PIPE_A,
869 PIPE_LEGACY_BLC_EVENT_STATUS);
871 spin_unlock_irq(&dev_priv->irq_lock);
875 * This timing diagram depicts the video signal in and
876 * around the vertical blanking period.
878 * Assumptions about the fictitious mode used in this example:
880 * vsync_start = vblank_start + 1
881 * vsync_end = vblank_start + 2
882 * vtotal = vblank_start + 3
885 * latch double buffered registers
886 * increment frame counter (ctg+)
887 * generate start of vblank interrupt (gen4+)
890 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
891 * | may be shifted forward 1-3 extra lines via PIPECONF
893 * | | start of vsync:
894 * | | generate vsync interrupt
896 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
897 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
898 * ----va---> <-----------------vb--------------------> <--------va-------------
899 * | | <----vs-----> |
900 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
901 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
902 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
904 * last visible pixel first visible pixel
905 * | increment frame counter (gen3/4)
906 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
908 * x = horizontal active
909 * _ = horizontal blanking
910 * hs = horizontal sync
911 * va = vertical active
912 * vb = vertical blanking
914 * vbs = vblank_start (number)
917 * - most events happen at the start of horizontal sync
918 * - frame start happens at the start of horizontal blank, 1-4 lines
919 * (depending on PIPECONF settings) after the start of vblank
920 * - gen3/4 pixel and frame counter are synchronized with the start
921 * of horizontal active on the first line of vertical active
924 /* Called from drm generic code, passed a 'crtc', which
925 * we use as a pipe index
927 u32 i915_get_vblank_counter(struct drm_crtc *crtc)
929 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
930 struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)];
931 const struct drm_display_mode *mode = &vblank->hwmode;
932 enum pipe pipe = to_intel_crtc(crtc)->pipe;
933 i915_reg_t high_frame, low_frame;
934 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
935 unsigned long irqflags;
938 * On i965gm TV output the frame counter only works up to
939 * the point when we enable the TV encoder. After that the
940 * frame counter ceases to work and reads zero. We need a
941 * vblank wait before enabling the TV encoder and so we
942 * have to enable vblank interrupts while the frame counter
943 * is still in a working state. However the core vblank code
944 * does not like us returning non-zero frame counter values
945 * when we've told it that we don't have a working frame
946 * counter. Thus we must stop non-zero values leaking out.
948 if (!vblank->max_vblank_count)
951 htotal = mode->crtc_htotal;
952 hsync_start = mode->crtc_hsync_start;
953 vbl_start = mode->crtc_vblank_start;
954 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
955 vbl_start = DIV_ROUND_UP(vbl_start, 2);
957 /* Convert to pixel count */
960 /* Start of vblank event occurs at start of hsync */
961 vbl_start -= htotal - hsync_start;
963 high_frame = PIPEFRAME(pipe);
964 low_frame = PIPEFRAMEPIXEL(pipe);
966 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
969 * High & low register fields aren't synchronized, so make sure
970 * we get a low value that's stable across two reads of the high
974 high1 = I915_READ_FW(high_frame) & PIPE_FRAME_HIGH_MASK;
975 low = I915_READ_FW(low_frame);
976 high2 = I915_READ_FW(high_frame) & PIPE_FRAME_HIGH_MASK;
977 } while (high1 != high2);
979 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
981 high1 >>= PIPE_FRAME_HIGH_SHIFT;
982 pixel = low & PIPE_PIXEL_MASK;
983 low >>= PIPE_FRAME_LOW_SHIFT;
986 * The frame counter increments at beginning of active.
987 * Cook up a vblank counter by also checking the pixel
988 * counter against vblank start.
990 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
993 u32 g4x_get_vblank_counter(struct drm_crtc *crtc)
995 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
996 enum pipe pipe = to_intel_crtc(crtc)->pipe;
998 return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
1002 * On certain encoders on certain platforms, pipe
1003 * scanline register will not work to get the scanline,
1004 * since the timings are driven from the PORT or issues
1005 * with scanline register updates.
1006 * This function will use Framestamp and current
1007 * timestamp registers to calculate the scanline.
1009 static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)
1011 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1012 struct drm_vblank_crtc *vblank =
1013 &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
1014 const struct drm_display_mode *mode = &vblank->hwmode;
1015 u32 vblank_start = mode->crtc_vblank_start;
1016 u32 vtotal = mode->crtc_vtotal;
1017 u32 htotal = mode->crtc_htotal;
1018 u32 clock = mode->crtc_clock;
1019 u32 scanline, scan_prev_time, scan_curr_time, scan_post_time;
1022 * To avoid the race condition where we might cross into the
1023 * next vblank just between the PIPE_FRMTMSTMP and TIMESTAMP_CTR
1024 * reads. We make sure we read PIPE_FRMTMSTMP and TIMESTAMP_CTR
1025 * during the same frame.
1029 * This field provides read back of the display
1030 * pipe frame time stamp. The time stamp value
1031 * is sampled at every start of vertical blank.
1033 scan_prev_time = I915_READ_FW(PIPE_FRMTMSTMP(crtc->pipe));
1036 * The TIMESTAMP_CTR register has the current
1039 scan_curr_time = I915_READ_FW(IVB_TIMESTAMP_CTR);
1041 scan_post_time = I915_READ_FW(PIPE_FRMTMSTMP(crtc->pipe));
1042 } while (scan_post_time != scan_prev_time);
1044 scanline = div_u64(mul_u32_u32(scan_curr_time - scan_prev_time,
1045 clock), 1000 * htotal);
1046 scanline = min(scanline, vtotal - 1);
1047 scanline = (scanline + vblank_start) % vtotal;
1052 /* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
1053 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
1055 struct drm_device *dev = crtc->base.dev;
1056 struct drm_i915_private *dev_priv = to_i915(dev);
1057 const struct drm_display_mode *mode;
1058 struct drm_vblank_crtc *vblank;
1059 enum pipe pipe = crtc->pipe;
1060 int position, vtotal;
1065 vblank = &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
1066 mode = &vblank->hwmode;
1068 if (mode->private_flags & I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP)
1069 return __intel_get_crtc_scanline_from_timestamp(crtc);
1071 vtotal = mode->crtc_vtotal;
1072 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1075 if (IS_GEN(dev_priv, 2))
1076 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
1078 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
1081 * On HSW, the DSL reg (0x70000) appears to return 0 if we
1082 * read it just before the start of vblank. So try it again
1083 * so we don't accidentally end up spanning a vblank frame
1084 * increment, causing the pipe_update_end() code to squak at us.
1086 * The nature of this problem means we can't simply check the ISR
1087 * bit and return the vblank start value; nor can we use the scanline
1088 * debug register in the transcoder as it appears to have the same
1089 * problem. We may need to extend this to include other platforms,
1090 * but so far testing only shows the problem on HSW.
1092 if (HAS_DDI(dev_priv) && !position) {
1095 for (i = 0; i < 100; i++) {
1097 temp = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
1098 if (temp != position) {
1106 * See update_scanline_offset() for the details on the
1107 * scanline_offset adjustment.
1109 return (position + crtc->scanline_offset) % vtotal;
1112 bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
1113 bool in_vblank_irq, int *vpos, int *hpos,
1114 ktime_t *stime, ktime_t *etime,
1115 const struct drm_display_mode *mode)
1117 struct drm_i915_private *dev_priv = to_i915(dev);
1118 struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1121 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
1122 unsigned long irqflags;
1123 bool use_scanline_counter = INTEL_GEN(dev_priv) >= 5 ||
1124 IS_G4X(dev_priv) || IS_GEN(dev_priv, 2) ||
1125 mode->private_flags & I915_MODE_FLAG_USE_SCANLINE_COUNTER;
1127 if (WARN_ON(!mode->crtc_clock)) {
1128 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
1129 "pipe %c\n", pipe_name(pipe));
1133 htotal = mode->crtc_htotal;
1134 hsync_start = mode->crtc_hsync_start;
1135 vtotal = mode->crtc_vtotal;
1136 vbl_start = mode->crtc_vblank_start;
1137 vbl_end = mode->crtc_vblank_end;
1139 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1140 vbl_start = DIV_ROUND_UP(vbl_start, 2);
1146 * Lock uncore.lock, as we will do multiple timing critical raw
1147 * register reads, potentially with preemption disabled, so the
1148 * following code must not block on uncore.lock.
1150 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1152 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1154 /* Get optional system timestamp before query. */
1156 *stime = ktime_get();
1158 if (use_scanline_counter) {
1159 /* No obvious pixelcount register. Only query vertical
1160 * scanout position from Display scan line register.
1162 position = __intel_get_crtc_scanline(intel_crtc);
1164 /* Have access to pixelcount since start of frame.
1165 * We can split this into vertical and horizontal
1168 position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
1170 /* convert to pixel counts */
1171 vbl_start *= htotal;
1176 * In interlaced modes, the pixel counter counts all pixels,
1177 * so one field will have htotal more pixels. In order to avoid
1178 * the reported position from jumping backwards when the pixel
1179 * counter is beyond the length of the shorter field, just
1180 * clamp the position the length of the shorter field. This
1181 * matches how the scanline counter based position works since
1182 * the scanline counter doesn't count the two half lines.
1184 if (position >= vtotal)
1185 position = vtotal - 1;
1188 * Start of vblank interrupt is triggered at start of hsync,
1189 * just prior to the first active line of vblank. However we
1190 * consider lines to start at the leading edge of horizontal
1191 * active. So, should we get here before we've crossed into
1192 * the horizontal active of the first line in vblank, we would
1193 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
1194 * always add htotal-hsync_start to the current pixel position.
1196 position = (position + htotal - hsync_start) % vtotal;
1199 /* Get optional system timestamp after query. */
1201 *etime = ktime_get();
1203 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1205 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1208 * While in vblank, position will be negative
1209 * counting up towards 0 at vbl_end. And outside
1210 * vblank, position will be positive counting
1213 if (position >= vbl_start)
1214 position -= vbl_end;
1216 position += vtotal - vbl_end;
1218 if (use_scanline_counter) {
1222 *vpos = position / htotal;
1223 *hpos = position - (*vpos * htotal);
1229 int intel_get_crtc_scanline(struct intel_crtc *crtc)
1231 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1232 unsigned long irqflags;
1235 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1236 position = __intel_get_crtc_scanline(crtc);
1237 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1242 static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv)
1244 struct intel_uncore *uncore = &dev_priv->uncore;
1245 u32 busy_up, busy_down, max_avg, min_avg;
1248 spin_lock(&mchdev_lock);
1250 intel_uncore_write16(uncore,
1252 intel_uncore_read(uncore, MEMINTRSTS));
1254 new_delay = dev_priv->ips.cur_delay;
1256 intel_uncore_write16(uncore, MEMINTRSTS, MEMINT_EVAL_CHG);
1257 busy_up = intel_uncore_read(uncore, RCPREVBSYTUPAVG);
1258 busy_down = intel_uncore_read(uncore, RCPREVBSYTDNAVG);
1259 max_avg = intel_uncore_read(uncore, RCBMAXAVG);
1260 min_avg = intel_uncore_read(uncore, RCBMINAVG);
1262 /* Handle RCS change request from hw */
1263 if (busy_up > max_avg) {
1264 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
1265 new_delay = dev_priv->ips.cur_delay - 1;
1266 if (new_delay < dev_priv->ips.max_delay)
1267 new_delay = dev_priv->ips.max_delay;
1268 } else if (busy_down < min_avg) {
1269 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
1270 new_delay = dev_priv->ips.cur_delay + 1;
1271 if (new_delay > dev_priv->ips.min_delay)
1272 new_delay = dev_priv->ips.min_delay;
1275 if (ironlake_set_drps(dev_priv, new_delay))
1276 dev_priv->ips.cur_delay = new_delay;
1278 spin_unlock(&mchdev_lock);
1283 static void vlv_c0_read(struct drm_i915_private *dev_priv,
1284 struct intel_rps_ei *ei)
1286 ei->ktime = ktime_get_raw();
1287 ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
1288 ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
1291 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
1293 memset(&dev_priv->gt_pm.rps.ei, 0, sizeof(dev_priv->gt_pm.rps.ei));
1296 static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
1298 struct intel_rps *rps = &dev_priv->gt_pm.rps;
1299 const struct intel_rps_ei *prev = &rps->ei;
1300 struct intel_rps_ei now;
1303 if ((pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) == 0)
1306 vlv_c0_read(dev_priv, &now);
1312 time = ktime_us_delta(now.ktime, prev->ktime);
1314 time *= dev_priv->czclk_freq;
1316 /* Workload can be split between render + media,
1317 * e.g. SwapBuffers being blitted in X after being rendered in
1318 * mesa. To account for this we need to combine both engines
1319 * into our activity counter.
1321 render = now.render_c0 - prev->render_c0;
1322 media = now.media_c0 - prev->media_c0;
1323 c0 = max(render, media);
1324 c0 *= 1000 * 100 << 8; /* to usecs and scale to threshold% */
1326 if (c0 > time * rps->power.up_threshold)
1327 events = GEN6_PM_RP_UP_THRESHOLD;
1328 else if (c0 < time * rps->power.down_threshold)
1329 events = GEN6_PM_RP_DOWN_THRESHOLD;
1336 static void gen6_pm_rps_work(struct work_struct *work)
1338 struct drm_i915_private *dev_priv =
1339 container_of(work, struct drm_i915_private, gt_pm.rps.work);
1340 struct intel_rps *rps = &dev_priv->gt_pm.rps;
1341 bool client_boost = false;
1342 int new_delay, adj, min, max;
1345 spin_lock_irq(&dev_priv->irq_lock);
1346 if (rps->interrupts_enabled) {
1347 pm_iir = fetch_and_zero(&rps->pm_iir);
1348 client_boost = atomic_read(&rps->num_waiters);
1350 spin_unlock_irq(&dev_priv->irq_lock);
1352 /* Make sure we didn't queue anything we're not going to process. */
1353 WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1354 if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
1357 mutex_lock(&rps->lock);
1359 pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
1361 adj = rps->last_adj;
1362 new_delay = rps->cur_freq;
1363 min = rps->min_freq_softlimit;
1364 max = rps->max_freq_softlimit;
1366 max = rps->max_freq;
1367 if (client_boost && new_delay < rps->boost_freq) {
1368 new_delay = rps->boost_freq;
1370 } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1373 else /* CHV needs even encode values */
1374 adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
1376 if (new_delay >= rps->max_freq_softlimit)
1378 } else if (client_boost) {
1380 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1381 if (rps->cur_freq > rps->efficient_freq)
1382 new_delay = rps->efficient_freq;
1383 else if (rps->cur_freq > rps->min_freq_softlimit)
1384 new_delay = rps->min_freq_softlimit;
1386 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1389 else /* CHV needs even encode values */
1390 adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
1392 if (new_delay <= rps->min_freq_softlimit)
1394 } else { /* unknown event */
1398 rps->last_adj = adj;
1401 * Limit deboosting and boosting to keep ourselves at the extremes
1402 * when in the respective power modes (i.e. slowly decrease frequencies
1403 * while in the HIGH_POWER zone and slowly increase frequencies while
1404 * in the LOW_POWER zone). On idle, we will hit the timeout and drop
1405 * to the next level quickly, and conversely if busy we expect to
1406 * hit a waitboost and rapidly switch into max power.
1408 if ((adj < 0 && rps->power.mode == HIGH_POWER) ||
1409 (adj > 0 && rps->power.mode == LOW_POWER))
1412 /* sysfs frequency interfaces may have snuck in while servicing the
1416 new_delay = clamp_t(int, new_delay, min, max);
1418 if (intel_set_rps(dev_priv, new_delay)) {
1419 DRM_DEBUG_DRIVER("Failed to set new GPU frequency\n");
1423 mutex_unlock(&rps->lock);
1426 /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1427 spin_lock_irq(&dev_priv->irq_lock);
1428 if (rps->interrupts_enabled)
1429 gen6_unmask_pm_irq(dev_priv, dev_priv->pm_rps_events);
1430 spin_unlock_irq(&dev_priv->irq_lock);
1435 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1437 * @work: workqueue struct
1439 * Doesn't actually do anything except notify userspace. As a consequence of
1440 * this event, userspace should try to remap the bad rows since statistically
1441 * it is likely the same row is more likely to go bad again.
1443 static void ivybridge_parity_work(struct work_struct *work)
1445 struct drm_i915_private *dev_priv =
1446 container_of(work, typeof(*dev_priv), l3_parity.error_work);
1447 u32 error_status, row, bank, subbank;
1448 char *parity_event[6];
1452 /* We must turn off DOP level clock gating to access the L3 registers.
1453 * In order to prevent a get/put style interface, acquire struct mutex
1454 * any time we access those registers.
1456 mutex_lock(&dev_priv->drm.struct_mutex);
1458 /* If we've screwed up tracking, just let the interrupt fire again */
1459 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1462 misccpctl = I915_READ(GEN7_MISCCPCTL);
1463 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1464 POSTING_READ(GEN7_MISCCPCTL);
1466 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1470 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv)))
1473 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1475 reg = GEN7_L3CDERRST1(slice);
1477 error_status = I915_READ(reg);
1478 row = GEN7_PARITY_ERROR_ROW(error_status);
1479 bank = GEN7_PARITY_ERROR_BANK(error_status);
1480 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1482 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1485 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1486 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1487 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1488 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1489 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1490 parity_event[5] = NULL;
1492 kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj,
1493 KOBJ_CHANGE, parity_event);
1495 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1496 slice, row, bank, subbank);
1498 kfree(parity_event[4]);
1499 kfree(parity_event[3]);
1500 kfree(parity_event[2]);
1501 kfree(parity_event[1]);
1504 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1507 WARN_ON(dev_priv->l3_parity.which_slice);
1508 spin_lock_irq(&dev_priv->irq_lock);
1509 gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1510 spin_unlock_irq(&dev_priv->irq_lock);
1512 mutex_unlock(&dev_priv->drm.struct_mutex);
1515 static void ivybridge_parity_error_irq_handler(struct drm_i915_private *dev_priv,
1518 if (!HAS_L3_DPF(dev_priv))
1521 spin_lock(&dev_priv->irq_lock);
1522 gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1523 spin_unlock(&dev_priv->irq_lock);
1525 iir &= GT_PARITY_ERROR(dev_priv);
1526 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1527 dev_priv->l3_parity.which_slice |= 1 << 1;
1529 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1530 dev_priv->l3_parity.which_slice |= 1 << 0;
1532 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1535 static void ilk_gt_irq_handler(struct drm_i915_private *dev_priv,
1538 if (gt_iir & GT_RENDER_USER_INTERRUPT)
1539 intel_engine_breadcrumbs_irq(dev_priv->engine[RCS0]);
1540 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1541 intel_engine_breadcrumbs_irq(dev_priv->engine[VCS0]);
1544 static void snb_gt_irq_handler(struct drm_i915_private *dev_priv,
1547 if (gt_iir & GT_RENDER_USER_INTERRUPT)
1548 intel_engine_breadcrumbs_irq(dev_priv->engine[RCS0]);
1549 if (gt_iir & GT_BSD_USER_INTERRUPT)
1550 intel_engine_breadcrumbs_irq(dev_priv->engine[VCS0]);
1551 if (gt_iir & GT_BLT_USER_INTERRUPT)
1552 intel_engine_breadcrumbs_irq(dev_priv->engine[BCS0]);
1554 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1555 GT_BSD_CS_ERROR_INTERRUPT |
1556 GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1557 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1559 if (gt_iir & GT_PARITY_ERROR(dev_priv))
1560 ivybridge_parity_error_irq_handler(dev_priv, gt_iir);
1564 gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
1566 bool tasklet = false;
1568 if (iir & GT_CONTEXT_SWITCH_INTERRUPT)
1571 if (iir & GT_RENDER_USER_INTERRUPT) {
1572 intel_engine_breadcrumbs_irq(engine);
1573 tasklet |= intel_engine_needs_breadcrumb_tasklet(engine);
1577 tasklet_hi_schedule(&engine->execlists.tasklet);
1580 static void gen8_gt_irq_ack(struct drm_i915_private *i915,
1581 u32 master_ctl, u32 gt_iir[4])
1583 void __iomem * const regs = i915->uncore.regs;
1585 #define GEN8_GT_IRQS (GEN8_GT_RCS_IRQ | \
1587 GEN8_GT_VCS0_IRQ | \
1588 GEN8_GT_VCS1_IRQ | \
1589 GEN8_GT_VECS_IRQ | \
1593 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1594 gt_iir[0] = raw_reg_read(regs, GEN8_GT_IIR(0));
1595 if (likely(gt_iir[0]))
1596 raw_reg_write(regs, GEN8_GT_IIR(0), gt_iir[0]);
1599 if (master_ctl & (GEN8_GT_VCS0_IRQ | GEN8_GT_VCS1_IRQ)) {
1600 gt_iir[1] = raw_reg_read(regs, GEN8_GT_IIR(1));
1601 if (likely(gt_iir[1]))
1602 raw_reg_write(regs, GEN8_GT_IIR(1), gt_iir[1]);
1605 if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
1606 gt_iir[2] = raw_reg_read(regs, GEN8_GT_IIR(2));
1607 if (likely(gt_iir[2]))
1608 raw_reg_write(regs, GEN8_GT_IIR(2), gt_iir[2]);
1611 if (master_ctl & GEN8_GT_VECS_IRQ) {
1612 gt_iir[3] = raw_reg_read(regs, GEN8_GT_IIR(3));
1613 if (likely(gt_iir[3]))
1614 raw_reg_write(regs, GEN8_GT_IIR(3), gt_iir[3]);
1618 static void gen8_gt_irq_handler(struct drm_i915_private *i915,
1619 u32 master_ctl, u32 gt_iir[4])
1621 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1622 gen8_cs_irq_handler(i915->engine[RCS0],
1623 gt_iir[0] >> GEN8_RCS_IRQ_SHIFT);
1624 gen8_cs_irq_handler(i915->engine[BCS0],
1625 gt_iir[0] >> GEN8_BCS_IRQ_SHIFT);
1628 if (master_ctl & (GEN8_GT_VCS0_IRQ | GEN8_GT_VCS1_IRQ)) {
1629 gen8_cs_irq_handler(i915->engine[VCS0],
1630 gt_iir[1] >> GEN8_VCS0_IRQ_SHIFT);
1631 gen8_cs_irq_handler(i915->engine[VCS1],
1632 gt_iir[1] >> GEN8_VCS1_IRQ_SHIFT);
1635 if (master_ctl & GEN8_GT_VECS_IRQ) {
1636 gen8_cs_irq_handler(i915->engine[VECS0],
1637 gt_iir[3] >> GEN8_VECS_IRQ_SHIFT);
1640 if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
1641 gen6_rps_irq_handler(i915, gt_iir[2]);
1642 gen9_guc_irq_handler(i915, gt_iir[2]);
1646 static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1650 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC1);
1652 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC2);
1654 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC3);
1656 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC4);
1662 static bool bxt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1666 return val & PORTA_HOTPLUG_LONG_DETECT;
1668 return val & PORTB_HOTPLUG_LONG_DETECT;
1670 return val & PORTC_HOTPLUG_LONG_DETECT;
1676 static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1680 return val & ICP_DDIA_HPD_LONG_DETECT;
1682 return val & ICP_DDIB_HPD_LONG_DETECT;
1688 static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1692 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
1694 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
1696 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
1698 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
1704 static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val)
1708 return val & PORTE_HOTPLUG_LONG_DETECT;
1714 static bool spt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1718 return val & PORTA_HOTPLUG_LONG_DETECT;
1720 return val & PORTB_HOTPLUG_LONG_DETECT;
1722 return val & PORTC_HOTPLUG_LONG_DETECT;
1724 return val & PORTD_HOTPLUG_LONG_DETECT;
1730 static bool ilk_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1734 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
1740 static bool pch_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1744 return val & PORTB_HOTPLUG_LONG_DETECT;
1746 return val & PORTC_HOTPLUG_LONG_DETECT;
1748 return val & PORTD_HOTPLUG_LONG_DETECT;
1754 static bool i9xx_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1758 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1760 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1762 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1769 * Get a bit mask of pins that have triggered, and which ones may be long.
1770 * This can be called multiple times with the same masks to accumulate
1771 * hotplug detection results from several registers.
1773 * Note that the caller is expected to zero out the masks initially.
1775 static void intel_get_hpd_pins(struct drm_i915_private *dev_priv,
1776 u32 *pin_mask, u32 *long_mask,
1777 u32 hotplug_trigger, u32 dig_hotplug_reg,
1778 const u32 hpd[HPD_NUM_PINS],
1779 bool long_pulse_detect(enum hpd_pin pin, u32 val))
1783 for_each_hpd_pin(pin) {
1784 if ((hpd[pin] & hotplug_trigger) == 0)
1787 *pin_mask |= BIT(pin);
1789 if (long_pulse_detect(pin, dig_hotplug_reg))
1790 *long_mask |= BIT(pin);
1793 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x, long 0x%08x\n",
1794 hotplug_trigger, dig_hotplug_reg, *pin_mask, *long_mask);
1798 static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
1800 wake_up_all(&dev_priv->gmbus_wait_queue);
1803 static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
1805 wake_up_all(&dev_priv->gmbus_wait_queue);
1808 #if defined(CONFIG_DEBUG_FS)
1809 static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1815 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1816 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1817 u32 crcs[5] = { crc0, crc1, crc2, crc3, crc4 };
1819 trace_intel_pipe_crc(crtc, crcs);
1821 spin_lock(&pipe_crc->lock);
1823 * For some not yet identified reason, the first CRC is
1824 * bonkers. So let's just wait for the next vblank and read
1825 * out the buggy result.
1827 * On GEN8+ sometimes the second CRC is bonkers as well, so
1828 * don't trust that one either.
1830 if (pipe_crc->skipped <= 0 ||
1831 (INTEL_GEN(dev_priv) >= 8 && pipe_crc->skipped == 1)) {
1832 pipe_crc->skipped++;
1833 spin_unlock(&pipe_crc->lock);
1836 spin_unlock(&pipe_crc->lock);
1838 drm_crtc_add_crc_entry(&crtc->base, true,
1839 drm_crtc_accurate_vblank_count(&crtc->base),
1844 display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1852 static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1855 display_pipe_crc_irq_handler(dev_priv, pipe,
1856 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1860 static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1863 display_pipe_crc_irq_handler(dev_priv, pipe,
1864 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1865 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1866 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1867 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1868 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1871 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1876 if (INTEL_GEN(dev_priv) >= 3)
1877 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1881 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1882 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1886 display_pipe_crc_irq_handler(dev_priv, pipe,
1887 I915_READ(PIPE_CRC_RES_RED(pipe)),
1888 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1889 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1893 /* The RPS events need forcewake, so we add them to a work queue and mask their
1894 * IMR bits until the work is done. Other interrupts can be processed without
1895 * the work queue. */
1896 static void gen11_rps_irq_handler(struct drm_i915_private *i915, u32 pm_iir)
1898 struct intel_rps *rps = &i915->gt_pm.rps;
1899 const u32 events = i915->pm_rps_events & pm_iir;
1901 lockdep_assert_held(&i915->irq_lock);
1903 if (unlikely(!events))
1906 gen6_mask_pm_irq(i915, events);
1908 if (!rps->interrupts_enabled)
1911 rps->pm_iir |= events;
1912 schedule_work(&rps->work);
1915 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1917 struct intel_rps *rps = &dev_priv->gt_pm.rps;
1919 if (pm_iir & dev_priv->pm_rps_events) {
1920 spin_lock(&dev_priv->irq_lock);
1921 gen6_mask_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1922 if (rps->interrupts_enabled) {
1923 rps->pm_iir |= pm_iir & dev_priv->pm_rps_events;
1924 schedule_work(&rps->work);
1926 spin_unlock(&dev_priv->irq_lock);
1929 if (INTEL_GEN(dev_priv) >= 8)
1932 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1933 intel_engine_breadcrumbs_irq(dev_priv->engine[VECS0]);
1935 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1936 DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
1939 static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir)
1941 if (gt_iir & GEN9_GUC_TO_HOST_INT_EVENT)
1942 intel_guc_to_host_event_handler(&dev_priv->guc);
1945 static void gen11_guc_irq_handler(struct drm_i915_private *i915, u16 iir)
1947 if (iir & GEN11_GUC_INTR_GUC2HOST)
1948 intel_guc_to_host_event_handler(&i915->guc);
1951 static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
1955 for_each_pipe(dev_priv, pipe) {
1956 I915_WRITE(PIPESTAT(pipe),
1957 PIPESTAT_INT_STATUS_MASK |
1958 PIPE_FIFO_UNDERRUN_STATUS);
1960 dev_priv->pipestat_irq_mask[pipe] = 0;
1964 static void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,
1965 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1969 spin_lock(&dev_priv->irq_lock);
1971 if (!dev_priv->display_irqs_enabled) {
1972 spin_unlock(&dev_priv->irq_lock);
1976 for_each_pipe(dev_priv, pipe) {
1978 u32 status_mask, enable_mask, iir_bit = 0;
1981 * PIPESTAT bits get signalled even when the interrupt is
1982 * disabled with the mask bits, and some of the status bits do
1983 * not generate interrupts at all (like the underrun bit). Hence
1984 * we need to be careful that we only handle what we want to
1988 /* fifo underruns are filterered in the underrun handler. */
1989 status_mask = PIPE_FIFO_UNDERRUN_STATUS;
1993 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1996 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1999 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
2003 status_mask |= dev_priv->pipestat_irq_mask[pipe];
2008 reg = PIPESTAT(pipe);
2009 pipe_stats[pipe] = I915_READ(reg) & status_mask;
2010 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
2013 * Clear the PIPE*STAT regs before the IIR
2015 * Toggle the enable bits to make sure we get an
2016 * edge in the ISR pipe event bit if we don't clear
2017 * all the enabled status bits. Otherwise the edge
2018 * triggered IIR on i965/g4x wouldn't notice that
2019 * an interrupt is still pending.
2021 if (pipe_stats[pipe]) {
2022 I915_WRITE(reg, pipe_stats[pipe]);
2023 I915_WRITE(reg, enable_mask);
2026 spin_unlock(&dev_priv->irq_lock);
2029 static void i8xx_pipestat_irq_handler(struct drm_i915_private *dev_priv,
2030 u16 iir, u32 pipe_stats[I915_MAX_PIPES])
2034 for_each_pipe(dev_priv, pipe) {
2035 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
2036 drm_handle_vblank(&dev_priv->drm, pipe);
2038 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
2039 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2041 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2042 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2046 static void i915_pipestat_irq_handler(struct drm_i915_private *dev_priv,
2047 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
2049 bool blc_event = false;
2052 for_each_pipe(dev_priv, pipe) {
2053 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
2054 drm_handle_vblank(&dev_priv->drm, pipe);
2056 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2059 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
2060 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2062 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2063 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2066 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2067 intel_opregion_asle_intr(dev_priv);
2070 static void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv,
2071 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
2073 bool blc_event = false;
2076 for_each_pipe(dev_priv, pipe) {
2077 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
2078 drm_handle_vblank(&dev_priv->drm, pipe);
2080 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2083 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
2084 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2086 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2087 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2090 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2091 intel_opregion_asle_intr(dev_priv);
2093 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
2094 gmbus_irq_handler(dev_priv);
2097 static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
2098 u32 pipe_stats[I915_MAX_PIPES])
2102 for_each_pipe(dev_priv, pipe) {
2103 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
2104 drm_handle_vblank(&dev_priv->drm, pipe);
2106 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
2107 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2109 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2110 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2113 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
2114 gmbus_irq_handler(dev_priv);
2117 static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
2119 u32 hotplug_status = 0, hotplug_status_mask;
2122 if (IS_G4X(dev_priv) ||
2123 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2124 hotplug_status_mask = HOTPLUG_INT_STATUS_G4X |
2125 DP_AUX_CHANNEL_MASK_INT_STATUS_G4X;
2127 hotplug_status_mask = HOTPLUG_INT_STATUS_I915;
2130 * We absolutely have to clear all the pending interrupt
2131 * bits in PORT_HOTPLUG_STAT. Otherwise the ISR port
2132 * interrupt bit won't have an edge, and the i965/g4x
2133 * edge triggered IIR will not notice that an interrupt
2134 * is still pending. We can't use PORT_HOTPLUG_EN to
2135 * guarantee the edge as the act of toggling the enable
2136 * bits can itself generate a new hotplug interrupt :(
2138 for (i = 0; i < 10; i++) {
2139 u32 tmp = I915_READ(PORT_HOTPLUG_STAT) & hotplug_status_mask;
2142 return hotplug_status;
2144 hotplug_status |= tmp;
2145 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2149 "PORT_HOTPLUG_STAT did not clear (0x%08x)\n",
2150 I915_READ(PORT_HOTPLUG_STAT));
2152 return hotplug_status;
2155 static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
2158 u32 pin_mask = 0, long_mask = 0;
2160 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
2161 IS_CHERRYVIEW(dev_priv)) {
2162 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
2164 if (hotplug_trigger) {
2165 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2166 hotplug_trigger, hotplug_trigger,
2168 i9xx_port_hotplug_long_detect);
2170 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2173 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
2174 dp_aux_irq_handler(dev_priv);
2176 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
2178 if (hotplug_trigger) {
2179 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2180 hotplug_trigger, hotplug_trigger,
2182 i9xx_port_hotplug_long_detect);
2183 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2188 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
2190 struct drm_i915_private *dev_priv = arg;
2191 irqreturn_t ret = IRQ_NONE;
2193 if (!intel_irqs_enabled(dev_priv))
2196 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2197 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2200 u32 iir, gt_iir, pm_iir;
2201 u32 pipe_stats[I915_MAX_PIPES] = {};
2202 u32 hotplug_status = 0;
2205 gt_iir = I915_READ(GTIIR);
2206 pm_iir = I915_READ(GEN6_PMIIR);
2207 iir = I915_READ(VLV_IIR);
2209 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
2215 * Theory on interrupt generation, based on empirical evidence:
2217 * x = ((VLV_IIR & VLV_IER) ||
2218 * (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
2219 * (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
2221 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
2222 * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
2223 * guarantee the CPU interrupt will be raised again even if we
2224 * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
2225 * bits this time around.
2227 I915_WRITE(VLV_MASTER_IER, 0);
2228 ier = I915_READ(VLV_IER);
2229 I915_WRITE(VLV_IER, 0);
2232 I915_WRITE(GTIIR, gt_iir);
2234 I915_WRITE(GEN6_PMIIR, pm_iir);
2236 if (iir & I915_DISPLAY_PORT_INTERRUPT)
2237 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
2239 /* Call regardless, as some status bits might not be
2240 * signalled in iir */
2241 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
2243 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
2244 I915_LPE_PIPE_B_INTERRUPT))
2245 intel_lpe_audio_irq_handler(dev_priv);
2248 * VLV_IIR is single buffered, and reflects the level
2249 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
2252 I915_WRITE(VLV_IIR, iir);
2254 I915_WRITE(VLV_IER, ier);
2255 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2258 snb_gt_irq_handler(dev_priv, gt_iir);
2260 gen6_rps_irq_handler(dev_priv, pm_iir);
2263 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
2265 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
2268 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2273 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
2275 struct drm_i915_private *dev_priv = arg;
2276 irqreturn_t ret = IRQ_NONE;
2278 if (!intel_irqs_enabled(dev_priv))
2281 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2282 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2285 u32 master_ctl, iir;
2286 u32 pipe_stats[I915_MAX_PIPES] = {};
2287 u32 hotplug_status = 0;
2291 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
2292 iir = I915_READ(VLV_IIR);
2294 if (master_ctl == 0 && iir == 0)
2300 * Theory on interrupt generation, based on empirical evidence:
2302 * x = ((VLV_IIR & VLV_IER) ||
2303 * ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
2304 * (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
2306 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
2307 * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
2308 * guarantee the CPU interrupt will be raised again even if we
2309 * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
2310 * bits this time around.
2312 I915_WRITE(GEN8_MASTER_IRQ, 0);
2313 ier = I915_READ(VLV_IER);
2314 I915_WRITE(VLV_IER, 0);
2316 gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
2318 if (iir & I915_DISPLAY_PORT_INTERRUPT)
2319 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
2321 /* Call regardless, as some status bits might not be
2322 * signalled in iir */
2323 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
2325 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
2326 I915_LPE_PIPE_B_INTERRUPT |
2327 I915_LPE_PIPE_C_INTERRUPT))
2328 intel_lpe_audio_irq_handler(dev_priv);
2331 * VLV_IIR is single buffered, and reflects the level
2332 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
2335 I915_WRITE(VLV_IIR, iir);
2337 I915_WRITE(VLV_IER, ier);
2338 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2340 gen8_gt_irq_handler(dev_priv, master_ctl, gt_iir);
2343 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
2345 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
2348 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2353 static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
2354 u32 hotplug_trigger,
2355 const u32 hpd[HPD_NUM_PINS])
2357 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2360 * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
2361 * unless we touch the hotplug register, even if hotplug_trigger is
2362 * zero. Not acking leads to "The master control interrupt lied (SDE)!"
2365 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2366 if (!hotplug_trigger) {
2367 u32 mask = PORTA_HOTPLUG_STATUS_MASK |
2368 PORTD_HOTPLUG_STATUS_MASK |
2369 PORTC_HOTPLUG_STATUS_MASK |
2370 PORTB_HOTPLUG_STATUS_MASK;
2371 dig_hotplug_reg &= ~mask;
2374 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2375 if (!hotplug_trigger)
2378 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
2379 dig_hotplug_reg, hpd,
2380 pch_port_hotplug_long_detect);
2382 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2385 static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2388 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
2390 ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ibx);
2392 if (pch_iir & SDE_AUDIO_POWER_MASK) {
2393 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
2394 SDE_AUDIO_POWER_SHIFT);
2395 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
2399 if (pch_iir & SDE_AUX_MASK)
2400 dp_aux_irq_handler(dev_priv);
2402 if (pch_iir & SDE_GMBUS)
2403 gmbus_irq_handler(dev_priv);
2405 if (pch_iir & SDE_AUDIO_HDCP_MASK)
2406 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
2408 if (pch_iir & SDE_AUDIO_TRANS_MASK)
2409 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
2411 if (pch_iir & SDE_POISON)
2412 DRM_ERROR("PCH poison interrupt\n");
2414 if (pch_iir & SDE_FDI_MASK)
2415 for_each_pipe(dev_priv, pipe)
2416 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2418 I915_READ(FDI_RX_IIR(pipe)));
2420 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
2421 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
2423 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
2424 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
2426 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
2427 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A);
2429 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
2430 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B);
2433 static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
2435 u32 err_int = I915_READ(GEN7_ERR_INT);
2438 if (err_int & ERR_INT_POISON)
2439 DRM_ERROR("Poison interrupt\n");
2441 for_each_pipe(dev_priv, pipe) {
2442 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
2443 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2445 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
2446 if (IS_IVYBRIDGE(dev_priv))
2447 ivb_pipe_crc_irq_handler(dev_priv, pipe);
2449 hsw_pipe_crc_irq_handler(dev_priv, pipe);
2453 I915_WRITE(GEN7_ERR_INT, err_int);
2456 static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
2458 u32 serr_int = I915_READ(SERR_INT);
2461 if (serr_int & SERR_INT_POISON)
2462 DRM_ERROR("PCH poison interrupt\n");
2464 for_each_pipe(dev_priv, pipe)
2465 if (serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pipe))
2466 intel_pch_fifo_underrun_irq_handler(dev_priv, pipe);
2468 I915_WRITE(SERR_INT, serr_int);
2471 static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2474 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2476 ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_cpt);
2478 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2479 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2480 SDE_AUDIO_POWER_SHIFT_CPT);
2481 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2485 if (pch_iir & SDE_AUX_MASK_CPT)
2486 dp_aux_irq_handler(dev_priv);
2488 if (pch_iir & SDE_GMBUS_CPT)
2489 gmbus_irq_handler(dev_priv);
2491 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2492 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2494 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2495 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2497 if (pch_iir & SDE_FDI_MASK_CPT)
2498 for_each_pipe(dev_priv, pipe)
2499 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2501 I915_READ(FDI_RX_IIR(pipe)));
2503 if (pch_iir & SDE_ERROR_CPT)
2504 cpt_serr_int_handler(dev_priv);
2507 static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir,
2510 u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
2511 u32 tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
2512 u32 pin_mask = 0, long_mask = 0;
2514 if (ddi_hotplug_trigger) {
2515 u32 dig_hotplug_reg;
2517 dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI);
2518 I915_WRITE(SHOTPLUG_CTL_DDI, dig_hotplug_reg);
2520 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2521 ddi_hotplug_trigger,
2522 dig_hotplug_reg, pins,
2523 icp_ddi_port_hotplug_long_detect);
2526 if (tc_hotplug_trigger) {
2527 u32 dig_hotplug_reg;
2529 dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC);
2530 I915_WRITE(SHOTPLUG_CTL_TC, dig_hotplug_reg);
2532 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2534 dig_hotplug_reg, pins,
2535 icp_tc_port_hotplug_long_detect);
2539 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2541 if (pch_iir & SDE_GMBUS_ICP)
2542 gmbus_irq_handler(dev_priv);
2545 static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2547 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
2548 ~SDE_PORTE_HOTPLUG_SPT;
2549 u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
2550 u32 pin_mask = 0, long_mask = 0;
2552 if (hotplug_trigger) {
2553 u32 dig_hotplug_reg;
2555 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2556 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2558 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2559 hotplug_trigger, dig_hotplug_reg, hpd_spt,
2560 spt_port_hotplug_long_detect);
2563 if (hotplug2_trigger) {
2564 u32 dig_hotplug_reg;
2566 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
2567 I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
2569 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2570 hotplug2_trigger, dig_hotplug_reg, hpd_spt,
2571 spt_port_hotplug2_long_detect);
2575 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2577 if (pch_iir & SDE_GMBUS_CPT)
2578 gmbus_irq_handler(dev_priv);
2581 static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
2582 u32 hotplug_trigger,
2583 const u32 hpd[HPD_NUM_PINS])
2585 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2587 dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
2588 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
2590 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
2591 dig_hotplug_reg, hpd,
2592 ilk_port_hotplug_long_detect);
2594 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2597 static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
2601 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
2603 if (hotplug_trigger)
2604 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk);
2606 if (de_iir & DE_AUX_CHANNEL_A)
2607 dp_aux_irq_handler(dev_priv);
2609 if (de_iir & DE_GSE)
2610 intel_opregion_asle_intr(dev_priv);
2612 if (de_iir & DE_POISON)
2613 DRM_ERROR("Poison interrupt\n");
2615 for_each_pipe(dev_priv, pipe) {
2616 if (de_iir & DE_PIPE_VBLANK(pipe))
2617 drm_handle_vblank(&dev_priv->drm, pipe);
2619 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2620 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2622 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2623 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2626 /* check event from PCH */
2627 if (de_iir & DE_PCH_EVENT) {
2628 u32 pch_iir = I915_READ(SDEIIR);
2630 if (HAS_PCH_CPT(dev_priv))
2631 cpt_irq_handler(dev_priv, pch_iir);
2633 ibx_irq_handler(dev_priv, pch_iir);
2635 /* should clear PCH hotplug event before clear CPU irq */
2636 I915_WRITE(SDEIIR, pch_iir);
2639 if (IS_GEN(dev_priv, 5) && de_iir & DE_PCU_EVENT)
2640 ironlake_rps_change_irq_handler(dev_priv);
2643 static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
2647 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2649 if (hotplug_trigger)
2650 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb);
2652 if (de_iir & DE_ERR_INT_IVB)
2653 ivb_err_int_handler(dev_priv);
2655 if (de_iir & DE_EDP_PSR_INT_HSW) {
2656 u32 psr_iir = I915_READ(EDP_PSR_IIR);
2658 intel_psr_irq_handler(dev_priv, psr_iir);
2659 I915_WRITE(EDP_PSR_IIR, psr_iir);
2662 if (de_iir & DE_AUX_CHANNEL_A_IVB)
2663 dp_aux_irq_handler(dev_priv);
2665 if (de_iir & DE_GSE_IVB)
2666 intel_opregion_asle_intr(dev_priv);
2668 for_each_pipe(dev_priv, pipe) {
2669 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
2670 drm_handle_vblank(&dev_priv->drm, pipe);
2673 /* check event from PCH */
2674 if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
2675 u32 pch_iir = I915_READ(SDEIIR);
2677 cpt_irq_handler(dev_priv, pch_iir);
2679 /* clear PCH hotplug event before clear CPU irq */
2680 I915_WRITE(SDEIIR, pch_iir);
2685 * To handle irqs with the minimum potential races with fresh interrupts, we:
2686 * 1 - Disable Master Interrupt Control.
2687 * 2 - Find the source(s) of the interrupt.
2688 * 3 - Clear the Interrupt Identity bits (IIR).
2689 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2690 * 5 - Re-enable Master Interrupt Control.
2692 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2694 struct drm_i915_private *dev_priv = arg;
2695 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2696 irqreturn_t ret = IRQ_NONE;
2698 if (!intel_irqs_enabled(dev_priv))
2701 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2702 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2704 /* disable master interrupt before clearing iir */
2705 de_ier = I915_READ(DEIER);
2706 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2708 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2709 * interrupts will will be stored on its back queue, and then we'll be
2710 * able to process them after we restore SDEIER (as soon as we restore
2711 * it, we'll get an interrupt if SDEIIR still has something to process
2712 * due to its back queue). */
2713 if (!HAS_PCH_NOP(dev_priv)) {
2714 sde_ier = I915_READ(SDEIER);
2715 I915_WRITE(SDEIER, 0);
2718 /* Find, clear, then process each source of interrupt */
2720 gt_iir = I915_READ(GTIIR);
2722 I915_WRITE(GTIIR, gt_iir);
2724 if (INTEL_GEN(dev_priv) >= 6)
2725 snb_gt_irq_handler(dev_priv, gt_iir);
2727 ilk_gt_irq_handler(dev_priv, gt_iir);
2730 de_iir = I915_READ(DEIIR);
2732 I915_WRITE(DEIIR, de_iir);
2734 if (INTEL_GEN(dev_priv) >= 7)
2735 ivb_display_irq_handler(dev_priv, de_iir);
2737 ilk_display_irq_handler(dev_priv, de_iir);
2740 if (INTEL_GEN(dev_priv) >= 6) {
2741 u32 pm_iir = I915_READ(GEN6_PMIIR);
2743 I915_WRITE(GEN6_PMIIR, pm_iir);
2745 gen6_rps_irq_handler(dev_priv, pm_iir);
2749 I915_WRITE(DEIER, de_ier);
2750 if (!HAS_PCH_NOP(dev_priv))
2751 I915_WRITE(SDEIER, sde_ier);
2753 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2754 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2759 static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
2760 u32 hotplug_trigger,
2761 const u32 hpd[HPD_NUM_PINS])
2763 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2765 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2766 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2768 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
2769 dig_hotplug_reg, hpd,
2770 bxt_port_hotplug_long_detect);
2772 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2775 static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
2777 u32 pin_mask = 0, long_mask = 0;
2778 u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK;
2779 u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK;
2782 u32 dig_hotplug_reg;
2784 dig_hotplug_reg = I915_READ(GEN11_TC_HOTPLUG_CTL);
2785 I915_WRITE(GEN11_TC_HOTPLUG_CTL, dig_hotplug_reg);
2787 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, trigger_tc,
2788 dig_hotplug_reg, hpd_gen11,
2789 gen11_port_hotplug_long_detect);
2793 u32 dig_hotplug_reg;
2795 dig_hotplug_reg = I915_READ(GEN11_TBT_HOTPLUG_CTL);
2796 I915_WRITE(GEN11_TBT_HOTPLUG_CTL, dig_hotplug_reg);
2798 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, trigger_tbt,
2799 dig_hotplug_reg, hpd_gen11,
2800 gen11_port_hotplug_long_detect);
2804 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2806 DRM_ERROR("Unexpected DE HPD interrupt 0x%08x\n", iir);
2809 static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
2811 u32 mask = GEN8_AUX_CHANNEL_A;
2813 if (INTEL_GEN(dev_priv) >= 9)
2814 mask |= GEN9_AUX_CHANNEL_B |
2815 GEN9_AUX_CHANNEL_C |
2818 if (IS_CNL_WITH_PORT_F(dev_priv))
2819 mask |= CNL_AUX_CHANNEL_F;
2821 if (INTEL_GEN(dev_priv) >= 11)
2822 mask |= ICL_AUX_CHANNEL_E |
2829 gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2831 irqreturn_t ret = IRQ_NONE;
2835 if (master_ctl & GEN8_DE_MISC_IRQ) {
2836 iir = I915_READ(GEN8_DE_MISC_IIR);
2840 I915_WRITE(GEN8_DE_MISC_IIR, iir);
2843 if (iir & GEN8_DE_MISC_GSE) {
2844 intel_opregion_asle_intr(dev_priv);
2848 if (iir & GEN8_DE_EDP_PSR) {
2849 u32 psr_iir = I915_READ(EDP_PSR_IIR);
2851 intel_psr_irq_handler(dev_priv, psr_iir);
2852 I915_WRITE(EDP_PSR_IIR, psr_iir);
2857 DRM_ERROR("Unexpected DE Misc interrupt\n");
2860 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2863 if (INTEL_GEN(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) {
2864 iir = I915_READ(GEN11_DE_HPD_IIR);
2866 I915_WRITE(GEN11_DE_HPD_IIR, iir);
2868 gen11_hpd_irq_handler(dev_priv, iir);
2870 DRM_ERROR("The master control interrupt lied, (DE HPD)!\n");
2874 if (master_ctl & GEN8_DE_PORT_IRQ) {
2875 iir = I915_READ(GEN8_DE_PORT_IIR);
2880 I915_WRITE(GEN8_DE_PORT_IIR, iir);
2883 if (iir & gen8_de_port_aux_mask(dev_priv)) {
2884 dp_aux_irq_handler(dev_priv);
2888 if (IS_GEN9_LP(dev_priv)) {
2889 tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
2891 bxt_hpd_irq_handler(dev_priv, tmp_mask,
2895 } else if (IS_BROADWELL(dev_priv)) {
2896 tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
2898 ilk_hpd_irq_handler(dev_priv,
2904 if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
2905 gmbus_irq_handler(dev_priv);
2910 DRM_ERROR("Unexpected DE Port interrupt\n");
2913 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2916 for_each_pipe(dev_priv, pipe) {
2919 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2922 iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2924 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2929 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
2931 if (iir & GEN8_PIPE_VBLANK)
2932 drm_handle_vblank(&dev_priv->drm, pipe);
2934 if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
2935 hsw_pipe_crc_irq_handler(dev_priv, pipe);
2937 if (iir & GEN8_PIPE_FIFO_UNDERRUN)
2938 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2941 if (INTEL_GEN(dev_priv) >= 9)
2942 fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2944 fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2947 DRM_ERROR("Fault errors on pipe %c: 0x%08x\n",
2952 if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
2953 master_ctl & GEN8_DE_PCH_IRQ) {
2955 * FIXME(BDW): Assume for now that the new interrupt handling
2956 * scheme also closed the SDE interrupt handling race we've seen
2957 * on older pch-split platforms. But this needs testing.
2959 iir = I915_READ(SDEIIR);
2961 I915_WRITE(SDEIIR, iir);
2964 if (INTEL_PCH_TYPE(dev_priv) >= PCH_MCC)
2965 icp_irq_handler(dev_priv, iir, hpd_mcc);
2966 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2967 icp_irq_handler(dev_priv, iir, hpd_icp);
2968 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
2969 spt_irq_handler(dev_priv, iir);
2971 cpt_irq_handler(dev_priv, iir);
2974 * Like on previous PCH there seems to be something
2975 * fishy going on with forwarding PCH interrupts.
2977 DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
2984 static inline u32 gen8_master_intr_disable(void __iomem * const regs)
2986 raw_reg_write(regs, GEN8_MASTER_IRQ, 0);
2989 * Now with master disabled, get a sample of level indications
2990 * for this interrupt. Indications will be cleared on related acks.
2991 * New indications can and will light up during processing,
2992 * and will generate new interrupt after enabling master.
2994 return raw_reg_read(regs, GEN8_MASTER_IRQ);
2997 static inline void gen8_master_intr_enable(void __iomem * const regs)
2999 raw_reg_write(regs, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3002 static irqreturn_t gen8_irq_handler(int irq, void *arg)
3004 struct drm_i915_private *dev_priv = arg;
3005 void __iomem * const regs = dev_priv->uncore.regs;
3009 if (!intel_irqs_enabled(dev_priv))
3012 master_ctl = gen8_master_intr_disable(regs);
3014 gen8_master_intr_enable(regs);
3018 /* Find, clear, then process each source of interrupt */
3019 gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
3021 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3022 if (master_ctl & ~GEN8_GT_IRQS) {
3023 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
3024 gen8_de_irq_handler(dev_priv, master_ctl);
3025 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
3028 gen8_master_intr_enable(regs);
3030 gen8_gt_irq_handler(dev_priv, master_ctl, gt_iir);
3036 gen11_gt_engine_identity(struct intel_gt *gt,
3037 const unsigned int bank, const unsigned int bit)
3039 void __iomem * const regs = gt->uncore->regs;
3043 lockdep_assert_held(>->i915->irq_lock);
3045 raw_reg_write(regs, GEN11_IIR_REG_SELECTOR(bank), BIT(bit));
3048 * NB: Specs do not specify how long to spin wait,
3049 * so we do ~100us as an educated guess.
3051 timeout_ts = (local_clock() >> 10) + 100;
3053 ident = raw_reg_read(regs, GEN11_INTR_IDENTITY_REG(bank));
3054 } while (!(ident & GEN11_INTR_DATA_VALID) &&
3055 !time_after32(local_clock() >> 10, timeout_ts));
3057 if (unlikely(!(ident & GEN11_INTR_DATA_VALID))) {
3058 DRM_ERROR("INTR_IDENTITY_REG%u:%u 0x%08x not valid!\n",
3063 raw_reg_write(regs, GEN11_INTR_IDENTITY_REG(bank),
3064 GEN11_INTR_DATA_VALID);
3070 gen11_other_irq_handler(struct intel_gt *gt, const u8 instance,
3073 struct drm_i915_private *i915 = gt->i915;
3075 if (instance == OTHER_GUC_INSTANCE)
3076 return gen11_guc_irq_handler(i915, iir);
3078 if (instance == OTHER_GTPM_INSTANCE)
3079 return gen11_rps_irq_handler(i915, iir);
3081 WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
3086 gen11_engine_irq_handler(struct intel_gt *gt, const u8 class,
3087 const u8 instance, const u16 iir)
3089 struct intel_engine_cs *engine;
3091 if (instance <= MAX_ENGINE_INSTANCE)
3092 engine = gt->i915->engine_class[class][instance];
3097 return gen8_cs_irq_handler(engine, iir);
3099 WARN_ONCE(1, "unhandled engine interrupt class=0x%x, instance=0x%x\n",
3104 gen11_gt_identity_handler(struct intel_gt *gt, const u32 identity)
3106 const u8 class = GEN11_INTR_ENGINE_CLASS(identity);
3107 const u8 instance = GEN11_INTR_ENGINE_INSTANCE(identity);
3108 const u16 intr = GEN11_INTR_ENGINE_INTR(identity);
3110 if (unlikely(!intr))
3113 if (class <= COPY_ENGINE_CLASS)
3114 return gen11_engine_irq_handler(gt, class, instance, intr);
3116 if (class == OTHER_CLASS)
3117 return gen11_other_irq_handler(gt, instance, intr);
3119 WARN_ONCE(1, "unknown interrupt class=0x%x, instance=0x%x, intr=0x%x\n",
3120 class, instance, intr);
3124 gen11_gt_bank_handler(struct intel_gt *gt, const unsigned int bank)
3126 void __iomem * const regs = gt->uncore->regs;
3127 unsigned long intr_dw;
3130 lockdep_assert_held(>->i915->irq_lock);
3132 intr_dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));
3134 for_each_set_bit(bit, &intr_dw, 32) {
3135 const u32 ident = gen11_gt_engine_identity(gt, bank, bit);
3137 gen11_gt_identity_handler(gt, ident);
3140 /* Clear must be after shared has been served for engine */
3141 raw_reg_write(regs, GEN11_GT_INTR_DW(bank), intr_dw);
3145 gen11_gt_irq_handler(struct intel_gt *gt, const u32 master_ctl)
3147 struct drm_i915_private *i915 = gt->i915;
3150 spin_lock(&i915->irq_lock);
3152 for (bank = 0; bank < 2; bank++) {
3153 if (master_ctl & GEN11_GT_DW_IRQ(bank))
3154 gen11_gt_bank_handler(gt, bank);
3157 spin_unlock(&i915->irq_lock);
3161 gen11_gu_misc_irq_ack(struct intel_gt *gt, const u32 master_ctl)
3163 void __iomem * const regs = gt->uncore->regs;
3166 if (!(master_ctl & GEN11_GU_MISC_IRQ))
3169 iir = raw_reg_read(regs, GEN11_GU_MISC_IIR);
3171 raw_reg_write(regs, GEN11_GU_MISC_IIR, iir);
3177 gen11_gu_misc_irq_handler(struct intel_gt *gt, const u32 iir)
3179 if (iir & GEN11_GU_MISC_GSE)
3180 intel_opregion_asle_intr(gt->i915);
3183 static inline u32 gen11_master_intr_disable(void __iomem * const regs)
3185 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, 0);
3188 * Now with master disabled, get a sample of level indications
3189 * for this interrupt. Indications will be cleared on related acks.
3190 * New indications can and will light up during processing,
3191 * and will generate new interrupt after enabling master.
3193 return raw_reg_read(regs, GEN11_GFX_MSTR_IRQ);
3196 static inline void gen11_master_intr_enable(void __iomem * const regs)
3198 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
3201 static irqreturn_t gen11_irq_handler(int irq, void *arg)
3203 struct drm_i915_private * const i915 = arg;
3204 void __iomem * const regs = i915->uncore.regs;
3205 struct intel_gt *gt = &i915->gt;
3209 if (!intel_irqs_enabled(i915))
3212 master_ctl = gen11_master_intr_disable(regs);
3214 gen11_master_intr_enable(regs);
3218 /* Find, clear, then process each source of interrupt. */
3219 gen11_gt_irq_handler(gt, master_ctl);
3221 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3222 if (master_ctl & GEN11_DISPLAY_IRQ) {
3223 const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL);
3225 disable_rpm_wakeref_asserts(&i915->runtime_pm);
3227 * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ
3228 * for the display related bits.
3230 gen8_de_irq_handler(i915, disp_ctl);
3231 enable_rpm_wakeref_asserts(&i915->runtime_pm);
3234 gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
3236 gen11_master_intr_enable(regs);
3238 gen11_gu_misc_irq_handler(gt, gu_misc_iir);
3243 /* Called from drm generic code, passed 'crtc' which
3244 * we use as a pipe index
3246 int i8xx_enable_vblank(struct drm_crtc *crtc)
3248 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3249 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3250 unsigned long irqflags;
3252 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3253 i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
3254 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3259 int i945gm_enable_vblank(struct drm_crtc *crtc)
3261 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3263 if (dev_priv->i945gm_vblank.enabled++ == 0)
3264 schedule_work(&dev_priv->i945gm_vblank.work);
3266 return i8xx_enable_vblank(crtc);
3269 int i965_enable_vblank(struct drm_crtc *crtc)
3271 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3272 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3273 unsigned long irqflags;
3275 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3276 i915_enable_pipestat(dev_priv, pipe,
3277 PIPE_START_VBLANK_INTERRUPT_STATUS);
3278 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3283 int ilk_enable_vblank(struct drm_crtc *crtc)
3285 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3286 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3287 unsigned long irqflags;
3288 u32 bit = INTEL_GEN(dev_priv) >= 7 ?
3289 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
3291 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3292 ilk_enable_display_irq(dev_priv, bit);
3293 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3295 /* Even though there is no DMC, frame counter can get stuck when
3296 * PSR is active as no frames are generated.
3298 if (HAS_PSR(dev_priv))
3299 drm_crtc_vblank_restore(crtc);
3304 int bdw_enable_vblank(struct drm_crtc *crtc)
3306 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3307 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3308 unsigned long irqflags;
3310 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3311 bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
3312 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3314 /* Even if there is no DMC, frame counter can get stuck when
3315 * PSR is active as no frames are generated, so check only for PSR.
3317 if (HAS_PSR(dev_priv))
3318 drm_crtc_vblank_restore(crtc);
3323 /* Called from drm generic code, passed 'crtc' which
3324 * we use as a pipe index
3326 void i8xx_disable_vblank(struct drm_crtc *crtc)
3328 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3329 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3330 unsigned long irqflags;
3332 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3333 i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
3334 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3337 void i945gm_disable_vblank(struct drm_crtc *crtc)
3339 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3341 i8xx_disable_vblank(crtc);
3343 if (--dev_priv->i945gm_vblank.enabled == 0)
3344 schedule_work(&dev_priv->i945gm_vblank.work);
3347 void i965_disable_vblank(struct drm_crtc *crtc)
3349 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3350 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3351 unsigned long irqflags;
3353 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3354 i915_disable_pipestat(dev_priv, pipe,
3355 PIPE_START_VBLANK_INTERRUPT_STATUS);
3356 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3359 void ilk_disable_vblank(struct drm_crtc *crtc)
3361 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3362 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3363 unsigned long irqflags;
3364 u32 bit = INTEL_GEN(dev_priv) >= 7 ?
3365 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
3367 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3368 ilk_disable_display_irq(dev_priv, bit);
3369 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3372 void bdw_disable_vblank(struct drm_crtc *crtc)
3374 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3375 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3376 unsigned long irqflags;
3378 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3379 bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
3380 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3383 static void i945gm_vblank_work_func(struct work_struct *work)
3385 struct drm_i915_private *dev_priv =
3386 container_of(work, struct drm_i915_private, i945gm_vblank.work);
3389 * Vblank interrupts fail to wake up the device from C3,
3390 * hence we want to prevent C3 usage while vblank interrupts
3393 pm_qos_update_request(&dev_priv->i945gm_vblank.pm_qos,
3394 READ_ONCE(dev_priv->i945gm_vblank.enabled) ?
3395 dev_priv->i945gm_vblank.c3_disable_latency :
3396 PM_QOS_DEFAULT_VALUE);
3399 static int cstate_disable_latency(const char *name)
3401 const struct cpuidle_driver *drv;
3404 drv = cpuidle_get_driver();
3408 for (i = 0; i < drv->state_count; i++) {
3409 const struct cpuidle_state *state = &drv->states[i];
3411 if (!strcmp(state->name, name))
3412 return state->exit_latency ?
3413 state->exit_latency - 1 : 0;
3419 static void i945gm_vblank_work_init(struct drm_i915_private *dev_priv)
3421 INIT_WORK(&dev_priv->i945gm_vblank.work,
3422 i945gm_vblank_work_func);
3424 dev_priv->i945gm_vblank.c3_disable_latency =
3425 cstate_disable_latency("C3");
3426 pm_qos_add_request(&dev_priv->i945gm_vblank.pm_qos,
3427 PM_QOS_CPU_DMA_LATENCY,
3428 PM_QOS_DEFAULT_VALUE);
3431 static void i945gm_vblank_work_fini(struct drm_i915_private *dev_priv)
3433 cancel_work_sync(&dev_priv->i945gm_vblank.work);
3434 pm_qos_remove_request(&dev_priv->i945gm_vblank.pm_qos);
3437 static void ibx_irq_reset(struct drm_i915_private *dev_priv)
3439 struct intel_uncore *uncore = &dev_priv->uncore;
3441 if (HAS_PCH_NOP(dev_priv))
3444 GEN3_IRQ_RESET(uncore, SDE);
3446 if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
3447 I915_WRITE(SERR_INT, 0xffffffff);
3451 * SDEIER is also touched by the interrupt handler to work around missed PCH
3452 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3453 * instead we unconditionally enable all PCH interrupt sources here, but then
3454 * only unmask them as needed with SDEIMR.
3456 * This function needs to be called before interrupts are enabled.
3458 static void ibx_irq_pre_postinstall(struct drm_i915_private *dev_priv)
3460 if (HAS_PCH_NOP(dev_priv))
3463 WARN_ON(I915_READ(SDEIER) != 0);
3464 I915_WRITE(SDEIER, 0xffffffff);
3465 POSTING_READ(SDEIER);
3468 static void gen5_gt_irq_reset(struct drm_i915_private *dev_priv)
3470 struct intel_uncore *uncore = &dev_priv->uncore;
3472 GEN3_IRQ_RESET(uncore, GT);
3473 if (INTEL_GEN(dev_priv) >= 6)
3474 GEN3_IRQ_RESET(uncore, GEN6_PM);
3477 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
3479 struct intel_uncore *uncore = &dev_priv->uncore;
3481 if (IS_CHERRYVIEW(dev_priv))
3482 intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3484 intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK);
3486 i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
3487 intel_uncore_write(uncore, PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3489 i9xx_pipestat_irq_reset(dev_priv);
3491 GEN3_IRQ_RESET(uncore, VLV_);
3492 dev_priv->irq_mask = ~0u;
3495 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
3497 struct intel_uncore *uncore = &dev_priv->uncore;
3503 pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS;
3505 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3506 for_each_pipe(dev_priv, pipe)
3507 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
3509 enable_mask = I915_DISPLAY_PORT_INTERRUPT |
3510 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3511 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3512 I915_LPE_PIPE_A_INTERRUPT |
3513 I915_LPE_PIPE_B_INTERRUPT;
3515 if (IS_CHERRYVIEW(dev_priv))
3516 enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT |
3517 I915_LPE_PIPE_C_INTERRUPT;
3519 WARN_ON(dev_priv->irq_mask != ~0u);
3521 dev_priv->irq_mask = ~enable_mask;
3523 GEN3_IRQ_INIT(uncore, VLV_, dev_priv->irq_mask, enable_mask);
3528 static void ironlake_irq_reset(struct drm_i915_private *dev_priv)
3530 struct intel_uncore *uncore = &dev_priv->uncore;
3532 GEN3_IRQ_RESET(uncore, DE);
3533 if (IS_GEN(dev_priv, 7))
3534 intel_uncore_write(uncore, GEN7_ERR_INT, 0xffffffff);
3536 if (IS_HASWELL(dev_priv)) {
3537 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
3538 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
3541 gen5_gt_irq_reset(dev_priv);
3543 ibx_irq_reset(dev_priv);
3546 static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
3548 I915_WRITE(VLV_MASTER_IER, 0);
3549 POSTING_READ(VLV_MASTER_IER);
3551 gen5_gt_irq_reset(dev_priv);
3553 spin_lock_irq(&dev_priv->irq_lock);
3554 if (dev_priv->display_irqs_enabled)
3555 vlv_display_irq_reset(dev_priv);
3556 spin_unlock_irq(&dev_priv->irq_lock);
3559 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3561 struct intel_uncore *uncore = &dev_priv->uncore;
3563 GEN8_IRQ_RESET_NDX(uncore, GT, 0);
3564 GEN8_IRQ_RESET_NDX(uncore, GT, 1);
3565 GEN8_IRQ_RESET_NDX(uncore, GT, 2);
3566 GEN8_IRQ_RESET_NDX(uncore, GT, 3);
3569 static void gen8_irq_reset(struct drm_i915_private *dev_priv)
3571 struct intel_uncore *uncore = &dev_priv->uncore;
3574 gen8_master_intr_disable(dev_priv->uncore.regs);
3576 gen8_gt_irq_reset(dev_priv);
3578 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
3579 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
3581 for_each_pipe(dev_priv, pipe)
3582 if (intel_display_power_is_enabled(dev_priv,
3583 POWER_DOMAIN_PIPE(pipe)))
3584 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
3586 GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);
3587 GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
3588 GEN3_IRQ_RESET(uncore, GEN8_PCU_);
3590 if (HAS_PCH_SPLIT(dev_priv))
3591 ibx_irq_reset(dev_priv);
3594 static void gen11_gt_irq_reset(struct intel_gt *gt)
3596 struct intel_uncore *uncore = gt->uncore;
3598 /* Disable RCS, BCS, VCS and VECS class engines. */
3599 intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, 0);
3600 intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, 0);
3602 /* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
3603 intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~0);
3604 intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK, ~0);
3605 intel_uncore_write(uncore, GEN11_VCS0_VCS1_INTR_MASK, ~0);
3606 intel_uncore_write(uncore, GEN11_VCS2_VCS3_INTR_MASK, ~0);
3607 intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK, ~0);
3609 intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
3610 intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
3611 intel_uncore_write(uncore, GEN11_GUC_SG_INTR_ENABLE, 0);
3612 intel_uncore_write(uncore, GEN11_GUC_SG_INTR_MASK, ~0);
3615 static void gen11_irq_reset(struct drm_i915_private *dev_priv)
3617 struct intel_uncore *uncore = &dev_priv->uncore;
3620 gen11_master_intr_disable(dev_priv->uncore.regs);
3622 gen11_gt_irq_reset(&dev_priv->gt);
3624 intel_uncore_write(uncore, GEN11_DISPLAY_INT_CTL, 0);
3626 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
3627 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
3629 for_each_pipe(dev_priv, pipe)
3630 if (intel_display_power_is_enabled(dev_priv,
3631 POWER_DOMAIN_PIPE(pipe)))
3632 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
3634 GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);
3635 GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
3636 GEN3_IRQ_RESET(uncore, GEN11_DE_HPD_);
3637 GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
3638 GEN3_IRQ_RESET(uncore, GEN8_PCU_);
3640 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3641 GEN3_IRQ_RESET(uncore, SDE);
3644 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
3647 struct intel_uncore *uncore = &dev_priv->uncore;
3649 u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3652 spin_lock_irq(&dev_priv->irq_lock);
3654 if (!intel_irqs_enabled(dev_priv)) {
3655 spin_unlock_irq(&dev_priv->irq_lock);
3659 for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3660 GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,
3661 dev_priv->de_irq_mask[pipe],
3662 ~dev_priv->de_irq_mask[pipe] | extra_ier);
3664 spin_unlock_irq(&dev_priv->irq_lock);
3667 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
3670 struct intel_uncore *uncore = &dev_priv->uncore;
3673 spin_lock_irq(&dev_priv->irq_lock);
3675 if (!intel_irqs_enabled(dev_priv)) {
3676 spin_unlock_irq(&dev_priv->irq_lock);
3680 for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3681 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
3683 spin_unlock_irq(&dev_priv->irq_lock);
3685 /* make sure we're done processing display irqs */
3686 intel_synchronize_irq(dev_priv);
3689 static void cherryview_irq_reset(struct drm_i915_private *dev_priv)
3691 struct intel_uncore *uncore = &dev_priv->uncore;
3693 I915_WRITE(GEN8_MASTER_IRQ, 0);
3694 POSTING_READ(GEN8_MASTER_IRQ);
3696 gen8_gt_irq_reset(dev_priv);
3698 GEN3_IRQ_RESET(uncore, GEN8_PCU_);
3700 spin_lock_irq(&dev_priv->irq_lock);
3701 if (dev_priv->display_irqs_enabled)
3702 vlv_display_irq_reset(dev_priv);
3703 spin_unlock_irq(&dev_priv->irq_lock);
3706 static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
3707 const u32 hpd[HPD_NUM_PINS])
3709 struct intel_encoder *encoder;
3710 u32 enabled_irqs = 0;
3712 for_each_intel_encoder(&dev_priv->drm, encoder)
3713 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
3714 enabled_irqs |= hpd[encoder->hpd_pin];
3716 return enabled_irqs;
3719 static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
3724 * Enable digital hotplug on the PCH, and configure the DP short pulse
3725 * duration to 2ms (which is the minimum in the Display Port spec).
3726 * The pulse duration bits are reserved on LPT+.
3728 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3729 hotplug &= ~(PORTB_PULSE_DURATION_MASK |
3730 PORTC_PULSE_DURATION_MASK |
3731 PORTD_PULSE_DURATION_MASK);
3732 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3733 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3734 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3736 * When CPU and PCH are on the same package, port A
3737 * HPD must be enabled in both north and south.
3739 if (HAS_PCH_LPT_LP(dev_priv))
3740 hotplug |= PORTA_HOTPLUG_ENABLE;
3741 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3744 static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
3746 u32 hotplug_irqs, enabled_irqs;
3748 if (HAS_PCH_IBX(dev_priv)) {
3749 hotplug_irqs = SDE_HOTPLUG_MASK;
3750 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ibx);
3752 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3753 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_cpt);
3756 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3758 ibx_hpd_detection_setup(dev_priv);
3761 static void icp_hpd_detection_setup(struct drm_i915_private *dev_priv)
3765 hotplug = I915_READ(SHOTPLUG_CTL_DDI);
3766 hotplug |= ICP_DDIA_HPD_ENABLE |
3767 ICP_DDIB_HPD_ENABLE;
3768 I915_WRITE(SHOTPLUG_CTL_DDI, hotplug);
3770 hotplug = I915_READ(SHOTPLUG_CTL_TC);
3771 hotplug |= ICP_TC_HPD_ENABLE(PORT_TC1) |
3772 ICP_TC_HPD_ENABLE(PORT_TC2) |
3773 ICP_TC_HPD_ENABLE(PORT_TC3) |
3774 ICP_TC_HPD_ENABLE(PORT_TC4);
3775 I915_WRITE(SHOTPLUG_CTL_TC, hotplug);
3778 static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv)
3780 u32 hotplug_irqs, enabled_irqs;
3782 hotplug_irqs = SDE_DDI_MASK_ICP | SDE_TC_MASK_ICP;
3783 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_icp);
3785 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3787 icp_hpd_detection_setup(dev_priv);
3790 static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
3794 hotplug = I915_READ(GEN11_TC_HOTPLUG_CTL);
3795 hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) |
3796 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) |
3797 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) |
3798 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4);
3799 I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug);
3801 hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL);
3802 hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) |
3803 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) |
3804 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) |
3805 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4);
3806 I915_WRITE(GEN11_TBT_HOTPLUG_CTL, hotplug);
3809 static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
3811 u32 hotplug_irqs, enabled_irqs;
3814 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_gen11);
3815 hotplug_irqs = GEN11_DE_TC_HOTPLUG_MASK | GEN11_DE_TBT_HOTPLUG_MASK;
3817 val = I915_READ(GEN11_DE_HPD_IMR);
3818 val &= ~hotplug_irqs;
3819 I915_WRITE(GEN11_DE_HPD_IMR, val);
3820 POSTING_READ(GEN11_DE_HPD_IMR);
3822 gen11_hpd_detection_setup(dev_priv);
3824 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3825 icp_hpd_irq_setup(dev_priv);
3828 static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3832 /* Display WA #1179 WaHardHangonHotPlug: cnp */
3833 if (HAS_PCH_CNP(dev_priv)) {
3834 val = I915_READ(SOUTH_CHICKEN1);
3835 val &= ~CHASSIS_CLK_REQ_DURATION_MASK;
3836 val |= CHASSIS_CLK_REQ_DURATION(0xf);
3837 I915_WRITE(SOUTH_CHICKEN1, val);
3840 /* Enable digital hotplug on the PCH */
3841 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3842 hotplug |= PORTA_HOTPLUG_ENABLE |
3843 PORTB_HOTPLUG_ENABLE |
3844 PORTC_HOTPLUG_ENABLE |
3845 PORTD_HOTPLUG_ENABLE;
3846 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3848 hotplug = I915_READ(PCH_PORT_HOTPLUG2);
3849 hotplug |= PORTE_HOTPLUG_ENABLE;
3850 I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
3853 static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3855 u32 hotplug_irqs, enabled_irqs;
3857 hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
3858 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt);
3860 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3862 spt_hpd_detection_setup(dev_priv);
3865 static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv)
3870 * Enable digital hotplug on the CPU, and configure the DP short pulse
3871 * duration to 2ms (which is the minimum in the Display Port spec)
3872 * The pulse duration bits are reserved on HSW+.
3874 hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
3875 hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
3876 hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE |
3877 DIGITAL_PORTA_PULSE_DURATION_2ms;
3878 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
3881 static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
3883 u32 hotplug_irqs, enabled_irqs;
3885 if (INTEL_GEN(dev_priv) >= 8) {
3886 hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
3887 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw);
3889 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3890 } else if (INTEL_GEN(dev_priv) >= 7) {
3891 hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
3892 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ivb);
3894 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3896 hotplug_irqs = DE_DP_A_HOTPLUG;
3897 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ilk);
3899 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3902 ilk_hpd_detection_setup(dev_priv);
3904 ibx_hpd_irq_setup(dev_priv);
3907 static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
3912 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3913 hotplug |= PORTA_HOTPLUG_ENABLE |
3914 PORTB_HOTPLUG_ENABLE |
3915 PORTC_HOTPLUG_ENABLE;
3917 DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x\n",
3918 hotplug, enabled_irqs);
3919 hotplug &= ~BXT_DDI_HPD_INVERT_MASK;
3922 * For BXT invert bit has to be set based on AOB design
3923 * for HPD detection logic, update it based on VBT fields.
3925 if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) &&
3926 intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
3927 hotplug |= BXT_DDIA_HPD_INVERT;
3928 if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) &&
3929 intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
3930 hotplug |= BXT_DDIB_HPD_INVERT;
3931 if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) &&
3932 intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
3933 hotplug |= BXT_DDIC_HPD_INVERT;
3935 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3938 static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3940 __bxt_hpd_detection_setup(dev_priv, BXT_DE_PORT_HOTPLUG_MASK);
3943 static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3945 u32 hotplug_irqs, enabled_irqs;
3947 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bxt);
3948 hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK;
3950 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3952 __bxt_hpd_detection_setup(dev_priv, enabled_irqs);
3955 static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
3959 if (HAS_PCH_NOP(dev_priv))
3962 if (HAS_PCH_IBX(dev_priv))
3963 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3964 else if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
3965 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3967 mask = SDE_GMBUS_CPT;
3969 gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
3970 I915_WRITE(SDEIMR, ~mask);
3972 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
3973 HAS_PCH_LPT(dev_priv))
3974 ibx_hpd_detection_setup(dev_priv);
3976 spt_hpd_detection_setup(dev_priv);
3979 static void gen5_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3981 struct intel_uncore *uncore = &dev_priv->uncore;
3982 u32 pm_irqs, gt_irqs;
3984 pm_irqs = gt_irqs = 0;
3986 dev_priv->gt_irq_mask = ~0;
3987 if (HAS_L3_DPF(dev_priv)) {
3988 /* L3 parity interrupt is always unmasked. */
3989 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev_priv);
3990 gt_irqs |= GT_PARITY_ERROR(dev_priv);
3993 gt_irqs |= GT_RENDER_USER_INTERRUPT;
3994 if (IS_GEN(dev_priv, 5)) {
3995 gt_irqs |= ILK_BSD_USER_INTERRUPT;
3997 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
4000 GEN3_IRQ_INIT(uncore, GT, dev_priv->gt_irq_mask, gt_irqs);
4002 if (INTEL_GEN(dev_priv) >= 6) {
4004 * RPS interrupts will get enabled/disabled on demand when RPS
4005 * itself is enabled/disabled.
4007 if (HAS_ENGINE(dev_priv, VECS0)) {
4008 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
4009 dev_priv->pm_ier |= PM_VEBOX_USER_INTERRUPT;
4012 dev_priv->pm_imr = 0xffffffff;
4013 GEN3_IRQ_INIT(uncore, GEN6_PM, dev_priv->pm_imr, pm_irqs);
4017 static void ironlake_irq_postinstall(struct drm_i915_private *dev_priv)
4019 struct intel_uncore *uncore = &dev_priv->uncore;
4020 u32 display_mask, extra_mask;
4022 if (INTEL_GEN(dev_priv) >= 7) {
4023 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
4024 DE_PCH_EVENT_IVB | DE_AUX_CHANNEL_A_IVB);
4025 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
4026 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
4027 DE_DP_A_HOTPLUG_IVB);
4029 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
4030 DE_AUX_CHANNEL_A | DE_PIPEB_CRC_DONE |
4031 DE_PIPEA_CRC_DONE | DE_POISON);
4032 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
4033 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
4037 if (IS_HASWELL(dev_priv)) {
4038 gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
4039 intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
4040 display_mask |= DE_EDP_PSR_INT_HSW;
4043 dev_priv->irq_mask = ~display_mask;
4045 ibx_irq_pre_postinstall(dev_priv);
4047 GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask,
4048 display_mask | extra_mask);
4050 gen5_gt_irq_postinstall(dev_priv);
4052 ilk_hpd_detection_setup(dev_priv);
4054 ibx_irq_postinstall(dev_priv);
4056 if (IS_IRONLAKE_M(dev_priv)) {
4057 /* Enable PCU event interrupts
4059 * spinlocking not required here for correctness since interrupt
4060 * setup is guaranteed to run in single-threaded context. But we
4061 * need it to make the assert_spin_locked happy. */
4062 spin_lock_irq(&dev_priv->irq_lock);
4063 ilk_enable_display_irq(dev_priv, DE_PCU_EVENT);
4064 spin_unlock_irq(&dev_priv->irq_lock);
4068 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
4070 lockdep_assert_held(&dev_priv->irq_lock);
4072 if (dev_priv->display_irqs_enabled)
4075 dev_priv->display_irqs_enabled = true;
4077 if (intel_irqs_enabled(dev_priv)) {
4078 vlv_display_irq_reset(dev_priv);
4079 vlv_display_irq_postinstall(dev_priv);
4083 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
4085 lockdep_assert_held(&dev_priv->irq_lock);
4087 if (!dev_priv->display_irqs_enabled)
4090 dev_priv->display_irqs_enabled = false;
4092 if (intel_irqs_enabled(dev_priv))
4093 vlv_display_irq_reset(dev_priv);
4097 static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv)
4099 gen5_gt_irq_postinstall(dev_priv);
4101 spin_lock_irq(&dev_priv->irq_lock);
4102 if (dev_priv->display_irqs_enabled)
4103 vlv_display_irq_postinstall(dev_priv);
4104 spin_unlock_irq(&dev_priv->irq_lock);
4106 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
4107 POSTING_READ(VLV_MASTER_IER);
4110 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
4112 struct intel_uncore *uncore = &dev_priv->uncore;
4114 /* These are interrupts we'll toggle with the ring mask register */
4115 u32 gt_interrupts[] = {
4116 (GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
4117 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
4118 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
4119 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT),
4121 (GT_RENDER_USER_INTERRUPT << GEN8_VCS0_IRQ_SHIFT |
4122 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS0_IRQ_SHIFT |
4123 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
4124 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT),
4128 (GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
4129 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT)
4132 dev_priv->pm_ier = 0x0;
4133 dev_priv->pm_imr = ~dev_priv->pm_ier;
4134 GEN8_IRQ_INIT_NDX(uncore, GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
4135 GEN8_IRQ_INIT_NDX(uncore, GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
4137 * RPS interrupts will get enabled/disabled on demand when RPS itself
4138 * is enabled/disabled. Same wil be the case for GuC interrupts.
4140 GEN8_IRQ_INIT_NDX(uncore, GT, 2, dev_priv->pm_imr, dev_priv->pm_ier);
4141 GEN8_IRQ_INIT_NDX(uncore, GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
4144 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
4146 struct intel_uncore *uncore = &dev_priv->uncore;
4148 u32 de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
4149 u32 de_pipe_enables;
4150 u32 de_port_masked = GEN8_AUX_CHANNEL_A;
4151 u32 de_port_enables;
4152 u32 de_misc_masked = GEN8_DE_EDP_PSR;
4155 if (INTEL_GEN(dev_priv) <= 10)
4156 de_misc_masked |= GEN8_DE_MISC_GSE;
4158 if (INTEL_GEN(dev_priv) >= 9) {
4159 de_pipe_masked |= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
4160 de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
4162 if (IS_GEN9_LP(dev_priv))
4163 de_port_masked |= BXT_DE_PORT_GMBUS;
4165 de_pipe_masked |= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
4168 if (INTEL_GEN(dev_priv) >= 11)
4169 de_port_masked |= ICL_AUX_CHANNEL_E;
4171 if (IS_CNL_WITH_PORT_F(dev_priv) || INTEL_GEN(dev_priv) >= 11)
4172 de_port_masked |= CNL_AUX_CHANNEL_F;
4174 de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
4175 GEN8_PIPE_FIFO_UNDERRUN;
4177 de_port_enables = de_port_masked;
4178 if (IS_GEN9_LP(dev_priv))
4179 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
4180 else if (IS_BROADWELL(dev_priv))
4181 de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
4183 gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
4184 intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
4186 for_each_pipe(dev_priv, pipe) {
4187 dev_priv->de_irq_mask[pipe] = ~de_pipe_masked;
4189 if (intel_display_power_is_enabled(dev_priv,
4190 POWER_DOMAIN_PIPE(pipe)))
4191 GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,
4192 dev_priv->de_irq_mask[pipe],
4196 GEN3_IRQ_INIT(uncore, GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
4197 GEN3_IRQ_INIT(uncore, GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
4199 if (INTEL_GEN(dev_priv) >= 11) {
4200 u32 de_hpd_masked = 0;
4201 u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK |
4202 GEN11_DE_TBT_HOTPLUG_MASK;
4204 GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked,
4206 gen11_hpd_detection_setup(dev_priv);
4207 } else if (IS_GEN9_LP(dev_priv)) {
4208 bxt_hpd_detection_setup(dev_priv);
4209 } else if (IS_BROADWELL(dev_priv)) {
4210 ilk_hpd_detection_setup(dev_priv);
4214 static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
4216 if (HAS_PCH_SPLIT(dev_priv))
4217 ibx_irq_pre_postinstall(dev_priv);
4219 gen8_gt_irq_postinstall(dev_priv);
4220 gen8_de_irq_postinstall(dev_priv);
4222 if (HAS_PCH_SPLIT(dev_priv))
4223 ibx_irq_postinstall(dev_priv);
4225 gen8_master_intr_enable(dev_priv->uncore.regs);
4228 static void gen11_gt_irq_postinstall(struct intel_gt *gt)
4230 const u32 irqs = GT_RENDER_USER_INTERRUPT | GT_CONTEXT_SWITCH_INTERRUPT;
4231 struct drm_i915_private *dev_priv = gt->i915;
4232 struct intel_uncore *uncore = gt->uncore;
4233 const u32 dmask = irqs << 16 | irqs;
4234 const u32 smask = irqs << 16;
4236 BUILD_BUG_ON(irqs & 0xffff0000);
4238 /* Enable RCS, BCS, VCS and VECS class interrupts. */
4239 intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, dmask);
4240 intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, dmask);
4242 /* Unmask irqs on RCS, BCS, VCS and VECS engines. */
4243 intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~smask);
4244 intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK, ~smask);
4245 intel_uncore_write(uncore, GEN11_VCS0_VCS1_INTR_MASK, ~dmask);
4246 intel_uncore_write(uncore, GEN11_VCS2_VCS3_INTR_MASK, ~dmask);
4247 intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK, ~dmask);
4250 * RPS interrupts will get enabled/disabled on demand when RPS itself
4251 * is enabled/disabled.
4253 dev_priv->pm_ier = 0x0;
4254 dev_priv->pm_imr = ~dev_priv->pm_ier;
4255 intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
4256 intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
4258 /* Same thing for GuC interrupts */
4259 intel_uncore_write(uncore, GEN11_GUC_SG_INTR_ENABLE, 0);
4260 intel_uncore_write(uncore, GEN11_GUC_SG_INTR_MASK, ~0);
4263 static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
4265 u32 mask = SDE_GMBUS_ICP;
4267 WARN_ON(I915_READ(SDEIER) != 0);
4268 I915_WRITE(SDEIER, 0xffffffff);
4269 POSTING_READ(SDEIER);
4271 gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
4272 I915_WRITE(SDEIMR, ~mask);
4274 icp_hpd_detection_setup(dev_priv);
4277 static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
4279 struct intel_uncore *uncore = &dev_priv->uncore;
4280 u32 gu_misc_masked = GEN11_GU_MISC_GSE;
4282 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
4283 icp_irq_postinstall(dev_priv);
4285 gen11_gt_irq_postinstall(&dev_priv->gt);
4286 gen8_de_irq_postinstall(dev_priv);
4288 GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
4290 I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
4292 gen11_master_intr_enable(uncore->regs);
4293 POSTING_READ(GEN11_GFX_MSTR_IRQ);
4296 static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
4298 gen8_gt_irq_postinstall(dev_priv);
4300 spin_lock_irq(&dev_priv->irq_lock);
4301 if (dev_priv->display_irqs_enabled)
4302 vlv_display_irq_postinstall(dev_priv);
4303 spin_unlock_irq(&dev_priv->irq_lock);
4305 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
4306 POSTING_READ(GEN8_MASTER_IRQ);
4309 static void i8xx_irq_reset(struct drm_i915_private *dev_priv)
4311 struct intel_uncore *uncore = &dev_priv->uncore;
4313 i9xx_pipestat_irq_reset(dev_priv);
4315 GEN2_IRQ_RESET(uncore);
4318 static void i8xx_irq_postinstall(struct drm_i915_private *dev_priv)
4320 struct intel_uncore *uncore = &dev_priv->uncore;
4323 intel_uncore_write16(uncore,
4325 ~(I915_ERROR_PAGE_TABLE |
4326 I915_ERROR_MEMORY_REFRESH));
4328 /* Unmask the interrupts that we always want on. */
4329 dev_priv->irq_mask =
4330 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4331 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4332 I915_MASTER_ERROR_INTERRUPT);
4335 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4336 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4337 I915_MASTER_ERROR_INTERRUPT |
4338 I915_USER_INTERRUPT;
4340 GEN2_IRQ_INIT(uncore, dev_priv->irq_mask, enable_mask);
4342 /* Interrupt setup is already guaranteed to be single-threaded, this is
4343 * just to make the assert_spin_locked check happy. */
4344 spin_lock_irq(&dev_priv->irq_lock);
4345 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4346 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4347 spin_unlock_irq(&dev_priv->irq_lock);
4350 static void i8xx_error_irq_ack(struct drm_i915_private *i915,
4351 u16 *eir, u16 *eir_stuck)
4353 struct intel_uncore *uncore = &i915->uncore;
4356 *eir = intel_uncore_read16(uncore, EIR);
4359 intel_uncore_write16(uncore, EIR, *eir);
4361 *eir_stuck = intel_uncore_read16(uncore, EIR);
4362 if (*eir_stuck == 0)
4366 * Toggle all EMR bits to make sure we get an edge
4367 * in the ISR master error bit if we don't clear
4368 * all the EIR bits. Otherwise the edge triggered
4369 * IIR on i965/g4x wouldn't notice that an interrupt
4370 * is still pending. Also some EIR bits can't be
4371 * cleared except by handling the underlying error
4372 * (or by a GPU reset) so we mask any bit that
4375 emr = intel_uncore_read16(uncore, EMR);
4376 intel_uncore_write16(uncore, EMR, 0xffff);
4377 intel_uncore_write16(uncore, EMR, emr | *eir_stuck);
4380 static void i8xx_error_irq_handler(struct drm_i915_private *dev_priv,
4381 u16 eir, u16 eir_stuck)
4383 DRM_DEBUG("Master Error: EIR 0x%04x\n", eir);
4386 DRM_DEBUG_DRIVER("EIR stuck: 0x%04x, masked\n", eir_stuck);
4389 static void i9xx_error_irq_ack(struct drm_i915_private *dev_priv,
4390 u32 *eir, u32 *eir_stuck)
4394 *eir = I915_READ(EIR);
4396 I915_WRITE(EIR, *eir);
4398 *eir_stuck = I915_READ(EIR);
4399 if (*eir_stuck == 0)
4403 * Toggle all EMR bits to make sure we get an edge
4404 * in the ISR master error bit if we don't clear
4405 * all the EIR bits. Otherwise the edge triggered
4406 * IIR on i965/g4x wouldn't notice that an interrupt
4407 * is still pending. Also some EIR bits can't be
4408 * cleared except by handling the underlying error
4409 * (or by a GPU reset) so we mask any bit that
4412 emr = I915_READ(EMR);
4413 I915_WRITE(EMR, 0xffffffff);
4414 I915_WRITE(EMR, emr | *eir_stuck);
4417 static void i9xx_error_irq_handler(struct drm_i915_private *dev_priv,
4418 u32 eir, u32 eir_stuck)
4420 DRM_DEBUG("Master Error, EIR 0x%08x\n", eir);
4423 DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masked\n", eir_stuck);
4426 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
4428 struct drm_i915_private *dev_priv = arg;
4429 irqreturn_t ret = IRQ_NONE;
4431 if (!intel_irqs_enabled(dev_priv))
4434 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4435 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4438 u32 pipe_stats[I915_MAX_PIPES] = {};
4439 u16 eir = 0, eir_stuck = 0;
4442 iir = intel_uncore_read16(&dev_priv->uncore, GEN2_IIR);
4448 /* Call regardless, as some status bits might not be
4449 * signalled in iir */
4450 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
4452 if (iir & I915_MASTER_ERROR_INTERRUPT)
4453 i8xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
4455 intel_uncore_write16(&dev_priv->uncore, GEN2_IIR, iir);
4457 if (iir & I915_USER_INTERRUPT)
4458 intel_engine_breadcrumbs_irq(dev_priv->engine[RCS0]);
4460 if (iir & I915_MASTER_ERROR_INTERRUPT)
4461 i8xx_error_irq_handler(dev_priv, eir, eir_stuck);
4463 i8xx_pipestat_irq_handler(dev_priv, iir, pipe_stats);
4466 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4471 static void i915_irq_reset(struct drm_i915_private *dev_priv)
4473 struct intel_uncore *uncore = &dev_priv->uncore;
4475 if (I915_HAS_HOTPLUG(dev_priv)) {
4476 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4477 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4480 i9xx_pipestat_irq_reset(dev_priv);
4482 GEN3_IRQ_RESET(uncore, GEN2_);
4485 static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
4487 struct intel_uncore *uncore = &dev_priv->uncore;
4490 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE |
4491 I915_ERROR_MEMORY_REFRESH));
4493 /* Unmask the interrupts that we always want on. */
4494 dev_priv->irq_mask =
4495 ~(I915_ASLE_INTERRUPT |
4496 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4497 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4498 I915_MASTER_ERROR_INTERRUPT);
4501 I915_ASLE_INTERRUPT |
4502 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4503 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4504 I915_MASTER_ERROR_INTERRUPT |
4505 I915_USER_INTERRUPT;
4507 if (I915_HAS_HOTPLUG(dev_priv)) {
4508 /* Enable in IER... */
4509 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
4510 /* and unmask in IMR */
4511 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
4514 GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);
4516 /* Interrupt setup is already guaranteed to be single-threaded, this is
4517 * just to make the assert_spin_locked check happy. */
4518 spin_lock_irq(&dev_priv->irq_lock);
4519 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4520 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4521 spin_unlock_irq(&dev_priv->irq_lock);
4523 i915_enable_asle_pipestat(dev_priv);
4526 static irqreturn_t i915_irq_handler(int irq, void *arg)
4528 struct drm_i915_private *dev_priv = arg;
4529 irqreturn_t ret = IRQ_NONE;
4531 if (!intel_irqs_enabled(dev_priv))
4534 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4535 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4538 u32 pipe_stats[I915_MAX_PIPES] = {};
4539 u32 eir = 0, eir_stuck = 0;
4540 u32 hotplug_status = 0;
4543 iir = I915_READ(GEN2_IIR);
4549 if (I915_HAS_HOTPLUG(dev_priv) &&
4550 iir & I915_DISPLAY_PORT_INTERRUPT)
4551 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4553 /* Call regardless, as some status bits might not be
4554 * signalled in iir */
4555 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
4557 if (iir & I915_MASTER_ERROR_INTERRUPT)
4558 i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
4560 I915_WRITE(GEN2_IIR, iir);
4562 if (iir & I915_USER_INTERRUPT)
4563 intel_engine_breadcrumbs_irq(dev_priv->engine[RCS0]);
4565 if (iir & I915_MASTER_ERROR_INTERRUPT)
4566 i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
4569 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4571 i915_pipestat_irq_handler(dev_priv, iir, pipe_stats);
4574 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4579 static void i965_irq_reset(struct drm_i915_private *dev_priv)
4581 struct intel_uncore *uncore = &dev_priv->uncore;
4583 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4584 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4586 i9xx_pipestat_irq_reset(dev_priv);
4588 GEN3_IRQ_RESET(uncore, GEN2_);
4591 static void i965_irq_postinstall(struct drm_i915_private *dev_priv)
4593 struct intel_uncore *uncore = &dev_priv->uncore;
4598 * Enable some error detection, note the instruction error mask
4599 * bit is reserved, so we leave it masked.
4601 if (IS_G4X(dev_priv)) {
4602 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4603 GM45_ERROR_MEM_PRIV |
4604 GM45_ERROR_CP_PRIV |
4605 I915_ERROR_MEMORY_REFRESH);
4607 error_mask = ~(I915_ERROR_PAGE_TABLE |
4608 I915_ERROR_MEMORY_REFRESH);
4610 I915_WRITE(EMR, error_mask);
4612 /* Unmask the interrupts that we always want on. */
4613 dev_priv->irq_mask =
4614 ~(I915_ASLE_INTERRUPT |
4615 I915_DISPLAY_PORT_INTERRUPT |
4616 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4617 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4618 I915_MASTER_ERROR_INTERRUPT);
4621 I915_ASLE_INTERRUPT |
4622 I915_DISPLAY_PORT_INTERRUPT |
4623 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4624 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4625 I915_MASTER_ERROR_INTERRUPT |
4626 I915_USER_INTERRUPT;
4628 if (IS_G4X(dev_priv))
4629 enable_mask |= I915_BSD_USER_INTERRUPT;
4631 GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);
4633 /* Interrupt setup is already guaranteed to be single-threaded, this is
4634 * just to make the assert_spin_locked check happy. */
4635 spin_lock_irq(&dev_priv->irq_lock);
4636 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4637 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4638 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4639 spin_unlock_irq(&dev_priv->irq_lock);
4641 i915_enable_asle_pipestat(dev_priv);
4644 static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
4648 lockdep_assert_held(&dev_priv->irq_lock);
4650 /* Note HDMI and DP share hotplug bits */
4651 /* enable bits are the same for all generations */
4652 hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);
4653 /* Programming the CRT detection parameters tends
4654 to generate a spurious hotplug event about three
4655 seconds later. So just do it once.
4657 if (IS_G4X(dev_priv))
4658 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4659 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4661 /* Ignore TV since it's buggy */
4662 i915_hotplug_interrupt_update_locked(dev_priv,
4663 HOTPLUG_INT_EN_MASK |
4664 CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
4665 CRT_HOTPLUG_ACTIVATION_PERIOD_64,
4669 static irqreturn_t i965_irq_handler(int irq, void *arg)
4671 struct drm_i915_private *dev_priv = arg;
4672 irqreturn_t ret = IRQ_NONE;
4674 if (!intel_irqs_enabled(dev_priv))
4677 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4678 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4681 u32 pipe_stats[I915_MAX_PIPES] = {};
4682 u32 eir = 0, eir_stuck = 0;
4683 u32 hotplug_status = 0;
4686 iir = I915_READ(GEN2_IIR);
4692 if (iir & I915_DISPLAY_PORT_INTERRUPT)
4693 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4695 /* Call regardless, as some status bits might not be
4696 * signalled in iir */
4697 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
4699 if (iir & I915_MASTER_ERROR_INTERRUPT)
4700 i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
4702 I915_WRITE(GEN2_IIR, iir);
4704 if (iir & I915_USER_INTERRUPT)
4705 intel_engine_breadcrumbs_irq(dev_priv->engine[RCS0]);
4707 if (iir & I915_BSD_USER_INTERRUPT)
4708 intel_engine_breadcrumbs_irq(dev_priv->engine[VCS0]);
4710 if (iir & I915_MASTER_ERROR_INTERRUPT)
4711 i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
4714 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4716 i965_pipestat_irq_handler(dev_priv, iir, pipe_stats);
4719 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4725 * intel_irq_init - initializes irq support
4726 * @dev_priv: i915 device instance
4728 * This function initializes all the irq support including work items, timers
4729 * and all the vtables. It does not setup the interrupt itself though.
4731 void intel_irq_init(struct drm_i915_private *dev_priv)
4733 struct drm_device *dev = &dev_priv->drm;
4734 struct intel_rps *rps = &dev_priv->gt_pm.rps;
4737 if (IS_I945GM(dev_priv))
4738 i945gm_vblank_work_init(dev_priv);
4740 intel_hpd_init_work(dev_priv);
4742 INIT_WORK(&rps->work, gen6_pm_rps_work);
4744 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4745 for (i = 0; i < MAX_L3_SLICES; ++i)
4746 dev_priv->l3_parity.remap_info[i] = NULL;
4748 if (HAS_GUC_SCHED(dev_priv) && INTEL_GEN(dev_priv) < 11)
4749 dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT;
4751 /* Let's track the enabled rps events */
4752 if (IS_VALLEYVIEW(dev_priv))
4753 /* WaGsvRC0ResidencyMethod:vlv */
4754 dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED;
4756 dev_priv->pm_rps_events = (GEN6_PM_RP_UP_THRESHOLD |
4757 GEN6_PM_RP_DOWN_THRESHOLD |
4758 GEN6_PM_RP_DOWN_TIMEOUT);
4760 /* We share the register with other engine */
4761 if (INTEL_GEN(dev_priv) > 9)
4762 GEM_WARN_ON(dev_priv->pm_rps_events & 0xffff0000);
4764 rps->pm_intrmsk_mbz = 0;
4767 * SNB,IVB,HSW can while VLV,CHV may hard hang on looping batchbuffer
4768 * if GEN6_PM_UP_EI_EXPIRED is masked.
4770 * TODO: verify if this can be reproduced on VLV,CHV.
4772 if (INTEL_GEN(dev_priv) <= 7)
4773 rps->pm_intrmsk_mbz |= GEN6_PM_RP_UP_EI_EXPIRED;
4775 if (INTEL_GEN(dev_priv) >= 8)
4776 rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
4778 dev->vblank_disable_immediate = true;
4780 /* Most platforms treat the display irq block as an always-on
4781 * power domain. vlv/chv can disable it at runtime and need
4782 * special care to avoid writing any of the display block registers
4783 * outside of the power domain. We defer setting up the display irqs
4784 * in this case to the runtime pm.
4786 dev_priv->display_irqs_enabled = true;
4787 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4788 dev_priv->display_irqs_enabled = false;
4790 dev_priv->hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD;
4791 /* If we have MST support, we want to avoid doing short HPD IRQ storm
4792 * detection, as short HPD storms will occur as a natural part of
4793 * sideband messaging with MST.
4794 * On older platforms however, IRQ storms can occur with both long and
4795 * short pulses, as seen on some G4x systems.
4797 dev_priv->hotplug.hpd_short_storm_enabled = !HAS_DP_MST(dev_priv);
4799 if (HAS_GMCH(dev_priv)) {
4800 if (I915_HAS_HOTPLUG(dev_priv))
4801 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4803 if (INTEL_GEN(dev_priv) >= 11)
4804 dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
4805 else if (IS_GEN9_LP(dev_priv))
4806 dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4807 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
4808 dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4810 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4815 * intel_irq_fini - deinitializes IRQ support
4816 * @i915: i915 device instance
4818 * This function deinitializes all the IRQ support.
4820 void intel_irq_fini(struct drm_i915_private *i915)
4824 if (IS_I945GM(i915))
4825 i945gm_vblank_work_fini(i915);
4827 for (i = 0; i < MAX_L3_SLICES; ++i)
4828 kfree(i915->l3_parity.remap_info[i]);
4831 static irq_handler_t intel_irq_handler(struct drm_i915_private *dev_priv)
4833 if (HAS_GMCH(dev_priv)) {
4834 if (IS_CHERRYVIEW(dev_priv))
4835 return cherryview_irq_handler;
4836 else if (IS_VALLEYVIEW(dev_priv))
4837 return valleyview_irq_handler;
4838 else if (IS_GEN(dev_priv, 4))
4839 return i965_irq_handler;
4840 else if (IS_GEN(dev_priv, 3))
4841 return i915_irq_handler;
4843 return i8xx_irq_handler;
4845 if (INTEL_GEN(dev_priv) >= 11)
4846 return gen11_irq_handler;
4847 else if (INTEL_GEN(dev_priv) >= 8)
4848 return gen8_irq_handler;
4850 return ironlake_irq_handler;
4854 static void intel_irq_reset(struct drm_i915_private *dev_priv)
4856 if (HAS_GMCH(dev_priv)) {
4857 if (IS_CHERRYVIEW(dev_priv))
4858 cherryview_irq_reset(dev_priv);
4859 else if (IS_VALLEYVIEW(dev_priv))
4860 valleyview_irq_reset(dev_priv);
4861 else if (IS_GEN(dev_priv, 4))
4862 i965_irq_reset(dev_priv);
4863 else if (IS_GEN(dev_priv, 3))
4864 i915_irq_reset(dev_priv);
4866 i8xx_irq_reset(dev_priv);
4868 if (INTEL_GEN(dev_priv) >= 11)
4869 gen11_irq_reset(dev_priv);
4870 else if (INTEL_GEN(dev_priv) >= 8)
4871 gen8_irq_reset(dev_priv);
4873 ironlake_irq_reset(dev_priv);
4877 static void intel_irq_postinstall(struct drm_i915_private *dev_priv)
4879 if (HAS_GMCH(dev_priv)) {
4880 if (IS_CHERRYVIEW(dev_priv))
4881 cherryview_irq_postinstall(dev_priv);
4882 else if (IS_VALLEYVIEW(dev_priv))
4883 valleyview_irq_postinstall(dev_priv);
4884 else if (IS_GEN(dev_priv, 4))
4885 i965_irq_postinstall(dev_priv);
4886 else if (IS_GEN(dev_priv, 3))
4887 i915_irq_postinstall(dev_priv);
4889 i8xx_irq_postinstall(dev_priv);
4891 if (INTEL_GEN(dev_priv) >= 11)
4892 gen11_irq_postinstall(dev_priv);
4893 else if (INTEL_GEN(dev_priv) >= 8)
4894 gen8_irq_postinstall(dev_priv);
4896 ironlake_irq_postinstall(dev_priv);
4901 * intel_irq_install - enables the hardware interrupt
4902 * @dev_priv: i915 device instance
4904 * This function enables the hardware interrupt handling, but leaves the hotplug
4905 * handling still disabled. It is called after intel_irq_init().
4907 * In the driver load and resume code we need working interrupts in a few places
4908 * but don't want to deal with the hassle of concurrent probe and hotplug
4909 * workers. Hence the split into this two-stage approach.
4911 int intel_irq_install(struct drm_i915_private *dev_priv)
4913 int irq = dev_priv->drm.pdev->irq;
4917 * We enable some interrupt sources in our postinstall hooks, so mark
4918 * interrupts as enabled _before_ actually enabling them to avoid
4919 * special cases in our ordering checks.
4921 dev_priv->runtime_pm.irqs_enabled = true;
4923 dev_priv->drm.irq_enabled = true;
4925 intel_irq_reset(dev_priv);
4927 ret = request_irq(irq, intel_irq_handler(dev_priv),
4928 IRQF_SHARED, DRIVER_NAME, dev_priv);
4930 dev_priv->drm.irq_enabled = false;
4934 intel_irq_postinstall(dev_priv);
4940 * intel_irq_uninstall - finilizes all irq handling
4941 * @dev_priv: i915 device instance
4943 * This stops interrupt and hotplug handling and unregisters and frees all
4944 * resources acquired in the init functions.
4946 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4948 int irq = dev_priv->drm.pdev->irq;
4951 * FIXME we can get called twice during driver load
4952 * error handling due to intel_modeset_cleanup()
4953 * calling us out of sequence. Would be nice if
4954 * it didn't do that...
4956 if (!dev_priv->drm.irq_enabled)
4959 dev_priv->drm.irq_enabled = false;
4961 intel_irq_reset(dev_priv);
4963 free_irq(irq, dev_priv);
4965 intel_hpd_cancel_work(dev_priv);
4966 dev_priv->runtime_pm.irqs_enabled = false;
4970 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4971 * @dev_priv: i915 device instance
4973 * This function is used to disable interrupts at runtime, both in the runtime
4974 * pm and the system suspend/resume code.
4976 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4978 intel_irq_reset(dev_priv);
4979 dev_priv->runtime_pm.irqs_enabled = false;
4980 intel_synchronize_irq(dev_priv);
4984 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4985 * @dev_priv: i915 device instance
4987 * This function is used to enable interrupts at runtime, both in the runtime
4988 * pm and the system suspend/resume code.
4990 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4992 dev_priv->runtime_pm.irqs_enabled = true;
4993 intel_irq_reset(dev_priv);
4994 intel_irq_postinstall(dev_priv);