2 * SPDX-License-Identifier: MIT
4 * Copyright � 2008-2018 Intel Corporation
7 #ifndef _I915_GPU_ERROR_H_
8 #define _I915_GPU_ERROR_H_
10 #include <linux/atomic.h>
11 #include <linux/kref.h>
12 #include <linux/ktime.h>
13 #include <linux/sched.h>
15 #include <drm/drm_mm.h>
17 #include "gt/intel_engine.h"
18 #include "gt/intel_gt_types.h"
19 #include "gt/uc/intel_uc_fw.h"
21 #include "intel_device_info.h"
24 #include "i915_gem_gtt.h"
25 #include "i915_params.h"
26 #include "i915_scheduler.h"
28 struct drm_i915_private;
29 struct i915_vma_compress;
30 struct intel_engine_capture_vma;
31 struct intel_overlay_error_state;
32 struct intel_display_error_state;
34 struct i915_vma_coredump {
35 struct i915_vma_coredump *next;
49 struct i915_request_coredump {
56 struct i915_sched_attr sched_attr;
59 struct intel_engine_coredump {
60 const struct intel_engine_cs *engine;
66 /* position of active request inside the ring */
67 u32 rq_head, rq_post, rq_tail;
87 u32 rc_psmi; /* sleep state */
88 struct intel_instdone instdone;
90 struct i915_gem_context_coredump {
91 char comm[TASK_COMM_LEN];
99 struct i915_sched_attr sched_attr;
102 struct i915_vma_coredump *vma;
104 struct i915_request_coredump execlist[EXECLIST_MAX_PORTS];
105 unsigned int num_ports;
115 struct intel_engine_coredump *next;
118 struct intel_gt_coredump {
119 const struct intel_gt *_gt;
123 struct intel_gt_info info;
125 /* Generic register state */
129 u32 gtier[6], ngtier;
132 u32 error; /* gen6+ */
133 u32 err_int; /* gen7 */
134 u32 fault_data0; /* gen8, gen9 */
135 u32 fault_data1; /* gen8, gen9 */
142 u32 aux_err; /* gen12 */
143 u32 sfc_done[GEN12_SFC_DONE_MAX]; /* gen12 */
144 u32 gam_done; /* gen12 */
147 u64 fence[I915_MAX_NUM_FENCES];
149 struct intel_engine_coredump *engine;
151 struct intel_uc_coredump {
152 struct intel_uc_fw guc_fw;
153 struct intel_uc_fw huc_fw;
154 struct i915_vma_coredump *guc_log;
157 struct intel_gt_coredump *next;
160 struct i915_gpu_coredump {
165 unsigned long capture;
167 struct drm_i915_private *i915;
169 struct intel_gt_coredump *gt;
179 struct intel_device_info device_info;
180 struct intel_runtime_info runtime_info;
181 struct intel_driver_caps driver_caps;
182 struct i915_params params;
184 struct intel_overlay_error_state *overlay;
185 struct intel_display_error_state *display;
187 struct scatterlist *sgl, *fit;
190 struct i915_gpu_error {
191 /* For reset and error_state handling. */
193 /* Protected by the above dev->gpu_error.lock. */
194 struct i915_gpu_coredump *first_error;
196 atomic_t pending_fb_pin;
198 /** Number of times the device has been reset (global) */
199 atomic_t reset_count;
201 /** Number of times an engine has been reset */
202 atomic_t reset_engine_count[I915_NUM_ENGINES];
205 struct drm_i915_error_state_buf {
206 struct drm_i915_private *i915;
207 struct scatterlist *sgl, *cur, *end;
217 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
220 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
222 struct i915_gpu_coredump *i915_gpu_coredump(struct intel_gt *gt,
223 intel_engine_mask_t engine_mask);
224 void i915_capture_error_state(struct intel_gt *gt,
225 intel_engine_mask_t engine_mask);
227 struct i915_gpu_coredump *
228 i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp);
230 struct intel_gt_coredump *
231 intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp);
233 struct intel_engine_coredump *
234 intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp);
236 struct intel_engine_capture_vma *
237 intel_engine_coredump_add_request(struct intel_engine_coredump *ee,
238 struct i915_request *rq,
241 void intel_engine_coredump_add_vma(struct intel_engine_coredump *ee,
242 struct intel_engine_capture_vma *capture,
243 struct i915_vma_compress *compress);
245 struct i915_vma_compress *
246 i915_vma_capture_prepare(struct intel_gt_coredump *gt);
248 void i915_vma_capture_finish(struct intel_gt_coredump *gt,
249 struct i915_vma_compress *compress);
251 void i915_error_state_store(struct i915_gpu_coredump *error);
253 static inline struct i915_gpu_coredump *
254 i915_gpu_coredump_get(struct i915_gpu_coredump *gpu)
261 i915_gpu_coredump_copy_to_buffer(struct i915_gpu_coredump *error,
262 char *buf, loff_t offset, size_t count);
264 void __i915_gpu_coredump_free(struct kref *kref);
265 static inline void i915_gpu_coredump_put(struct i915_gpu_coredump *gpu)
268 kref_put(&gpu->ref, __i915_gpu_coredump_free);
271 struct i915_gpu_coredump *i915_first_error_state(struct drm_i915_private *i915);
272 void i915_reset_error_state(struct drm_i915_private *i915);
273 void i915_disable_error_state(struct drm_i915_private *i915, int err);
278 i915_capture_error_state(struct intel_gt *gt, intel_engine_mask_t engine_mask)
282 static inline struct i915_gpu_coredump *
283 i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp)
288 static inline struct intel_gt_coredump *
289 intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp)
294 static inline struct intel_engine_coredump *
295 intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp)
300 static inline struct intel_engine_capture_vma *
301 intel_engine_coredump_add_request(struct intel_engine_coredump *ee,
302 struct i915_request *rq,
309 intel_engine_coredump_add_vma(struct intel_engine_coredump *ee,
310 struct intel_engine_capture_vma *capture,
311 struct i915_vma_compress *compress)
315 static inline struct i915_vma_compress *
316 i915_vma_capture_prepare(struct intel_gt_coredump *gt)
322 i915_vma_capture_finish(struct intel_gt_coredump *gt,
323 struct i915_vma_compress *compress)
328 i915_error_state_store(struct i915_gpu_coredump *error)
332 static inline void i915_gpu_coredump_put(struct i915_gpu_coredump *gpu)
336 static inline struct i915_gpu_coredump *
337 i915_first_error_state(struct drm_i915_private *i915)
339 return ERR_PTR(-ENODEV);
342 static inline void i915_reset_error_state(struct drm_i915_private *i915)
346 static inline void i915_disable_error_state(struct drm_i915_private *i915,
351 #endif /* IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) */
353 #endif /* _I915_GPU_ERROR_H_ */