2 * SPDX-License-Identifier: MIT
4 * Copyright � 2008-2018 Intel Corporation
7 #ifndef _I915_GPU_ERROR_H_
8 #define _I915_GPU_ERROR_H_
10 #include <linux/kref.h>
11 #include <linux/ktime.h>
12 #include <linux/sched.h>
14 #include <drm/drm_mm.h>
16 #include "intel_device_info.h"
17 #include "intel_ringbuffer.h"
18 #include "intel_uc_fw.h"
21 #include "i915_gem_gtt.h"
22 #include "i915_params.h"
23 #include "i915_scheduler.h"
25 struct drm_i915_private;
26 struct intel_overlay_error_state;
27 struct intel_display_error_state;
29 struct i915_gpu_state {
34 unsigned long capture;
37 struct drm_i915_private *i915;
47 struct intel_device_info device_info;
48 struct intel_runtime_info runtime_info;
49 struct intel_driver_caps driver_caps;
50 struct i915_params params;
52 struct i915_error_uc {
53 struct intel_uc_fw guc_fw;
54 struct intel_uc_fw huc_fw;
55 struct drm_i915_error_object *guc_log;
58 /* Generic register state */
66 u32 error; /* gen6+ */
67 u32 err_int; /* gen7 */
68 u32 fault_data0; /* gen8, gen9 */
69 u32 fault_data1; /* gen8, gen9 */
77 u64 fence[I915_MAX_NUM_FENCES];
78 struct intel_overlay_error_state *overlay;
79 struct intel_display_error_state *display;
81 struct drm_i915_error_engine {
83 /* Software tracked state */
85 unsigned long hangcheck_timestamp;
86 struct i915_address_space *vm;
90 /* position of active request inside the ring */
91 u32 rq_head, rq_post, rq_tail;
93 /* our own tracking of ring head and tail */
113 u32 rc_psmi; /* sleep state */
114 struct intel_instdone instdone;
116 struct drm_i915_error_context {
117 char comm[TASK_COMM_LEN];
122 struct i915_sched_attr sched_attr;
125 struct drm_i915_error_object {
132 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
134 struct drm_i915_error_object **user_bo;
137 struct drm_i915_error_object *wa_ctx;
138 struct drm_i915_error_object *default_state;
140 struct drm_i915_error_request {
149 struct i915_sched_attr sched_attr;
150 } *requests, execlist[EXECLIST_MAX_PORTS];
151 unsigned int num_ports;
160 } engine[I915_NUM_ENGINES];
162 struct drm_i915_error_buffer {
168 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
174 } *active_bo[I915_NUM_ENGINES], *pinned_bo;
175 u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
176 struct i915_address_space *active_vm[I915_NUM_ENGINES];
178 struct scatterlist *sgl, *fit;
181 struct i915_gpu_restart;
183 struct i915_gpu_error {
184 /* For hangcheck timer */
185 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
186 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
188 struct delayed_work hangcheck_work;
190 /* For reset and error_state handling. */
192 /* Protected by the above dev->gpu_error.lock. */
193 struct i915_gpu_state *first_error;
195 atomic_t pending_fb_pin;
198 * flags: Control various stages of the GPU reset
200 * #I915_RESET_BACKOFF - When we start a global reset, we need to
201 * serialise with any other users attempting to do the same, and
202 * any global resources that may be clobber by the reset (such as
205 * #I915_RESET_ENGINE[num_engines] - Since the driver doesn't need to
206 * acquire the struct_mutex to reset an engine, we need an explicit
207 * flag to prevent two concurrent reset attempts in the same engine.
208 * As the number of engines continues to grow, allocate the flags from
209 * the most significant bits.
211 * #I915_WEDGED - If reset fails and we can no longer use the GPU,
212 * we set the #I915_WEDGED bit. Prior to command submission, e.g.
213 * i915_request_alloc(), this bit is checked and the sequence
214 * aborted (with -EIO reported to userspace) if set.
217 #define I915_RESET_BACKOFF 0
218 #define I915_RESET_MODESET 1
219 #define I915_RESET_ENGINE 2
220 #define I915_WEDGED (BITS_PER_LONG - 1)
222 /** Number of times the device has been reset (global) */
225 /** Number of times an engine has been reset */
226 u32 reset_engine_count[I915_NUM_ENGINES];
228 struct mutex wedge_mutex; /* serialises wedging/unwedging */
231 * Waitqueue to signal when a hang is detected. Used to for waiters
232 * to release the struct_mutex for the reset to procede.
234 wait_queue_head_t wait_queue;
237 * Waitqueue to signal when the reset has completed. Used by clients
238 * that wait for dev_priv->mm.wedged to settle.
240 wait_queue_head_t reset_queue;
242 struct srcu_struct reset_backoff_srcu;
244 struct i915_gpu_restart *restart;
247 struct drm_i915_error_state_buf {
248 struct drm_i915_private *i915;
249 struct scatterlist *sgl, *cur, *end;
259 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
262 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
264 struct i915_gpu_state *i915_capture_gpu_state(struct drm_i915_private *i915);
265 void i915_capture_error_state(struct drm_i915_private *dev_priv,
266 intel_engine_mask_t engine_mask,
267 const char *error_msg);
269 static inline struct i915_gpu_state *
270 i915_gpu_state_get(struct i915_gpu_state *gpu)
276 ssize_t i915_gpu_state_copy_to_buffer(struct i915_gpu_state *error,
277 char *buf, loff_t offset, size_t count);
279 void __i915_gpu_state_free(struct kref *kref);
280 static inline void i915_gpu_state_put(struct i915_gpu_state *gpu)
283 kref_put(&gpu->ref, __i915_gpu_state_free);
286 struct i915_gpu_state *i915_first_error_state(struct drm_i915_private *i915);
287 void i915_reset_error_state(struct drm_i915_private *i915);
288 void i915_disable_error_state(struct drm_i915_private *i915, int err);
292 static inline void i915_capture_error_state(struct drm_i915_private *dev_priv,
294 const char *error_msg)
298 static inline struct i915_gpu_state *
299 i915_first_error_state(struct drm_i915_private *i915)
301 return ERR_PTR(-ENODEV);
304 static inline void i915_reset_error_state(struct drm_i915_private *i915)
308 static inline void i915_disable_error_state(struct drm_i915_private *i915,
313 #endif /* IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) */
315 #endif /* _I915_GPU_ERROR_H_ */