2 * SPDX-License-Identifier: MIT
4 * Copyright � 2008-2018 Intel Corporation
7 #ifndef _I915_GPU_ERROR_H_
8 #define _I915_GPU_ERROR_H_
10 #include <linux/kref.h>
11 #include <linux/ktime.h>
12 #include <linux/sched.h>
14 #include <drm/drm_mm.h>
16 #include "gt/intel_engine.h"
18 #include "intel_device_info.h"
19 #include "intel_uc_fw.h"
22 #include "i915_gem_gtt.h"
23 #include "i915_params.h"
24 #include "i915_scheduler.h"
26 struct drm_i915_private;
27 struct intel_overlay_error_state;
28 struct intel_display_error_state;
30 struct i915_gpu_state {
35 unsigned long capture;
38 struct drm_i915_private *i915;
48 struct intel_device_info device_info;
49 struct intel_runtime_info runtime_info;
50 struct intel_driver_caps driver_caps;
51 struct i915_params params;
53 struct i915_error_uc {
54 struct intel_uc_fw guc_fw;
55 struct intel_uc_fw huc_fw;
56 struct drm_i915_error_object *guc_log;
59 /* Generic register state */
67 u32 error; /* gen6+ */
68 u32 err_int; /* gen7 */
69 u32 fault_data0; /* gen8, gen9 */
70 u32 fault_data1; /* gen8, gen9 */
78 u64 fence[I915_MAX_NUM_FENCES];
79 struct intel_overlay_error_state *overlay;
80 struct intel_display_error_state *display;
82 struct drm_i915_error_engine {
84 /* Software tracked state */
86 unsigned long hangcheck_timestamp;
87 struct i915_address_space *vm;
91 /* position of active request inside the ring */
92 u32 rq_head, rq_post, rq_tail;
94 /* our own tracking of ring head and tail */
114 u32 rc_psmi; /* sleep state */
115 struct intel_instdone instdone;
117 struct drm_i915_error_context {
118 char comm[TASK_COMM_LEN];
123 struct i915_sched_attr sched_attr;
126 struct drm_i915_error_object {
133 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
135 struct drm_i915_error_object **user_bo;
138 struct drm_i915_error_object *wa_ctx;
139 struct drm_i915_error_object *default_state;
141 struct drm_i915_error_request {
150 struct i915_sched_attr sched_attr;
151 } *requests, execlist[EXECLIST_MAX_PORTS];
152 unsigned int num_ports;
161 } engine[I915_NUM_ENGINES];
163 struct drm_i915_error_buffer {
169 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
175 } *active_bo[I915_NUM_ENGINES], *pinned_bo;
176 u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
177 struct i915_address_space *active_vm[I915_NUM_ENGINES];
179 struct scatterlist *sgl, *fit;
182 struct i915_gpu_error {
183 /* For hangcheck timer */
184 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
185 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
187 struct delayed_work hangcheck_work;
189 /* For reset and error_state handling. */
191 /* Protected by the above dev->gpu_error.lock. */
192 struct i915_gpu_state *first_error;
194 atomic_t pending_fb_pin;
197 * flags: Control various stages of the GPU reset
199 * #I915_RESET_BACKOFF - When we start a global reset, we need to
200 * serialise with any other users attempting to do the same, and
201 * any global resources that may be clobber by the reset (such as
204 * #I915_RESET_ENGINE[num_engines] - Since the driver doesn't need to
205 * acquire the struct_mutex to reset an engine, we need an explicit
206 * flag to prevent two concurrent reset attempts in the same engine.
207 * As the number of engines continues to grow, allocate the flags from
208 * the most significant bits.
210 * #I915_WEDGED - If reset fails and we can no longer use the GPU,
211 * we set the #I915_WEDGED bit. Prior to command submission, e.g.
212 * i915_request_alloc(), this bit is checked and the sequence
213 * aborted (with -EIO reported to userspace) if set.
216 #define I915_RESET_BACKOFF 0
217 #define I915_RESET_MODESET 1
218 #define I915_RESET_ENGINE 2
219 #define I915_WEDGED (BITS_PER_LONG - 1)
221 /** Number of times the device has been reset (global) */
224 /** Number of times an engine has been reset */
225 u32 reset_engine_count[I915_NUM_ENGINES];
227 struct mutex wedge_mutex; /* serialises wedging/unwedging */
230 * Waitqueue to signal when a hang is detected. Used to for waiters
231 * to release the struct_mutex for the reset to procede.
233 wait_queue_head_t wait_queue;
236 * Waitqueue to signal when the reset has completed. Used by clients
237 * that wait for dev_priv->mm.wedged to settle.
239 wait_queue_head_t reset_queue;
241 struct srcu_struct reset_backoff_srcu;
244 struct drm_i915_error_state_buf {
245 struct drm_i915_private *i915;
246 struct scatterlist *sgl, *cur, *end;
256 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
259 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
261 struct i915_gpu_state *i915_capture_gpu_state(struct drm_i915_private *i915);
262 void i915_capture_error_state(struct drm_i915_private *dev_priv,
263 intel_engine_mask_t engine_mask,
264 const char *error_msg);
266 static inline struct i915_gpu_state *
267 i915_gpu_state_get(struct i915_gpu_state *gpu)
273 ssize_t i915_gpu_state_copy_to_buffer(struct i915_gpu_state *error,
274 char *buf, loff_t offset, size_t count);
276 void __i915_gpu_state_free(struct kref *kref);
277 static inline void i915_gpu_state_put(struct i915_gpu_state *gpu)
280 kref_put(&gpu->ref, __i915_gpu_state_free);
283 struct i915_gpu_state *i915_first_error_state(struct drm_i915_private *i915);
284 void i915_reset_error_state(struct drm_i915_private *i915);
285 void i915_disable_error_state(struct drm_i915_private *i915, int err);
289 static inline void i915_capture_error_state(struct drm_i915_private *dev_priv,
291 const char *error_msg)
295 static inline struct i915_gpu_state *
296 i915_first_error_state(struct drm_i915_private *i915)
298 return ERR_PTR(-ENODEV);
301 static inline void i915_reset_error_state(struct drm_i915_private *i915)
305 static inline void i915_disable_error_state(struct drm_i915_private *i915,
310 #endif /* IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) */
312 #endif /* _I915_GPU_ERROR_H_ */