2 * SPDX-License-Identifier: MIT
4 * Copyright © 2008-2018 Intel Corporation
7 #ifndef _I915_GPU_ERROR_H_
8 #define _I915_GPU_ERROR_H_
10 #include <linux/atomic.h>
11 #include <linux/kref.h>
12 #include <linux/ktime.h>
13 #include <linux/sched.h>
15 #include <drm/drm_mm.h>
17 #include "display/intel_display_device.h"
18 #include "display/intel_display_params.h"
19 #include "gt/intel_engine.h"
20 #include "gt/intel_engine_types.h"
21 #include "gt/intel_gt_types.h"
22 #include "gt/uc/intel_uc_fw.h"
24 #include "intel_device_info.h"
27 #include "i915_gem_gtt.h"
28 #include "i915_params.h"
29 #include "i915_scheduler.h"
31 struct drm_i915_private;
32 struct i915_vma_compress;
33 struct intel_engine_capture_vma;
34 struct intel_overlay_error_state;
36 struct i915_vma_coredump {
37 struct i915_vma_coredump *next;
46 struct list_head page_list;
49 struct i915_request_coredump {
56 struct i915_sched_attr sched_attr;
59 struct __guc_capture_parsed_output;
61 struct intel_engine_coredump {
62 const struct intel_engine_cs *engine;
68 /* position of active request inside the ring */
69 u32 rq_head, rq_post, rq_tail;
89 u32 rc_psmi; /* sleep state */
97 struct intel_instdone instdone;
99 /* GuC matched capture-lists info */
100 struct intel_guc_state_capture *guc_capture;
101 struct __guc_capture_parsed_output *guc_capture_node;
103 struct i915_gem_context_coredump {
104 char comm[TASK_COMM_LEN];
112 struct i915_sched_attr sched_attr;
116 struct i915_vma_coredump *vma;
118 struct i915_request_coredump execlist[EXECLIST_MAX_PORTS];
119 unsigned int num_ports;
129 struct intel_engine_coredump *next;
132 struct intel_ctb_coredump {
141 struct intel_gt_coredump {
142 const struct intel_gt *_gt;
146 struct intel_gt_info info;
148 /* Generic register state */
152 u32 gtier[6], ngtier;
154 u32 error; /* gen6+ */
155 u32 err_int; /* gen7 */
156 u32 fault_data0; /* gen8, gen9 */
157 u32 fault_data1; /* gen8, gen9 */
164 u32 aux_err; /* gen12 */
165 u32 gam_done; /* gen12 */
169 /* Display related */
171 u32 sfc_done[I915_MAX_SFC]; /* gen12 */
174 u64 fence[I915_MAX_NUM_FENCES];
176 struct intel_engine_coredump *engine;
178 struct intel_uc_coredump {
179 struct intel_uc_fw guc_fw;
180 struct intel_uc_fw huc_fw;
182 struct intel_ctb_coredump ctb[2];
183 struct i915_vma_coredump *vma_ctb;
184 struct i915_vma_coredump *vma_log;
191 struct intel_gt_coredump *next;
194 struct i915_gpu_coredump {
199 unsigned long capture;
201 struct drm_i915_private *i915;
203 struct intel_gt_coredump *gt;
213 struct intel_device_info device_info;
214 struct intel_runtime_info runtime_info;
215 struct intel_display_device_info display_device_info;
216 struct intel_display_runtime_info display_runtime_info;
217 struct intel_driver_caps driver_caps;
218 struct i915_params params;
219 struct intel_display_params display_params;
221 struct intel_overlay_error_state *overlay;
223 struct scatterlist *sgl, *fit;
226 struct i915_gpu_error {
227 /* For reset and error_state handling. */
229 /* Protected by the above dev->gpu_error.lock. */
230 struct i915_gpu_coredump *first_error;
232 atomic_t pending_fb_pin;
234 /** Number of times the device has been reset (global) */
235 atomic_t reset_count;
237 /** Number of times an engine has been reset */
238 atomic_t reset_engine_count[MAX_ENGINE_CLASS];
241 struct drm_i915_error_state_buf {
242 struct drm_i915_private *i915;
243 struct scatterlist *sgl, *cur, *end;
253 static inline u32 i915_reset_count(struct i915_gpu_error *error)
255 return atomic_read(&error->reset_count);
258 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
259 const struct intel_engine_cs *engine)
261 return atomic_read(&error->reset_engine_count[engine->class]);
265 i915_increase_reset_engine_count(struct i915_gpu_error *error,
266 const struct intel_engine_cs *engine)
268 atomic_inc(&error->reset_engine_count[engine->class]);
271 #define CORE_DUMP_FLAG_NONE 0x0
272 #define CORE_DUMP_FLAG_IS_GUC_CAPTURE BIT(0)
274 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) && IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
275 void intel_klog_error_capture(struct intel_gt *gt,
276 intel_engine_mask_t engine_mask);
278 static inline void intel_klog_error_capture(struct intel_gt *gt,
279 intel_engine_mask_t engine_mask)
284 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
287 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
289 void i915_capture_error_state(struct intel_gt *gt,
290 intel_engine_mask_t engine_mask, u32 dump_flags);
292 struct i915_gpu_coredump *
293 i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp);
295 struct intel_gt_coredump *
296 intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp, u32 dump_flags);
298 struct intel_engine_coredump *
299 intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp, u32 dump_flags);
301 struct intel_engine_capture_vma *
302 intel_engine_coredump_add_request(struct intel_engine_coredump *ee,
303 struct i915_request *rq,
306 void intel_engine_coredump_add_vma(struct intel_engine_coredump *ee,
307 struct intel_engine_capture_vma *capture,
308 struct i915_vma_compress *compress);
310 struct i915_vma_compress *
311 i915_vma_capture_prepare(struct intel_gt_coredump *gt);
313 void i915_vma_capture_finish(struct intel_gt_coredump *gt,
314 struct i915_vma_compress *compress);
316 void i915_error_state_store(struct i915_gpu_coredump *error);
318 static inline struct i915_gpu_coredump *
319 i915_gpu_coredump_get(struct i915_gpu_coredump *gpu)
326 i915_gpu_coredump_copy_to_buffer(struct i915_gpu_coredump *error,
327 char *buf, loff_t offset, size_t count);
329 void __i915_gpu_coredump_free(struct kref *kref);
330 static inline void i915_gpu_coredump_put(struct i915_gpu_coredump *gpu)
333 kref_put(&gpu->ref, __i915_gpu_coredump_free);
336 void i915_reset_error_state(struct drm_i915_private *i915);
337 void i915_disable_error_state(struct drm_i915_private *i915, int err);
339 void i915_gpu_error_debugfs_register(struct drm_i915_private *i915);
340 void i915_gpu_error_sysfs_setup(struct drm_i915_private *i915);
341 void i915_gpu_error_sysfs_teardown(struct drm_i915_private *i915);
347 i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
352 i915_capture_error_state(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags)
356 static inline struct i915_gpu_coredump *
357 i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp)
362 static inline struct intel_gt_coredump *
363 intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp, u32 dump_flags)
368 static inline struct intel_engine_coredump *
369 intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp, u32 dump_flags)
374 static inline struct intel_engine_capture_vma *
375 intel_engine_coredump_add_request(struct intel_engine_coredump *ee,
376 struct i915_request *rq,
383 intel_engine_coredump_add_vma(struct intel_engine_coredump *ee,
384 struct intel_engine_capture_vma *capture,
385 struct i915_vma_compress *compress)
389 static inline struct i915_vma_compress *
390 i915_vma_capture_prepare(struct intel_gt_coredump *gt)
396 i915_vma_capture_finish(struct intel_gt_coredump *gt,
397 struct i915_vma_compress *compress)
402 i915_error_state_store(struct i915_gpu_coredump *error)
406 static inline void i915_gpu_coredump_put(struct i915_gpu_coredump *gpu)
410 static inline void i915_reset_error_state(struct drm_i915_private *i915)
414 static inline void i915_disable_error_state(struct drm_i915_private *i915,
419 static inline void i915_gpu_error_debugfs_register(struct drm_i915_private *i915)
423 static inline void i915_gpu_error_sysfs_setup(struct drm_i915_private *i915)
427 static inline void i915_gpu_error_sysfs_teardown(struct drm_i915_private *i915)
431 #endif /* IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) */
433 #endif /* _I915_GPU_ERROR_H_ */