2 * SPDX-License-Identifier: MIT
4 * Copyright � 2008-2018 Intel Corporation
7 #ifndef _I915_GPU_ERROR_H_
8 #define _I915_GPU_ERROR_H_
10 #include <linux/atomic.h>
11 #include <linux/kref.h>
12 #include <linux/ktime.h>
13 #include <linux/sched.h>
15 #include <drm/drm_mm.h>
17 #include "gt/intel_engine.h"
18 #include "gt/uc/intel_uc_fw.h"
20 #include "intel_device_info.h"
23 #include "i915_gem_gtt.h"
24 #include "i915_params.h"
25 #include "i915_scheduler.h"
27 struct drm_i915_private;
28 struct intel_overlay_error_state;
29 struct intel_display_error_state;
31 struct i915_gpu_state {
36 unsigned long capture;
39 struct drm_i915_private *i915;
49 struct intel_device_info device_info;
50 struct intel_runtime_info runtime_info;
51 struct intel_driver_caps driver_caps;
52 struct i915_params params;
54 struct i915_error_uc {
55 struct intel_uc_fw guc_fw;
56 struct intel_uc_fw huc_fw;
57 struct drm_i915_error_object *guc_log;
60 /* Generic register state */
68 u32 error; /* gen6+ */
69 u32 err_int; /* gen7 */
70 u32 fault_data0; /* gen8, gen9 */
71 u32 fault_data1; /* gen8, gen9 */
79 u64 fence[I915_MAX_NUM_FENCES];
80 struct intel_overlay_error_state *overlay;
81 struct intel_display_error_state *display;
83 struct drm_i915_error_engine {
85 /* Software tracked state */
87 unsigned long hangcheck_timestamp;
91 /* position of active request inside the ring */
92 u32 rq_head, rq_post, rq_tail;
94 /* our own tracking of ring head and tail */
114 u32 rc_psmi; /* sleep state */
115 struct intel_instdone instdone;
117 struct drm_i915_error_context {
118 char comm[TASK_COMM_LEN];
123 struct i915_sched_attr sched_attr;
126 struct drm_i915_error_object {
133 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
135 struct drm_i915_error_object **user_bo;
138 struct drm_i915_error_object *wa_ctx;
139 struct drm_i915_error_object *default_state;
141 struct drm_i915_error_request {
150 struct i915_sched_attr sched_attr;
151 } *requests, execlist[EXECLIST_MAX_PORTS];
152 unsigned int num_ports;
161 } engine[I915_NUM_ENGINES];
163 struct scatterlist *sgl, *fit;
166 struct i915_gpu_error {
167 /* For reset and error_state handling. */
169 /* Protected by the above dev->gpu_error.lock. */
170 struct i915_gpu_state *first_error;
172 atomic_t pending_fb_pin;
174 /** Number of times the device has been reset (global) */
175 atomic_t reset_count;
177 /** Number of times an engine has been reset */
178 atomic_t reset_engine_count[I915_NUM_ENGINES];
181 struct drm_i915_error_state_buf {
182 struct drm_i915_private *i915;
183 struct scatterlist *sgl, *cur, *end;
193 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
196 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
198 struct i915_gpu_state *i915_capture_gpu_state(struct drm_i915_private *i915);
199 void i915_capture_error_state(struct drm_i915_private *dev_priv,
200 intel_engine_mask_t engine_mask,
201 const char *error_msg);
203 static inline struct i915_gpu_state *
204 i915_gpu_state_get(struct i915_gpu_state *gpu)
210 ssize_t i915_gpu_state_copy_to_buffer(struct i915_gpu_state *error,
211 char *buf, loff_t offset, size_t count);
213 void __i915_gpu_state_free(struct kref *kref);
214 static inline void i915_gpu_state_put(struct i915_gpu_state *gpu)
217 kref_put(&gpu->ref, __i915_gpu_state_free);
220 struct i915_gpu_state *i915_first_error_state(struct drm_i915_private *i915);
221 void i915_reset_error_state(struct drm_i915_private *i915);
222 void i915_disable_error_state(struct drm_i915_private *i915, int err);
226 static inline void i915_capture_error_state(struct drm_i915_private *dev_priv,
228 const char *error_msg)
232 static inline struct i915_gpu_state *
233 i915_first_error_state(struct drm_i915_private *i915)
235 return ERR_PTR(-ENODEV);
238 static inline void i915_reset_error_state(struct drm_i915_private *i915)
242 static inline void i915_disable_error_state(struct drm_i915_private *i915,
247 #endif /* IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) */
249 #endif /* _I915_GPU_ERROR_H_ */