2 * SPDX-License-Identifier: MIT
4 * Copyright � 2008-2018 Intel Corporation
7 #ifndef _I915_GPU_ERROR_H_
8 #define _I915_GPU_ERROR_H_
10 #include <linux/atomic.h>
11 #include <linux/kref.h>
12 #include <linux/ktime.h>
13 #include <linux/sched.h>
15 #include <drm/drm_mm.h>
17 #include "gt/intel_engine.h"
18 #include "gt/uc/intel_uc_fw.h"
20 #include "intel_device_info.h"
23 #include "i915_gem_gtt.h"
24 #include "i915_params.h"
25 #include "i915_scheduler.h"
27 struct drm_i915_private;
28 struct i915_vma_compress;
29 struct intel_engine_capture_vma;
30 struct intel_overlay_error_state;
31 struct intel_display_error_state;
33 struct i915_vma_coredump {
34 struct i915_vma_coredump *next;
48 struct i915_request_coredump {
56 struct i915_sched_attr sched_attr;
59 struct intel_engine_coredump {
60 const struct intel_engine_cs *engine;
65 /* position of active request inside the ring */
66 u32 rq_head, rq_post, rq_tail;
86 u32 rc_psmi; /* sleep state */
87 struct intel_instdone instdone;
89 struct i915_gem_context_coredump {
90 char comm[TASK_COMM_LEN];
98 struct i915_sched_attr sched_attr;
101 struct i915_vma_coredump *vma;
103 struct i915_request_coredump execlist[EXECLIST_MAX_PORTS];
104 unsigned int num_ports;
114 struct intel_engine_coredump *next;
117 struct intel_gt_coredump {
118 const struct intel_gt *_gt;
122 /* Generic register state */
126 u32 gtier[6], ngtier;
129 u32 error; /* gen6+ */
130 u32 err_int; /* gen7 */
131 u32 fault_data0; /* gen8, gen9 */
132 u32 fault_data1; /* gen8, gen9 */
139 u32 aux_err; /* gen12 */
140 u32 sfc_done[GEN12_SFC_DONE_MAX]; /* gen12 */
141 u32 gam_done; /* gen12 */
144 u64 fence[I915_MAX_NUM_FENCES];
146 struct intel_engine_coredump *engine;
148 struct intel_uc_coredump {
149 struct intel_uc_fw guc_fw;
150 struct intel_uc_fw huc_fw;
151 struct i915_vma_coredump *guc_log;
154 struct intel_gt_coredump *next;
157 struct i915_gpu_coredump {
162 unsigned long capture;
164 struct drm_i915_private *i915;
166 struct intel_gt_coredump *gt;
176 struct intel_device_info device_info;
177 struct intel_runtime_info runtime_info;
178 struct intel_driver_caps driver_caps;
179 struct i915_params params;
181 struct intel_overlay_error_state *overlay;
182 struct intel_display_error_state *display;
184 struct scatterlist *sgl, *fit;
187 struct i915_gpu_error {
188 /* For reset and error_state handling. */
190 /* Protected by the above dev->gpu_error.lock. */
191 struct i915_gpu_coredump *first_error;
193 atomic_t pending_fb_pin;
195 /** Number of times the device has been reset (global) */
196 atomic_t reset_count;
198 /** Number of times an engine has been reset */
199 atomic_t reset_engine_count[I915_NUM_ENGINES];
202 struct drm_i915_error_state_buf {
203 struct drm_i915_private *i915;
204 struct scatterlist *sgl, *cur, *end;
214 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
217 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
219 struct i915_gpu_coredump *i915_gpu_coredump(struct drm_i915_private *i915);
220 void i915_capture_error_state(struct drm_i915_private *i915);
222 struct i915_gpu_coredump *
223 i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp);
225 struct intel_gt_coredump *
226 intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp);
228 struct intel_engine_coredump *
229 intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp);
231 struct intel_engine_capture_vma *
232 intel_engine_coredump_add_request(struct intel_engine_coredump *ee,
233 struct i915_request *rq,
236 void intel_engine_coredump_add_vma(struct intel_engine_coredump *ee,
237 struct intel_engine_capture_vma *capture,
238 struct i915_vma_compress *compress);
240 struct i915_vma_compress *
241 i915_vma_capture_prepare(struct intel_gt_coredump *gt);
243 void i915_vma_capture_finish(struct intel_gt_coredump *gt,
244 struct i915_vma_compress *compress);
246 void i915_error_state_store(struct i915_gpu_coredump *error);
248 static inline struct i915_gpu_coredump *
249 i915_gpu_coredump_get(struct i915_gpu_coredump *gpu)
256 i915_gpu_coredump_copy_to_buffer(struct i915_gpu_coredump *error,
257 char *buf, loff_t offset, size_t count);
259 void __i915_gpu_coredump_free(struct kref *kref);
260 static inline void i915_gpu_coredump_put(struct i915_gpu_coredump *gpu)
263 kref_put(&gpu->ref, __i915_gpu_coredump_free);
266 struct i915_gpu_coredump *i915_first_error_state(struct drm_i915_private *i915);
267 void i915_reset_error_state(struct drm_i915_private *i915);
268 void i915_disable_error_state(struct drm_i915_private *i915, int err);
272 static inline void i915_capture_error_state(struct drm_i915_private *i915)
276 static inline struct i915_gpu_coredump *
277 i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp)
282 static inline struct intel_gt_coredump *
283 intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp)
288 static inline struct intel_engine_coredump *
289 intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp)
294 static inline struct intel_engine_capture_vma *
295 intel_engine_coredump_add_request(struct intel_engine_coredump *ee,
296 struct i915_request *rq,
303 intel_engine_coredump_add_vma(struct intel_engine_coredump *ee,
304 struct intel_engine_capture_vma *capture,
305 struct i915_vma_compress *compress)
309 static inline struct i915_vma_compress *
310 i915_vma_capture_prepare(struct intel_gt_coredump *gt)
316 i915_vma_capture_finish(struct intel_gt_coredump *gt,
317 struct i915_vma_compress *compress)
322 i915_error_state_store(struct i915_gpu_coredump *error)
326 static inline void i915_gpu_coredump_put(struct i915_gpu_coredump *gpu)
330 static inline struct i915_gpu_coredump *
331 i915_first_error_state(struct drm_i915_private *i915)
333 return ERR_PTR(-ENODEV);
336 static inline void i915_reset_error_state(struct drm_i915_private *i915)
340 static inline void i915_disable_error_state(struct drm_i915_private *i915,
345 #endif /* IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) */
347 #endif /* _I915_GPU_ERROR_H_ */