drivers/gpu/drm/i915/i915_gpu_error.c

   1 /*
   2  * Copyright (c) 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *    Mika Kuoppala <mika.kuoppala@intel.com>
  27  *
  28  */
  29
  30 #include <linux/ascii85.h>
  31 #include <linux/nmi.h>
  32 #include <linux/pagevec.h>
  33 #include <linux/scatterlist.h>
  34 #include <linux/utsname.h>
  35 #include <linux/zlib.h>
  36
  37 #include <drm/drm_print.h>
  38
  39 #include "display/intel_atomic.h"
  40 #include "display/intel_overlay.h"
  41
  42 #include "gem/i915_gem_context.h"
  43 #include "gem/i915_gem_lmem.h"
  44 #include "gt/intel_gt_pm.h"
  45
  46 #include "i915_drv.h"
  47 #include "i915_gpu_error.h"
  48 #include "i915_memcpy.h"
  49 #include "i915_scatterlist.h"
  50 #include "intel_csr.h"
  51
  52 #define ALLOW_FAIL (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN)
  53 #define ATOMIC_MAYFAIL (GFP_ATOMIC | __GFP_NOWARN)
  54
  55 static void __sg_set_buf(struct scatterlist *sg,
  56                          void *addr, unsigned int len, loff_t it)
  57 {
  58         sg->page_link = (unsigned long)virt_to_page(addr);
  59         sg->offset = offset_in_page(addr);
  60         sg->length = len;
  61         sg->dma_address = it;
  62 }
  63
  64 static bool __i915_error_grow(struct drm_i915_error_state_buf *e, size_t len)
  65 {
  66         if (!len)
  67                 return false;
  68
  69         if (e->bytes + len + 1 <= e->size)
  70                 return true;
  71
  72         if (e->bytes) {
  73                 __sg_set_buf(e->cur++, e->buf, e->bytes, e->iter);
  74                 e->iter += e->bytes;
  75                 e->buf = NULL;
  76                 e->bytes = 0;
  77         }
  78
  79         if (e->cur == e->end) {
  80                 struct scatterlist *sgl;
  81
  82                 sgl = (typeof(sgl))__get_free_page(ALLOW_FAIL);
  83                 if (!sgl) {
  84                         e->err = -ENOMEM;
  85                         return false;
  86                 }
  87
  88                 if (e->cur) {
  89                         e->cur->offset = 0;
  90                         e->cur->length = 0;
  91                         e->cur->page_link =
  92                                 (unsigned long)sgl | SG_CHAIN;
  93                 } else {
  94                         e->sgl = sgl;
  95                 }
  96
  97                 e->cur = sgl;
  98                 e->end = sgl + SG_MAX_SINGLE_ALLOC - 1;
  99         }
 100
 101         e->size = ALIGN(len + 1, SZ_64K);
 102         e->buf = kmalloc(e->size, ALLOW_FAIL);
 103         if (!e->buf) {
 104                 e->size = PAGE_ALIGN(len + 1);
 105                 e->buf = kmalloc(e->size, GFP_KERNEL);
 106         }
 107         if (!e->buf) {
 108                 e->err = -ENOMEM;
 109                 return false;
 110         }
 111
 112         return true;
 113 }
 114
 115 __printf(2, 0)
 116 static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
 117                                const char *fmt, va_list args)
 118 {
 119         va_list ap;
 120         int len;
 121
 122         if (e->err)
 123                 return;
 124
 125         va_copy(ap, args);
 126         len = vsnprintf(NULL, 0, fmt, ap);
 127         va_end(ap);
 128         if (len <= 0) {
 129                 e->err = len;
 130                 return;
 131         }
 132
 133         if (!__i915_error_grow(e, len))
 134                 return;
 135
 136         GEM_BUG_ON(e->bytes >= e->size);
 137         len = vscnprintf(e->buf + e->bytes, e->size - e->bytes, fmt, args);
 138         if (len < 0) {
 139                 e->err = len;
 140                 return;
 141         }
 142         e->bytes += len;
 143 }
 144
 145 static void i915_error_puts(struct drm_i915_error_state_buf *e, const char *str)
 146 {
 147         unsigned len;
 148
 149         if (e->err || !str)
 150                 return;
 151
 152         len = strlen(str);
 153         if (!__i915_error_grow(e, len))
 154                 return;
 155
 156         GEM_BUG_ON(e->bytes + len > e->size);
 157         memcpy(e->buf + e->bytes, str, len);
 158         e->bytes += len;
 159 }
 160
 161 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
 162 #define err_puts(e, s) i915_error_puts(e, s)
 163
 164 static void __i915_printfn_error(struct drm_printer *p, struct va_format *vaf)
 165 {
 166         i915_error_vprintf(p->arg, vaf->fmt, *vaf->va);
 167 }
 168
 169 static inline struct drm_printer
 170 i915_error_printer(struct drm_i915_error_state_buf *e)
 171 {
 172         struct drm_printer p = {
 173                 .printfn = __i915_printfn_error,
 174                 .arg = e,
 175         };
 176         return p;
 177 }
 178
 179 /* single threaded page allocator with a reserved stash for emergencies */
 180 static void pool_fini(struct pagevec *pv)
 181 {
 182         pagevec_release(pv);
 183 }
 184
 185 static int pool_refill(struct pagevec *pv, gfp_t gfp)
 186 {
 187         while (pagevec_space(pv)) {
 188                 struct page *p;
 189
 190                 p = alloc_page(gfp);
 191                 if (!p)
 192                         return -ENOMEM;
 193
 194                 pagevec_add(pv, p);
 195         }
 196
 197         return 0;
 198 }
 199
 200 static int pool_init(struct pagevec *pv, gfp_t gfp)
 201 {
 202         int err;
 203
 204         pagevec_init(pv);
 205
 206         err = pool_refill(pv, gfp);
 207         if (err)
 208                 pool_fini(pv);
 209
 210         return err;
 211 }
 212
 213 static void *pool_alloc(struct pagevec *pv, gfp_t gfp)
 214 {
 215         struct page *p;
 216
 217         p = alloc_page(gfp);
 218         if (!p && pagevec_count(pv))
 219                 p = pv->pages[--pv->nr];
 220
 221         return p ? page_address(p) : NULL;
 222 }
 223
 224 static void pool_free(struct pagevec *pv, void *addr)
 225 {
 226         struct page *p = virt_to_page(addr);
 227
 228         if (pagevec_space(pv))
 229                 pagevec_add(pv, p);
 230         else
 231                 __free_page(p);
 232 }
 233
 234 #ifdef CONFIG_DRM_I915_COMPRESS_ERROR
 235
 236 struct i915_vma_compress {
 237         struct pagevec pool;
 238         struct z_stream_s zstream;
 239         void *tmp;
 240 };
 241
 242 static bool compress_init(struct i915_vma_compress *c)
 243 {
 244         struct z_stream_s *zstream = &c->zstream;
 245
 246         if (pool_init(&c->pool, ALLOW_FAIL))
 247                 return false;
 248
 249         zstream->workspace =
 250                 kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL),
 251                         ALLOW_FAIL);
 252         if (!zstream->workspace) {
 253                 pool_fini(&c->pool);
 254                 return false;
 255         }
 256
 257         c->tmp = NULL;
 258         if (i915_has_memcpy_from_wc())
 259                 c->tmp = pool_alloc(&c->pool, ALLOW_FAIL);
 260
 261         return true;
 262 }
 263
 264 static bool compress_start(struct i915_vma_compress *c)
 265 {
 266         struct z_stream_s *zstream = &c->zstream;
 267         void *workspace = zstream->workspace;
 268
 269         memset(zstream, 0, sizeof(*zstream));
 270         zstream->workspace = workspace;
 271
 272         return zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) == Z_OK;
 273 }
 274
 275 static void *compress_next_page(struct i915_vma_compress *c,
 276                                 struct i915_vma_coredump *dst)
 277 {
 278         void *page;
 279
 280         if (dst->page_count >= dst->num_pages)
 281                 return ERR_PTR(-ENOSPC);
 282
 283         page = pool_alloc(&c->pool, ALLOW_FAIL);
 284         if (!page)
 285                 return ERR_PTR(-ENOMEM);
 286
 287         return dst->pages[dst->page_count++] = page;
 288 }
 289
 290 static int compress_page(struct i915_vma_compress *c,
 291                          void *src,
 292                          struct i915_vma_coredump *dst,
 293                          bool wc)
 294 {
 295         struct z_stream_s *zstream = &c->zstream;
 296
 297         zstream->next_in = src;
 298         if (wc && c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE))
 299                 zstream->next_in = c->tmp;
 300         zstream->avail_in = PAGE_SIZE;
 301
 302         do {
 303                 if (zstream->avail_out == 0) {
 304                         zstream->next_out = compress_next_page(c, dst);
 305                         if (IS_ERR(zstream->next_out))
 306                                 return PTR_ERR(zstream->next_out);
 307
 308                         zstream->avail_out = PAGE_SIZE;
 309                 }
 310
 311                 if (zlib_deflate(zstream, Z_NO_FLUSH) != Z_OK)
 312                         return -EIO;
 313         } while (zstream->avail_in);
 314
 315         /* Fallback to uncompressed if we increase size? */
 316         if (0 && zstream->total_out > zstream->total_in)
 317                 return -E2BIG;
 318
 319         return 0;
 320 }
 321
 322 static int compress_flush(struct i915_vma_compress *c,
 323                           struct i915_vma_coredump *dst)
 324 {
 325         struct z_stream_s *zstream = &c->zstream;
 326
 327         do {
 328                 switch (zlib_deflate(zstream, Z_FINISH)) {
 329                 case Z_OK: /* more space requested */
 330                         zstream->next_out = compress_next_page(c, dst);
 331                         if (IS_ERR(zstream->next_out))
 332                                 return PTR_ERR(zstream->next_out);
 333
 334                         zstream->avail_out = PAGE_SIZE;
 335                         break;
 336
 337                 case Z_STREAM_END:
 338                         goto end;
 339
 340                 default: /* any error */
 341                         return -EIO;
 342                 }
 343         } while (1);
 344
 345 end:
 346         memset(zstream->next_out, 0, zstream->avail_out);
 347         dst->unused = zstream->avail_out;
 348         return 0;
 349 }
 350
 351 static void compress_finish(struct i915_vma_compress *c)
 352 {
 353         zlib_deflateEnd(&c->zstream);
 354 }
 355
 356 static void compress_fini(struct i915_vma_compress *c)
 357 {
 358         kfree(c->zstream.workspace);
 359         if (c->tmp)
 360                 pool_free(&c->pool, c->tmp);
 361         pool_fini(&c->pool);
 362 }
 363
 364 static void err_compression_marker(struct drm_i915_error_state_buf *m)
 365 {
 366         err_puts(m, ":");
 367 }
 368
 369 #else
 370
 371 struct i915_vma_compress {
 372         struct pagevec pool;
 373 };
 374
 375 static bool compress_init(struct i915_vma_compress *c)
 376 {
 377         return pool_init(&c->pool, ALLOW_FAIL) == 0;
 378 }
 379
 380 static bool compress_start(struct i915_vma_compress *c)
 381 {
 382         return true;
 383 }
 384
 385 static int compress_page(struct i915_vma_compress *c,
 386                          void *src,
 387                          struct i915_vma_coredump *dst,
 388                          bool wc)
 389 {
 390         void *ptr;
 391
 392         ptr = pool_alloc(&c->pool, ALLOW_FAIL);
 393         if (!ptr)
 394                 return -ENOMEM;
 395
 396         if (!(wc && i915_memcpy_from_wc(ptr, src, PAGE_SIZE)))
 397                 memcpy(ptr, src, PAGE_SIZE);
 398         dst->pages[dst->page_count++] = ptr;
 399
 400         return 0;
 401 }
 402
 403 static int compress_flush(struct i915_vma_compress *c,
 404                           struct i915_vma_coredump *dst)
 405 {
 406         return 0;
 407 }
 408
 409 static void compress_finish(struct i915_vma_compress *c)
 410 {
 411 }
 412
 413 static void compress_fini(struct i915_vma_compress *c)
 414 {
 415         pool_fini(&c->pool);
 416 }
 417
 418 static void err_compression_marker(struct drm_i915_error_state_buf *m)
 419 {
 420         err_puts(m, "~");
 421 }
 422
 423 #endif
 424
 425 static void error_print_instdone(struct drm_i915_error_state_buf *m,
 426                                  const struct intel_engine_coredump *ee)
 427 {
 428         const struct sseu_dev_info *sseu = &RUNTIME_INFO(m->i915)->sseu;
 429         int slice;
 430         int subslice;
 431
 432         err_printf(m, "  INSTDONE: 0x%08x\n",
 433                    ee->instdone.instdone);
 434
 435         if (ee->engine->class != RENDER_CLASS || INTEL_GEN(m->i915) <= 3)
 436                 return;
 437
 438         err_printf(m, "  SC_INSTDONE: 0x%08x\n",
 439                    ee->instdone.slice_common);
 440
 441         if (INTEL_GEN(m->i915) <= 6)
 442                 return;
 443
 444         for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice)
 445                 err_printf(m, "  SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
 446                            slice, subslice,
 447                            ee->instdone.sampler[slice][subslice]);
 448
 449         for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice)
 450                 err_printf(m, "  ROW_INSTDONE[%d][%d]: 0x%08x\n",
 451                            slice, subslice,
 452                            ee->instdone.row[slice][subslice]);
 453 }
 454
 455 static void error_print_request(struct drm_i915_error_state_buf *m,
 456                                 const char *prefix,
 457                                 const struct i915_request_coredump *erq)
 458 {
 459         if (!erq->seqno)
 460                 return;
 461
 462         err_printf(m, "%s pid %d, seqno %8x:%08x%s%s, prio %d, start %08x, head %08x, tail %08x\n",
 463                    prefix, erq->pid, erq->context, erq->seqno,
 464                    test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
 465                             &erq->flags) ? "!" : "",
 466                    test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
 467                             &erq->flags) ? "+" : "",
 468                    erq->sched_attr.priority,
 469                    erq->start, erq->head, erq->tail);
 470 }
 471
 472 static void error_print_context(struct drm_i915_error_state_buf *m,
 473                                 const char *header,
 474                                 const struct i915_gem_context_coredump *ctx)
 475 {
 476         err_printf(m, "%s%s[%d] prio %d, guilty %d active %d\n",
 477                    header, ctx->comm, ctx->pid, ctx->sched_attr.priority,
 478                    ctx->guilty, ctx->active);
 479 }
 480
 481 static struct i915_vma_coredump *
 482 __find_vma(struct i915_vma_coredump *vma, const char *name)
 483 {
 484         while (vma) {
 485                 if (strcmp(vma->name, name) == 0)
 486                         return vma;
 487                 vma = vma->next;
 488         }
 489
 490         return NULL;
 491 }
 492
 493 static struct i915_vma_coredump *
 494 find_batch(const struct intel_engine_coredump *ee)
 495 {
 496         return __find_vma(ee->vma, "batch");
 497 }
 498
 499 static void error_print_engine(struct drm_i915_error_state_buf *m,
 500                                const struct intel_engine_coredump *ee)
 501 {
 502         struct i915_vma_coredump *batch;
 503         int n;
 504
 505         err_printf(m, "%s command stream:\n", ee->engine->name);
 506         err_printf(m, "  CCID:  0x%08x\n", ee->ccid);
 507         err_printf(m, "  START: 0x%08x\n", ee->start);
 508         err_printf(m, "  HEAD:  0x%08x [0x%08x]\n", ee->head, ee->rq_head);
 509         err_printf(m, "  TAIL:  0x%08x [0x%08x, 0x%08x]\n",
 510                    ee->tail, ee->rq_post, ee->rq_tail);
 511         err_printf(m, "  CTL:   0x%08x\n", ee->ctl);
 512         err_printf(m, "  MODE:  0x%08x\n", ee->mode);
 513         err_printf(m, "  HWS:   0x%08x\n", ee->hws);
 514         err_printf(m, "  ACTHD: 0x%08x %08x\n",
 515                    (u32)(ee->acthd>>32), (u32)ee->acthd);
 516         err_printf(m, "  IPEIR: 0x%08x\n", ee->ipeir);
 517         err_printf(m, "  IPEHR: 0x%08x\n", ee->ipehr);
 518
 519         error_print_instdone(m, ee);
 520
 521         batch = find_batch(ee);
 522         if (batch) {
 523                 u64 start = batch->gtt_offset;
 524                 u64 end = start + batch->gtt_size;
 525
 526                 err_printf(m, "  batch: [0x%08x_%08x, 0x%08x_%08x]\n",
 527                            upper_32_bits(start), lower_32_bits(start),
 528                            upper_32_bits(end), lower_32_bits(end));
 529         }
 530         if (INTEL_GEN(m->i915) >= 4) {
 531                 err_printf(m, "  BBADDR: 0x%08x_%08x\n",
 532                            (u32)(ee->bbaddr>>32), (u32)ee->bbaddr);
 533                 err_printf(m, "  BB_STATE: 0x%08x\n", ee->bbstate);
 534                 err_printf(m, "  INSTPS: 0x%08x\n", ee->instps);
 535         }
 536         err_printf(m, "  INSTPM: 0x%08x\n", ee->instpm);
 537         err_printf(m, "  FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr),
 538                    lower_32_bits(ee->faddr));
 539         if (INTEL_GEN(m->i915) >= 6) {
 540                 err_printf(m, "  RC PSMI: 0x%08x\n", ee->rc_psmi);
 541                 err_printf(m, "  FAULT_REG: 0x%08x\n", ee->fault_reg);
 542         }
 543         if (HAS_PPGTT(m->i915)) {
 544                 err_printf(m, "  GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
 545
 546                 if (INTEL_GEN(m->i915) >= 8) {
 547                         int i;
 548                         for (i = 0; i < 4; i++)
 549                                 err_printf(m, "  PDP%d: 0x%016llx\n",
 550                                            i, ee->vm_info.pdp[i]);
 551                 } else {
 552                         err_printf(m, "  PP_DIR_BASE: 0x%08x\n",
 553                                    ee->vm_info.pp_dir_base);
 554                 }
 555         }
 556         err_printf(m, "  engine reset count: %u\n", ee->reset_count);
 557
 558         for (n = 0; n < ee->num_ports; n++) {
 559                 err_printf(m, "  ELSP[%d]:", n);
 560                 error_print_request(m, " ", &ee->execlist[n]);
 561         }
 562
 563         error_print_context(m, "  Active context: ", &ee->context);
 564 }
 565
 566 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
 567 {
 568         va_list args;
 569
 570         va_start(args, f);
 571         i915_error_vprintf(e, f, args);
 572         va_end(args);
 573 }
 574
 575 static void print_error_vma(struct drm_i915_error_state_buf *m,
 576                             const struct intel_engine_cs *engine,
 577                             const struct i915_vma_coredump *vma)
 578 {
 579         char out[ASCII85_BUFSZ];
 580         int page;
 581
 582         if (!vma)
 583                 return;
 584
 585         err_printf(m, "%s --- %s = 0x%08x %08x\n",
 586                    engine ? engine->name : "global", vma->name,
 587                    upper_32_bits(vma->gtt_offset),
 588                    lower_32_bits(vma->gtt_offset));
 589
 590         if (vma->gtt_page_sizes > I915_GTT_PAGE_SIZE_4K)
 591                 err_printf(m, "gtt_page_sizes = 0x%08x\n", vma->gtt_page_sizes);
 592
 593         err_compression_marker(m);
 594         for (page = 0; page < vma->page_count; page++) {
 595                 int i, len;
 596
 597                 len = PAGE_SIZE;
 598                 if (page == vma->page_count - 1)
 599                         len -= vma->unused;
 600                 len = ascii85_encode_len(len);
 601
 602                 for (i = 0; i < len; i++)
 603                         err_puts(m, ascii85_encode(vma->pages[page][i], out));
 604         }
 605         err_puts(m, "\n");
 606 }
 607
 608 static void err_print_capabilities(struct drm_i915_error_state_buf *m,
 609                                    const struct intel_device_info *info,
 610                                    const struct intel_runtime_info *runtime,
 611                                    const struct intel_driver_caps *caps)
 612 {
 613         struct drm_printer p = i915_error_printer(m);
 614
 615         intel_device_info_print_static(info, &p);
 616         intel_device_info_print_runtime(runtime, &p);
 617         intel_device_info_print_topology(&runtime->sseu, &p);
 618         intel_driver_caps_print(caps, &p);
 619 }
 620
 621 static void err_print_params(struct drm_i915_error_state_buf *m,
 622                              const struct i915_params *params)
 623 {
 624         struct drm_printer p = i915_error_printer(m);
 625
 626         i915_params_dump(params, &p);
 627 }
 628
 629 static void err_print_pciid(struct drm_i915_error_state_buf *m,
 630                             struct drm_i915_private *i915)
 631 {
 632         struct pci_dev *pdev = i915->drm.pdev;
 633
 634         err_printf(m, "PCI ID: 0x%04x\n", pdev->device);
 635         err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision);
 636         err_printf(m, "PCI Subsystem: %04x:%04x\n",
 637                    pdev->subsystem_vendor,
 638                    pdev->subsystem_device);
 639 }
 640
 641 static void err_print_uc(struct drm_i915_error_state_buf *m,
 642                          const struct intel_uc_coredump *error_uc)
 643 {
 644         struct drm_printer p = i915_error_printer(m);
 645
 646         intel_uc_fw_dump(&error_uc->guc_fw, &p);
 647         intel_uc_fw_dump(&error_uc->huc_fw, &p);
 648         print_error_vma(m, NULL, error_uc->guc_log);
 649 }
 650
 651 static void err_free_sgl(struct scatterlist *sgl)
 652 {
 653         while (sgl) {
 654                 struct scatterlist *sg;
 655
 656                 for (sg = sgl; !sg_is_chain(sg); sg++) {
 657                         kfree(sg_virt(sg));
 658                         if (sg_is_last(sg))
 659                                 break;
 660                 }
 661
 662                 sg = sg_is_last(sg) ? NULL : sg_chain_ptr(sg);
 663                 free_page((unsigned long)sgl);
 664                 sgl = sg;
 665         }
 666 }
 667
 668 static void err_print_gt(struct drm_i915_error_state_buf *m,
 669                          struct intel_gt_coredump *gt)
 670 {
 671         const struct intel_engine_coredump *ee;
 672         int i;
 673
 674         err_printf(m, "GT awake: %s\n", yesno(gt->awake));
 675         err_printf(m, "EIR: 0x%08x\n", gt->eir);
 676         err_printf(m, "IER: 0x%08x\n", gt->ier);
 677         for (i = 0; i < gt->ngtier; i++)
 678                 err_printf(m, "GTIER[%d]: 0x%08x\n", i, gt->gtier[i]);
 679         err_printf(m, "PGTBL_ER: 0x%08x\n", gt->pgtbl_er);
 680         err_printf(m, "FORCEWAKE: 0x%08x\n", gt->forcewake);
 681         err_printf(m, "DERRMR: 0x%08x\n", gt->derrmr);
 682
 683         for (i = 0; i < gt->nfence; i++)
 684                 err_printf(m, "  fence[%d] = %08llx\n", i, gt->fence[i]);
 685
 686         if (IS_GEN_RANGE(m->i915, 6, 11)) {
 687                 err_printf(m, "ERROR: 0x%08x\n", gt->error);
 688                 err_printf(m, "DONE_REG: 0x%08x\n", gt->done_reg);
 689         }
 690
 691         if (INTEL_GEN(m->i915) >= 8)
 692                 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
 693                            gt->fault_data1, gt->fault_data0);
 694
 695         if (IS_GEN(m->i915, 7))
 696                 err_printf(m, "ERR_INT: 0x%08x\n", gt->err_int);
 697
 698         if (IS_GEN_RANGE(m->i915, 8, 11))
 699                 err_printf(m, "GTT_CACHE_EN: 0x%08x\n", gt->gtt_cache);
 700
 701         if (IS_GEN(m->i915, 12))
 702                 err_printf(m, "AUX_ERR_DBG: 0x%08x\n", gt->aux_err);
 703
 704         if (INTEL_GEN(m->i915) >= 12) {
 705                 int i;
 706
 707                 for (i = 0; i < GEN12_SFC_DONE_MAX; i++)
 708                         err_printf(m, "  SFC_DONE[%d]: 0x%08x\n", i,
 709                                    gt->sfc_done[i]);
 710
 711                 err_printf(m, "  GAM_DONE: 0x%08x\n", gt->gam_done);
 712         }
 713
 714         for (ee = gt->engine; ee; ee = ee->next) {
 715                 const struct i915_vma_coredump *vma;
 716
 717                 error_print_engine(m, ee);
 718                 for (vma = ee->vma; vma; vma = vma->next)
 719                         print_error_vma(m, ee->engine, vma);
 720         }
 721
 722         if (gt->uc)
 723                 err_print_uc(m, gt->uc);
 724 }
 725
 726 static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
 727                                struct i915_gpu_coredump *error)
 728 {
 729         const struct intel_engine_coredump *ee;
 730         struct timespec64 ts;
 731
 732         if (*error->error_msg)
 733                 err_printf(m, "%s\n", error->error_msg);
 734         err_printf(m, "Kernel: %s %s\n",
 735                    init_utsname()->release,
 736                    init_utsname()->machine);
 737         err_printf(m, "Driver: %s\n", DRIVER_DATE);
 738         ts = ktime_to_timespec64(error->time);
 739         err_printf(m, "Time: %lld s %ld us\n",
 740                    (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
 741         ts = ktime_to_timespec64(error->boottime);
 742         err_printf(m, "Boottime: %lld s %ld us\n",
 743                    (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
 744         ts = ktime_to_timespec64(error->uptime);
 745         err_printf(m, "Uptime: %lld s %ld us\n",
 746                    (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
 747         err_printf(m, "Capture: %lu jiffies; %d ms ago\n",
 748                    error->capture, jiffies_to_msecs(jiffies - error->capture));
 749
 750         for (ee = error->gt ? error->gt->engine : NULL; ee; ee = ee->next)
 751                 err_printf(m, "Active process (on ring %s): %s [%d]\n",
 752                            ee->engine->name,
 753                            ee->context.comm,
 754                            ee->context.pid);
 755
 756         err_printf(m, "Reset count: %u\n", error->reset_count);
 757         err_printf(m, "Suspend count: %u\n", error->suspend_count);
 758         err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform));
 759         err_printf(m, "Subplatform: 0x%x\n",
 760                    intel_subplatform(&error->runtime_info,
 761                                      error->device_info.platform));
 762         err_print_pciid(m, m->i915);
 763
 764         err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
 765
 766         if (HAS_CSR(m->i915)) {
 767                 struct intel_csr *csr = &m->i915->csr;
 768
 769                 err_printf(m, "DMC loaded: %s\n",
 770                            yesno(csr->dmc_payload != NULL));
 771                 err_printf(m, "DMC fw version: %d.%d\n",
 772                            CSR_VERSION_MAJOR(csr->version),
 773                            CSR_VERSION_MINOR(csr->version));
 774         }
 775
 776         err_printf(m, "RPM wakelock: %s\n", yesno(error->wakelock));
 777         err_printf(m, "PM suspended: %s\n", yesno(error->suspended));
 778
 779         if (error->gt)
 780                 err_print_gt(m, error->gt);
 781
 782         if (error->overlay)
 783                 intel_overlay_print_error_state(m, error->overlay);
 784
 785         if (error->display)
 786                 intel_display_print_error_state(m, error->display);
 787
 788         err_print_capabilities(m, &error->device_info, &error->runtime_info,
 789                                &error->driver_caps);
 790         err_print_params(m, &error->params);
 791 }
 792
 793 static int err_print_to_sgl(struct i915_gpu_coredump *error)
 794 {
 795         struct drm_i915_error_state_buf m;
 796
 797         if (IS_ERR(error))
 798                 return PTR_ERR(error);
 799
 800         if (READ_ONCE(error->sgl))
 801                 return 0;
 802
 803         memset(&m, 0, sizeof(m));
 804         m.i915 = error->i915;
 805
 806         __err_print_to_sgl(&m, error);
 807
 808         if (m.buf) {
 809                 __sg_set_buf(m.cur++, m.buf, m.bytes, m.iter);
 810                 m.bytes = 0;
 811                 m.buf = NULL;
 812         }
 813         if (m.cur) {
 814                 GEM_BUG_ON(m.end < m.cur);
 815                 sg_mark_end(m.cur - 1);
 816         }
 817         GEM_BUG_ON(m.sgl && !m.cur);
 818
 819         if (m.err) {
 820                 err_free_sgl(m.sgl);
 821                 return m.err;
 822         }
 823
 824         if (cmpxchg(&error->sgl, NULL, m.sgl))
 825                 err_free_sgl(m.sgl);
 826
 827         return 0;
 828 }
 829
 830 ssize_t i915_gpu_coredump_copy_to_buffer(struct i915_gpu_coredump *error,
 831                                          char *buf, loff_t off, size_t rem)
 832 {
 833         struct scatterlist *sg;
 834         size_t count;
 835         loff_t pos;
 836         int err;
 837
 838         if (!error || !rem)
 839                 return 0;
 840
 841         err = err_print_to_sgl(error);
 842         if (err)
 843                 return err;
 844
 845         sg = READ_ONCE(error->fit);
 846         if (!sg || off < sg->dma_address)
 847                 sg = error->sgl;
 848         if (!sg)
 849                 return 0;
 850
 851         pos = sg->dma_address;
 852         count = 0;
 853         do {
 854                 size_t len, start;
 855
 856                 if (sg_is_chain(sg)) {
 857                         sg = sg_chain_ptr(sg);
 858                         GEM_BUG_ON(sg_is_chain(sg));
 859                 }
 860
 861                 len = sg->length;
 862                 if (pos + len <= off) {
 863                         pos += len;
 864                         continue;
 865                 }
 866
 867                 start = sg->offset;
 868                 if (pos < off) {
 869                         GEM_BUG_ON(off - pos > len);
 870                         len -= off - pos;
 871                         start += off - pos;
 872                         pos = off;
 873                 }
 874
 875                 len = min(len, rem);
 876                 GEM_BUG_ON(!len || len > sg->length);
 877
 878                 memcpy(buf, page_address(sg_page(sg)) + start, len);
 879
 880                 count += len;
 881                 pos += len;
 882
 883                 buf += len;
 884                 rem -= len;
 885                 if (!rem) {
 886                         WRITE_ONCE(error->fit, sg);
 887                         break;
 888                 }
 889         } while (!sg_is_last(sg++));
 890
 891         return count;
 892 }
 893
 894 static void i915_vma_coredump_free(struct i915_vma_coredump *vma)
 895 {
 896         while (vma) {
 897                 struct i915_vma_coredump *next = vma->next;
 898                 int page;
 899
 900                 for (page = 0; page < vma->page_count; page++)
 901                         free_page((unsigned long)vma->pages[page]);
 902
 903                 kfree(vma);
 904                 vma = next;
 905         }
 906 }
 907
 908 static void cleanup_params(struct i915_gpu_coredump *error)
 909 {
 910         i915_params_free(&error->params);
 911 }
 912
 913 static void cleanup_uc(struct intel_uc_coredump *uc)
 914 {
 915         kfree(uc->guc_fw.path);
 916         kfree(uc->huc_fw.path);
 917         i915_vma_coredump_free(uc->guc_log);
 918
 919         kfree(uc);
 920 }
 921
 922 static void cleanup_gt(struct intel_gt_coredump *gt)
 923 {
 924         while (gt->engine) {
 925                 struct intel_engine_coredump *ee = gt->engine;
 926
 927                 gt->engine = ee->next;
 928
 929                 i915_vma_coredump_free(ee->vma);
 930                 kfree(ee);
 931         }
 932
 933         if (gt->uc)
 934                 cleanup_uc(gt->uc);
 935
 936         kfree(gt);
 937 }
 938
 939 void __i915_gpu_coredump_free(struct kref *error_ref)
 940 {
 941         struct i915_gpu_coredump *error =
 942                 container_of(error_ref, typeof(*error), ref);
 943
 944         while (error->gt) {
 945                 struct intel_gt_coredump *gt = error->gt;
 946
 947                 error->gt = gt->next;
 948                 cleanup_gt(gt);
 949         }
 950
 951         kfree(error->overlay);
 952         kfree(error->display);
 953
 954         cleanup_params(error);
 955
 956         err_free_sgl(error->sgl);
 957         kfree(error);
 958 }
 959
 960 static struct i915_vma_coredump *
 961 i915_vma_coredump_create(const struct intel_gt *gt,
 962                          const struct i915_vma *vma,
 963                          const char *name,
 964                          struct i915_vma_compress *compress)
 965 {
 966         struct i915_ggtt *ggtt = gt->ggtt;
 967         const u64 slot = ggtt->error_capture.start;
 968         struct i915_vma_coredump *dst;
 969         unsigned long num_pages;
 970         struct sgt_iter iter;
 971         int ret;
 972
 973         might_sleep();
 974
 975         if (!vma || !vma->pages || !compress)
 976                 return NULL;
 977
 978         num_pages = min_t(u64, vma->size, vma->obj->base.size) >> PAGE_SHIFT;
 979         num_pages = DIV_ROUND_UP(10 * num_pages, 8); /* worstcase zlib growth */
 980         dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), ALLOW_FAIL);
 981         if (!dst)
 982                 return NULL;
 983
 984         if (!compress_start(compress)) {
 985                 kfree(dst);
 986                 return NULL;
 987         }
 988
 989         strcpy(dst->name, name);
 990         dst->next = NULL;
 991
 992         dst->gtt_offset = vma->node.start;
 993         dst->gtt_size = vma->node.size;
 994         dst->gtt_page_sizes = vma->page_sizes.gtt;
 995         dst->num_pages = num_pages;
 996         dst->page_count = 0;
 997         dst->unused = 0;
 998
 999         ret = -EINVAL;
1000         if (drm_mm_node_allocated(&ggtt->error_capture)) {
1001                 void __iomem *s;
1002                 dma_addr_t dma;
1003
1004                 for_each_sgt_daddr(dma, iter, vma->pages) {
1005                         ggtt->vm.insert_page(&ggtt->vm, dma, slot,
1006                                              I915_CACHE_NONE, 0);
1007                         mb();
1008
1009                         s = io_mapping_map_wc(&ggtt->iomap, slot, PAGE_SIZE);
1010                         ret = compress_page(compress,
1011                                             (void  __force *)s, dst,
1012                                             true);
1013                         io_mapping_unmap(s);
1014                         if (ret)
1015                                 break;
1016                 }
1017         } else if (i915_gem_object_is_lmem(vma->obj)) {
1018                 struct intel_memory_region *mem = vma->obj->mm.region;
1019                 dma_addr_t dma;
1020
1021                 for_each_sgt_daddr(dma, iter, vma->pages) {
1022                         void __iomem *s;
1023
1024                         s = io_mapping_map_wc(&mem->iomap, dma, PAGE_SIZE);
1025                         ret = compress_page(compress,
1026                                             (void __force *)s, dst,
1027                                             true);
1028                         io_mapping_unmap(s);
1029                         if (ret)
1030                                 break;
1031                 }
1032         } else {
1033                 struct page *page;
1034
1035                 for_each_sgt_page(page, iter, vma->pages) {
1036                         void *s;
1037
1038                         drm_clflush_pages(&page, 1);
1039
1040                         s = kmap(page);
1041                         ret = compress_page(compress, s, dst, false);
1042                         kunmap(page);
1043
1044                         drm_clflush_pages(&page, 1);
1045
1046                         if (ret)
1047                                 break;
1048                 }
1049         }
1050
1051         if (ret || compress_flush(compress, dst)) {
1052                 while (dst->page_count--)
1053                         pool_free(&compress->pool, dst->pages[dst->page_count]);
1054                 kfree(dst);
1055                 dst = NULL;
1056         }
1057         compress_finish(compress);
1058
1059         return dst;
1060 }
1061
1062 static void gt_record_fences(struct intel_gt_coredump *gt)
1063 {
1064         struct i915_ggtt *ggtt = gt->_gt->ggtt;
1065         struct intel_uncore *uncore = gt->_gt->uncore;
1066         int i;
1067
1068         if (INTEL_GEN(uncore->i915) >= 6) {
1069                 for (i = 0; i < ggtt->num_fences; i++)
1070                         gt->fence[i] =
1071                                 intel_uncore_read64(uncore,
1072                                                     FENCE_REG_GEN6_LO(i));
1073         } else if (INTEL_GEN(uncore->i915) >= 4) {
1074                 for (i = 0; i < ggtt->num_fences; i++)
1075                         gt->fence[i] =
1076                                 intel_uncore_read64(uncore,
1077                                                     FENCE_REG_965_LO(i));
1078         } else {
1079                 for (i = 0; i < ggtt->num_fences; i++)
1080                         gt->fence[i] =
1081                                 intel_uncore_read(uncore, FENCE_REG(i));
1082         }
1083         gt->nfence = i;
1084 }
1085
1086 static void engine_record_registers(struct intel_engine_coredump *ee)
1087 {
1088         const struct intel_engine_cs *engine = ee->engine;
1089         struct drm_i915_private *i915 = engine->i915;
1090
1091         if (INTEL_GEN(i915) >= 6) {
1092                 ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL);
1093
1094                 if (INTEL_GEN(i915) >= 12)
1095                         ee->fault_reg = intel_uncore_read(engine->uncore,
1096                                                           GEN12_RING_FAULT_REG);
1097                 else if (INTEL_GEN(i915) >= 8)
1098                         ee->fault_reg = intel_uncore_read(engine->uncore,
1099                                                           GEN8_RING_FAULT_REG);
1100                 else
1101                         ee->fault_reg = GEN6_RING_FAULT_REG_READ(engine);
1102         }
1103
1104         if (INTEL_GEN(i915) >= 4) {
1105                 ee->faddr = ENGINE_READ(engine, RING_DMA_FADD);
1106                 ee->ipeir = ENGINE_READ(engine, RING_IPEIR);
1107                 ee->ipehr = ENGINE_READ(engine, RING_IPEHR);
1108                 ee->instps = ENGINE_READ(engine, RING_INSTPS);
1109                 ee->bbaddr = ENGINE_READ(engine, RING_BBADDR);
1110                 ee->ccid = ENGINE_READ(engine, CCID);
1111                 if (INTEL_GEN(i915) >= 8) {
1112                         ee->faddr |= (u64)ENGINE_READ(engine, RING_DMA_FADD_UDW) << 32;
1113                         ee->bbaddr |= (u64)ENGINE_READ(engine, RING_BBADDR_UDW) << 32;
1114                 }
1115                 ee->bbstate = ENGINE_READ(engine, RING_BBSTATE);
1116         } else {
1117                 ee->faddr = ENGINE_READ(engine, DMA_FADD_I8XX);
1118                 ee->ipeir = ENGINE_READ(engine, IPEIR);
1119                 ee->ipehr = ENGINE_READ(engine, IPEHR);
1120         }
1121
1122         intel_engine_get_instdone(engine, &ee->instdone);
1123
1124         ee->instpm = ENGINE_READ(engine, RING_INSTPM);
1125         ee->acthd = intel_engine_get_active_head(engine);
1126         ee->start = ENGINE_READ(engine, RING_START);
1127         ee->head = ENGINE_READ(engine, RING_HEAD);
1128         ee->tail = ENGINE_READ(engine, RING_TAIL);
1129         ee->ctl = ENGINE_READ(engine, RING_CTL);
1130         if (INTEL_GEN(i915) > 2)
1131                 ee->mode = ENGINE_READ(engine, RING_MI_MODE);
1132
1133         if (!HWS_NEEDS_PHYSICAL(i915)) {
1134                 i915_reg_t mmio;
1135
1136                 if (IS_GEN(i915, 7)) {
1137                         switch (engine->id) {
1138                         default:
1139                                 MISSING_CASE(engine->id);
1140                                 /* fall through */
1141                         case RCS0:
1142                                 mmio = RENDER_HWS_PGA_GEN7;
1143                                 break;
1144                         case BCS0:
1145                                 mmio = BLT_HWS_PGA_GEN7;
1146                                 break;
1147                         case VCS0:
1148                                 mmio = BSD_HWS_PGA_GEN7;
1149                                 break;
1150                         case VECS0:
1151                                 mmio = VEBOX_HWS_PGA_GEN7;
1152                                 break;
1153                         }
1154                 } else if (IS_GEN(engine->i915, 6)) {
1155                         mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
1156                 } else {
1157                         /* XXX: gen8 returns to sanity */
1158                         mmio = RING_HWS_PGA(engine->mmio_base);
1159                 }
1160
1161                 ee->hws = intel_uncore_read(engine->uncore, mmio);
1162         }
1163
1164         ee->reset_count = i915_reset_engine_count(&i915->gpu_error, engine);
1165
1166         if (HAS_PPGTT(i915)) {
1167                 int i;
1168
1169                 ee->vm_info.gfx_mode = ENGINE_READ(engine, RING_MODE_GEN7);
1170
1171                 if (IS_GEN(i915, 6)) {
1172                         ee->vm_info.pp_dir_base =
1173                                 ENGINE_READ(engine, RING_PP_DIR_BASE_READ);
1174                 } else if (IS_GEN(i915, 7)) {
1175                         ee->vm_info.pp_dir_base =
1176                                 ENGINE_READ(engine, RING_PP_DIR_BASE);
1177                 } else if (INTEL_GEN(i915) >= 8) {
1178                         u32 base = engine->mmio_base;
1179
1180                         for (i = 0; i < 4; i++) {
1181                                 ee->vm_info.pdp[i] =
1182                                         intel_uncore_read(engine->uncore,
1183                                                           GEN8_RING_PDP_UDW(base, i));
1184                                 ee->vm_info.pdp[i] <<= 32;
1185                                 ee->vm_info.pdp[i] |=
1186                                         intel_uncore_read(engine->uncore,
1187                                                           GEN8_RING_PDP_LDW(base, i));
1188                         }
1189                 }
1190         }
1191 }
1192
1193 static void record_request(const struct i915_request *request,
1194                            struct i915_request_coredump *erq)
1195 {
1196         const struct i915_gem_context *ctx;
1197
1198         erq->flags = request->fence.flags;
1199         erq->context = request->fence.context;
1200         erq->seqno = request->fence.seqno;
1201         erq->sched_attr = request->sched.attr;
1202         erq->start = i915_ggtt_offset(request->ring->vma);
1203         erq->head = request->head;
1204         erq->tail = request->tail;
1205
1206         erq->pid = 0;
1207         rcu_read_lock();
1208         ctx = rcu_dereference(request->context->gem_context);
1209         if (ctx)
1210                 erq->pid = pid_nr(ctx->pid);
1211         rcu_read_unlock();
1212 }
1213
1214 static void engine_record_execlists(struct intel_engine_coredump *ee)
1215 {
1216         const struct intel_engine_execlists * const el = &ee->engine->execlists;
1217         struct i915_request * const *port = el->active;
1218         unsigned int n = 0;
1219
1220         while (*port)
1221                 record_request(*port++, &ee->execlist[n++]);
1222
1223         ee->num_ports = n;
1224 }
1225
1226 static bool record_context(struct i915_gem_context_coredump *e,
1227                            const struct i915_request *rq)
1228 {
1229         struct i915_gem_context *ctx;
1230         struct task_struct *task;
1231         bool capture;
1232
1233         rcu_read_lock();
1234         ctx = rcu_dereference(rq->context->gem_context);
1235         if (ctx && !kref_get_unless_zero(&ctx->ref))
1236                 ctx = NULL;
1237         rcu_read_unlock();
1238         if (!ctx)
1239                 return false;
1240
1241         rcu_read_lock();
1242         task = pid_task(ctx->pid, PIDTYPE_PID);
1243         if (task) {
1244                 strcpy(e->comm, task->comm);
1245                 e->pid = task->pid;
1246         }
1247         rcu_read_unlock();
1248
1249         e->sched_attr = ctx->sched;
1250         e->guilty = atomic_read(&ctx->guilty_count);
1251         e->active = atomic_read(&ctx->active_count);
1252
1253         capture = i915_gem_context_no_error_capture(ctx);
1254
1255         i915_gem_context_put(ctx);
1256         return capture;
1257 }
1258
1259 struct intel_engine_capture_vma {
1260         struct intel_engine_capture_vma *next;
1261         struct i915_vma *vma;
1262         char name[16];
1263 };
1264
1265 static struct intel_engine_capture_vma *
1266 capture_vma(struct intel_engine_capture_vma *next,
1267             struct i915_vma *vma,
1268             const char *name,
1269             gfp_t gfp)
1270 {
1271         struct intel_engine_capture_vma *c;
1272
1273         if (!vma)
1274                 return next;
1275
1276         c = kmalloc(sizeof(*c), gfp);
1277         if (!c)
1278                 return next;
1279
1280         if (!i915_active_acquire_if_busy(&vma->active)) {
1281                 kfree(c);
1282                 return next;
1283         }
1284
1285         strcpy(c->name, name);
1286         c->vma = i915_vma_get(vma);
1287
1288         c->next = next;
1289         return c;
1290 }
1291
1292 static struct intel_engine_capture_vma *
1293 capture_user(struct intel_engine_capture_vma *capture,
1294              const struct i915_request *rq,
1295              gfp_t gfp)
1296 {
1297         struct i915_capture_list *c;
1298
1299         for (c = rq->capture_list; c; c = c->next)
1300                 capture = capture_vma(capture, c->vma, "user", gfp);
1301
1302         return capture;
1303 }
1304
1305 static struct i915_vma_coredump *
1306 capture_object(const struct intel_gt *gt,
1307                struct drm_i915_gem_object *obj,
1308                const char *name,
1309                struct i915_vma_compress *compress)
1310 {
1311         if (obj && i915_gem_object_has_pages(obj)) {
1312                 struct i915_vma fake = {
1313                         .node = { .start = U64_MAX, .size = obj->base.size },
1314                         .size = obj->base.size,
1315                         .pages = obj->mm.pages,
1316                         .obj = obj,
1317                 };
1318
1319                 return i915_vma_coredump_create(gt, &fake, name, compress);
1320         } else {
1321                 return NULL;
1322         }
1323 }
1324
1325 static void add_vma(struct intel_engine_coredump *ee,
1326                     struct i915_vma_coredump *vma)
1327 {
1328         if (vma) {
1329                 vma->next = ee->vma;
1330                 ee->vma = vma;
1331         }
1332 }
1333
1334 struct intel_engine_coredump *
1335 intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp)
1336 {
1337         struct intel_engine_coredump *ee;
1338
1339         ee = kzalloc(sizeof(*ee), gfp);
1340         if (!ee)
1341                 return NULL;
1342
1343         ee->engine = engine;
1344
1345         engine_record_registers(ee);
1346         engine_record_execlists(ee);
1347
1348         return ee;
1349 }
1350
1351 struct intel_engine_capture_vma *
1352 intel_engine_coredump_add_request(struct intel_engine_coredump *ee,
1353                                   struct i915_request *rq,
1354                                   gfp_t gfp)
1355 {
1356         struct intel_engine_capture_vma *vma = NULL;
1357
1358         ee->simulated |= record_context(&ee->context, rq);
1359         if (ee->simulated)
1360                 return NULL;
1361
1362         /*
1363          * We need to copy these to an anonymous buffer
1364          * as the simplest method to avoid being overwritten
1365          * by userspace.
1366          */
1367         vma = capture_vma(vma, rq->batch, "batch", gfp);
1368         vma = capture_user(vma, rq, gfp);
1369         vma = capture_vma(vma, rq->ring->vma, "ring", gfp);
1370         vma = capture_vma(vma, rq->context->state, "HW context", gfp);
1371
1372         ee->rq_head = rq->head;
1373         ee->rq_post = rq->postfix;
1374         ee->rq_tail = rq->tail;
1375
1376         return vma;
1377 }
1378
1379 void
1380 intel_engine_coredump_add_vma(struct intel_engine_coredump *ee,
1381                               struct intel_engine_capture_vma *capture,
1382                               struct i915_vma_compress *compress)
1383 {
1384         const struct intel_engine_cs *engine = ee->engine;
1385
1386         while (capture) {
1387                 struct intel_engine_capture_vma *this = capture;
1388                 struct i915_vma *vma = this->vma;
1389
1390                 add_vma(ee,
1391                         i915_vma_coredump_create(engine->gt,
1392                                                  vma, this->name,
1393                                                  compress));
1394
1395                 i915_active_release(&vma->active);
1396                 i915_vma_put(vma);
1397
1398                 capture = this->next;
1399                 kfree(this);
1400         }
1401
1402         add_vma(ee,
1403                 i915_vma_coredump_create(engine->gt,
1404                                          engine->status_page.vma,
1405                                          "HW Status",
1406                                          compress));
1407
1408         add_vma(ee,
1409                 i915_vma_coredump_create(engine->gt,
1410                                          engine->wa_ctx.vma,
1411                                          "WA context",
1412                                          compress));
1413
1414         add_vma(ee,
1415                 capture_object(engine->gt,
1416                                engine->default_state,
1417                                "NULL context",
1418                                compress));
1419 }
1420
1421 static struct intel_engine_coredump *
1422 capture_engine(struct intel_engine_cs *engine,
1423                struct i915_vma_compress *compress)
1424 {
1425         struct intel_engine_capture_vma *capture = NULL;
1426         struct intel_engine_coredump *ee;
1427         struct i915_request *rq;
1428         unsigned long flags;
1429
1430         ee = intel_engine_coredump_alloc(engine, GFP_KERNEL);
1431         if (!ee)
1432                 return NULL;
1433
1434         spin_lock_irqsave(&engine->active.lock, flags);
1435         rq = intel_engine_find_active_request(engine);
1436         if (rq)
1437                 capture = intel_engine_coredump_add_request(ee, rq,
1438                                                             ATOMIC_MAYFAIL);
1439         spin_unlock_irqrestore(&engine->active.lock, flags);
1440         if (!capture) {
1441                 kfree(ee);
1442                 return NULL;
1443         }
1444
1445         intel_engine_coredump_add_vma(ee, capture, compress);
1446
1447         return ee;
1448 }
1449
1450 static void
1451 gt_record_engines(struct intel_gt_coredump *gt,
1452                   struct i915_vma_compress *compress)
1453 {
1454         struct intel_engine_cs *engine;
1455         enum intel_engine_id id;
1456
1457         for_each_engine(engine, gt->_gt, id) {
1458                 struct intel_engine_coredump *ee;
1459
1460                 /* Refill our page pool before entering atomic section */
1461                 pool_refill(&compress->pool, ALLOW_FAIL);
1462
1463                 ee = capture_engine(engine, compress);
1464                 if (!ee)
1465                         continue;
1466
1467                 gt->simulated |= ee->simulated;
1468                 if (ee->simulated) {
1469                         kfree(ee);
1470                         continue;
1471                 }
1472
1473                 ee->next = gt->engine;
1474                 gt->engine = ee;
1475         }
1476 }
1477
1478 static struct intel_uc_coredump *
1479 gt_record_uc(struct intel_gt_coredump *gt,
1480              struct i915_vma_compress *compress)
1481 {
1482         const struct intel_uc *uc = &gt->_gt->uc;
1483         struct intel_uc_coredump *error_uc;
1484
1485         error_uc = kzalloc(sizeof(*error_uc), ALLOW_FAIL);
1486         if (!error_uc)
1487                 return NULL;
1488
1489         memcpy(&error_uc->guc_fw, &uc->guc.fw, sizeof(uc->guc.fw));
1490         memcpy(&error_uc->huc_fw, &uc->huc.fw, sizeof(uc->huc.fw));
1491
1492         /* Non-default firmware paths will be specified by the modparam.
1493          * As modparams are generally accesible from the userspace make
1494          * explicit copies of the firmware paths.
1495          */
1496         error_uc->guc_fw.path = kstrdup(uc->guc.fw.path, ALLOW_FAIL);
1497         error_uc->huc_fw.path = kstrdup(uc->huc.fw.path, ALLOW_FAIL);
1498         error_uc->guc_log =
1499                 i915_vma_coredump_create(gt->_gt,
1500                                          uc->guc.log.vma, "GuC log buffer",
1501                                          compress);
1502
1503         return error_uc;
1504 }
1505
1506 static void gt_capture_prepare(struct intel_gt_coredump *gt)
1507 {
1508         struct i915_ggtt *ggtt = gt->_gt->ggtt;
1509
1510         mutex_lock(&ggtt->error_mutex);
1511 }
1512
1513 static void gt_capture_finish(struct intel_gt_coredump *gt)
1514 {
1515         struct i915_ggtt *ggtt = gt->_gt->ggtt;
1516
1517         if (drm_mm_node_allocated(&ggtt->error_capture))
1518                 ggtt->vm.clear_range(&ggtt->vm,
1519                                      ggtt->error_capture.start,
1520                                      PAGE_SIZE);
1521
1522         mutex_unlock(&ggtt->error_mutex);
1523 }
1524
1525 /* Capture all registers which don't fit into another category. */
1526 static void gt_record_regs(struct intel_gt_coredump *gt)
1527 {
1528         struct intel_uncore *uncore = gt->_gt->uncore;
1529         struct drm_i915_private *i915 = uncore->i915;
1530         int i;
1531
1532         /*
1533          * General organization
1534          * 1. Registers specific to a single generation
1535          * 2. Registers which belong to multiple generations
1536          * 3. Feature specific registers.
1537          * 4. Everything else
1538          * Please try to follow the order.
1539          */
1540
1541         /* 1: Registers specific to a single generation */
1542         if (IS_VALLEYVIEW(i915)) {
1543                 gt->gtier[0] = intel_uncore_read(uncore, GTIER);
1544                 gt->ier = intel_uncore_read(uncore, VLV_IER);
1545                 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_VLV);
1546         }
1547
1548         if (IS_GEN(i915, 7))
1549                 gt->err_int = intel_uncore_read(uncore, GEN7_ERR_INT);
1550
1551         if (INTEL_GEN(i915) >= 12) {
1552                 gt->fault_data0 = intel_uncore_read(uncore,
1553                                                     GEN12_FAULT_TLB_DATA0);
1554                 gt->fault_data1 = intel_uncore_read(uncore,
1555                                                     GEN12_FAULT_TLB_DATA1);
1556         } else if (INTEL_GEN(i915) >= 8) {
1557                 gt->fault_data0 = intel_uncore_read(uncore,
1558                                                     GEN8_FAULT_TLB_DATA0);
1559                 gt->fault_data1 = intel_uncore_read(uncore,
1560                                                     GEN8_FAULT_TLB_DATA1);
1561         }
1562
1563         if (IS_GEN(i915, 6)) {
1564                 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE);
1565                 gt->gab_ctl = intel_uncore_read(uncore, GAB_CTL);
1566                 gt->gfx_mode = intel_uncore_read(uncore, GFX_MODE);
1567         }
1568
1569         /* 2: Registers which belong to multiple generations */
1570         if (INTEL_GEN(i915) >= 7)
1571                 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_MT);
1572
1573         if (INTEL_GEN(i915) >= 6) {
1574                 gt->derrmr = intel_uncore_read(uncore, DERRMR);
1575                 if (INTEL_GEN(i915) < 12) {
1576                         gt->error = intel_uncore_read(uncore, ERROR_GEN6);
1577                         gt->done_reg = intel_uncore_read(uncore, DONE_REG);
1578                 }
1579         }
1580
1581         /* 3: Feature specific registers */
1582         if (IS_GEN_RANGE(i915, 6, 7)) {
1583                 gt->gam_ecochk = intel_uncore_read(uncore, GAM_ECOCHK);
1584                 gt->gac_eco = intel_uncore_read(uncore, GAC_ECO_BITS);
1585         }
1586
1587         if (IS_GEN_RANGE(i915, 8, 11))
1588                 gt->gtt_cache = intel_uncore_read(uncore, HSW_GTT_CACHE_EN);
1589
1590         if (IS_GEN(i915, 12))
1591                 gt->aux_err = intel_uncore_read(uncore, GEN12_AUX_ERR_DBG);
1592
1593         if (INTEL_GEN(i915) >= 12) {
1594                 for (i = 0; i < GEN12_SFC_DONE_MAX; i++) {
1595                         gt->sfc_done[i] =
1596                                 intel_uncore_read(uncore, GEN12_SFC_DONE(i));
1597                 }
1598
1599                 gt->gam_done = intel_uncore_read(uncore, GEN12_GAM_DONE);
1600         }
1601
1602         /* 4: Everything else */
1603         if (INTEL_GEN(i915) >= 11) {
1604                 gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER);
1605                 gt->gtier[0] =
1606                         intel_uncore_read(uncore,
1607                                           GEN11_RENDER_COPY_INTR_ENABLE);
1608                 gt->gtier[1] =
1609                         intel_uncore_read(uncore, GEN11_VCS_VECS_INTR_ENABLE);
1610                 gt->gtier[2] =
1611                         intel_uncore_read(uncore, GEN11_GUC_SG_INTR_ENABLE);
1612                 gt->gtier[3] =
1613                         intel_uncore_read(uncore,
1614                                           GEN11_GPM_WGBOXPERF_INTR_ENABLE);
1615                 gt->gtier[4] =
1616                         intel_uncore_read(uncore,
1617                                           GEN11_CRYPTO_RSVD_INTR_ENABLE);
1618                 gt->gtier[5] =
1619                         intel_uncore_read(uncore,
1620                                           GEN11_GUNIT_CSME_INTR_ENABLE);
1621                 gt->ngtier = 6;
1622         } else if (INTEL_GEN(i915) >= 8) {
1623                 gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER);
1624                 for (i = 0; i < 4; i++)
1625                         gt->gtier[i] =
1626                                 intel_uncore_read(uncore, GEN8_GT_IER(i));
1627                 gt->ngtier = 4;
1628         } else if (HAS_PCH_SPLIT(i915)) {
1629                 gt->ier = intel_uncore_read(uncore, DEIER);
1630                 gt->gtier[0] = intel_uncore_read(uncore, GTIER);
1631                 gt->ngtier = 1;
1632         } else if (IS_GEN(i915, 2)) {
1633                 gt->ier = intel_uncore_read16(uncore, GEN2_IER);
1634         } else if (!IS_VALLEYVIEW(i915)) {
1635                 gt->ier = intel_uncore_read(uncore, GEN2_IER);
1636         }
1637         gt->eir = intel_uncore_read(uncore, EIR);
1638         gt->pgtbl_er = intel_uncore_read(uncore, PGTBL_ER);
1639 }
1640
1641 /*
1642  * Generate a semi-unique error code. The code is not meant to have meaning, The
1643  * code's only purpose is to try to prevent false duplicated bug reports by
1644  * grossly estimating a GPU error state.
1645  *
1646  * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
1647  * the hang if we could strip the GTT offset information from it.
1648  *
1649  * It's only a small step better than a random number in its current form.
1650  */
1651 static u32 generate_ecode(const struct intel_engine_coredump *ee)
1652 {
1653         /*
1654          * IPEHR would be an ideal way to detect errors, as it's the gross
1655          * measure of "the command that hung." However, has some very common
1656          * synchronization commands which almost always appear in the case
1657          * strictly a client bug. Use instdone to differentiate those some.
1658          */
1659         return ee ? ee->ipehr ^ ee->instdone.instdone : 0;
1660 }
1661
1662 static const char *error_msg(struct i915_gpu_coredump *error)
1663 {
1664         struct intel_engine_coredump *first = NULL;
1665         struct intel_gt_coredump *gt;
1666         intel_engine_mask_t engines;
1667         int len;
1668
1669         engines = 0;
1670         for (gt = error->gt; gt; gt = gt->next) {
1671                 struct intel_engine_coredump *cs;
1672
1673                 if (gt->engine && !first)
1674                         first = gt->engine;
1675
1676                 for (cs = gt->engine; cs; cs = cs->next)
1677                         engines |= cs->engine->mask;
1678         }
1679
1680         len = scnprintf(error->error_msg, sizeof(error->error_msg),
1681                         "GPU HANG: ecode %d:%x:%08x",
1682                         INTEL_GEN(error->i915), engines,
1683                         generate_ecode(first));
1684         if (first && first->context.pid) {
1685                 /* Just show the first executing process, more is confusing */
1686                 len += scnprintf(error->error_msg + len,
1687                                  sizeof(error->error_msg) - len,
1688                                  ", in %s [%d]",
1689                                  first->context.comm, first->context.pid);
1690         }
1691
1692         return error->error_msg;
1693 }
1694
1695 static void capture_gen(struct i915_gpu_coredump *error)
1696 {
1697         struct drm_i915_private *i915 = error->i915;
1698
1699         error->wakelock = atomic_read(&i915->runtime_pm.wakeref_count);
1700         error->suspended = i915->runtime_pm.suspended;
1701
1702         error->iommu = -1;
1703 #ifdef CONFIG_INTEL_IOMMU
1704         error->iommu = intel_iommu_gfx_mapped;
1705 #endif
1706         error->reset_count = i915_reset_count(&i915->gpu_error);
1707         error->suspend_count = i915->suspend_count;
1708
1709         i915_params_copy(&error->params, &i915_modparams);
1710         memcpy(&error->device_info,
1711                INTEL_INFO(i915),
1712                sizeof(error->device_info));
1713         memcpy(&error->runtime_info,
1714                RUNTIME_INFO(i915),
1715                sizeof(error->runtime_info));
1716         error->driver_caps = i915->caps;
1717 }
1718
1719 struct i915_gpu_coredump *
1720 i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp)
1721 {
1722         struct i915_gpu_coredump *error;
1723
1724         if (!i915_modparams.error_capture)
1725                 return NULL;
1726
1727         error = kzalloc(sizeof(*error), gfp);
1728         if (!error)
1729                 return NULL;
1730
1731         kref_init(&error->ref);
1732         error->i915 = i915;
1733
1734         error->time = ktime_get_real();
1735         error->boottime = ktime_get_boottime();
1736         error->uptime = ktime_sub(ktime_get(), i915->gt.last_init_time);
1737         error->capture = jiffies;
1738
1739         capture_gen(error);
1740
1741         return error;
1742 }
1743
1744 #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x))
1745
1746 struct intel_gt_coredump *
1747 intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp)
1748 {
1749         struct intel_gt_coredump *gc;
1750
1751         gc = kzalloc(sizeof(*gc), gfp);
1752         if (!gc)
1753                 return NULL;
1754
1755         gc->_gt = gt;
1756         gc->awake = intel_gt_pm_is_awake(gt);
1757
1758         gt_record_regs(gc);
1759         gt_record_fences(gc);
1760
1761         return gc;
1762 }
1763
1764 struct i915_vma_compress *
1765 i915_vma_capture_prepare(struct intel_gt_coredump *gt)
1766 {
1767         struct i915_vma_compress *compress;
1768
1769         compress = kmalloc(sizeof(*compress), ALLOW_FAIL);
1770         if (!compress)
1771                 return NULL;
1772
1773         if (!compress_init(compress)) {
1774                 kfree(compress);
1775                 return NULL;
1776         }
1777
1778         gt_capture_prepare(gt);
1779
1780         return compress;
1781 }
1782
1783 void i915_vma_capture_finish(struct intel_gt_coredump *gt,
1784                              struct i915_vma_compress *compress)
1785 {
1786         if (!compress)
1787                 return;
1788
1789         gt_capture_finish(gt);
1790
1791         compress_fini(compress);
1792         kfree(compress);
1793 }
1794
1795 struct i915_gpu_coredump *i915_gpu_coredump(struct drm_i915_private *i915)
1796 {
1797         struct i915_gpu_coredump *error;
1798
1799         /* Check if GPU capture has been disabled */
1800         error = READ_ONCE(i915->gpu_error.first_error);
1801         if (IS_ERR(error))
1802                 return error;
1803
1804         error = i915_gpu_coredump_alloc(i915, ALLOW_FAIL);
1805         if (!error)
1806                 return ERR_PTR(-ENOMEM);
1807
1808         error->gt = intel_gt_coredump_alloc(&i915->gt, ALLOW_FAIL);
1809         if (error->gt) {
1810                 struct i915_vma_compress *compress;
1811
1812                 compress = i915_vma_capture_prepare(error->gt);
1813                 if (!compress) {
1814                         kfree(error->gt);
1815                         kfree(error);
1816                         return ERR_PTR(-ENOMEM);
1817                 }
1818
1819                 gt_record_engines(error->gt, compress);
1820
1821                 if (INTEL_INFO(i915)->has_gt_uc)
1822                         error->gt->uc = gt_record_uc(error->gt, compress);
1823
1824                 i915_vma_capture_finish(error->gt, compress);
1825
1826                 error->simulated |= error->gt->simulated;
1827         }
1828
1829         error->overlay = intel_overlay_capture_error_state(i915);
1830         error->display = intel_display_capture_error_state(i915);
1831
1832         return error;
1833 }
1834
1835 void i915_error_state_store(struct i915_gpu_coredump *error)
1836 {
1837         struct drm_i915_private *i915;
1838         static bool warned;
1839
1840         if (IS_ERR_OR_NULL(error))
1841                 return;
1842
1843         i915 = error->i915;
1844         dev_info(i915->drm.dev, "%s\n", error_msg(error));
1845
1846         if (error->simulated ||
1847             cmpxchg(&i915->gpu_error.first_error, NULL, error))
1848                 return;
1849
1850         i915_gpu_coredump_get(error);
1851
1852         if (!xchg(&warned, true) &&
1853             ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) {
1854                 pr_info("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
1855                 pr_info("Please file a _new_ bug report at https://gitlab.freedesktop.org/drm/intel/issues/new.\n");
1856                 pr_info("Please see https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs for details.\n");
1857                 pr_info("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
1858                 pr_info("The GPU crash dump is required to analyze GPU hangs, so please always attach it.\n");
1859                 pr_info("GPU crash dump saved to /sys/class/drm/card%d/error\n",
1860                         i915->drm.primary->index);
1861         }
1862 }
1863
1864 /**
1865  * i915_capture_error_state - capture an error record for later analysis
1866  * @i915: i915 device
1867  *
1868  * Should be called when an error is detected (either a hang or an error
1869  * interrupt) to capture error state from the time of the error.  Fills
1870  * out a structure which becomes available in debugfs for user level tools
1871  * to pick up.
1872  */
1873 void i915_capture_error_state(struct drm_i915_private *i915)
1874 {
1875         struct i915_gpu_coredump *error;
1876
1877         error = i915_gpu_coredump(i915);
1878         if (IS_ERR(error)) {
1879                 cmpxchg(&i915->gpu_error.first_error, NULL, error);
1880                 return;
1881         }
1882
1883         i915_error_state_store(error);
1884         i915_gpu_coredump_put(error);
1885 }
1886
1887 struct i915_gpu_coredump *
1888 i915_first_error_state(struct drm_i915_private *i915)
1889 {
1890         struct i915_gpu_coredump *error;
1891
1892         spin_lock_irq(&i915->gpu_error.lock);
1893         error = i915->gpu_error.first_error;
1894         if (!IS_ERR_OR_NULL(error))
1895                 i915_gpu_coredump_get(error);
1896         spin_unlock_irq(&i915->gpu_error.lock);
1897
1898         return error;
1899 }
1900
1901 void i915_reset_error_state(struct drm_i915_private *i915)
1902 {
1903         struct i915_gpu_coredump *error;
1904
1905         spin_lock_irq(&i915->gpu_error.lock);
1906         error = i915->gpu_error.first_error;
1907         if (error != ERR_PTR(-ENODEV)) /* if disabled, always disabled */
1908                 i915->gpu_error.first_error = NULL;
1909         spin_unlock_irq(&i915->gpu_error.lock);
1910
1911         if (!IS_ERR_OR_NULL(error))
1912                 i915_gpu_coredump_put(error);
1913 }
1914
1915 void i915_disable_error_state(struct drm_i915_private *i915, int err)
1916 {
1917         spin_lock_irq(&i915->gpu_error.lock);
1918         if (!i915->gpu_error.first_error)
1919                 i915->gpu_error.first_error = ERR_PTR(err);
1920         spin_unlock_irq(&i915->gpu_error.lock);
1921 }