drivers/gpu/drm/i915/i915_gpu_error.c

   1 /*
   2  * Copyright (c) 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *    Mika Kuoppala <mika.kuoppala@intel.com>
  27  *
  28  */
  29
  30 #include <linux/ascii85.h>
  31 #include <linux/nmi.h>
  32 #include <linux/pagevec.h>
  33 #include <linux/scatterlist.h>
  34 #include <linux/utsname.h>
  35 #include <linux/zlib.h>
  36
  37 #include <drm/drm_print.h>
  38
  39 #include "display/intel_atomic.h"
  40 #include "display/intel_overlay.h"
  41
  42 #include "gem/i915_gem_context.h"
  43
  44 #include "i915_drv.h"
  45 #include "i915_gpu_error.h"
  46 #include "i915_memcpy.h"
  47 #include "i915_scatterlist.h"
  48 #include "intel_csr.h"
  49
  50 #define ALLOW_FAIL (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN)
  51 #define ATOMIC_MAYFAIL (GFP_ATOMIC | __GFP_NOWARN)
  52
  53 static void __sg_set_buf(struct scatterlist *sg,
  54                          void *addr, unsigned int len, loff_t it)
  55 {
  56         sg->page_link = (unsigned long)virt_to_page(addr);
  57         sg->offset = offset_in_page(addr);
  58         sg->length = len;
  59         sg->dma_address = it;
  60 }
  61
  62 static bool __i915_error_grow(struct drm_i915_error_state_buf *e, size_t len)
  63 {
  64         if (!len)
  65                 return false;
  66
  67         if (e->bytes + len + 1 <= e->size)
  68                 return true;
  69
  70         if (e->bytes) {
  71                 __sg_set_buf(e->cur++, e->buf, e->bytes, e->iter);
  72                 e->iter += e->bytes;
  73                 e->buf = NULL;
  74                 e->bytes = 0;
  75         }
  76
  77         if (e->cur == e->end) {
  78                 struct scatterlist *sgl;
  79
  80                 sgl = (typeof(sgl))__get_free_page(ALLOW_FAIL);
  81                 if (!sgl) {
  82                         e->err = -ENOMEM;
  83                         return false;
  84                 }
  85
  86                 if (e->cur) {
  87                         e->cur->offset = 0;
  88                         e->cur->length = 0;
  89                         e->cur->page_link =
  90                                 (unsigned long)sgl | SG_CHAIN;
  91                 } else {
  92                         e->sgl = sgl;
  93                 }
  94
  95                 e->cur = sgl;
  96                 e->end = sgl + SG_MAX_SINGLE_ALLOC - 1;
  97         }
  98
  99         e->size = ALIGN(len + 1, SZ_64K);
 100         e->buf = kmalloc(e->size, ALLOW_FAIL);
 101         if (!e->buf) {
 102                 e->size = PAGE_ALIGN(len + 1);
 103                 e->buf = kmalloc(e->size, GFP_KERNEL);
 104         }
 105         if (!e->buf) {
 106                 e->err = -ENOMEM;
 107                 return false;
 108         }
 109
 110         return true;
 111 }
 112
 113 __printf(2, 0)
 114 static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
 115                                const char *fmt, va_list args)
 116 {
 117         va_list ap;
 118         int len;
 119
 120         if (e->err)
 121                 return;
 122
 123         va_copy(ap, args);
 124         len = vsnprintf(NULL, 0, fmt, ap);
 125         va_end(ap);
 126         if (len <= 0) {
 127                 e->err = len;
 128                 return;
 129         }
 130
 131         if (!__i915_error_grow(e, len))
 132                 return;
 133
 134         GEM_BUG_ON(e->bytes >= e->size);
 135         len = vscnprintf(e->buf + e->bytes, e->size - e->bytes, fmt, args);
 136         if (len < 0) {
 137                 e->err = len;
 138                 return;
 139         }
 140         e->bytes += len;
 141 }
 142
 143 static void i915_error_puts(struct drm_i915_error_state_buf *e, const char *str)
 144 {
 145         unsigned len;
 146
 147         if (e->err || !str)
 148                 return;
 149
 150         len = strlen(str);
 151         if (!__i915_error_grow(e, len))
 152                 return;
 153
 154         GEM_BUG_ON(e->bytes + len > e->size);
 155         memcpy(e->buf + e->bytes, str, len);
 156         e->bytes += len;
 157 }
 158
 159 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
 160 #define err_puts(e, s) i915_error_puts(e, s)
 161
 162 static void __i915_printfn_error(struct drm_printer *p, struct va_format *vaf)
 163 {
 164         i915_error_vprintf(p->arg, vaf->fmt, *vaf->va);
 165 }
 166
 167 static inline struct drm_printer
 168 i915_error_printer(struct drm_i915_error_state_buf *e)
 169 {
 170         struct drm_printer p = {
 171                 .printfn = __i915_printfn_error,
 172                 .arg = e,
 173         };
 174         return p;
 175 }
 176
 177 /* single threaded page allocator with a reserved stash for emergencies */
 178 static void pool_fini(struct pagevec *pv)
 179 {
 180         pagevec_release(pv);
 181 }
 182
 183 static int pool_refill(struct pagevec *pv, gfp_t gfp)
 184 {
 185         while (pagevec_space(pv)) {
 186                 struct page *p;
 187
 188                 p = alloc_page(gfp);
 189                 if (!p)
 190                         return -ENOMEM;
 191
 192                 pagevec_add(pv, p);
 193         }
 194
 195         return 0;
 196 }
 197
 198 static int pool_init(struct pagevec *pv, gfp_t gfp)
 199 {
 200         int err;
 201
 202         pagevec_init(pv);
 203
 204         err = pool_refill(pv, gfp);
 205         if (err)
 206                 pool_fini(pv);
 207
 208         return err;
 209 }
 210
 211 static void *pool_alloc(struct pagevec *pv, gfp_t gfp)
 212 {
 213         struct page *p;
 214
 215         p = alloc_page(gfp);
 216         if (!p && pagevec_count(pv))
 217                 p = pv->pages[--pv->nr];
 218
 219         return p ? page_address(p) : NULL;
 220 }
 221
 222 static void pool_free(struct pagevec *pv, void *addr)
 223 {
 224         struct page *p = virt_to_page(addr);
 225
 226         if (pagevec_space(pv))
 227                 pagevec_add(pv, p);
 228         else
 229                 __free_page(p);
 230 }
 231
 232 #ifdef CONFIG_DRM_I915_COMPRESS_ERROR
 233
 234 struct compress {
 235         struct pagevec pool;
 236         struct z_stream_s zstream;
 237         void *tmp;
 238 };
 239
 240 static bool compress_init(struct compress *c)
 241 {
 242         struct z_stream_s *zstream = &c->zstream;
 243
 244         if (pool_init(&c->pool, ALLOW_FAIL))
 245                 return false;
 246
 247         zstream->workspace =
 248                 kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL),
 249                         ALLOW_FAIL);
 250         if (!zstream->workspace) {
 251                 pool_fini(&c->pool);
 252                 return false;
 253         }
 254
 255         c->tmp = NULL;
 256         if (i915_has_memcpy_from_wc())
 257                 c->tmp = pool_alloc(&c->pool, ALLOW_FAIL);
 258
 259         return true;
 260 }
 261
 262 static bool compress_start(struct compress *c)
 263 {
 264         struct z_stream_s *zstream = &c->zstream;
 265         void *workspace = zstream->workspace;
 266
 267         memset(zstream, 0, sizeof(*zstream));
 268         zstream->workspace = workspace;
 269
 270         return zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) == Z_OK;
 271 }
 272
 273 static void *compress_next_page(struct compress *c,
 274                                 struct drm_i915_error_object *dst)
 275 {
 276         void *page;
 277
 278         if (dst->page_count >= dst->num_pages)
 279                 return ERR_PTR(-ENOSPC);
 280
 281         page = pool_alloc(&c->pool, ALLOW_FAIL);
 282         if (!page)
 283                 return ERR_PTR(-ENOMEM);
 284
 285         return dst->pages[dst->page_count++] = page;
 286 }
 287
 288 static int compress_page(struct compress *c,
 289                          void *src,
 290                          struct drm_i915_error_object *dst)
 291 {
 292         struct z_stream_s *zstream = &c->zstream;
 293
 294         zstream->next_in = src;
 295         if (c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE))
 296                 zstream->next_in = c->tmp;
 297         zstream->avail_in = PAGE_SIZE;
 298
 299         do {
 300                 if (zstream->avail_out == 0) {
 301                         zstream->next_out = compress_next_page(c, dst);
 302                         if (IS_ERR(zstream->next_out))
 303                                 return PTR_ERR(zstream->next_out);
 304
 305                         zstream->avail_out = PAGE_SIZE;
 306                 }
 307
 308                 if (zlib_deflate(zstream, Z_NO_FLUSH) != Z_OK)
 309                         return -EIO;
 310         } while (zstream->avail_in);
 311
 312         /* Fallback to uncompressed if we increase size? */
 313         if (0 && zstream->total_out > zstream->total_in)
 314                 return -E2BIG;
 315
 316         return 0;
 317 }
 318
 319 static int compress_flush(struct compress *c,
 320                           struct drm_i915_error_object *dst)
 321 {
 322         struct z_stream_s *zstream = &c->zstream;
 323
 324         do {
 325                 switch (zlib_deflate(zstream, Z_FINISH)) {
 326                 case Z_OK: /* more space requested */
 327                         zstream->next_out = compress_next_page(c, dst);
 328                         if (IS_ERR(zstream->next_out))
 329                                 return PTR_ERR(zstream->next_out);
 330
 331                         zstream->avail_out = PAGE_SIZE;
 332                         break;
 333
 334                 case Z_STREAM_END:
 335                         goto end;
 336
 337                 default: /* any error */
 338                         return -EIO;
 339                 }
 340         } while (1);
 341
 342 end:
 343         memset(zstream->next_out, 0, zstream->avail_out);
 344         dst->unused = zstream->avail_out;
 345         return 0;
 346 }
 347
 348 static void compress_finish(struct compress *c)
 349 {
 350         zlib_deflateEnd(&c->zstream);
 351 }
 352
 353 static void compress_fini(struct compress *c)
 354 {
 355         kfree(c->zstream.workspace);
 356         if (c->tmp)
 357                 pool_free(&c->pool, c->tmp);
 358         pool_fini(&c->pool);
 359 }
 360
 361 static void err_compression_marker(struct drm_i915_error_state_buf *m)
 362 {
 363         err_puts(m, ":");
 364 }
 365
 366 #else
 367
 368 struct compress {
 369         struct pagevec pool;
 370 };
 371
 372 static bool compress_init(struct compress *c)
 373 {
 374         return pool_init(&c->pool, ALLOW_FAIL) == 0;
 375 }
 376
 377 static bool compress_start(struct compress *c)
 378 {
 379         return true;
 380 }
 381
 382 static int compress_page(struct compress *c,
 383                          void *src,
 384                          struct drm_i915_error_object *dst)
 385 {
 386         void *ptr;
 387
 388         ptr = pool_alloc(&c->pool, ALLOW_FAIL);
 389         if (!ptr)
 390                 return -ENOMEM;
 391
 392         if (!i915_memcpy_from_wc(ptr, src, PAGE_SIZE))
 393                 memcpy(ptr, src, PAGE_SIZE);
 394         dst->pages[dst->page_count++] = ptr;
 395
 396         return 0;
 397 }
 398
 399 static int compress_flush(struct compress *c,
 400                           struct drm_i915_error_object *dst)
 401 {
 402         return 0;
 403 }
 404
 405 static void compress_finish(struct compress *c)
 406 {
 407 }
 408
 409 static void compress_fini(struct compress *c)
 410 {
 411         pool_fini(&c->pool);
 412 }
 413
 414 static void err_compression_marker(struct drm_i915_error_state_buf *m)
 415 {
 416         err_puts(m, "~");
 417 }
 418
 419 #endif
 420
 421 static void error_print_instdone(struct drm_i915_error_state_buf *m,
 422                                  const struct drm_i915_error_engine *ee)
 423 {
 424         const struct sseu_dev_info *sseu = &RUNTIME_INFO(m->i915)->sseu;
 425         int slice;
 426         int subslice;
 427
 428         err_printf(m, "  INSTDONE: 0x%08x\n",
 429                    ee->instdone.instdone);
 430
 431         if (ee->engine->class != RENDER_CLASS || INTEL_GEN(m->i915) <= 3)
 432                 return;
 433
 434         err_printf(m, "  SC_INSTDONE: 0x%08x\n",
 435                    ee->instdone.slice_common);
 436
 437         if (INTEL_GEN(m->i915) <= 6)
 438                 return;
 439
 440         for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice)
 441                 err_printf(m, "  SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
 442                            slice, subslice,
 443                            ee->instdone.sampler[slice][subslice]);
 444
 445         for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice)
 446                 err_printf(m, "  ROW_INSTDONE[%d][%d]: 0x%08x\n",
 447                            slice, subslice,
 448                            ee->instdone.row[slice][subslice]);
 449 }
 450
 451 static void error_print_request(struct drm_i915_error_state_buf *m,
 452                                 const char *prefix,
 453                                 const struct drm_i915_error_request *erq,
 454                                 const unsigned long epoch)
 455 {
 456         if (!erq->seqno)
 457                 return;
 458
 459         err_printf(m, "%s pid %d, seqno %8x:%08x%s%s, prio %d, emitted %dms, start %08x, head %08x, tail %08x\n",
 460                    prefix, erq->pid, erq->context, erq->seqno,
 461                    test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
 462                             &erq->flags) ? "!" : "",
 463                    test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
 464                             &erq->flags) ? "+" : "",
 465                    erq->sched_attr.priority,
 466                    jiffies_to_msecs(erq->jiffies - epoch),
 467                    erq->start, erq->head, erq->tail);
 468 }
 469
 470 static void error_print_context(struct drm_i915_error_state_buf *m,
 471                                 const char *header,
 472                                 const struct drm_i915_error_context *ctx)
 473 {
 474         err_printf(m, "%s%s[%d] hw_id %d, prio %d, guilty %d active %d\n",
 475                    header, ctx->comm, ctx->pid, ctx->hw_id,
 476                    ctx->sched_attr.priority, ctx->guilty, ctx->active);
 477 }
 478
 479 static void error_print_engine(struct drm_i915_error_state_buf *m,
 480                                const struct drm_i915_error_engine *ee,
 481                                const unsigned long epoch)
 482 {
 483         int n;
 484
 485         err_printf(m, "%s command stream:\n", ee->engine->name);
 486         err_printf(m, "  IDLE?: %s\n", yesno(ee->idle));
 487         err_printf(m, "  START: 0x%08x\n", ee->start);
 488         err_printf(m, "  HEAD:  0x%08x [0x%08x]\n", ee->head, ee->rq_head);
 489         err_printf(m, "  TAIL:  0x%08x [0x%08x, 0x%08x]\n",
 490                    ee->tail, ee->rq_post, ee->rq_tail);
 491         err_printf(m, "  CTL:   0x%08x\n", ee->ctl);
 492         err_printf(m, "  MODE:  0x%08x\n", ee->mode);
 493         err_printf(m, "  HWS:   0x%08x\n", ee->hws);
 494         err_printf(m, "  ACTHD: 0x%08x %08x\n",
 495                    (u32)(ee->acthd>>32), (u32)ee->acthd);
 496         err_printf(m, "  IPEIR: 0x%08x\n", ee->ipeir);
 497         err_printf(m, "  IPEHR: 0x%08x\n", ee->ipehr);
 498
 499         error_print_instdone(m, ee);
 500
 501         if (ee->batchbuffer) {
 502                 u64 start = ee->batchbuffer->gtt_offset;
 503                 u64 end = start + ee->batchbuffer->gtt_size;
 504
 505                 err_printf(m, "  batch: [0x%08x_%08x, 0x%08x_%08x]\n",
 506                            upper_32_bits(start), lower_32_bits(start),
 507                            upper_32_bits(end), lower_32_bits(end));
 508         }
 509         if (INTEL_GEN(m->i915) >= 4) {
 510                 err_printf(m, "  BBADDR: 0x%08x_%08x\n",
 511                            (u32)(ee->bbaddr>>32), (u32)ee->bbaddr);
 512                 err_printf(m, "  BB_STATE: 0x%08x\n", ee->bbstate);
 513                 err_printf(m, "  INSTPS: 0x%08x\n", ee->instps);
 514         }
 515         err_printf(m, "  INSTPM: 0x%08x\n", ee->instpm);
 516         err_printf(m, "  FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr),
 517                    lower_32_bits(ee->faddr));
 518         if (INTEL_GEN(m->i915) >= 6) {
 519                 err_printf(m, "  RC PSMI: 0x%08x\n", ee->rc_psmi);
 520                 err_printf(m, "  FAULT_REG: 0x%08x\n", ee->fault_reg);
 521         }
 522         if (HAS_PPGTT(m->i915)) {
 523                 err_printf(m, "  GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
 524
 525                 if (INTEL_GEN(m->i915) >= 8) {
 526                         int i;
 527                         for (i = 0; i < 4; i++)
 528                                 err_printf(m, "  PDP%d: 0x%016llx\n",
 529                                            i, ee->vm_info.pdp[i]);
 530                 } else {
 531                         err_printf(m, "  PP_DIR_BASE: 0x%08x\n",
 532                                    ee->vm_info.pp_dir_base);
 533                 }
 534         }
 535         err_printf(m, "  ring->head: 0x%08x\n", ee->cpu_ring_head);
 536         err_printf(m, "  ring->tail: 0x%08x\n", ee->cpu_ring_tail);
 537         err_printf(m, "  hangcheck timestamp: %dms (%lu%s)\n",
 538                    jiffies_to_msecs(ee->hangcheck_timestamp - epoch),
 539                    ee->hangcheck_timestamp,
 540                    ee->hangcheck_timestamp == epoch ? "; epoch" : "");
 541         err_printf(m, "  engine reset count: %u\n", ee->reset_count);
 542
 543         for (n = 0; n < ee->num_ports; n++) {
 544                 err_printf(m, "  ELSP[%d]:", n);
 545                 error_print_request(m, " ", &ee->execlist[n], epoch);
 546         }
 547
 548         error_print_context(m, "  Active context: ", &ee->context);
 549 }
 550
 551 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
 552 {
 553         va_list args;
 554
 555         va_start(args, f);
 556         i915_error_vprintf(e, f, args);
 557         va_end(args);
 558 }
 559
 560 static void print_error_obj(struct drm_i915_error_state_buf *m,
 561                             const struct intel_engine_cs *engine,
 562                             const char *name,
 563                             const struct drm_i915_error_object *obj)
 564 {
 565         char out[ASCII85_BUFSZ];
 566         int page;
 567
 568         if (!obj)
 569                 return;
 570
 571         if (name) {
 572                 err_printf(m, "%s --- %s = 0x%08x %08x\n",
 573                            engine ? engine->name : "global", name,
 574                            upper_32_bits(obj->gtt_offset),
 575                            lower_32_bits(obj->gtt_offset));
 576         }
 577
 578         err_compression_marker(m);
 579         for (page = 0; page < obj->page_count; page++) {
 580                 int i, len;
 581
 582                 len = PAGE_SIZE;
 583                 if (page == obj->page_count - 1)
 584                         len -= obj->unused;
 585                 len = ascii85_encode_len(len);
 586
 587                 for (i = 0; i < len; i++)
 588                         err_puts(m, ascii85_encode(obj->pages[page][i], out));
 589         }
 590         err_puts(m, "\n");
 591 }
 592
 593 static void err_print_capabilities(struct drm_i915_error_state_buf *m,
 594                                    const struct intel_device_info *info,
 595                                    const struct intel_runtime_info *runtime,
 596                                    const struct intel_driver_caps *caps)
 597 {
 598         struct drm_printer p = i915_error_printer(m);
 599
 600         intel_device_info_dump_flags(info, &p);
 601         intel_driver_caps_print(caps, &p);
 602         intel_device_info_dump_topology(&runtime->sseu, &p);
 603 }
 604
 605 static void err_print_params(struct drm_i915_error_state_buf *m,
 606                              const struct i915_params *params)
 607 {
 608         struct drm_printer p = i915_error_printer(m);
 609
 610         i915_params_dump(params, &p);
 611 }
 612
 613 static void err_print_pciid(struct drm_i915_error_state_buf *m,
 614                             struct drm_i915_private *i915)
 615 {
 616         struct pci_dev *pdev = i915->drm.pdev;
 617
 618         err_printf(m, "PCI ID: 0x%04x\n", pdev->device);
 619         err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision);
 620         err_printf(m, "PCI Subsystem: %04x:%04x\n",
 621                    pdev->subsystem_vendor,
 622                    pdev->subsystem_device);
 623 }
 624
 625 static void err_print_uc(struct drm_i915_error_state_buf *m,
 626                          const struct i915_error_uc *error_uc)
 627 {
 628         struct drm_printer p = i915_error_printer(m);
 629         const struct i915_gpu_state *error =
 630                 container_of(error_uc, typeof(*error), uc);
 631
 632         if (!error->device_info.has_gt_uc)
 633                 return;
 634
 635         intel_uc_fw_dump(&error_uc->guc_fw, &p);
 636         intel_uc_fw_dump(&error_uc->huc_fw, &p);
 637         print_error_obj(m, NULL, "GuC log buffer", error_uc->guc_log);
 638 }
 639
 640 static void err_free_sgl(struct scatterlist *sgl)
 641 {
 642         while (sgl) {
 643                 struct scatterlist *sg;
 644
 645                 for (sg = sgl; !sg_is_chain(sg); sg++) {
 646                         kfree(sg_virt(sg));
 647                         if (sg_is_last(sg))
 648                                 break;
 649                 }
 650
 651                 sg = sg_is_last(sg) ? NULL : sg_chain_ptr(sg);
 652                 free_page((unsigned long)sgl);
 653                 sgl = sg;
 654         }
 655 }
 656
 657 static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
 658                                struct i915_gpu_state *error)
 659 {
 660         const struct drm_i915_error_engine *ee;
 661         struct timespec64 ts;
 662         int i, j;
 663
 664         if (*error->error_msg)
 665                 err_printf(m, "%s\n", error->error_msg);
 666         err_printf(m, "Kernel: %s %s\n",
 667                    init_utsname()->release,
 668                    init_utsname()->machine);
 669         err_printf(m, "Driver: %s\n", DRIVER_DATE);
 670         ts = ktime_to_timespec64(error->time);
 671         err_printf(m, "Time: %lld s %ld us\n",
 672                    (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
 673         ts = ktime_to_timespec64(error->boottime);
 674         err_printf(m, "Boottime: %lld s %ld us\n",
 675                    (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
 676         ts = ktime_to_timespec64(error->uptime);
 677         err_printf(m, "Uptime: %lld s %ld us\n",
 678                    (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
 679         err_printf(m, "Epoch: %lu jiffies (%u HZ)\n", error->epoch, HZ);
 680         err_printf(m, "Capture: %lu jiffies; %d ms ago, %d ms after epoch\n",
 681                    error->capture,
 682                    jiffies_to_msecs(jiffies - error->capture),
 683                    jiffies_to_msecs(error->capture - error->epoch));
 684
 685         for (ee = error->engine; ee; ee = ee->next)
 686                 err_printf(m, "Active process (on ring %s): %s [%d]\n",
 687                            ee->engine->name,
 688                            ee->context.comm,
 689                            ee->context.pid);
 690
 691         err_printf(m, "Reset count: %u\n", error->reset_count);
 692         err_printf(m, "Suspend count: %u\n", error->suspend_count);
 693         err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform));
 694         err_printf(m, "Subplatform: 0x%x\n",
 695                    intel_subplatform(&error->runtime_info,
 696                                      error->device_info.platform));
 697         err_print_pciid(m, m->i915);
 698
 699         err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
 700
 701         if (HAS_CSR(m->i915)) {
 702                 struct intel_csr *csr = &m->i915->csr;
 703
 704                 err_printf(m, "DMC loaded: %s\n",
 705                            yesno(csr->dmc_payload != NULL));
 706                 err_printf(m, "DMC fw version: %d.%d\n",
 707                            CSR_VERSION_MAJOR(csr->version),
 708                            CSR_VERSION_MINOR(csr->version));
 709         }
 710
 711         err_printf(m, "GT awake: %s\n", yesno(error->awake));
 712         err_printf(m, "RPM wakelock: %s\n", yesno(error->wakelock));
 713         err_printf(m, "PM suspended: %s\n", yesno(error->suspended));
 714         err_printf(m, "EIR: 0x%08x\n", error->eir);
 715         err_printf(m, "IER: 0x%08x\n", error->ier);
 716         for (i = 0; i < error->ngtier; i++)
 717                 err_printf(m, "GTIER[%d]: 0x%08x\n", i, error->gtier[i]);
 718         err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
 719         err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
 720         err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
 721         err_printf(m, "CCID: 0x%08x\n", error->ccid);
 722
 723         for (i = 0; i < error->nfence; i++)
 724                 err_printf(m, "  fence[%d] = %08llx\n", i, error->fence[i]);
 725
 726         if (IS_GEN_RANGE(m->i915, 6, 11)) {
 727                 err_printf(m, "ERROR: 0x%08x\n", error->error);
 728                 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
 729         }
 730
 731         if (INTEL_GEN(m->i915) >= 8)
 732                 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
 733                            error->fault_data1, error->fault_data0);
 734
 735         if (IS_GEN(m->i915, 7))
 736                 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
 737
 738         for (ee = error->engine; ee; ee = ee->next)
 739                 error_print_engine(m, ee, error->epoch);
 740
 741         for (ee = error->engine; ee; ee = ee->next) {
 742                 const struct drm_i915_error_object *obj;
 743
 744                 obj = ee->batchbuffer;
 745                 if (obj) {
 746                         err_puts(m, ee->engine->name);
 747                         if (ee->context.pid)
 748                                 err_printf(m, " (submitted by %s [%d])",
 749                                            ee->context.comm,
 750                                            ee->context.pid);
 751                         err_printf(m, " --- gtt_offset = 0x%08x %08x\n",
 752                                    upper_32_bits(obj->gtt_offset),
 753                                    lower_32_bits(obj->gtt_offset));
 754                         print_error_obj(m, ee->engine, NULL, obj);
 755                 }
 756
 757                 for (j = 0; j < ee->user_bo_count; j++)
 758                         print_error_obj(m, ee->engine, "user", ee->user_bo[j]);
 759
 760                 if (ee->num_requests) {
 761                         err_printf(m, "%s --- %d requests\n",
 762                                    ee->engine->name,
 763                                    ee->num_requests);
 764                         for (j = 0; j < ee->num_requests; j++)
 765                                 error_print_request(m, " ",
 766                                                     &ee->requests[j],
 767                                                     error->epoch);
 768                 }
 769
 770                 print_error_obj(m, ee->engine, "ringbuffer", ee->ringbuffer);
 771                 print_error_obj(m, ee->engine, "HW Status", ee->hws_page);
 772                 print_error_obj(m, ee->engine, "HW context", ee->ctx);
 773                 print_error_obj(m, ee->engine, "WA context", ee->wa_ctx);
 774                 print_error_obj(m, ee->engine,
 775                                 "WA batchbuffer", ee->wa_batchbuffer);
 776                 print_error_obj(m, ee->engine,
 777                                 "NULL context", ee->default_state);
 778         }
 779
 780         if (error->overlay)
 781                 intel_overlay_print_error_state(m, error->overlay);
 782
 783         if (error->display)
 784                 intel_display_print_error_state(m, error->display);
 785
 786         err_print_capabilities(m, &error->device_info, &error->runtime_info,
 787                                &error->driver_caps);
 788         err_print_params(m, &error->params);
 789         err_print_uc(m, &error->uc);
 790 }
 791
 792 static int err_print_to_sgl(struct i915_gpu_state *error)
 793 {
 794         struct drm_i915_error_state_buf m;
 795
 796         if (IS_ERR(error))
 797                 return PTR_ERR(error);
 798
 799         if (READ_ONCE(error->sgl))
 800                 return 0;
 801
 802         memset(&m, 0, sizeof(m));
 803         m.i915 = error->i915;
 804
 805         __err_print_to_sgl(&m, error);
 806
 807         if (m.buf) {
 808                 __sg_set_buf(m.cur++, m.buf, m.bytes, m.iter);
 809                 m.bytes = 0;
 810                 m.buf = NULL;
 811         }
 812         if (m.cur) {
 813                 GEM_BUG_ON(m.end < m.cur);
 814                 sg_mark_end(m.cur - 1);
 815         }
 816         GEM_BUG_ON(m.sgl && !m.cur);
 817
 818         if (m.err) {
 819                 err_free_sgl(m.sgl);
 820                 return m.err;
 821         }
 822
 823         if (cmpxchg(&error->sgl, NULL, m.sgl))
 824                 err_free_sgl(m.sgl);
 825
 826         return 0;
 827 }
 828
 829 ssize_t i915_gpu_state_copy_to_buffer(struct i915_gpu_state *error,
 830                                       char *buf, loff_t off, size_t rem)
 831 {
 832         struct scatterlist *sg;
 833         size_t count;
 834         loff_t pos;
 835         int err;
 836
 837         if (!error || !rem)
 838                 return 0;
 839
 840         err = err_print_to_sgl(error);
 841         if (err)
 842                 return err;
 843
 844         sg = READ_ONCE(error->fit);
 845         if (!sg || off < sg->dma_address)
 846                 sg = error->sgl;
 847         if (!sg)
 848                 return 0;
 849
 850         pos = sg->dma_address;
 851         count = 0;
 852         do {
 853                 size_t len, start;
 854
 855                 if (sg_is_chain(sg)) {
 856                         sg = sg_chain_ptr(sg);
 857                         GEM_BUG_ON(sg_is_chain(sg));
 858                 }
 859
 860                 len = sg->length;
 861                 if (pos + len <= off) {
 862                         pos += len;
 863                         continue;
 864                 }
 865
 866                 start = sg->offset;
 867                 if (pos < off) {
 868                         GEM_BUG_ON(off - pos > len);
 869                         len -= off - pos;
 870                         start += off - pos;
 871                         pos = off;
 872                 }
 873
 874                 len = min(len, rem);
 875                 GEM_BUG_ON(!len || len > sg->length);
 876
 877                 memcpy(buf, page_address(sg_page(sg)) + start, len);
 878
 879                 count += len;
 880                 pos += len;
 881
 882                 buf += len;
 883                 rem -= len;
 884                 if (!rem) {
 885                         WRITE_ONCE(error->fit, sg);
 886                         break;
 887                 }
 888         } while (!sg_is_last(sg++));
 889
 890         return count;
 891 }
 892
 893 static void i915_error_object_free(struct drm_i915_error_object *obj)
 894 {
 895         int page;
 896
 897         if (obj == NULL)
 898                 return;
 899
 900         for (page = 0; page < obj->page_count; page++)
 901                 free_page((unsigned long)obj->pages[page]);
 902
 903         kfree(obj);
 904 }
 905
 906
 907 static void cleanup_params(struct i915_gpu_state *error)
 908 {
 909         i915_params_free(&error->params);
 910 }
 911
 912 static void cleanup_uc_state(struct i915_gpu_state *error)
 913 {
 914         struct i915_error_uc *error_uc = &error->uc;
 915
 916         kfree(error_uc->guc_fw.path);
 917         kfree(error_uc->huc_fw.path);
 918         i915_error_object_free(error_uc->guc_log);
 919 }
 920
 921 void __i915_gpu_state_free(struct kref *error_ref)
 922 {
 923         struct i915_gpu_state *error =
 924                 container_of(error_ref, typeof(*error), ref);
 925         long i;
 926
 927         while (error->engine) {
 928                 struct drm_i915_error_engine *ee = error->engine;
 929
 930                 error->engine = ee->next;
 931
 932                 for (i = 0; i < ee->user_bo_count; i++)
 933                         i915_error_object_free(ee->user_bo[i]);
 934                 kfree(ee->user_bo);
 935
 936                 i915_error_object_free(ee->batchbuffer);
 937                 i915_error_object_free(ee->wa_batchbuffer);
 938                 i915_error_object_free(ee->ringbuffer);
 939                 i915_error_object_free(ee->hws_page);
 940                 i915_error_object_free(ee->ctx);
 941                 i915_error_object_free(ee->wa_ctx);
 942
 943                 kfree(ee->requests);
 944                 kfree(ee);
 945         }
 946
 947         kfree(error->overlay);
 948         kfree(error->display);
 949
 950         cleanup_params(error);
 951         cleanup_uc_state(error);
 952
 953         err_free_sgl(error->sgl);
 954         kfree(error);
 955 }
 956
 957 static struct drm_i915_error_object *
 958 i915_error_object_create(struct drm_i915_private *i915,
 959                          struct i915_vma *vma,
 960                          struct compress *compress)
 961 {
 962         struct i915_ggtt *ggtt = &i915->ggtt;
 963         const u64 slot = ggtt->error_capture.start;
 964         struct drm_i915_error_object *dst;
 965         unsigned long num_pages;
 966         struct sgt_iter iter;
 967         dma_addr_t dma;
 968         int ret;
 969
 970         might_sleep();
 971
 972         if (!vma || !vma->pages)
 973                 return NULL;
 974
 975         num_pages = min_t(u64, vma->size, vma->obj->base.size) >> PAGE_SHIFT;
 976         num_pages = DIV_ROUND_UP(10 * num_pages, 8); /* worstcase zlib growth */
 977         dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), ALLOW_FAIL);
 978         if (!dst)
 979                 return NULL;
 980
 981         if (!compress_start(compress)) {
 982                 kfree(dst);
 983                 return NULL;
 984         }
 985
 986         dst->gtt_offset = vma->node.start;
 987         dst->gtt_size = vma->node.size;
 988         dst->num_pages = num_pages;
 989         dst->page_count = 0;
 990         dst->unused = 0;
 991
 992         ret = -EINVAL;
 993         for_each_sgt_daddr(dma, iter, vma->pages) {
 994                 void __iomem *s;
 995
 996                 ggtt->vm.insert_page(&ggtt->vm, dma, slot, I915_CACHE_NONE, 0);
 997
 998                 s = io_mapping_map_wc(&ggtt->iomap, slot, PAGE_SIZE);
 999                 ret = compress_page(compress, (void  __force *)s, dst);
1000                 io_mapping_unmap(s);
1001                 if (ret)
1002                         break;
1003         }
1004
1005         if (ret || compress_flush(compress, dst)) {
1006                 while (dst->page_count--)
1007                         pool_free(&compress->pool, dst->pages[dst->page_count]);
1008                 kfree(dst);
1009                 dst = NULL;
1010         }
1011         compress_finish(compress);
1012
1013         return dst;
1014 }
1015
1016 /*
1017  * Generate a semi-unique error code. The code is not meant to have meaning, The
1018  * code's only purpose is to try to prevent false duplicated bug reports by
1019  * grossly estimating a GPU error state.
1020  *
1021  * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
1022  * the hang if we could strip the GTT offset information from it.
1023  *
1024  * It's only a small step better than a random number in its current form.
1025  */
1026 static u32 i915_error_generate_code(struct i915_gpu_state *error)
1027 {
1028         const struct drm_i915_error_engine *ee = error->engine;
1029
1030         /*
1031          * IPEHR would be an ideal way to detect errors, as it's the gross
1032          * measure of "the command that hung." However, has some very common
1033          * synchronization commands which almost always appear in the case
1034          * strictly a client bug. Use instdone to differentiate those some.
1035          */
1036         return ee ? ee->ipehr ^ ee->instdone.instdone : 0;
1037 }
1038
1039 static void gem_record_fences(struct i915_gpu_state *error)
1040 {
1041         struct drm_i915_private *dev_priv = error->i915;
1042         struct intel_uncore *uncore = &dev_priv->uncore;
1043         int i;
1044
1045         if (INTEL_GEN(dev_priv) >= 6) {
1046                 for (i = 0; i < dev_priv->ggtt.num_fences; i++)
1047                         error->fence[i] =
1048                                 intel_uncore_read64(uncore,
1049                                                     FENCE_REG_GEN6_LO(i));
1050         } else if (INTEL_GEN(dev_priv) >= 4) {
1051                 for (i = 0; i < dev_priv->ggtt.num_fences; i++)
1052                         error->fence[i] =
1053                                 intel_uncore_read64(uncore,
1054                                                     FENCE_REG_965_LO(i));
1055         } else {
1056                 for (i = 0; i < dev_priv->ggtt.num_fences; i++)
1057                         error->fence[i] =
1058                                 intel_uncore_read(uncore, FENCE_REG(i));
1059         }
1060         error->nfence = i;
1061 }
1062
1063 static void error_record_engine_registers(struct i915_gpu_state *error,
1064                                           struct intel_engine_cs *engine,
1065                                           struct drm_i915_error_engine *ee)
1066 {
1067         struct drm_i915_private *dev_priv = engine->i915;
1068
1069         if (INTEL_GEN(dev_priv) >= 6) {
1070                 ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL);
1071
1072                 if (INTEL_GEN(dev_priv) >= 12)
1073                         ee->fault_reg = I915_READ(GEN12_RING_FAULT_REG);
1074                 else if (INTEL_GEN(dev_priv) >= 8)
1075                         ee->fault_reg = I915_READ(GEN8_RING_FAULT_REG);
1076                 else
1077                         ee->fault_reg = GEN6_RING_FAULT_REG_READ(engine);
1078         }
1079
1080         if (INTEL_GEN(dev_priv) >= 4) {
1081                 ee->faddr = ENGINE_READ(engine, RING_DMA_FADD);
1082                 ee->ipeir = ENGINE_READ(engine, RING_IPEIR);
1083                 ee->ipehr = ENGINE_READ(engine, RING_IPEHR);
1084                 ee->instps = ENGINE_READ(engine, RING_INSTPS);
1085                 ee->bbaddr = ENGINE_READ(engine, RING_BBADDR);
1086                 if (INTEL_GEN(dev_priv) >= 8) {
1087                         ee->faddr |= (u64)ENGINE_READ(engine, RING_DMA_FADD_UDW) << 32;
1088                         ee->bbaddr |= (u64)ENGINE_READ(engine, RING_BBADDR_UDW) << 32;
1089                 }
1090                 ee->bbstate = ENGINE_READ(engine, RING_BBSTATE);
1091         } else {
1092                 ee->faddr = ENGINE_READ(engine, DMA_FADD_I8XX);
1093                 ee->ipeir = ENGINE_READ(engine, IPEIR);
1094                 ee->ipehr = ENGINE_READ(engine, IPEHR);
1095         }
1096
1097         intel_engine_get_instdone(engine, &ee->instdone);
1098
1099         ee->instpm = ENGINE_READ(engine, RING_INSTPM);
1100         ee->acthd = intel_engine_get_active_head(engine);
1101         ee->start = ENGINE_READ(engine, RING_START);
1102         ee->head = ENGINE_READ(engine, RING_HEAD);
1103         ee->tail = ENGINE_READ(engine, RING_TAIL);
1104         ee->ctl = ENGINE_READ(engine, RING_CTL);
1105         if (INTEL_GEN(dev_priv) > 2)
1106                 ee->mode = ENGINE_READ(engine, RING_MI_MODE);
1107
1108         if (!HWS_NEEDS_PHYSICAL(dev_priv)) {
1109                 i915_reg_t mmio;
1110
1111                 if (IS_GEN(dev_priv, 7)) {
1112                         switch (engine->id) {
1113                         default:
1114                                 MISSING_CASE(engine->id);
1115                                 /* fall through */
1116                         case RCS0:
1117                                 mmio = RENDER_HWS_PGA_GEN7;
1118                                 break;
1119                         case BCS0:
1120                                 mmio = BLT_HWS_PGA_GEN7;
1121                                 break;
1122                         case VCS0:
1123                                 mmio = BSD_HWS_PGA_GEN7;
1124                                 break;
1125                         case VECS0:
1126                                 mmio = VEBOX_HWS_PGA_GEN7;
1127                                 break;
1128                         }
1129                 } else if (IS_GEN(engine->i915, 6)) {
1130                         mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
1131                 } else {
1132                         /* XXX: gen8 returns to sanity */
1133                         mmio = RING_HWS_PGA(engine->mmio_base);
1134                 }
1135
1136                 ee->hws = I915_READ(mmio);
1137         }
1138
1139         ee->idle = intel_engine_is_idle(engine);
1140         if (!ee->idle)
1141                 ee->hangcheck_timestamp = engine->hangcheck.action_timestamp;
1142         ee->reset_count = i915_reset_engine_count(&dev_priv->gpu_error,
1143                                                   engine);
1144
1145         if (HAS_PPGTT(dev_priv)) {
1146                 int i;
1147
1148                 ee->vm_info.gfx_mode = ENGINE_READ(engine, RING_MODE_GEN7);
1149
1150                 if (IS_GEN(dev_priv, 6)) {
1151                         ee->vm_info.pp_dir_base =
1152                                 ENGINE_READ(engine, RING_PP_DIR_BASE_READ);
1153                 } else if (IS_GEN(dev_priv, 7)) {
1154                         ee->vm_info.pp_dir_base =
1155                                 ENGINE_READ(engine, RING_PP_DIR_BASE);
1156                 } else if (INTEL_GEN(dev_priv) >= 8) {
1157                         u32 base = engine->mmio_base;
1158
1159                         for (i = 0; i < 4; i++) {
1160                                 ee->vm_info.pdp[i] =
1161                                         I915_READ(GEN8_RING_PDP_UDW(base, i));
1162                                 ee->vm_info.pdp[i] <<= 32;
1163                                 ee->vm_info.pdp[i] |=
1164                                         I915_READ(GEN8_RING_PDP_LDW(base, i));
1165                         }
1166                 }
1167         }
1168 }
1169
1170 static void record_request(const struct i915_request *request,
1171                            struct drm_i915_error_request *erq)
1172 {
1173         const struct i915_gem_context *ctx = request->gem_context;
1174
1175         erq->flags = request->fence.flags;
1176         erq->context = request->fence.context;
1177         erq->seqno = request->fence.seqno;
1178         erq->sched_attr = request->sched.attr;
1179         erq->jiffies = request->emitted_jiffies;
1180         erq->start = i915_ggtt_offset(request->ring->vma);
1181         erq->head = request->head;
1182         erq->tail = request->tail;
1183
1184         rcu_read_lock();
1185         erq->pid = ctx->pid ? pid_nr(ctx->pid) : 0;
1186         rcu_read_unlock();
1187 }
1188
1189 static void engine_record_requests(struct intel_engine_cs *engine,
1190                                    struct i915_request *first,
1191                                    struct drm_i915_error_engine *ee)
1192 {
1193         struct i915_request *request;
1194         int count;
1195
1196         count = 0;
1197         request = first;
1198         list_for_each_entry_from(request, &engine->active.requests, sched.link)
1199                 count++;
1200         if (!count)
1201                 return;
1202
1203         ee->requests = kcalloc(count, sizeof(*ee->requests), ATOMIC_MAYFAIL);
1204         if (!ee->requests)
1205                 return;
1206
1207         ee->num_requests = count;
1208
1209         count = 0;
1210         request = first;
1211         list_for_each_entry_from(request,
1212                                  &engine->active.requests, sched.link) {
1213                 if (count >= ee->num_requests) {
1214                         /*
1215                          * If the ring request list was changed in
1216                          * between the point where the error request
1217                          * list was created and dimensioned and this
1218                          * point then just exit early to avoid crashes.
1219                          *
1220                          * We don't need to communicate that the
1221                          * request list changed state during error
1222                          * state capture and that the error state is
1223                          * slightly incorrect as a consequence since we
1224                          * are typically only interested in the request
1225                          * list state at the point of error state
1226                          * capture, not in any changes happening during
1227                          * the capture.
1228                          */
1229                         break;
1230                 }
1231
1232                 record_request(request, &ee->requests[count++]);
1233         }
1234         ee->num_requests = count;
1235 }
1236
1237 static void error_record_engine_execlists(const struct intel_engine_cs *engine,
1238                                           struct drm_i915_error_engine *ee)
1239 {
1240         const struct intel_engine_execlists * const execlists = &engine->execlists;
1241         struct i915_request * const *port = execlists->active;
1242         unsigned int n = 0;
1243
1244         while (*port)
1245                 record_request(*port++, &ee->execlist[n++]);
1246
1247         ee->num_ports = n;
1248 }
1249
1250 static bool record_context(struct drm_i915_error_context *e,
1251                            const struct i915_request *rq)
1252 {
1253         const struct i915_gem_context *ctx = rq->gem_context;
1254
1255         if (ctx->pid) {
1256                 struct task_struct *task;
1257
1258                 rcu_read_lock();
1259                 task = pid_task(ctx->pid, PIDTYPE_PID);
1260                 if (task) {
1261                         strcpy(e->comm, task->comm);
1262                         e->pid = task->pid;
1263                 }
1264                 rcu_read_unlock();
1265         }
1266
1267         e->hw_id = ctx->hw_id;
1268         e->sched_attr = ctx->sched;
1269         e->guilty = atomic_read(&ctx->guilty_count);
1270         e->active = atomic_read(&ctx->active_count);
1271
1272         return i915_gem_context_no_error_capture(ctx);
1273 }
1274
1275 struct capture_vma {
1276         struct capture_vma *next;
1277         void **slot;
1278 };
1279
1280 static struct capture_vma *
1281 capture_vma(struct capture_vma *next,
1282             struct i915_vma *vma,
1283             struct drm_i915_error_object **out)
1284 {
1285         struct capture_vma *c;
1286
1287         *out = NULL;
1288         if (!vma)
1289                 return next;
1290
1291         c = kmalloc(sizeof(*c), ATOMIC_MAYFAIL);
1292         if (!c)
1293                 return next;
1294
1295         if (!i915_active_trygrab(&vma->active)) {
1296                 kfree(c);
1297                 return next;
1298         }
1299
1300         c->slot = (void **)out;
1301         *c->slot = i915_vma_get(vma);
1302
1303         c->next = next;
1304         return c;
1305 }
1306
1307 static struct capture_vma *
1308 request_record_user_bo(struct i915_request *request,
1309                        struct drm_i915_error_engine *ee,
1310                        struct capture_vma *capture)
1311 {
1312         struct i915_capture_list *c;
1313         struct drm_i915_error_object **bo;
1314         long count, max;
1315
1316         max = 0;
1317         for (c = request->capture_list; c; c = c->next)
1318                 max++;
1319         if (!max)
1320                 return capture;
1321
1322         bo = kmalloc_array(max, sizeof(*bo), ATOMIC_MAYFAIL);
1323         if (!bo) {
1324                 /* If we can't capture everything, try to capture something. */
1325                 max = min_t(long, max, PAGE_SIZE / sizeof(*bo));
1326                 bo = kmalloc_array(max, sizeof(*bo), ATOMIC_MAYFAIL);
1327         }
1328         if (!bo)
1329                 return capture;
1330
1331         count = 0;
1332         for (c = request->capture_list; c; c = c->next) {
1333                 capture = capture_vma(capture, c->vma, &bo[count]);
1334                 if (++count == max)
1335                         break;
1336         }
1337
1338         ee->user_bo = bo;
1339         ee->user_bo_count = count;
1340
1341         return capture;
1342 }
1343
1344 static struct drm_i915_error_object *
1345 capture_object(struct drm_i915_private *dev_priv,
1346                struct drm_i915_gem_object *obj,
1347                struct compress *compress)
1348 {
1349         if (obj && i915_gem_object_has_pages(obj)) {
1350                 struct i915_vma fake = {
1351                         .node = { .start = U64_MAX, .size = obj->base.size },
1352                         .size = obj->base.size,
1353                         .pages = obj->mm.pages,
1354                         .obj = obj,
1355                 };
1356
1357                 return i915_error_object_create(dev_priv, &fake, compress);
1358         } else {
1359                 return NULL;
1360         }
1361 }
1362
1363 static void
1364 gem_record_rings(struct i915_gpu_state *error, struct compress *compress)
1365 {
1366         struct drm_i915_private *i915 = error->i915;
1367         struct intel_engine_cs *engine;
1368         struct drm_i915_error_engine *ee;
1369
1370         ee = kzalloc(sizeof(*ee), GFP_KERNEL);
1371         if (!ee)
1372                 return;
1373
1374         for_each_uabi_engine(engine, i915) {
1375                 struct capture_vma *capture = NULL;
1376                 struct i915_request *request;
1377                 unsigned long flags;
1378
1379                 /* Refill our page pool before entering atomic section */
1380                 pool_refill(&compress->pool, ALLOW_FAIL);
1381
1382                 spin_lock_irqsave(&engine->active.lock, flags);
1383                 request = intel_engine_find_active_request(engine);
1384                 if (!request) {
1385                         spin_unlock_irqrestore(&engine->active.lock, flags);
1386                         continue;
1387                 }
1388
1389                 error->simulated |= record_context(&ee->context, request);
1390
1391                 /*
1392                  * We need to copy these to an anonymous buffer
1393                  * as the simplest method to avoid being overwritten
1394                  * by userspace.
1395                  */
1396                 capture = capture_vma(capture,
1397                                       request->batch,
1398                                       &ee->batchbuffer);
1399
1400                 if (HAS_BROKEN_CS_TLB(i915))
1401                         capture = capture_vma(capture,
1402                                               engine->gt->scratch,
1403                                               &ee->wa_batchbuffer);
1404
1405                 capture = request_record_user_bo(request, ee, capture);
1406
1407                 capture = capture_vma(capture,
1408                                       request->hw_context->state,
1409                                       &ee->ctx);
1410
1411                 capture = capture_vma(capture,
1412                                       request->ring->vma,
1413                                       &ee->ringbuffer);
1414
1415                 ee->cpu_ring_head = request->ring->head;
1416                 ee->cpu_ring_tail = request->ring->tail;
1417
1418                 ee->rq_head = request->head;
1419                 ee->rq_post = request->postfix;
1420                 ee->rq_tail = request->tail;
1421
1422                 engine_record_requests(engine, request, ee);
1423                 spin_unlock_irqrestore(&engine->active.lock, flags);
1424
1425                 error_record_engine_registers(error, engine, ee);
1426                 error_record_engine_execlists(engine, ee);
1427
1428                 while (capture) {
1429                         struct capture_vma *this = capture;
1430                         struct i915_vma *vma = *this->slot;
1431
1432                         *this->slot =
1433                                 i915_error_object_create(i915, vma, compress);
1434
1435                         i915_active_ungrab(&vma->active);
1436                         i915_vma_put(vma);
1437
1438                         capture = this->next;
1439                         kfree(this);
1440                 }
1441
1442                 ee->hws_page =
1443                         i915_error_object_create(i915,
1444                                                  engine->status_page.vma,
1445                                                  compress);
1446
1447                 ee->wa_ctx =
1448                         i915_error_object_create(i915,
1449                                                  engine->wa_ctx.vma,
1450                                                  compress);
1451
1452                 ee->default_state =
1453                         capture_object(i915, engine->default_state, compress);
1454
1455                 ee->engine = engine;
1456
1457                 ee->next = error->engine;
1458                 error->engine = ee;
1459
1460                 ee = kzalloc(sizeof(*ee), GFP_KERNEL);
1461                 if (!ee)
1462                         return;
1463         }
1464
1465         kfree(ee);
1466 }
1467
1468 static void
1469 capture_uc_state(struct i915_gpu_state *error, struct compress *compress)
1470 {
1471         struct drm_i915_private *i915 = error->i915;
1472         struct i915_error_uc *error_uc = &error->uc;
1473         struct intel_uc *uc = &i915->gt.uc;
1474
1475         /* Capturing uC state won't be useful if there is no GuC */
1476         if (!error->device_info.has_gt_uc)
1477                 return;
1478
1479         memcpy(&error_uc->guc_fw, &uc->guc.fw, sizeof(uc->guc.fw));
1480         memcpy(&error_uc->huc_fw, &uc->huc.fw, sizeof(uc->huc.fw));
1481
1482         /* Non-default firmware paths will be specified by the modparam.
1483          * As modparams are generally accesible from the userspace make
1484          * explicit copies of the firmware paths.
1485          */
1486         error_uc->guc_fw.path = kstrdup(uc->guc.fw.path, ALLOW_FAIL);
1487         error_uc->huc_fw.path = kstrdup(uc->huc.fw.path, ALLOW_FAIL);
1488         error_uc->guc_log = i915_error_object_create(i915,
1489                                                      uc->guc.log.vma,
1490                                                      compress);
1491 }
1492
1493 /* Capture all registers which don't fit into another category. */
1494 static void capture_reg_state(struct i915_gpu_state *error)
1495 {
1496         struct drm_i915_private *i915 = error->i915;
1497         struct intel_uncore *uncore = &i915->uncore;
1498         int i;
1499
1500         /* General organization
1501          * 1. Registers specific to a single generation
1502          * 2. Registers which belong to multiple generations
1503          * 3. Feature specific registers.
1504          * 4. Everything else
1505          * Please try to follow the order.
1506          */
1507
1508         /* 1: Registers specific to a single generation */
1509         if (IS_VALLEYVIEW(i915)) {
1510                 error->gtier[0] = intel_uncore_read(uncore, GTIER);
1511                 error->ier = intel_uncore_read(uncore, VLV_IER);
1512                 error->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_VLV);
1513         }
1514
1515         if (IS_GEN(i915, 7))
1516                 error->err_int = intel_uncore_read(uncore, GEN7_ERR_INT);
1517
1518         if (INTEL_GEN(i915) >= 12) {
1519                 error->fault_data0 = intel_uncore_read(uncore,
1520                                                        GEN12_FAULT_TLB_DATA0);
1521                 error->fault_data1 = intel_uncore_read(uncore,
1522                                                        GEN12_FAULT_TLB_DATA1);
1523         } else if (INTEL_GEN(i915) >= 8) {
1524                 error->fault_data0 = intel_uncore_read(uncore,
1525                                                        GEN8_FAULT_TLB_DATA0);
1526                 error->fault_data1 = intel_uncore_read(uncore,
1527                                                        GEN8_FAULT_TLB_DATA1);
1528         }
1529
1530         if (IS_GEN(i915, 6)) {
1531                 error->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE);
1532                 error->gab_ctl = intel_uncore_read(uncore, GAB_CTL);
1533                 error->gfx_mode = intel_uncore_read(uncore, GFX_MODE);
1534         }
1535
1536         /* 2: Registers which belong to multiple generations */
1537         if (INTEL_GEN(i915) >= 7)
1538                 error->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_MT);
1539
1540         if (INTEL_GEN(i915) >= 6) {
1541                 error->derrmr = intel_uncore_read(uncore, DERRMR);
1542                 if (INTEL_GEN(i915) < 12) {
1543                         error->error = intel_uncore_read(uncore, ERROR_GEN6);
1544                         error->done_reg = intel_uncore_read(uncore, DONE_REG);
1545                 }
1546         }
1547
1548         if (INTEL_GEN(i915) >= 5)
1549                 error->ccid = intel_uncore_read(uncore, CCID(RENDER_RING_BASE));
1550
1551         /* 3: Feature specific registers */
1552         if (IS_GEN_RANGE(i915, 6, 7)) {
1553                 error->gam_ecochk = intel_uncore_read(uncore, GAM_ECOCHK);
1554                 error->gac_eco = intel_uncore_read(uncore, GAC_ECO_BITS);
1555         }
1556
1557         /* 4: Everything else */
1558         if (INTEL_GEN(i915) >= 11) {
1559                 error->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER);
1560                 error->gtier[0] =
1561                         intel_uncore_read(uncore,
1562                                           GEN11_RENDER_COPY_INTR_ENABLE);
1563                 error->gtier[1] =
1564                         intel_uncore_read(uncore, GEN11_VCS_VECS_INTR_ENABLE);
1565                 error->gtier[2] =
1566                         intel_uncore_read(uncore, GEN11_GUC_SG_INTR_ENABLE);
1567                 error->gtier[3] =
1568                         intel_uncore_read(uncore,
1569                                           GEN11_GPM_WGBOXPERF_INTR_ENABLE);
1570                 error->gtier[4] =
1571                         intel_uncore_read(uncore,
1572                                           GEN11_CRYPTO_RSVD_INTR_ENABLE);
1573                 error->gtier[5] =
1574                         intel_uncore_read(uncore,
1575                                           GEN11_GUNIT_CSME_INTR_ENABLE);
1576                 error->ngtier = 6;
1577         } else if (INTEL_GEN(i915) >= 8) {
1578                 error->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER);
1579                 for (i = 0; i < 4; i++)
1580                         error->gtier[i] = intel_uncore_read(uncore,
1581                                                             GEN8_GT_IER(i));
1582                 error->ngtier = 4;
1583         } else if (HAS_PCH_SPLIT(i915)) {
1584                 error->ier = intel_uncore_read(uncore, DEIER);
1585                 error->gtier[0] = intel_uncore_read(uncore, GTIER);
1586                 error->ngtier = 1;
1587         } else if (IS_GEN(i915, 2)) {
1588                 error->ier = intel_uncore_read16(uncore, GEN2_IER);
1589         } else if (!IS_VALLEYVIEW(i915)) {
1590                 error->ier = intel_uncore_read(uncore, GEN2_IER);
1591         }
1592         error->eir = intel_uncore_read(uncore, EIR);
1593         error->pgtbl_er = intel_uncore_read(uncore, PGTBL_ER);
1594 }
1595
1596 static const char *
1597 error_msg(struct i915_gpu_state *error,
1598           intel_engine_mask_t engines, const char *msg)
1599 {
1600         int len;
1601
1602         len = scnprintf(error->error_msg, sizeof(error->error_msg),
1603                         "GPU HANG: ecode %d:%x:0x%08x",
1604                         INTEL_GEN(error->i915), engines,
1605                         i915_error_generate_code(error));
1606         if (error->engine) {
1607                 /* Just show the first executing process, more is confusing */
1608                 len += scnprintf(error->error_msg + len,
1609                                  sizeof(error->error_msg) - len,
1610                                  ", in %s [%d]",
1611                                  error->engine->context.comm,
1612                                  error->engine->context.pid);
1613         }
1614         if (msg)
1615                 len += scnprintf(error->error_msg + len,
1616                                  sizeof(error->error_msg) - len,
1617                                  ", %s", msg);
1618
1619         return error->error_msg;
1620 }
1621
1622 static void capture_gen_state(struct i915_gpu_state *error)
1623 {
1624         struct drm_i915_private *i915 = error->i915;
1625
1626         error->awake = i915->gt.awake;
1627         error->wakelock = atomic_read(&i915->runtime_pm.wakeref_count);
1628         error->suspended = i915->runtime_pm.suspended;
1629
1630         error->iommu = -1;
1631 #ifdef CONFIG_INTEL_IOMMU
1632         error->iommu = intel_iommu_gfx_mapped;
1633 #endif
1634         error->reset_count = i915_reset_count(&i915->gpu_error);
1635         error->suspend_count = i915->suspend_count;
1636
1637         memcpy(&error->device_info,
1638                INTEL_INFO(i915),
1639                sizeof(error->device_info));
1640         memcpy(&error->runtime_info,
1641                RUNTIME_INFO(i915),
1642                sizeof(error->runtime_info));
1643         error->driver_caps = i915->caps;
1644 }
1645
1646 static void capture_params(struct i915_gpu_state *error)
1647 {
1648         i915_params_copy(&error->params, &i915_modparams);
1649 }
1650
1651 static unsigned long capture_find_epoch(const struct i915_gpu_state *error)
1652 {
1653         const struct drm_i915_error_engine *ee;
1654         unsigned long epoch = error->capture;
1655
1656         for (ee = error->engine; ee; ee = ee->next) {
1657                 if (ee->hangcheck_timestamp &&
1658                     time_before(ee->hangcheck_timestamp, epoch))
1659                         epoch = ee->hangcheck_timestamp;
1660         }
1661
1662         return epoch;
1663 }
1664
1665 static void capture_finish(struct i915_gpu_state *error)
1666 {
1667         struct i915_ggtt *ggtt = &error->i915->ggtt;
1668         const u64 slot = ggtt->error_capture.start;
1669
1670         ggtt->vm.clear_range(&ggtt->vm, slot, PAGE_SIZE);
1671 }
1672
1673 #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x))
1674
1675 struct i915_gpu_state *
1676 i915_capture_gpu_state(struct drm_i915_private *i915)
1677 {
1678         struct i915_gpu_state *error;
1679         struct compress compress;
1680
1681         /* Check if GPU capture has been disabled */
1682         error = READ_ONCE(i915->gpu_error.first_error);
1683         if (IS_ERR(error))
1684                 return error;
1685
1686         error = kzalloc(sizeof(*error), ALLOW_FAIL);
1687         if (!error) {
1688                 i915_disable_error_state(i915, -ENOMEM);
1689                 return ERR_PTR(-ENOMEM);
1690         }
1691
1692         if (!compress_init(&compress)) {
1693                 kfree(error);
1694                 i915_disable_error_state(i915, -ENOMEM);
1695                 return ERR_PTR(-ENOMEM);
1696         }
1697
1698         kref_init(&error->ref);
1699         error->i915 = i915;
1700
1701         error->time = ktime_get_real();
1702         error->boottime = ktime_get_boottime();
1703         error->uptime = ktime_sub(ktime_get(), i915->gt.last_init_time);
1704         error->capture = jiffies;
1705
1706         capture_params(error);
1707         capture_gen_state(error);
1708         capture_uc_state(error, &compress);
1709         capture_reg_state(error);
1710         gem_record_fences(error);
1711         gem_record_rings(error, &compress);
1712
1713         error->overlay = intel_overlay_capture_error_state(i915);
1714         error->display = intel_display_capture_error_state(i915);
1715
1716         error->epoch = capture_find_epoch(error);
1717
1718         capture_finish(error);
1719         compress_fini(&compress);
1720
1721         return error;
1722 }
1723
1724 /**
1725  * i915_capture_error_state - capture an error record for later analysis
1726  * @i915: i915 device
1727  * @engine_mask: the mask of engines triggering the hang
1728  * @msg: a message to insert into the error capture header
1729  *
1730  * Should be called when an error is detected (either a hang or an error
1731  * interrupt) to capture error state from the time of the error.  Fills
1732  * out a structure which becomes available in debugfs for user level tools
1733  * to pick up.
1734  */
1735 void i915_capture_error_state(struct drm_i915_private *i915,
1736                               intel_engine_mask_t engine_mask,
1737                               const char *msg)
1738 {
1739         static bool warned;
1740         struct i915_gpu_state *error;
1741         unsigned long flags;
1742
1743         if (!i915_modparams.error_capture)
1744                 return;
1745
1746         if (READ_ONCE(i915->gpu_error.first_error))
1747                 return;
1748
1749         error = i915_capture_gpu_state(i915);
1750         if (IS_ERR(error))
1751                 return;
1752
1753         dev_info(i915->drm.dev, "%s\n", error_msg(error, engine_mask, msg));
1754
1755         if (!error->simulated) {
1756                 spin_lock_irqsave(&i915->gpu_error.lock, flags);
1757                 if (!i915->gpu_error.first_error) {
1758                         i915->gpu_error.first_error = error;
1759                         error = NULL;
1760                 }
1761                 spin_unlock_irqrestore(&i915->gpu_error.lock, flags);
1762         }
1763
1764         if (error) {
1765                 __i915_gpu_state_free(&error->ref);
1766                 return;
1767         }
1768
1769         if (!xchg(&warned, true) &&
1770             ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) {
1771                 pr_info("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
1772                 pr_info("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
1773                 pr_info("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
1774                 pr_info("The GPU crash dump is required to analyze GPU hangs, so please always attach it.\n");
1775                 pr_info("GPU crash dump saved to /sys/class/drm/card%d/error\n",
1776                         i915->drm.primary->index);
1777         }
1778 }
1779
1780 struct i915_gpu_state *
1781 i915_first_error_state(struct drm_i915_private *i915)
1782 {
1783         struct i915_gpu_state *error;
1784
1785         spin_lock_irq(&i915->gpu_error.lock);
1786         error = i915->gpu_error.first_error;
1787         if (!IS_ERR_OR_NULL(error))
1788                 i915_gpu_state_get(error);
1789         spin_unlock_irq(&i915->gpu_error.lock);
1790
1791         return error;
1792 }
1793
1794 void i915_reset_error_state(struct drm_i915_private *i915)
1795 {
1796         struct i915_gpu_state *error;
1797
1798         spin_lock_irq(&i915->gpu_error.lock);
1799         error = i915->gpu_error.first_error;
1800         if (error != ERR_PTR(-ENODEV)) /* if disabled, always disabled */
1801                 i915->gpu_error.first_error = NULL;
1802         spin_unlock_irq(&i915->gpu_error.lock);
1803
1804         if (!IS_ERR_OR_NULL(error))
1805                 i915_gpu_state_put(error);
1806 }
1807
1808 void i915_disable_error_state(struct drm_i915_private *i915, int err)
1809 {
1810         spin_lock_irq(&i915->gpu_error.lock);
1811         if (!i915->gpu_error.first_error)
1812                 i915->gpu_error.first_error = ERR_PTR(err);
1813         spin_unlock_irq(&i915->gpu_error.lock);
1814 }