drivers/gpu/drm/i915/i915_getparam.c

   1 /*
   2  * SPDX-License-Identifier: MIT
   3  */
   4
   5 #include "gt/intel_engine_user.h"
   6
   7 #include "i915_drv.h"
   8
   9 int i915_getparam_ioctl(struct drm_device *dev, void *data,
  10                         struct drm_file *file_priv)
  11 {
  12         struct drm_i915_private *i915 = to_i915(dev);
  13         const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
  14         drm_i915_getparam_t *param = data;
  15         int value;
  16
  17         switch (param->param) {
  18         case I915_PARAM_IRQ_ACTIVE:
  19         case I915_PARAM_ALLOW_BATCHBUFFER:
  20         case I915_PARAM_LAST_DISPATCH:
  21         case I915_PARAM_HAS_EXEC_CONSTANTS:
  22                 /* Reject all old ums/dri params. */
  23                 return -ENODEV;
  24         case I915_PARAM_CHIPSET_ID:
  25                 value = i915->drm.pdev->device;
  26                 break;
  27         case I915_PARAM_REVISION:
  28                 value = i915->drm.pdev->revision;
  29                 break;
  30         case I915_PARAM_NUM_FENCES_AVAIL:
  31                 value = i915->ggtt.num_fences;
  32                 break;
  33         case I915_PARAM_HAS_OVERLAY:
  34                 value = !!i915->overlay;
  35                 break;
  36         case I915_PARAM_HAS_BSD:
  37                 value = !!intel_engine_lookup_user(i915,
  38                                                    I915_ENGINE_CLASS_VIDEO, 0);
  39                 break;
  40         case I915_PARAM_HAS_BLT:
  41                 value = !!intel_engine_lookup_user(i915,
  42                                                    I915_ENGINE_CLASS_COPY, 0);
  43                 break;
  44         case I915_PARAM_HAS_VEBOX:
  45                 value = !!intel_engine_lookup_user(i915,
  46                                                    I915_ENGINE_CLASS_VIDEO_ENHANCE, 0);
  47                 break;
  48         case I915_PARAM_HAS_BSD2:
  49                 value = !!intel_engine_lookup_user(i915,
  50                                                    I915_ENGINE_CLASS_VIDEO, 1);
  51                 break;
  52         case I915_PARAM_HAS_LLC:
  53                 value = HAS_LLC(i915);
  54                 break;
  55         case I915_PARAM_HAS_WT:
  56                 value = HAS_WT(i915);
  57                 break;
  58         case I915_PARAM_HAS_ALIASING_PPGTT:
  59                 value = INTEL_PPGTT(i915);
  60                 break;
  61         case I915_PARAM_HAS_SEMAPHORES:
  62                 value = !!(i915->caps.scheduler & I915_SCHEDULER_CAP_SEMAPHORES);
  63                 break;
  64         case I915_PARAM_HAS_SECURE_BATCHES:
  65                 value = HAS_SECURE_BATCHES(i915) && capable(CAP_SYS_ADMIN);
  66                 break;
  67         case I915_PARAM_CMD_PARSER_VERSION:
  68                 value = i915_cmd_parser_get_version(i915);
  69                 break;
  70         case I915_PARAM_SUBSLICE_TOTAL:
  71                 value = intel_sseu_subslice_total(sseu);
  72                 if (!value)
  73                         return -ENODEV;
  74                 break;
  75         case I915_PARAM_EU_TOTAL:
  76                 value = sseu->eu_total;
  77                 if (!value)
  78                         return -ENODEV;
  79                 break;
  80         case I915_PARAM_HAS_GPU_RESET:
  81                 value = i915_modparams.enable_hangcheck &&
  82                         intel_has_gpu_reset(i915);
  83                 if (value && intel_has_reset_engine(i915))
  84                         value = 2;
  85                 break;
  86         case I915_PARAM_HAS_RESOURCE_STREAMER:
  87                 value = 0;
  88                 break;
  89         case I915_PARAM_HAS_POOLED_EU:
  90                 value = HAS_POOLED_EU(i915);
  91                 break;
  92         case I915_PARAM_MIN_EU_IN_POOL:
  93                 value = sseu->min_eu_in_pool;
  94                 break;
  95         case I915_PARAM_HUC_STATUS:
  96                 value = intel_huc_check_status(&i915->gt.uc.huc);
  97                 if (value < 0)
  98                         return value;
  99                 break;
 100         case I915_PARAM_MMAP_GTT_VERSION:
 101                 /* Though we've started our numbering from 1, and so class all
 102                  * earlier versions as 0, in effect their value is undefined as
 103                  * the ioctl will report EINVAL for the unknown param!
 104                  */
 105                 value = i915_gem_mmap_gtt_version();
 106                 break;
 107         case I915_PARAM_HAS_SCHEDULER:
 108                 value = i915->caps.scheduler;
 109                 break;
 110
 111         case I915_PARAM_MMAP_VERSION:
 112                 /* Remember to bump this if the version changes! */
 113         case I915_PARAM_HAS_GEM:
 114         case I915_PARAM_HAS_PAGEFLIPPING:
 115         case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
 116         case I915_PARAM_HAS_RELAXED_FENCING:
 117         case I915_PARAM_HAS_COHERENT_RINGS:
 118         case I915_PARAM_HAS_RELAXED_DELTA:
 119         case I915_PARAM_HAS_GEN7_SOL_RESET:
 120         case I915_PARAM_HAS_WAIT_TIMEOUT:
 121         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 122         case I915_PARAM_HAS_PINNED_BATCHES:
 123         case I915_PARAM_HAS_EXEC_NO_RELOC:
 124         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 125         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 126         case I915_PARAM_HAS_EXEC_SOFTPIN:
 127         case I915_PARAM_HAS_EXEC_ASYNC:
 128         case I915_PARAM_HAS_EXEC_FENCE:
 129         case I915_PARAM_HAS_EXEC_CAPTURE:
 130         case I915_PARAM_HAS_EXEC_BATCH_FIRST:
 131         case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
 132         case I915_PARAM_HAS_EXEC_SUBMIT_FENCE:
 133                 /* For the time being all of these are always true;
 134                  * if some supported hardware does not have one of these
 135                  * features this value needs to be provided from
 136                  * INTEL_INFO(), a feature macro, or similar.
 137                  */
 138                 value = 1;
 139                 break;
 140         case I915_PARAM_HAS_CONTEXT_ISOLATION:
 141                 value = intel_engines_has_context_isolation(i915);
 142                 break;
 143         case I915_PARAM_SLICE_MASK:
 144                 value = sseu->slice_mask;
 145                 if (!value)
 146                         return -ENODEV;
 147                 break;
 148         case I915_PARAM_SUBSLICE_MASK:
 149                 value = sseu->subslice_mask[0];
 150                 if (!value)
 151                         return -ENODEV;
 152                 break;
 153         case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
 154                 value = 1000 * RUNTIME_INFO(i915)->cs_timestamp_frequency_khz;
 155                 break;
 156         case I915_PARAM_MMAP_GTT_COHERENT:
 157                 value = INTEL_INFO(i915)->has_coherent_ggtt;
 158                 break;
 159         default:
 160                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 161                 return -EINVAL;
 162         }
 163
 164         if (put_user(value, param->value))
 165                 return -EFAULT;
 166
 167         return 0;
 168 }