2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * Please try to maintain the following order within this file unless it makes
24 * sense to do otherwise. From top to bottom:
26 * 2. #defines, and macros
27 * 3. structure definitions
28 * 4. function prototypes
30 * Within each section, please try to order by generation in ascending order,
31 * from top to bottom (ie. gen6 on the top, gen8 on the bottom).
34 #ifndef __I915_GEM_GTT_H__
35 #define __I915_GEM_GTT_H__
37 #include <linux/io-mapping.h>
38 #include <linux/kref.h>
40 #include <linux/pagevec.h>
41 #include <linux/workqueue.h>
43 #include <drm/drm_mm.h>
45 #include "gt/intel_reset.h"
46 #include "i915_gem_fence_reg.h"
47 #include "i915_request.h"
48 #include "i915_scatterlist.h"
49 #include "i915_selftest.h"
50 #include "gt/intel_timeline.h"
52 #define I915_GTT_PAGE_SIZE_4K BIT_ULL(12)
53 #define I915_GTT_PAGE_SIZE_64K BIT_ULL(16)
54 #define I915_GTT_PAGE_SIZE_2M BIT_ULL(21)
56 #define I915_GTT_PAGE_SIZE I915_GTT_PAGE_SIZE_4K
57 #define I915_GTT_MAX_PAGE_SIZE I915_GTT_PAGE_SIZE_2M
59 #define I915_GTT_PAGE_MASK -I915_GTT_PAGE_SIZE
61 #define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE
63 #define I915_FENCE_REG_NONE -1
64 #define I915_MAX_NUM_FENCES 32
65 /* 32 fences + sign bit for FENCE_REG_NONE */
66 #define I915_MAX_NUM_FENCE_BITS 6
68 struct drm_i915_file_private;
69 struct drm_i915_gem_object;
73 typedef u32 gen6_pte_t;
74 typedef u64 gen8_pte_t;
76 #define ggtt_total_entries(ggtt) ((ggtt)->vm.total >> PAGE_SHIFT)
78 /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */
79 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
80 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
81 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
82 #define GEN6_PTE_CACHE_LLC (2 << 1)
83 #define GEN6_PTE_UNCACHED (1 << 1)
84 #define GEN6_PTE_VALID (1 << 0)
86 #define I915_PTES(pte_len) ((unsigned int)(PAGE_SIZE / (pte_len)))
87 #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1)
89 #define I915_PDE_MASK (I915_PDES - 1)
90 #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT))
92 #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t))
93 #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE)
94 #define GEN6_PD_ALIGN (PAGE_SIZE * 16)
95 #define GEN6_PDE_SHIFT 22
96 #define GEN6_PDE_VALID (1 << 0)
98 #define GEN7_PTE_CACHE_L3_LLC (3 << 1)
100 #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2)
101 #define BYT_PTE_WRITEABLE (1 << 1)
103 /* Cacheability Control is a 4-bit value. The low three bits are stored in bits
104 * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
106 #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \
107 (((bits) & 0x8) << (11 - 3)))
108 #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2)
109 #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3)
110 #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8)
111 #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb)
112 #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7)
113 #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6)
114 #define HSW_PTE_UNCACHED (0)
115 #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0))
116 #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr)
119 * GEN8 32b style address is defined as a 3 level page table:
120 * 31:30 | 29:21 | 20:12 | 11:0
121 * PDPE | PDE | PTE | offset
122 * The difference as compared to normal x86 3 level page table is the PDPEs are
123 * programmed via register.
125 * GEN8 48b style address is defined as a 4 level page table:
126 * 47:39 | 38:30 | 29:21 | 20:12 | 11:0
127 * PML4E | PDPE | PDE | PTE | offset
129 #define GEN8_3LVL_PDPES 4
131 #define PPAT_UNCACHED (_PAGE_PWT | _PAGE_PCD)
132 #define PPAT_CACHED_PDE 0 /* WB LLC */
133 #define PPAT_CACHED _PAGE_PAT /* WB LLCeLLC */
134 #define PPAT_DISPLAY_ELLC _PAGE_PCD /* WT eLLC */
136 #define CHV_PPAT_SNOOP (1<<6)
137 #define GEN8_PPAT_AGE(x) ((x)<<4)
138 #define GEN8_PPAT_LLCeLLC (3<<2)
139 #define GEN8_PPAT_LLCELLC (2<<2)
140 #define GEN8_PPAT_LLC (1<<2)
141 #define GEN8_PPAT_WB (3<<0)
142 #define GEN8_PPAT_WT (2<<0)
143 #define GEN8_PPAT_WC (1<<0)
144 #define GEN8_PPAT_UC (0<<0)
145 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2)
146 #define GEN8_PPAT(i, x) ((u64)(x) << ((i) * 8))
148 #define GEN8_PDE_IPS_64K BIT(11)
149 #define GEN8_PDE_PS_2M BIT(7)
151 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
152 __for_each_sgt_dma(__dmap, __iter, __sgt, I915_GTT_PAGE_SIZE)
154 struct intel_remapped_plane_info {
156 unsigned int width, height, stride, offset;
159 struct intel_remapped_info {
160 struct intel_remapped_plane_info plane[2];
161 unsigned int unused_mbz;
164 struct intel_rotation_info {
165 struct intel_remapped_plane_info plane[2];
168 struct intel_partial_info {
173 enum i915_ggtt_view_type {
174 I915_GGTT_VIEW_NORMAL = 0,
175 I915_GGTT_VIEW_ROTATED = sizeof(struct intel_rotation_info),
176 I915_GGTT_VIEW_PARTIAL = sizeof(struct intel_partial_info),
177 I915_GGTT_VIEW_REMAPPED = sizeof(struct intel_remapped_info),
180 static inline void assert_i915_gem_gtt_types(void)
182 BUILD_BUG_ON(sizeof(struct intel_rotation_info) != 8*sizeof(unsigned int));
183 BUILD_BUG_ON(sizeof(struct intel_partial_info) != sizeof(u64) + sizeof(unsigned int));
184 BUILD_BUG_ON(sizeof(struct intel_remapped_info) != 9*sizeof(unsigned int));
186 /* Check that rotation/remapped shares offsets for simplicity */
187 BUILD_BUG_ON(offsetof(struct intel_remapped_info, plane[0]) !=
188 offsetof(struct intel_rotation_info, plane[0]));
189 BUILD_BUG_ON(offsetofend(struct intel_remapped_info, plane[1]) !=
190 offsetofend(struct intel_rotation_info, plane[1]));
192 /* As we encode the size of each branch inside the union into its type,
193 * we have to be careful that each branch has a unique size.
195 switch ((enum i915_ggtt_view_type)0) {
196 case I915_GGTT_VIEW_NORMAL:
197 case I915_GGTT_VIEW_PARTIAL:
198 case I915_GGTT_VIEW_ROTATED:
199 case I915_GGTT_VIEW_REMAPPED:
200 /* gcc complains if these are identical cases */
205 struct i915_ggtt_view {
206 enum i915_ggtt_view_type type;
208 /* Members need to contain no holes/padding */
209 struct intel_partial_info partial;
210 struct intel_rotation_info rotated;
211 struct intel_remapped_info remapped;
215 enum i915_cache_level;
219 struct i915_page_dma {
224 /* For gen6/gen7 only. This is the offset in the GGTT
225 * where the page directory entries for PPGTT begin
231 struct i915_page_scratch {
232 struct i915_page_dma base;
236 struct i915_page_table {
237 struct i915_page_dma base;
241 struct i915_page_directory {
242 struct i915_page_table pt;
247 #define __px_choose_expr(x, type, expr, other) \
248 __builtin_choose_expr( \
249 __builtin_types_compatible_p(typeof(x), type) || \
250 __builtin_types_compatible_p(typeof(x), const type), \
251 ({ type __x = (type)(x); expr; }), \
254 #define px_base(px) \
255 __px_choose_expr(px, struct i915_page_dma *, __x, \
256 __px_choose_expr(px, struct i915_page_scratch *, &__x->base, \
257 __px_choose_expr(px, struct i915_page_table *, &__x->base, \
258 __px_choose_expr(px, struct i915_page_directory *, &__x->pt.base, \
260 #define px_dma(px) (px_base(px)->daddr)
263 __px_choose_expr(px, struct i915_page_table *, __x, \
264 __px_choose_expr(px, struct i915_page_directory *, &__x->pt, \
266 #define px_used(px) (&px_pt(px)->used)
268 struct i915_vma_ops {
269 /* Map an object into an address space with the given cache flags. */
270 int (*bind_vma)(struct i915_vma *vma,
271 enum i915_cache_level cache_level,
274 * Unmap an object from an address space. This usually consists of
275 * setting the valid PTE entries to a reserved scratch page.
277 void (*unbind_vma)(struct i915_vma *vma);
279 int (*set_pages)(struct i915_vma *vma);
280 void (*clear_pages)(struct i915_vma *vma);
288 struct i915_address_space {
294 struct drm_i915_private *i915;
296 /* Every address space belongs to a struct file - except for the global
297 * GTT that is owned by the driver (and so @file is set to NULL). In
298 * principle, no information should leak from one context to another
299 * (or between files/processes etc) unless explicitly shared by the
300 * owner. Tracking the owner is important in order to free up per-file
301 * objects along with the file, to aide resource tracking, and to
304 struct drm_i915_file_private *file;
305 u64 total; /* size addr space maps (ex. 2GB for ggtt) */
306 u64 reserved; /* size addr space reserved */
310 struct mutex mutex; /* protects vma and our lists */
311 #define VM_CLASS_GGTT 0
312 #define VM_CLASS_PPGTT 1
314 struct i915_page_scratch scratch[4];
315 unsigned int scratch_order;
319 * List of vma currently bound.
321 struct list_head bound_list;
324 * List of vma that are not unbound.
326 struct list_head unbound_list;
328 struct pagestash free_pages;
333 /* Some systems require uncached updates of the page directories */
336 /* Some systems support read-only mappings for GGTT and/or PPGTT */
337 bool has_read_only:1;
339 u64 (*pte_encode)(dma_addr_t addr,
340 enum i915_cache_level level,
341 u32 flags); /* Create a valid PTE */
342 #define PTE_READ_ONLY (1<<0)
344 int (*allocate_va_range)(struct i915_address_space *vm,
345 u64 start, u64 length);
346 void (*clear_range)(struct i915_address_space *vm,
347 u64 start, u64 length);
348 void (*insert_page)(struct i915_address_space *vm,
351 enum i915_cache_level cache_level,
353 void (*insert_entries)(struct i915_address_space *vm,
354 struct i915_vma *vma,
355 enum i915_cache_level cache_level,
357 void (*cleanup)(struct i915_address_space *vm);
359 struct i915_vma_ops vma_ops;
361 I915_SELFTEST_DECLARE(struct fault_attr fault_attr);
362 I915_SELFTEST_DECLARE(bool scrub_64K);
365 #define i915_is_ggtt(vm) ((vm)->is_ggtt)
368 i915_vm_is_4lvl(const struct i915_address_space *vm)
370 return (vm->total - 1) >> 32;
374 i915_vm_has_scratch_64K(struct i915_address_space *vm)
376 return vm->scratch_order == get_order(I915_GTT_PAGE_SIZE_64K);
379 /* The Graphics Translation Table is the way in which GEN hardware translates a
380 * Graphics Virtual Address into a Physical Address. In addition to the normal
381 * collateral associated with any va->pa translations GEN hardware also has a
382 * portion of the GTT which can be mapped by the CPU and remain both coherent
383 * and correct (in cases like swizzling). That region is referred to as GMADR in
387 struct i915_address_space vm;
389 struct io_mapping iomap; /* Mapping to our CPU mappable region */
390 struct resource gmadr; /* GMADR resource */
391 resource_size_t mappable_end; /* End offset that we can CPU map */
393 /** "Graphics Stolen Memory" holds the global PTEs */
395 void (*invalidate)(struct i915_ggtt *ggtt);
403 unsigned int num_fences;
404 struct i915_fence_reg fence_regs[I915_MAX_NUM_FENCES];
405 struct list_head fence_list;
407 /** List of all objects in gtt_space, currently mmaped by userspace.
408 * All objects within this list must also be on bound_list.
410 struct list_head userfault_list;
412 /* Manual runtime pm autosuspend delay for user GGTT mmaps */
413 struct intel_wakeref_auto userfault_wakeref;
415 struct drm_mm_node error_capture;
416 struct drm_mm_node uc_fw;
420 struct i915_address_space vm;
422 intel_engine_mask_t pd_dirty_engines;
423 struct i915_page_directory *pd;
427 struct i915_ppgtt base;
429 struct i915_vma *vma;
430 gen6_pte_t __iomem *pd_addr;
432 unsigned int pin_count;
433 bool scan_for_unused_pt;
436 #define __to_gen6_ppgtt(base) container_of(base, struct gen6_ppgtt, base)
438 static inline struct gen6_ppgtt *to_gen6_ppgtt(struct i915_ppgtt *base)
440 BUILD_BUG_ON(offsetof(struct gen6_ppgtt, base));
441 return __to_gen6_ppgtt(base);
445 * gen6_for_each_pde() iterates over every pde from start until start+length.
446 * If start and start+length are not perfectly divisible, the macro will round
447 * down and up as needed. Start=0 and length=2G effectively iterates over
448 * every PDE in the system. The macro modifies ALL its parameters except 'pd',
449 * so each of the other parameters should preferably be a simple variable, or
450 * at most an lvalue with no side-effects!
452 #define gen6_for_each_pde(pt, pd, start, length, iter) \
453 for (iter = gen6_pde_index(start); \
454 length > 0 && iter < I915_PDES && \
455 (pt = i915_pt_entry(pd, iter), true); \
456 ({ u32 temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT); \
457 temp = min(temp - start, length); \
458 start += temp, length -= temp; }), ++iter)
460 #define gen6_for_all_pdes(pt, pd, iter) \
462 iter < I915_PDES && \
463 (pt = i915_pt_entry(pd, iter), true); \
466 static inline u32 i915_pte_index(u64 address, unsigned int pde_shift)
468 const u32 mask = NUM_PTE(pde_shift) - 1;
470 return (address >> PAGE_SHIFT) & mask;
473 /* Helper to counts the number of PTEs within the given length. This count
474 * does not cross a page table boundary, so the max value would be
475 * GEN6_PTES for GEN6, and GEN8_PTES for GEN8.
477 static inline u32 i915_pte_count(u64 addr, u64 length, unsigned int pde_shift)
479 const u64 mask = ~((1ULL << pde_shift) - 1);
482 GEM_BUG_ON(length == 0);
483 GEM_BUG_ON(offset_in_page(addr | length));
487 if ((addr & mask) != (end & mask))
488 return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift);
490 return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift);
493 static inline u32 i915_pde_index(u64 addr, u32 shift)
495 return (addr >> shift) & I915_PDE_MASK;
498 static inline u32 gen6_pte_index(u32 addr)
500 return i915_pte_index(addr, GEN6_PDE_SHIFT);
503 static inline u32 gen6_pte_count(u32 addr, u32 length)
505 return i915_pte_count(addr, length, GEN6_PDE_SHIFT);
508 static inline u32 gen6_pde_index(u32 addr)
510 return i915_pde_index(addr, GEN6_PDE_SHIFT);
513 static inline struct i915_page_table *
514 i915_pt_entry(const struct i915_page_directory * const pd,
515 const unsigned short n)
520 static inline struct i915_page_directory *
521 i915_pd_entry(const struct i915_page_directory * const pdp,
522 const unsigned short n)
524 return pdp->entry[n];
527 static inline dma_addr_t
528 i915_page_dir_dma_addr(const struct i915_ppgtt *ppgtt, const unsigned int n)
530 struct i915_page_dma *pt = ppgtt->pd->entry[n];
532 return px_dma(pt ?: px_base(&ppgtt->vm.scratch[ppgtt->vm.top]));
535 static inline struct i915_ggtt *
536 i915_vm_to_ggtt(struct i915_address_space *vm)
538 BUILD_BUG_ON(offsetof(struct i915_ggtt, vm));
539 GEM_BUG_ON(!i915_is_ggtt(vm));
540 return container_of(vm, struct i915_ggtt, vm);
543 static inline struct i915_ppgtt *
544 i915_vm_to_ppgtt(struct i915_address_space *vm)
546 BUILD_BUG_ON(offsetof(struct i915_ppgtt, vm));
547 GEM_BUG_ON(i915_is_ggtt(vm));
548 return container_of(vm, struct i915_ppgtt, vm);
551 int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv);
552 int i915_ggtt_init_hw(struct drm_i915_private *dev_priv);
553 int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv);
554 void i915_ggtt_enable_guc(struct i915_ggtt *ggtt);
555 void i915_ggtt_disable_guc(struct i915_ggtt *ggtt);
556 int i915_init_ggtt(struct drm_i915_private *dev_priv);
557 void i915_ggtt_driver_release(struct drm_i915_private *dev_priv);
559 int i915_ppgtt_init_hw(struct intel_gt *gt);
561 struct i915_ppgtt *i915_ppgtt_create(struct drm_i915_private *dev_priv);
563 static inline struct i915_address_space *
564 i915_vm_get(struct i915_address_space *vm)
570 void i915_vm_release(struct kref *kref);
572 static inline void i915_vm_put(struct i915_address_space *vm)
574 kref_put(&vm->ref, i915_vm_release);
577 int gen6_ppgtt_pin(struct i915_ppgtt *base);
578 void gen6_ppgtt_unpin(struct i915_ppgtt *base);
579 void gen6_ppgtt_unpin_all(struct i915_ppgtt *base);
581 void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv);
582 void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv);
584 int __must_check i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj,
585 struct sg_table *pages);
586 void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj,
587 struct sg_table *pages);
589 int i915_gem_gtt_reserve(struct i915_address_space *vm,
590 struct drm_mm_node *node,
591 u64 size, u64 offset, unsigned long color,
594 int i915_gem_gtt_insert(struct i915_address_space *vm,
595 struct drm_mm_node *node,
596 u64 size, u64 alignment, unsigned long color,
597 u64 start, u64 end, unsigned int flags);
599 /* Flags used by pin/bind&friends. */
600 #define PIN_NONBLOCK BIT_ULL(0)
601 #define PIN_NONFAULT BIT_ULL(1)
602 #define PIN_NOEVICT BIT_ULL(2)
603 #define PIN_MAPPABLE BIT_ULL(3)
604 #define PIN_ZONE_4G BIT_ULL(4)
605 #define PIN_HIGH BIT_ULL(5)
606 #define PIN_OFFSET_BIAS BIT_ULL(6)
607 #define PIN_OFFSET_FIXED BIT_ULL(7)
609 #define PIN_MBZ BIT_ULL(8) /* I915_VMA_PIN_OVERFLOW */
610 #define PIN_GLOBAL BIT_ULL(9) /* I915_VMA_GLOBAL_BIND */
611 #define PIN_USER BIT_ULL(10) /* I915_VMA_LOCAL_BIND */
612 #define PIN_UPDATE BIT_ULL(11)
614 #define PIN_OFFSET_MASK (-I915_GTT_PAGE_SIZE)