drivers/gpu/drm/i915/i915_gem_gtt.c

   1 /*
   2  * Copyright © 2010 Daniel Vetter
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <drm/drmP.h>
  26 #include <drm/i915_drm.h>
  27 #include "i915_drv.h"
  28 #include "i915_trace.h"
  29 #include "intel_drv.h"
  30
  31 #define GEN6_PPGTT_PD_ENTRIES 512
  32 #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t))
  33 typedef uint64_t gen8_gtt_pte_t;
  34 typedef gen8_gtt_pte_t gen8_ppgtt_pde_t;
  35
  36 /* PPGTT stuff */
  37 #define GEN6_GTT_ADDR_ENCODE(addr)      ((addr) | (((addr) >> 28) & 0xff0))
  38 #define HSW_GTT_ADDR_ENCODE(addr)       ((addr) | (((addr) >> 28) & 0x7f0))
  39
  40 #define GEN6_PDE_VALID                  (1 << 0)
  41 /* gen6+ has bit 11-4 for physical addr bit 39-32 */
  42 #define GEN6_PDE_ADDR_ENCODE(addr)      GEN6_GTT_ADDR_ENCODE(addr)
  43
  44 #define GEN6_PTE_VALID                  (1 << 0)
  45 #define GEN6_PTE_UNCACHED               (1 << 1)
  46 #define HSW_PTE_UNCACHED                (0)
  47 #define GEN6_PTE_CACHE_LLC              (2 << 1)
  48 #define GEN7_PTE_CACHE_L3_LLC           (3 << 1)
  49 #define GEN6_PTE_ADDR_ENCODE(addr)      GEN6_GTT_ADDR_ENCODE(addr)
  50 #define HSW_PTE_ADDR_ENCODE(addr)       HSW_GTT_ADDR_ENCODE(addr)
  51
  52 /* Cacheability Control is a 4-bit value. The low three bits are stored in *
  53  * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
  54  */
  55 #define HSW_CACHEABILITY_CONTROL(bits)  ((((bits) & 0x7) << 1) | \
  56                                          (((bits) & 0x8) << (11 - 3)))
  57 #define HSW_WB_LLC_AGE3                 HSW_CACHEABILITY_CONTROL(0x2)
  58 #define HSW_WB_LLC_AGE0                 HSW_CACHEABILITY_CONTROL(0x3)
  59 #define HSW_WB_ELLC_LLC_AGE0            HSW_CACHEABILITY_CONTROL(0xb)
  60 #define HSW_WB_ELLC_LLC_AGE3            HSW_CACHEABILITY_CONTROL(0x8)
  61 #define HSW_WT_ELLC_LLC_AGE0            HSW_CACHEABILITY_CONTROL(0x6)
  62 #define HSW_WT_ELLC_LLC_AGE3            HSW_CACHEABILITY_CONTROL(0x7)
  63
  64 #define GEN8_PTES_PER_PAGE              (PAGE_SIZE / sizeof(gen8_gtt_pte_t))
  65 #define GEN8_PDES_PER_PAGE              (PAGE_SIZE / sizeof(gen8_ppgtt_pde_t))
  66 #define GEN8_LEGACY_PDPS                4
  67
  68 #define PPAT_UNCACHED_INDEX             (_PAGE_PWT | _PAGE_PCD)
  69 #define PPAT_CACHED_PDE_INDEX           0 /* WB LLC */
  70 #define PPAT_CACHED_INDEX               _PAGE_PAT /* WB LLCeLLC */
  71 #define PPAT_DISPLAY_ELLC_INDEX         _PAGE_PCD /* WT eLLC */
  72
  73 static void ppgtt_bind_vma(struct i915_vma *vma,
  74                            enum i915_cache_level cache_level,
  75                            u32 flags);
  76 static void ppgtt_unbind_vma(struct i915_vma *vma);
  77 static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt);
  78
  79 static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr,
  80                                              enum i915_cache_level level,
  81                                              bool valid)
  82 {
  83         gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
  84         pte |= addr;
  85         if (level != I915_CACHE_NONE)
  86                 pte |= PPAT_CACHED_INDEX;
  87         else
  88                 pte |= PPAT_UNCACHED_INDEX;
  89         return pte;
  90 }
  91
  92 static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev,
  93                                              dma_addr_t addr,
  94                                              enum i915_cache_level level)
  95 {
  96         gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
  97         pde |= addr;
  98         if (level != I915_CACHE_NONE)
  99                 pde |= PPAT_CACHED_PDE_INDEX;
 100         else
 101                 pde |= PPAT_UNCACHED_INDEX;
 102         return pde;
 103 }
 104
 105 static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr,
 106                                      enum i915_cache_level level,
 107                                      bool valid)
 108 {
 109         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 110         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 111
 112         switch (level) {
 113         case I915_CACHE_L3_LLC:
 114         case I915_CACHE_LLC:
 115                 pte |= GEN6_PTE_CACHE_LLC;
 116                 break;
 117         case I915_CACHE_NONE:
 118                 pte |= GEN6_PTE_UNCACHED;
 119                 break;
 120         default:
 121                 WARN_ON(1);
 122         }
 123
 124         return pte;
 125 }
 126
 127 static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr,
 128                                      enum i915_cache_level level,
 129                                      bool valid)
 130 {
 131         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 132         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 133
 134         switch (level) {
 135         case I915_CACHE_L3_LLC:
 136                 pte |= GEN7_PTE_CACHE_L3_LLC;
 137                 break;
 138         case I915_CACHE_LLC:
 139                 pte |= GEN6_PTE_CACHE_LLC;
 140                 break;
 141         case I915_CACHE_NONE:
 142                 pte |= GEN6_PTE_UNCACHED;
 143                 break;
 144         default:
 145                 WARN_ON(1);
 146         }
 147
 148         return pte;
 149 }
 150
 151 #define BYT_PTE_WRITEABLE               (1 << 1)
 152 #define BYT_PTE_SNOOPED_BY_CPU_CACHES   (1 << 2)
 153
 154 static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr,
 155                                      enum i915_cache_level level,
 156                                      bool valid)
 157 {
 158         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 159         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 160
 161         /* Mark the page as writeable.  Other platforms don't have a
 162          * setting for read-only/writable, so this matches that behavior.
 163          */
 164         pte |= BYT_PTE_WRITEABLE;
 165
 166         if (level != I915_CACHE_NONE)
 167                 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
 168
 169         return pte;
 170 }
 171
 172 static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr,
 173                                      enum i915_cache_level level,
 174                                      bool valid)
 175 {
 176         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 177         pte |= HSW_PTE_ADDR_ENCODE(addr);
 178
 179         if (level != I915_CACHE_NONE)
 180                 pte |= HSW_WB_LLC_AGE3;
 181
 182         return pte;
 183 }
 184
 185 static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
 186                                       enum i915_cache_level level,
 187                                       bool valid)
 188 {
 189         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 190         pte |= HSW_PTE_ADDR_ENCODE(addr);
 191
 192         switch (level) {
 193         case I915_CACHE_NONE:
 194                 break;
 195         case I915_CACHE_WT:
 196                 pte |= HSW_WT_ELLC_LLC_AGE3;
 197                 break;
 198         default:
 199                 pte |= HSW_WB_ELLC_LLC_AGE3;
 200                 break;
 201         }
 202
 203         return pte;
 204 }
 205
 206 /* Broadwell Page Directory Pointer Descriptors */
 207 static int gen8_write_pdp(struct intel_ring_buffer *ring, unsigned entry,
 208                            uint64_t val, bool synchronous)
 209 {
 210         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 211         int ret;
 212
 213         BUG_ON(entry >= 4);
 214
 215         if (synchronous) {
 216                 I915_WRITE(GEN8_RING_PDP_UDW(ring, entry), val >> 32);
 217                 I915_WRITE(GEN8_RING_PDP_LDW(ring, entry), (u32)val);
 218                 return 0;
 219         }
 220
 221         ret = intel_ring_begin(ring, 6);
 222         if (ret)
 223                 return ret;
 224
 225         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 226         intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
 227         intel_ring_emit(ring, (u32)(val >> 32));
 228         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 229         intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
 230         intel_ring_emit(ring, (u32)(val));
 231         intel_ring_advance(ring);
 232
 233         return 0;
 234 }
 235
 236 static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
 237                           struct intel_ring_buffer *ring,
 238                           bool synchronous)
 239 {
 240         int i, ret;
 241
 242         /* bit of a hack to find the actual last used pd */
 243         int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE;
 244
 245         for (i = used_pd - 1; i >= 0; i--) {
 246                 dma_addr_t addr = ppgtt->pd_dma_addr[i];
 247                 ret = gen8_write_pdp(ring, i, addr, synchronous);
 248                 if (ret)
 249                         return ret;
 250         }
 251
 252         return 0;
 253 }
 254
 255 static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
 256                                    unsigned first_entry,
 257                                    unsigned num_entries,
 258                                    bool use_scratch)
 259 {
 260         struct i915_hw_ppgtt *ppgtt =
 261                 container_of(vm, struct i915_hw_ppgtt, base);
 262         gen8_gtt_pte_t *pt_vaddr, scratch_pte;
 263         unsigned act_pt = first_entry / GEN8_PTES_PER_PAGE;
 264         unsigned first_pte = first_entry % GEN8_PTES_PER_PAGE;
 265         unsigned last_pte, i;
 266
 267         scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr,
 268                                       I915_CACHE_LLC, use_scratch);
 269
 270         while (num_entries) {
 271                 struct page *page_table = &ppgtt->gen8_pt_pages[act_pt];
 272
 273                 last_pte = first_pte + num_entries;
 274                 if (last_pte > GEN8_PTES_PER_PAGE)
 275                         last_pte = GEN8_PTES_PER_PAGE;
 276
 277                 pt_vaddr = kmap_atomic(page_table);
 278
 279                 for (i = first_pte; i < last_pte; i++)
 280                         pt_vaddr[i] = scratch_pte;
 281
 282                 kunmap_atomic(pt_vaddr);
 283
 284                 num_entries -= last_pte - first_pte;
 285                 first_pte = 0;
 286                 act_pt++;
 287         }
 288 }
 289
 290 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
 291                                       struct sg_table *pages,
 292                                       unsigned first_entry,
 293                                       enum i915_cache_level cache_level)
 294 {
 295         struct i915_hw_ppgtt *ppgtt =
 296                 container_of(vm, struct i915_hw_ppgtt, base);
 297         gen8_gtt_pte_t *pt_vaddr;
 298         unsigned act_pt = first_entry / GEN8_PTES_PER_PAGE;
 299         unsigned act_pte = first_entry % GEN8_PTES_PER_PAGE;
 300         struct sg_page_iter sg_iter;
 301
 302         pt_vaddr = kmap_atomic(&ppgtt->gen8_pt_pages[act_pt]);
 303         for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
 304                 dma_addr_t page_addr;
 305
 306                 page_addr = sg_dma_address(sg_iter.sg) +
 307                                 (sg_iter.sg_pgoffset << PAGE_SHIFT);
 308                 pt_vaddr[act_pte] = gen8_pte_encode(page_addr, cache_level,
 309                                                     true);
 310                 if (++act_pte == GEN8_PTES_PER_PAGE) {
 311                         kunmap_atomic(pt_vaddr);
 312                         act_pt++;
 313                         pt_vaddr = kmap_atomic(&ppgtt->gen8_pt_pages[act_pt]);
 314                         act_pte = 0;
 315
 316                 }
 317         }
 318         kunmap_atomic(pt_vaddr);
 319 }
 320
 321 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
 322 {
 323         struct i915_hw_ppgtt *ppgtt =
 324                 container_of(vm, struct i915_hw_ppgtt, base);
 325         int i, j;
 326
 327         list_del(&vm->global_link);
 328         drm_mm_takedown(&vm->mm);
 329
 330         for (i = 0; i < ppgtt->num_pd_pages ; i++) {
 331                 if (ppgtt->pd_dma_addr[i]) {
 332                         pci_unmap_page(ppgtt->base.dev->pdev,
 333                                        ppgtt->pd_dma_addr[i],
 334                                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 335
 336                         for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
 337                                 dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
 338                                 if (addr)
 339                                         pci_unmap_page(ppgtt->base.dev->pdev,
 340                                                        addr,
 341                                                        PAGE_SIZE,
 342                                                        PCI_DMA_BIDIRECTIONAL);
 343
 344                         }
 345                 }
 346                 kfree(ppgtt->gen8_pt_dma_addr[i]);
 347         }
 348
 349         __free_pages(ppgtt->gen8_pt_pages, get_order(ppgtt->num_pt_pages << PAGE_SHIFT));
 350         __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT));
 351 }
 352
 353 /**
 354  * GEN8 legacy ppgtt programming is accomplished through 4 PDP registers with a
 355  * net effect resembling a 2-level page table in normal x86 terms. Each PDP
 356  * represents 1GB of memory
 357  * 4 * 512 * 512 * 4096 = 4GB legacy 32b address space.
 358  *
 359  * TODO: Do something with the size parameter
 360  **/
 361 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
 362 {
 363         struct page *pt_pages;
 364         int i, j, ret = -ENOMEM;
 365         const int max_pdp = DIV_ROUND_UP(size, 1 << 30);
 366         const int num_pt_pages = GEN8_PDES_PER_PAGE * max_pdp;
 367
 368         if (size % (1<<30))
 369                 DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size);
 370
 371         /* FIXME: split allocation into smaller pieces. For now we only ever do
 372          * this once, but with full PPGTT, the multiple contiguous allocations
 373          * will be bad.
 374          */
 375         ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT));
 376         if (!ppgtt->pd_pages)
 377                 return -ENOMEM;
 378
 379         pt_pages = alloc_pages(GFP_KERNEL, get_order(num_pt_pages << PAGE_SHIFT));
 380         if (!pt_pages) {
 381                 __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT));
 382                 return -ENOMEM;
 383         }
 384
 385         ppgtt->gen8_pt_pages = pt_pages;
 386         ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT);
 387         ppgtt->num_pt_pages = 1 << get_order(num_pt_pages << PAGE_SHIFT);
 388         ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE;
 389         ppgtt->enable = gen8_ppgtt_enable;
 390         ppgtt->switch_mm = gen8_mm_switch;
 391         ppgtt->base.clear_range = gen8_ppgtt_clear_range;
 392         ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
 393         ppgtt->base.cleanup = gen8_ppgtt_cleanup;
 394         ppgtt->base.start = 0;
 395         ppgtt->base.total = ppgtt->num_pt_pages * GEN8_PTES_PER_PAGE * PAGE_SIZE;
 396
 397         BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS);
 398
 399         /*
 400          * - Create a mapping for the page directories.
 401          * - For each page directory:
 402          *      allocate space for page table mappings.
 403          *      map each page table
 404          */
 405         for (i = 0; i < max_pdp; i++) {
 406                 dma_addr_t temp;
 407                 temp = pci_map_page(ppgtt->base.dev->pdev,
 408                                     &ppgtt->pd_pages[i], 0,
 409                                     PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 410                 if (pci_dma_mapping_error(ppgtt->base.dev->pdev, temp))
 411                         goto err_out;
 412
 413                 ppgtt->pd_dma_addr[i] = temp;
 414
 415                 ppgtt->gen8_pt_dma_addr[i] = kmalloc(sizeof(dma_addr_t) * GEN8_PDES_PER_PAGE, GFP_KERNEL);
 416                 if (!ppgtt->gen8_pt_dma_addr[i])
 417                         goto err_out;
 418
 419                 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
 420                         struct page *p = &pt_pages[i * GEN8_PDES_PER_PAGE + j];
 421                         temp = pci_map_page(ppgtt->base.dev->pdev,
 422                                             p, 0, PAGE_SIZE,
 423                                             PCI_DMA_BIDIRECTIONAL);
 424
 425                         if (pci_dma_mapping_error(ppgtt->base.dev->pdev, temp))
 426                                 goto err_out;
 427
 428                         ppgtt->gen8_pt_dma_addr[i][j] = temp;
 429                 }
 430         }
 431
 432         /* For now, the PPGTT helper functions all require that the PDEs are
 433          * plugged in correctly. So we do that now/here. For aliasing PPGTT, we
 434          * will never need to touch the PDEs again */
 435         for (i = 0; i < max_pdp; i++) {
 436                 gen8_ppgtt_pde_t *pd_vaddr;
 437                 pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]);
 438                 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
 439                         dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
 440                         pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr,
 441                                                       I915_CACHE_LLC);
 442                 }
 443                 kunmap_atomic(pd_vaddr);
 444         }
 445
 446         ppgtt->base.clear_range(&ppgtt->base, 0,
 447                                 ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE,
 448                                 true);
 449
 450         DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n",
 451                          ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp);
 452         DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n",
 453                          ppgtt->num_pt_pages,
 454                          (ppgtt->num_pt_pages - num_pt_pages) +
 455                          size % (1<<30));
 456         return 0;
 457
 458 err_out:
 459         ppgtt->base.cleanup(&ppgtt->base);
 460         return ret;
 461 }
 462
 463 static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt)
 464 {
 465         struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
 466         gen6_gtt_pte_t __iomem *pd_addr;
 467         uint32_t pd_entry;
 468         int i;
 469
 470         WARN_ON(ppgtt->pd_offset & 0x3f);
 471         pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm +
 472                 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
 473         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 474                 dma_addr_t pt_addr;
 475
 476                 pt_addr = ppgtt->pt_dma_addr[i];
 477                 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
 478                 pd_entry |= GEN6_PDE_VALID;
 479
 480                 writel(pd_entry, pd_addr + i);
 481         }
 482         readl(pd_addr);
 483 }
 484
 485 static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
 486 {
 487         BUG_ON(ppgtt->pd_offset & 0x3f);
 488
 489         return (ppgtt->pd_offset / 64) << 16;
 490 }
 491
 492 static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
 493                          struct intel_ring_buffer *ring,
 494                          bool synchronous)
 495 {
 496         struct drm_device *dev = ppgtt->base.dev;
 497         struct drm_i915_private *dev_priv = dev->dev_private;
 498         int ret;
 499
 500         /* If we're in reset, we can assume the GPU is sufficiently idle to
 501          * manually frob these bits. Ideally we could use the ring functions,
 502          * except our error handling makes it quite difficult (can't use
 503          * intel_ring_begin, ring->flush, or intel_ring_advance)
 504          *
 505          * FIXME: We should try not to special case reset
 506          */
 507         if (synchronous ||
 508             i915_reset_in_progress(&dev_priv->gpu_error)) {
 509                 WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt);
 510                 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
 511                 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
 512                 POSTING_READ(RING_PP_DIR_BASE(ring));
 513                 return 0;
 514         }
 515
 516         /* NB: TLBs must be flushed and invalidated before a switch */
 517         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
 518         if (ret)
 519                 return ret;
 520
 521         ret = intel_ring_begin(ring, 6);
 522         if (ret)
 523                 return ret;
 524
 525         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
 526         intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
 527         intel_ring_emit(ring, PP_DIR_DCLV_2G);
 528         intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
 529         intel_ring_emit(ring, get_pd_offset(ppgtt));
 530         intel_ring_emit(ring, MI_NOOP);
 531         intel_ring_advance(ring);
 532
 533         return 0;
 534 }
 535
 536 static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
 537                           struct intel_ring_buffer *ring,
 538                           bool synchronous)
 539 {
 540         struct drm_device *dev = ppgtt->base.dev;
 541         struct drm_i915_private *dev_priv = dev->dev_private;
 542         int ret;
 543
 544         /* If we're in reset, we can assume the GPU is sufficiently idle to
 545          * manually frob these bits. Ideally we could use the ring functions,
 546          * except our error handling makes it quite difficult (can't use
 547          * intel_ring_begin, ring->flush, or intel_ring_advance)
 548          *
 549          * FIXME: We should try not to special case reset
 550          */
 551         if (synchronous ||
 552             i915_reset_in_progress(&dev_priv->gpu_error)) {
 553                 WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt);
 554                 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
 555                 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
 556                 POSTING_READ(RING_PP_DIR_BASE(ring));
 557                 return 0;
 558         }
 559
 560         /* NB: TLBs must be flushed and invalidated before a switch */
 561         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
 562         if (ret)
 563                 return ret;
 564
 565         ret = intel_ring_begin(ring, 6);
 566         if (ret)
 567                 return ret;
 568
 569         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
 570         intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
 571         intel_ring_emit(ring, PP_DIR_DCLV_2G);
 572         intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
 573         intel_ring_emit(ring, get_pd_offset(ppgtt));
 574         intel_ring_emit(ring, MI_NOOP);
 575         intel_ring_advance(ring);
 576
 577         /* XXX: RCS is the only one to auto invalidate the TLBs? */
 578         if (ring->id != RCS) {
 579                 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
 580                 if (ret)
 581                         return ret;
 582         }
 583
 584         return 0;
 585 }
 586
 587 static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
 588                           struct intel_ring_buffer *ring,
 589                           bool synchronous)
 590 {
 591         struct drm_device *dev = ppgtt->base.dev;
 592         struct drm_i915_private *dev_priv = dev->dev_private;
 593
 594         if (!synchronous)
 595                 return 0;
 596
 597         I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
 598         I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
 599
 600         POSTING_READ(RING_PP_DIR_DCLV(ring));
 601
 602         return 0;
 603 }
 604
 605 static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt)
 606 {
 607         struct drm_device *dev = ppgtt->base.dev;
 608         struct drm_i915_private *dev_priv = dev->dev_private;
 609         struct intel_ring_buffer *ring;
 610         int j, ret;
 611
 612         for_each_ring(ring, dev_priv, j) {
 613                 I915_WRITE(RING_MODE_GEN7(ring),
 614                            _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 615                 ret = ppgtt->switch_mm(ppgtt, ring, true);
 616                 if (ret)
 617                         goto err_out;
 618         }
 619
 620         return 0;
 621
 622 err_out:
 623         for_each_ring(ring, dev_priv, j)
 624                 I915_WRITE(RING_MODE_GEN7(ring),
 625                            _MASKED_BIT_DISABLE(GFX_PPGTT_ENABLE));
 626         return ret;
 627 }
 628
 629 static int gen7_ppgtt_enable(struct i915_hw_ppgtt *ppgtt)
 630 {
 631         struct drm_device *dev = ppgtt->base.dev;
 632         drm_i915_private_t *dev_priv = dev->dev_private;
 633         struct intel_ring_buffer *ring;
 634         uint32_t ecochk, ecobits;
 635         int i;
 636
 637         ecobits = I915_READ(GAC_ECO_BITS);
 638         I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
 639
 640         ecochk = I915_READ(GAM_ECOCHK);
 641         if (IS_HASWELL(dev)) {
 642                 ecochk |= ECOCHK_PPGTT_WB_HSW;
 643         } else {
 644                 ecochk |= ECOCHK_PPGTT_LLC_IVB;
 645                 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
 646         }
 647         I915_WRITE(GAM_ECOCHK, ecochk);
 648
 649         for_each_ring(ring, dev_priv, i) {
 650                 int ret;
 651                 /* GFX_MODE is per-ring on gen7+ */
 652                 I915_WRITE(RING_MODE_GEN7(ring),
 653                            _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 654                 ret = ppgtt->switch_mm(ppgtt, ring, true);
 655                 if (ret)
 656                         return ret;
 657
 658         }
 659         return 0;
 660 }
 661
 662 static int gen6_ppgtt_enable(struct i915_hw_ppgtt *ppgtt)
 663 {
 664         struct drm_device *dev = ppgtt->base.dev;
 665         drm_i915_private_t *dev_priv = dev->dev_private;
 666         struct intel_ring_buffer *ring;
 667         uint32_t ecochk, gab_ctl, ecobits;
 668         int i;
 669
 670         ecobits = I915_READ(GAC_ECO_BITS);
 671         I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
 672                    ECOBITS_PPGTT_CACHE64B);
 673
 674         gab_ctl = I915_READ(GAB_CTL);
 675         I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
 676
 677         ecochk = I915_READ(GAM_ECOCHK);
 678         I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
 679
 680         I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 681
 682         for_each_ring(ring, dev_priv, i) {
 683                 int ret = ppgtt->switch_mm(ppgtt, ring, true);
 684                 if (ret)
 685                         return ret;
 686         }
 687
 688         return 0;
 689 }
 690
 691 /* PPGTT support for Sandybdrige/Gen6 and later */
 692 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
 693                                    unsigned first_entry,
 694                                    unsigned num_entries,
 695                                    bool use_scratch)
 696 {
 697         struct i915_hw_ppgtt *ppgtt =
 698                 container_of(vm, struct i915_hw_ppgtt, base);
 699         gen6_gtt_pte_t *pt_vaddr, scratch_pte;
 700         unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
 701         unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
 702         unsigned last_pte, i;
 703
 704         scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true);
 705
 706         while (num_entries) {
 707                 last_pte = first_pte + num_entries;
 708                 if (last_pte > I915_PPGTT_PT_ENTRIES)
 709                         last_pte = I915_PPGTT_PT_ENTRIES;
 710
 711                 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 712
 713                 for (i = first_pte; i < last_pte; i++)
 714                         pt_vaddr[i] = scratch_pte;
 715
 716                 kunmap_atomic(pt_vaddr);
 717
 718                 num_entries -= last_pte - first_pte;
 719                 first_pte = 0;
 720                 act_pt++;
 721         }
 722 }
 723
 724 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
 725                                       struct sg_table *pages,
 726                                       unsigned first_entry,
 727                                       enum i915_cache_level cache_level)
 728 {
 729         struct i915_hw_ppgtt *ppgtt =
 730                 container_of(vm, struct i915_hw_ppgtt, base);
 731         gen6_gtt_pte_t *pt_vaddr;
 732         unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
 733         unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES;
 734         struct sg_page_iter sg_iter;
 735
 736         pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 737         for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
 738                 dma_addr_t page_addr;
 739
 740                 page_addr = sg_page_iter_dma_address(&sg_iter);
 741                 pt_vaddr[act_pte] = vm->pte_encode(page_addr, cache_level, true);
 742                 if (++act_pte == I915_PPGTT_PT_ENTRIES) {
 743                         kunmap_atomic(pt_vaddr);
 744                         act_pt++;
 745                         pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 746                         act_pte = 0;
 747
 748                 }
 749         }
 750         kunmap_atomic(pt_vaddr);
 751 }
 752
 753 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
 754 {
 755         struct i915_hw_ppgtt *ppgtt =
 756                 container_of(vm, struct i915_hw_ppgtt, base);
 757         int i;
 758
 759         list_del(&vm->global_link);
 760         drm_mm_takedown(&ppgtt->base.mm);
 761         drm_mm_remove_node(&ppgtt->node);
 762
 763         if (ppgtt->pt_dma_addr) {
 764                 for (i = 0; i < ppgtt->num_pd_entries; i++)
 765                         pci_unmap_page(ppgtt->base.dev->pdev,
 766                                        ppgtt->pt_dma_addr[i],
 767                                        4096, PCI_DMA_BIDIRECTIONAL);
 768         }
 769
 770         kfree(ppgtt->pt_dma_addr);
 771         for (i = 0; i < ppgtt->num_pd_entries; i++)
 772                 __free_page(ppgtt->pt_pages[i]);
 773         kfree(ppgtt->pt_pages);
 774         kfree(ppgtt);
 775 }
 776
 777 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
 778 {
 779 #define GEN6_PD_ALIGN (PAGE_SIZE * 16)
 780 #define GEN6_PD_SIZE (GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE)
 781         struct drm_device *dev = ppgtt->base.dev;
 782         struct drm_i915_private *dev_priv = dev->dev_private;
 783         bool retried = false;
 784         int i, ret;
 785
 786         /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
 787          * allocator works in address space sizes, so it's multiplied by page
 788          * size. We allocate at the top of the GTT to avoid fragmentation.
 789          */
 790         BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
 791 alloc:
 792         ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
 793                                                   &ppgtt->node, GEN6_PD_SIZE,
 794                                                   GEN6_PD_ALIGN, 0,
 795                                                   0, dev_priv->gtt.base.total,
 796                                                   DRM_MM_SEARCH_DEFAULT);
 797         if (ret == -ENOSPC && !retried) {
 798                 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
 799                                                GEN6_PD_SIZE, GEN6_PD_ALIGN,
 800                                                I915_CACHE_NONE, false, true);
 801                 if (ret)
 802                         return ret;
 803
 804                 retried = true;
 805                 goto alloc;
 806         }
 807
 808         if (ppgtt->node.start < dev_priv->gtt.mappable_end)
 809                 DRM_DEBUG("Forced to use aperture for PDEs\n");
 810
 811         ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
 812         ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES;
 813         if (IS_GEN6(dev)) {
 814                 ppgtt->enable = gen6_ppgtt_enable;
 815                 ppgtt->switch_mm = gen6_mm_switch;
 816         } else if (IS_HASWELL(dev)) {
 817                 ppgtt->enable = gen7_ppgtt_enable;
 818                 ppgtt->switch_mm = hsw_mm_switch;
 819         } else if (IS_GEN7(dev)) {
 820                 ppgtt->enable = gen7_ppgtt_enable;
 821                 ppgtt->switch_mm = gen7_mm_switch;
 822         } else
 823                 BUG();
 824         ppgtt->base.clear_range = gen6_ppgtt_clear_range;
 825         ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
 826         ppgtt->base.cleanup = gen6_ppgtt_cleanup;
 827         ppgtt->base.scratch = dev_priv->gtt.base.scratch;
 828         ppgtt->base.start = 0;
 829         ppgtt->base.total = GEN6_PPGTT_PD_ENTRIES * I915_PPGTT_PT_ENTRIES * PAGE_SIZE;
 830         ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *),
 831                                   GFP_KERNEL);
 832         if (!ppgtt->pt_pages) {
 833                 drm_mm_remove_node(&ppgtt->node);
 834                 return -ENOMEM;
 835         }
 836
 837         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 838                 ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
 839                 if (!ppgtt->pt_pages[i])
 840                         goto err_pt_alloc;
 841         }
 842
 843         ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t),
 844                                      GFP_KERNEL);
 845         if (!ppgtt->pt_dma_addr)
 846                 goto err_pt_alloc;
 847
 848         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 849                 dma_addr_t pt_addr;
 850
 851                 pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096,
 852                                        PCI_DMA_BIDIRECTIONAL);
 853
 854                 if (pci_dma_mapping_error(dev->pdev, pt_addr)) {
 855                         ret = -EIO;
 856                         goto err_pd_pin;
 857
 858                 }
 859                 ppgtt->pt_dma_addr[i] = pt_addr;
 860         }
 861
 862         ppgtt->base.clear_range(&ppgtt->base, 0,
 863                                 ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES, true);
 864
 865         DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n",
 866                          ppgtt->node.size >> 20,
 867                          ppgtt->node.start / PAGE_SIZE);
 868         ppgtt->pd_offset =
 869                 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_gtt_pte_t);
 870
 871         return 0;
 872
 873 err_pd_pin:
 874         if (ppgtt->pt_dma_addr) {
 875                 for (i--; i >= 0; i--)
 876                         pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i],
 877                                        4096, PCI_DMA_BIDIRECTIONAL);
 878         }
 879 err_pt_alloc:
 880         kfree(ppgtt->pt_dma_addr);
 881         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 882                 if (ppgtt->pt_pages[i])
 883                         __free_page(ppgtt->pt_pages[i]);
 884         }
 885         kfree(ppgtt->pt_pages);
 886         drm_mm_remove_node(&ppgtt->node);
 887
 888         return ret;
 889 }
 890
 891 int i915_gem_init_ppgtt(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
 892 {
 893         struct drm_i915_private *dev_priv = dev->dev_private;
 894         int ret = 0;
 895
 896         ppgtt->base.dev = dev;
 897
 898         if (INTEL_INFO(dev)->gen < 8)
 899                 ret = gen6_ppgtt_init(ppgtt);
 900         else if (IS_GEN8(dev))
 901                 ret = gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total);
 902         else
 903                 BUG();
 904
 905         if (!ret) {
 906                 struct drm_i915_private *dev_priv = dev->dev_private;
 907                 kref_init(&ppgtt->ref);
 908                 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
 909                             ppgtt->base.total);
 910                 i915_init_vm(dev_priv, &ppgtt->base);
 911                 if (INTEL_INFO(dev)->gen < 8) {
 912                         gen6_write_pdes(ppgtt);
 913                         DRM_DEBUG("Adding PPGTT at offset %x\n",
 914                                   ppgtt->pd_offset << 10);
 915                 }
 916         }
 917
 918         return ret;
 919 }
 920
 921 static void
 922 ppgtt_bind_vma(struct i915_vma *vma,
 923                enum i915_cache_level cache_level,
 924                u32 flags)
 925 {
 926         const unsigned long entry = vma->node.start >> PAGE_SHIFT;
 927
 928         WARN_ON(flags);
 929
 930         vma->vm->insert_entries(vma->vm, vma->obj->pages, entry, cache_level);
 931 }
 932
 933 static void ppgtt_unbind_vma(struct i915_vma *vma)
 934 {
 935         const unsigned long entry = vma->node.start >> PAGE_SHIFT;
 936
 937         vma->vm->clear_range(vma->vm,
 938                              entry,
 939                              vma->obj->base.size >> PAGE_SHIFT,
 940                              true);
 941 }
 942
 943 extern int intel_iommu_gfx_mapped;
 944 /* Certain Gen5 chipsets require require idling the GPU before
 945  * unmapping anything from the GTT when VT-d is enabled.
 946  */
 947 static inline bool needs_idle_maps(struct drm_device *dev)
 948 {
 949 #ifdef CONFIG_INTEL_IOMMU
 950         /* Query intel_iommu to see if we need the workaround. Presumably that
 951          * was loaded first.
 952          */
 953         if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
 954                 return true;
 955 #endif
 956         return false;
 957 }
 958
 959 static bool do_idling(struct drm_i915_private *dev_priv)
 960 {
 961         bool ret = dev_priv->mm.interruptible;
 962
 963         if (unlikely(dev_priv->gtt.do_idle_maps)) {
 964                 dev_priv->mm.interruptible = false;
 965                 if (i915_gpu_idle(dev_priv->dev)) {
 966                         DRM_ERROR("Couldn't idle GPU\n");
 967                         /* Wait a bit, in hopes it avoids the hang */
 968                         udelay(10);
 969                 }
 970         }
 971
 972         return ret;
 973 }
 974
 975 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
 976 {
 977         if (unlikely(dev_priv->gtt.do_idle_maps))
 978                 dev_priv->mm.interruptible = interruptible;
 979 }
 980
 981 void i915_check_and_clear_faults(struct drm_device *dev)
 982 {
 983         struct drm_i915_private *dev_priv = dev->dev_private;
 984         struct intel_ring_buffer *ring;
 985         int i;
 986
 987         if (INTEL_INFO(dev)->gen < 6)
 988                 return;
 989
 990         for_each_ring(ring, dev_priv, i) {
 991                 u32 fault_reg;
 992                 fault_reg = I915_READ(RING_FAULT_REG(ring));
 993                 if (fault_reg & RING_FAULT_VALID) {
 994                         DRM_DEBUG_DRIVER("Unexpected fault\n"
 995                                          "\tAddr: 0x%08lx\\n"
 996                                          "\tAddress space: %s\n"
 997                                          "\tSource ID: %d\n"
 998                                          "\tType: %d\n",
 999                                          fault_reg & PAGE_MASK,
1000                                          fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
1001                                          RING_FAULT_SRCID(fault_reg),
1002                                          RING_FAULT_FAULT_TYPE(fault_reg));
1003                         I915_WRITE(RING_FAULT_REG(ring),
1004                                    fault_reg & ~RING_FAULT_VALID);
1005                 }
1006         }
1007         POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
1008 }
1009
1010 void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
1011 {
1012         struct drm_i915_private *dev_priv = dev->dev_private;
1013
1014         /* Don't bother messing with faults pre GEN6 as we have little
1015          * documentation supporting that it's a good idea.
1016          */
1017         if (INTEL_INFO(dev)->gen < 6)
1018                 return;
1019
1020         i915_check_and_clear_faults(dev);
1021
1022         dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1023                                        dev_priv->gtt.base.start / PAGE_SIZE,
1024                                        dev_priv->gtt.base.total / PAGE_SIZE,
1025                                        false);
1026 }
1027
1028 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
1029 {
1030         struct drm_i915_private *dev_priv = dev->dev_private;
1031         struct drm_i915_gem_object *obj;
1032         struct i915_address_space *vm;
1033
1034         i915_check_and_clear_faults(dev);
1035
1036         /* First fill our portion of the GTT with scratch pages */
1037         dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1038                                        dev_priv->gtt.base.start / PAGE_SIZE,
1039                                        dev_priv->gtt.base.total / PAGE_SIZE,
1040                                        true);
1041
1042         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1043                 struct i915_vma *vma = i915_gem_obj_to_vma(obj,
1044                                                            &dev_priv->gtt.base);
1045                 if (!vma)
1046                         continue;
1047
1048                 i915_gem_clflush_object(obj, obj->pin_display);
1049                 /* The bind_vma code tries to be smart about tracking mappings.
1050                  * Unfortunately above, we've just wiped out the mappings
1051                  * without telling our object about it. So we need to fake it.
1052                  */
1053                 obj->has_global_gtt_mapping = 0;
1054                 vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
1055         }
1056
1057
1058         if (INTEL_INFO(dev)->gen >= 8)
1059                 return;
1060
1061         list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
1062                 /* TODO: Perhaps it shouldn't be gen6 specific */
1063                 if (i915_is_ggtt(vm)) {
1064                         if (dev_priv->mm.aliasing_ppgtt)
1065                                 gen6_write_pdes(dev_priv->mm.aliasing_ppgtt);
1066                         continue;
1067                 }
1068
1069                 gen6_write_pdes(container_of(vm, struct i915_hw_ppgtt, base));
1070         }
1071
1072         i915_gem_chipset_flush(dev);
1073 }
1074
1075 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
1076 {
1077         if (obj->has_dma_mapping)
1078                 return 0;
1079
1080         if (!dma_map_sg(&obj->base.dev->pdev->dev,
1081                         obj->pages->sgl, obj->pages->nents,
1082                         PCI_DMA_BIDIRECTIONAL))
1083                 return -ENOSPC;
1084
1085         return 0;
1086 }
1087
1088 static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte)
1089 {
1090 #ifdef writeq
1091         writeq(pte, addr);
1092 #else
1093         iowrite32((u32)pte, addr);
1094         iowrite32(pte >> 32, addr + 4);
1095 #endif
1096 }
1097
1098 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
1099                                      struct sg_table *st,
1100                                      unsigned int first_entry,
1101                                      enum i915_cache_level level)
1102 {
1103         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1104         gen8_gtt_pte_t __iomem *gtt_entries =
1105                 (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1106         int i = 0;
1107         struct sg_page_iter sg_iter;
1108         dma_addr_t addr;
1109
1110         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1111                 addr = sg_dma_address(sg_iter.sg) +
1112                         (sg_iter.sg_pgoffset << PAGE_SHIFT);
1113                 gen8_set_pte(&gtt_entries[i],
1114                              gen8_pte_encode(addr, level, true));
1115                 i++;
1116         }
1117
1118         /*
1119          * XXX: This serves as a posting read to make sure that the PTE has
1120          * actually been updated. There is some concern that even though
1121          * registers and PTEs are within the same BAR that they are potentially
1122          * of NUMA access patterns. Therefore, even with the way we assume
1123          * hardware should work, we must keep this posting read for paranoia.
1124          */
1125         if (i != 0)
1126                 WARN_ON(readq(&gtt_entries[i-1])
1127                         != gen8_pte_encode(addr, level, true));
1128
1129 #if 0 /* TODO: Still needed on GEN8? */
1130         /* This next bit makes the above posting read even more important. We
1131          * want to flush the TLBs only after we're certain all the PTE updates
1132          * have finished.
1133          */
1134         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1135         POSTING_READ(GFX_FLSH_CNTL_GEN6);
1136 #endif
1137 }
1138
1139 /*
1140  * Binds an object into the global gtt with the specified cache level. The object
1141  * will be accessible to the GPU via commands whose operands reference offsets
1142  * within the global GTT as well as accessible by the GPU through the GMADR
1143  * mapped BAR (dev_priv->mm.gtt->gtt).
1144  */
1145 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
1146                                      struct sg_table *st,
1147                                      unsigned int first_entry,
1148                                      enum i915_cache_level level)
1149 {
1150         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1151         gen6_gtt_pte_t __iomem *gtt_entries =
1152                 (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1153         int i = 0;
1154         struct sg_page_iter sg_iter;
1155         dma_addr_t addr;
1156
1157         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1158                 addr = sg_page_iter_dma_address(&sg_iter);
1159                 iowrite32(vm->pte_encode(addr, level, true), &gtt_entries[i]);
1160                 i++;
1161         }
1162
1163         /* XXX: This serves as a posting read to make sure that the PTE has
1164          * actually been updated. There is some concern that even though
1165          * registers and PTEs are within the same BAR that they are potentially
1166          * of NUMA access patterns. Therefore, even with the way we assume
1167          * hardware should work, we must keep this posting read for paranoia.
1168          */
1169         if (i != 0)
1170                 WARN_ON(readl(&gtt_entries[i-1]) !=
1171                         vm->pte_encode(addr, level, true));
1172
1173         /* This next bit makes the above posting read even more important. We
1174          * want to flush the TLBs only after we're certain all the PTE updates
1175          * have finished.
1176          */
1177         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1178         POSTING_READ(GFX_FLSH_CNTL_GEN6);
1179 }
1180
1181 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
1182                                   unsigned int first_entry,
1183                                   unsigned int num_entries,
1184                                   bool use_scratch)
1185 {
1186         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1187         gen8_gtt_pte_t scratch_pte, __iomem *gtt_base =
1188                 (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1189         const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1190         int i;
1191
1192         if (WARN(num_entries > max_entries,
1193                  "First entry = %d; Num entries = %d (max=%d)\n",
1194                  first_entry, num_entries, max_entries))
1195                 num_entries = max_entries;
1196
1197         scratch_pte = gen8_pte_encode(vm->scratch.addr,
1198                                       I915_CACHE_LLC,
1199                                       use_scratch);
1200         for (i = 0; i < num_entries; i++)
1201                 gen8_set_pte(&gtt_base[i], scratch_pte);
1202         readl(gtt_base);
1203 }
1204
1205 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
1206                                   unsigned int first_entry,
1207                                   unsigned int num_entries,
1208                                   bool use_scratch)
1209 {
1210         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1211         gen6_gtt_pte_t scratch_pte, __iomem *gtt_base =
1212                 (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1213         const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1214         int i;
1215
1216         if (WARN(num_entries > max_entries,
1217                  "First entry = %d; Num entries = %d (max=%d)\n",
1218                  first_entry, num_entries, max_entries))
1219                 num_entries = max_entries;
1220
1221         scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch);
1222
1223         for (i = 0; i < num_entries; i++)
1224                 iowrite32(scratch_pte, &gtt_base[i]);
1225         readl(gtt_base);
1226 }
1227
1228
1229 static void i915_ggtt_bind_vma(struct i915_vma *vma,
1230                                enum i915_cache_level cache_level,
1231                                u32 unused)
1232 {
1233         const unsigned long entry = vma->node.start >> PAGE_SHIFT;
1234         unsigned int flags = (cache_level == I915_CACHE_NONE) ?
1235                 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
1236
1237         BUG_ON(!i915_is_ggtt(vma->vm));
1238         intel_gtt_insert_sg_entries(vma->obj->pages, entry, flags);
1239         vma->obj->has_global_gtt_mapping = 1;
1240 }
1241
1242 static void i915_ggtt_clear_range(struct i915_address_space *vm,
1243                                   unsigned int first_entry,
1244                                   unsigned int num_entries,
1245                                   bool unused)
1246 {
1247         intel_gtt_clear_range(first_entry, num_entries);
1248 }
1249
1250 static void i915_ggtt_unbind_vma(struct i915_vma *vma)
1251 {
1252         const unsigned int first = vma->node.start >> PAGE_SHIFT;
1253         const unsigned int size = vma->obj->base.size >> PAGE_SHIFT;
1254
1255         BUG_ON(!i915_is_ggtt(vma->vm));
1256         vma->obj->has_global_gtt_mapping = 0;
1257         intel_gtt_clear_range(first, size);
1258 }
1259
1260 static void ggtt_bind_vma(struct i915_vma *vma,
1261                           enum i915_cache_level cache_level,
1262                           u32 flags)
1263 {
1264         struct drm_device *dev = vma->vm->dev;
1265         struct drm_i915_private *dev_priv = dev->dev_private;
1266         struct drm_i915_gem_object *obj = vma->obj;
1267         const unsigned long entry = vma->node.start >> PAGE_SHIFT;
1268
1269         /* If there is no aliasing PPGTT, or the caller needs a global mapping,
1270          * or we have a global mapping already but the cacheability flags have
1271          * changed, set the global PTEs.
1272          *
1273          * If there is an aliasing PPGTT it is anecdotally faster, so use that
1274          * instead if none of the above hold true.
1275          *
1276          * NB: A global mapping should only be needed for special regions like
1277          * "gtt mappable", SNB errata, or if specified via special execbuf
1278          * flags. At all other times, the GPU will use the aliasing PPGTT.
1279          */
1280         if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) {
1281                 if (!obj->has_global_gtt_mapping ||
1282                     (cache_level != obj->cache_level)) {
1283                         vma->vm->insert_entries(vma->vm, obj->pages, entry,
1284                                                 cache_level);
1285                         obj->has_global_gtt_mapping = 1;
1286                 }
1287         }
1288
1289         if (dev_priv->mm.aliasing_ppgtt &&
1290             (!obj->has_aliasing_ppgtt_mapping ||
1291              (cache_level != obj->cache_level))) {
1292                 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1293                 appgtt->base.insert_entries(&appgtt->base,
1294                                             vma->obj->pages, entry, cache_level);
1295                 vma->obj->has_aliasing_ppgtt_mapping = 1;
1296         }
1297 }
1298
1299 static void ggtt_unbind_vma(struct i915_vma *vma)
1300 {
1301         struct drm_device *dev = vma->vm->dev;
1302         struct drm_i915_private *dev_priv = dev->dev_private;
1303         struct drm_i915_gem_object *obj = vma->obj;
1304         const unsigned long entry = vma->node.start >> PAGE_SHIFT;
1305
1306         if (obj->has_global_gtt_mapping) {
1307                 vma->vm->clear_range(vma->vm, entry,
1308                                      vma->obj->base.size >> PAGE_SHIFT,
1309                                      true);
1310                 obj->has_global_gtt_mapping = 0;
1311         }
1312
1313         if (obj->has_aliasing_ppgtt_mapping) {
1314                 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1315                 appgtt->base.clear_range(&appgtt->base,
1316                                          entry,
1317                                          obj->base.size >> PAGE_SHIFT,
1318                                          true);
1319                 obj->has_aliasing_ppgtt_mapping = 0;
1320         }
1321 }
1322
1323 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
1324 {
1325         struct drm_device *dev = obj->base.dev;
1326         struct drm_i915_private *dev_priv = dev->dev_private;
1327         bool interruptible;
1328
1329         interruptible = do_idling(dev_priv);
1330
1331         if (!obj->has_dma_mapping)
1332                 dma_unmap_sg(&dev->pdev->dev,
1333                              obj->pages->sgl, obj->pages->nents,
1334                              PCI_DMA_BIDIRECTIONAL);
1335
1336         undo_idling(dev_priv, interruptible);
1337 }
1338
1339 static void i915_gtt_color_adjust(struct drm_mm_node *node,
1340                                   unsigned long color,
1341                                   unsigned long *start,
1342                                   unsigned long *end)
1343 {
1344         if (node->color != color)
1345                 *start += 4096;
1346
1347         if (!list_empty(&node->node_list)) {
1348                 node = list_entry(node->node_list.next,
1349                                   struct drm_mm_node,
1350                                   node_list);
1351                 if (node->allocated && node->color != color)
1352                         *end -= 4096;
1353         }
1354 }
1355
1356 void i915_gem_setup_global_gtt(struct drm_device *dev,
1357                                unsigned long start,
1358                                unsigned long mappable_end,
1359                                unsigned long end)
1360 {
1361         /* Let GEM Manage all of the aperture.
1362          *
1363          * However, leave one page at the end still bound to the scratch page.
1364          * There are a number of places where the hardware apparently prefetches
1365          * past the end of the object, and we've seen multiple hangs with the
1366          * GPU head pointer stuck in a batchbuffer bound at the last page of the
1367          * aperture.  One page should be enough to keep any prefetching inside
1368          * of the aperture.
1369          */
1370         struct drm_i915_private *dev_priv = dev->dev_private;
1371         struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
1372         struct drm_mm_node *entry;
1373         struct drm_i915_gem_object *obj;
1374         unsigned long hole_start, hole_end;
1375
1376         BUG_ON(mappable_end > end);
1377
1378         /* Subtract the guard page ... */
1379         drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
1380         if (!HAS_LLC(dev))
1381                 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
1382
1383         /* Mark any preallocated objects as occupied */
1384         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1385                 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
1386                 int ret;
1387                 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
1388                               i915_gem_obj_ggtt_offset(obj), obj->base.size);
1389
1390                 WARN_ON(i915_gem_obj_ggtt_bound(obj));
1391                 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
1392                 if (ret)
1393                         DRM_DEBUG_KMS("Reservation failed\n");
1394                 obj->has_global_gtt_mapping = 1;
1395         }
1396
1397         dev_priv->gtt.base.start = start;
1398         dev_priv->gtt.base.total = end - start;
1399
1400         /* Clear any non-preallocated blocks */
1401         drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
1402                 const unsigned long count = (hole_end - hole_start) / PAGE_SIZE;
1403                 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
1404                               hole_start, hole_end);
1405                 ggtt_vm->clear_range(ggtt_vm, hole_start / PAGE_SIZE, count, true);
1406         }
1407
1408         /* And finally clear the reserved guard page */
1409         ggtt_vm->clear_range(ggtt_vm, end / PAGE_SIZE - 1, 1, true);
1410 }
1411
1412 void i915_gem_init_global_gtt(struct drm_device *dev)
1413 {
1414         struct drm_i915_private *dev_priv = dev->dev_private;
1415         unsigned long gtt_size, mappable_size;
1416
1417         gtt_size = dev_priv->gtt.base.total;
1418         mappable_size = dev_priv->gtt.mappable_end;
1419
1420         i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
1421 }
1422
1423 static int setup_scratch_page(struct drm_device *dev)
1424 {
1425         struct drm_i915_private *dev_priv = dev->dev_private;
1426         struct page *page;
1427         dma_addr_t dma_addr;
1428
1429         page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
1430         if (page == NULL)
1431                 return -ENOMEM;
1432         get_page(page);
1433         set_pages_uc(page, 1);
1434
1435 #ifdef CONFIG_INTEL_IOMMU
1436         dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
1437                                 PCI_DMA_BIDIRECTIONAL);
1438         if (pci_dma_mapping_error(dev->pdev, dma_addr))
1439                 return -EINVAL;
1440 #else
1441         dma_addr = page_to_phys(page);
1442 #endif
1443         dev_priv->gtt.base.scratch.page = page;
1444         dev_priv->gtt.base.scratch.addr = dma_addr;
1445
1446         return 0;
1447 }
1448
1449 static void teardown_scratch_page(struct drm_device *dev)
1450 {
1451         struct drm_i915_private *dev_priv = dev->dev_private;
1452         struct page *page = dev_priv->gtt.base.scratch.page;
1453
1454         set_pages_wb(page, 1);
1455         pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr,
1456                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1457         put_page(page);
1458         __free_page(page);
1459 }
1460
1461 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
1462 {
1463         snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
1464         snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
1465         return snb_gmch_ctl << 20;
1466 }
1467
1468 static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
1469 {
1470         bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
1471         bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
1472         if (bdw_gmch_ctl)
1473                 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
1474         if (bdw_gmch_ctl > 4) {
1475                 WARN_ON(!i915_preliminary_hw_support);
1476                 return 4<<20;
1477         }
1478
1479         return bdw_gmch_ctl << 20;
1480 }
1481
1482 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
1483 {
1484         snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
1485         snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
1486         return snb_gmch_ctl << 25; /* 32 MB units */
1487 }
1488
1489 static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
1490 {
1491         bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
1492         bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
1493         return bdw_gmch_ctl << 25; /* 32 MB units */
1494 }
1495
1496 static int ggtt_probe_common(struct drm_device *dev,
1497                              size_t gtt_size)
1498 {
1499         struct drm_i915_private *dev_priv = dev->dev_private;
1500         phys_addr_t gtt_bus_addr;
1501         int ret;
1502
1503         /* For Modern GENs the PTEs and register space are split in the BAR */
1504         gtt_bus_addr = pci_resource_start(dev->pdev, 0) +
1505                 (pci_resource_len(dev->pdev, 0) / 2);
1506
1507         dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size);
1508         if (!dev_priv->gtt.gsm) {
1509                 DRM_ERROR("Failed to map the gtt page table\n");
1510                 return -ENOMEM;
1511         }
1512
1513         ret = setup_scratch_page(dev);
1514         if (ret) {
1515                 DRM_ERROR("Scratch setup failed\n");
1516                 /* iounmap will also get called at remove, but meh */
1517                 iounmap(dev_priv->gtt.gsm);
1518         }
1519
1520         return ret;
1521 }
1522
1523 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
1524  * bits. When using advanced contexts each context stores its own PAT, but
1525  * writing this data shouldn't be harmful even in those cases. */
1526 static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv)
1527 {
1528 #define GEN8_PPAT_UC            (0<<0)
1529 #define GEN8_PPAT_WC            (1<<0)
1530 #define GEN8_PPAT_WT            (2<<0)
1531 #define GEN8_PPAT_WB            (3<<0)
1532 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2)
1533 /* FIXME(BDW): Bspec is completely confused about cache control bits. */
1534 #define GEN8_PPAT_LLC           (1<<2)
1535 #define GEN8_PPAT_LLCELLC       (2<<2)
1536 #define GEN8_PPAT_LLCeLLC       (3<<2)
1537 #define GEN8_PPAT_AGE(x)        (x<<4)
1538 #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8))
1539         uint64_t pat;
1540
1541         pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC)     | /* for normal objects, no eLLC */
1542               GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
1543               GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
1544               GEN8_PPAT(3, GEN8_PPAT_UC)                     | /* Uncached objects, mostly for scanout */
1545               GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
1546               GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
1547               GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
1548               GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
1549
1550         /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
1551          * write would work. */
1552         I915_WRITE(GEN8_PRIVATE_PAT, pat);
1553         I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
1554 }
1555
1556 static int gen8_gmch_probe(struct drm_device *dev,
1557                            size_t *gtt_total,
1558                            size_t *stolen,
1559                            phys_addr_t *mappable_base,
1560                            unsigned long *mappable_end)
1561 {
1562         struct drm_i915_private *dev_priv = dev->dev_private;
1563         unsigned int gtt_size;
1564         u16 snb_gmch_ctl;
1565         int ret;
1566
1567         /* TODO: We're not aware of mappable constraints on gen8 yet */
1568         *mappable_base = pci_resource_start(dev->pdev, 2);
1569         *mappable_end = pci_resource_len(dev->pdev, 2);
1570
1571         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
1572                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
1573
1574         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1575
1576         *stolen = gen8_get_stolen_size(snb_gmch_ctl);
1577
1578         gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
1579         *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT;
1580
1581         gen8_setup_private_ppat(dev_priv);
1582
1583         ret = ggtt_probe_common(dev, gtt_size);
1584
1585         dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
1586         dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
1587
1588         return ret;
1589 }
1590
1591 static int gen6_gmch_probe(struct drm_device *dev,
1592                            size_t *gtt_total,
1593                            size_t *stolen,
1594                            phys_addr_t *mappable_base,
1595                            unsigned long *mappable_end)
1596 {
1597         struct drm_i915_private *dev_priv = dev->dev_private;
1598         unsigned int gtt_size;
1599         u16 snb_gmch_ctl;
1600         int ret;
1601
1602         *mappable_base = pci_resource_start(dev->pdev, 2);
1603         *mappable_end = pci_resource_len(dev->pdev, 2);
1604
1605         /* 64/512MB is the current min/max we actually know of, but this is just
1606          * a coarse sanity check.
1607          */
1608         if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
1609                 DRM_ERROR("Unknown GMADR size (%lx)\n",
1610                           dev_priv->gtt.mappable_end);
1611                 return -ENXIO;
1612         }
1613
1614         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
1615                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
1616         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1617
1618         *stolen = gen6_get_stolen_size(snb_gmch_ctl);
1619
1620         gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
1621         *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
1622
1623         ret = ggtt_probe_common(dev, gtt_size);
1624
1625         dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
1626         dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
1627
1628         return ret;
1629 }
1630
1631 static void gen6_gmch_remove(struct i915_address_space *vm)
1632 {
1633
1634         struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
1635
1636         drm_mm_takedown(&vm->mm);
1637         iounmap(gtt->gsm);
1638         teardown_scratch_page(vm->dev);
1639 }
1640
1641 static int i915_gmch_probe(struct drm_device *dev,
1642                            size_t *gtt_total,
1643                            size_t *stolen,
1644                            phys_addr_t *mappable_base,
1645                            unsigned long *mappable_end)
1646 {
1647         struct drm_i915_private *dev_priv = dev->dev_private;
1648         int ret;
1649
1650         ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
1651         if (!ret) {
1652                 DRM_ERROR("failed to set up gmch\n");
1653                 return -EIO;
1654         }
1655
1656         intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
1657
1658         dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
1659         dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
1660
1661         return 0;
1662 }
1663
1664 static void i915_gmch_remove(struct i915_address_space *vm)
1665 {
1666         intel_gmch_remove();
1667 }
1668
1669 int i915_gem_gtt_init(struct drm_device *dev)
1670 {
1671         struct drm_i915_private *dev_priv = dev->dev_private;
1672         struct i915_gtt *gtt = &dev_priv->gtt;
1673         int ret;
1674
1675         if (INTEL_INFO(dev)->gen <= 5) {
1676                 gtt->gtt_probe = i915_gmch_probe;
1677                 gtt->base.cleanup = i915_gmch_remove;
1678         } else if (INTEL_INFO(dev)->gen < 8) {
1679                 gtt->gtt_probe = gen6_gmch_probe;
1680                 gtt->base.cleanup = gen6_gmch_remove;
1681                 if (IS_HASWELL(dev) && dev_priv->ellc_size)
1682                         gtt->base.pte_encode = iris_pte_encode;
1683                 else if (IS_HASWELL(dev))
1684                         gtt->base.pte_encode = hsw_pte_encode;
1685                 else if (IS_VALLEYVIEW(dev))
1686                         gtt->base.pte_encode = byt_pte_encode;
1687                 else if (INTEL_INFO(dev)->gen >= 7)
1688                         gtt->base.pte_encode = ivb_pte_encode;
1689                 else
1690                         gtt->base.pte_encode = snb_pte_encode;
1691         } else {
1692                 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
1693                 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
1694         }
1695
1696         ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,
1697                              &gtt->mappable_base, &gtt->mappable_end);
1698         if (ret)
1699                 return ret;
1700
1701         gtt->base.dev = dev;
1702
1703         /* GMADR is the PCI mmio aperture into the global GTT. */
1704         DRM_INFO("Memory usable by graphics device = %zdM\n",
1705                  gtt->base.total >> 20);
1706         DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
1707         DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
1708
1709         return 0;
1710 }
1711
1712 static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj,
1713                                               struct i915_address_space *vm)
1714 {
1715         struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL);
1716         if (vma == NULL)
1717                 return ERR_PTR(-ENOMEM);
1718
1719         INIT_LIST_HEAD(&vma->vma_link);
1720         INIT_LIST_HEAD(&vma->mm_list);
1721         INIT_LIST_HEAD(&vma->exec_list);
1722         vma->vm = vm;
1723         vma->obj = obj;
1724
1725         switch (INTEL_INFO(vm->dev)->gen) {
1726         case 8:
1727         case 7:
1728         case 6:
1729                 if (i915_is_ggtt(vm)) {
1730                         vma->unbind_vma = ggtt_unbind_vma;
1731                         vma->bind_vma = ggtt_bind_vma;
1732                 } else {
1733                         vma->unbind_vma = ppgtt_unbind_vma;
1734                         vma->bind_vma = ppgtt_bind_vma;
1735                 }
1736                 break;
1737         case 5:
1738         case 4:
1739         case 3:
1740         case 2:
1741                 BUG_ON(!i915_is_ggtt(vm));
1742                 vma->unbind_vma = i915_ggtt_unbind_vma;
1743                 vma->bind_vma = i915_ggtt_bind_vma;
1744                 break;
1745         default:
1746                 BUG();
1747         }
1748
1749         /* Keep GGTT vmas first to make debug easier */
1750         if (i915_is_ggtt(vm))
1751                 list_add(&vma->vma_link, &obj->vma_list);
1752         else
1753                 list_add_tail(&vma->vma_link, &obj->vma_list);
1754
1755         return vma;
1756 }
1757
1758 struct i915_vma *
1759 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
1760                                   struct i915_address_space *vm)
1761 {
1762         struct i915_vma *vma;
1763
1764         vma = i915_gem_obj_to_vma(obj, vm);
1765         if (!vma)
1766                 vma = __i915_gem_vma_create(obj, vm);
1767
1768         return vma;
1769 }