drivers/gpu/drm/i915/i915_gem_fence_reg.c

   1 /*
   2  * Copyright © 2008-2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "i915_drv.h"
  25 #include "i915_scatterlist.h"
  26 #include "i915_pvinfo.h"
  27 #include "i915_vgpu.h"
  28
  29 /**
  30  * DOC: fence register handling
  31  *
  32  * Important to avoid confusions: "fences" in the i915 driver are not execution
  33  * fences used to track command completion but hardware detiler objects which
  34  * wrap a given range of the global GTT. Each platform has only a fairly limited
  35  * set of these objects.
  36  *
  37  * Fences are used to detile GTT memory mappings. They're also connected to the
  38  * hardware frontbuffer render tracking and hence interact with frontbuffer
  39  * compression. Furthermore on older platforms fences are required for tiled
  40  * objects used by the display engine. They can also be used by the render
  41  * engine - they're required for blitter commands and are optional for render
  42  * commands. But on gen4+ both display (with the exception of fbc) and rendering
  43  * have their own tiling state bits and don't need fences.
  44  *
  45  * Also note that fences only support X and Y tiling and hence can't be used for
  46  * the fancier new tiling formats like W, Ys and Yf.
  47  *
  48  * Finally note that because fences are such a restricted resource they're
  49  * dynamically associated with objects. Furthermore fence state is committed to
  50  * the hardware lazily to avoid unnecessary stalls on gen2/3. Therefore code must
  51  * explicitly call i915_gem_object_get_fence() to synchronize fencing status
  52  * for cpu access. Also note that some code wants an unfenced view, for those
  53  * cases the fence can be removed forcefully with i915_gem_object_put_fence().
  54  *
  55  * Internally these functions will synchronize with userspace access by removing
  56  * CPU ptes into GTT mmaps (not the GTT ptes themselves) as needed.
  57  */
  58
  59 #define pipelined 0
  60
  61 static struct drm_i915_private *fence_to_i915(struct i915_fence_reg *fence)
  62 {
  63         return fence->ggtt->vm.i915;
  64 }
  65
  66 static struct intel_uncore *fence_to_uncore(struct i915_fence_reg *fence)
  67 {
  68         return fence->ggtt->vm.gt->uncore;
  69 }
  70
  71 static void i965_write_fence_reg(struct i915_fence_reg *fence,
  72                                  struct i915_vma *vma)
  73 {
  74         i915_reg_t fence_reg_lo, fence_reg_hi;
  75         int fence_pitch_shift;
  76         u64 val;
  77
  78         if (INTEL_GEN(fence_to_i915(fence)) >= 6) {
  79                 fence_reg_lo = FENCE_REG_GEN6_LO(fence->id);
  80                 fence_reg_hi = FENCE_REG_GEN6_HI(fence->id);
  81                 fence_pitch_shift = GEN6_FENCE_PITCH_SHIFT;
  82
  83         } else {
  84                 fence_reg_lo = FENCE_REG_965_LO(fence->id);
  85                 fence_reg_hi = FENCE_REG_965_HI(fence->id);
  86                 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
  87         }
  88
  89         val = 0;
  90         if (vma) {
  91                 unsigned int stride = i915_gem_object_get_stride(vma->obj);
  92
  93                 GEM_BUG_ON(!i915_vma_is_map_and_fenceable(vma));
  94                 GEM_BUG_ON(!IS_ALIGNED(vma->node.start, I965_FENCE_PAGE));
  95                 GEM_BUG_ON(!IS_ALIGNED(vma->fence_size, I965_FENCE_PAGE));
  96                 GEM_BUG_ON(!IS_ALIGNED(stride, 128));
  97
  98                 val = (vma->node.start + vma->fence_size - I965_FENCE_PAGE) << 32;
  99                 val |= vma->node.start;
 100                 val |= (u64)((stride / 128) - 1) << fence_pitch_shift;
 101                 if (i915_gem_object_get_tiling(vma->obj) == I915_TILING_Y)
 102                         val |= BIT(I965_FENCE_TILING_Y_SHIFT);
 103                 val |= I965_FENCE_REG_VALID;
 104         }
 105
 106         if (!pipelined) {
 107                 struct intel_uncore *uncore = fence_to_uncore(fence);
 108
 109                 /*
 110                  * To w/a incoherency with non-atomic 64-bit register updates,
 111                  * we split the 64-bit update into two 32-bit writes. In order
 112                  * for a partial fence not to be evaluated between writes, we
 113                  * precede the update with write to turn off the fence register,
 114                  * and only enable the fence as the last step.
 115                  *
 116                  * For extra levels of paranoia, we make sure each step lands
 117                  * before applying the next step.
 118                  */
 119                 intel_uncore_write_fw(uncore, fence_reg_lo, 0);
 120                 intel_uncore_posting_read_fw(uncore, fence_reg_lo);
 121
 122                 intel_uncore_write_fw(uncore, fence_reg_hi, upper_32_bits(val));
 123                 intel_uncore_write_fw(uncore, fence_reg_lo, lower_32_bits(val));
 124                 intel_uncore_posting_read_fw(uncore, fence_reg_lo);
 125         }
 126 }
 127
 128 static void i915_write_fence_reg(struct i915_fence_reg *fence,
 129                                  struct i915_vma *vma)
 130 {
 131         u32 val;
 132
 133         val = 0;
 134         if (vma) {
 135                 unsigned int tiling = i915_gem_object_get_tiling(vma->obj);
 136                 bool is_y_tiled = tiling == I915_TILING_Y;
 137                 unsigned int stride = i915_gem_object_get_stride(vma->obj);
 138
 139                 GEM_BUG_ON(!i915_vma_is_map_and_fenceable(vma));
 140                 GEM_BUG_ON(vma->node.start & ~I915_FENCE_START_MASK);
 141                 GEM_BUG_ON(!is_power_of_2(vma->fence_size));
 142                 GEM_BUG_ON(!IS_ALIGNED(vma->node.start, vma->fence_size));
 143
 144                 if (is_y_tiled && HAS_128_BYTE_Y_TILING(fence_to_i915(fence)))
 145                         stride /= 128;
 146                 else
 147                         stride /= 512;
 148                 GEM_BUG_ON(!is_power_of_2(stride));
 149
 150                 val = vma->node.start;
 151                 if (is_y_tiled)
 152                         val |= BIT(I830_FENCE_TILING_Y_SHIFT);
 153                 val |= I915_FENCE_SIZE_BITS(vma->fence_size);
 154                 val |= ilog2(stride) << I830_FENCE_PITCH_SHIFT;
 155
 156                 val |= I830_FENCE_REG_VALID;
 157         }
 158
 159         if (!pipelined) {
 160                 struct intel_uncore *uncore = fence_to_uncore(fence);
 161                 i915_reg_t reg = FENCE_REG(fence->id);
 162
 163                 intel_uncore_write_fw(uncore, reg, val);
 164                 intel_uncore_posting_read_fw(uncore, reg);
 165         }
 166 }
 167
 168 static void i830_write_fence_reg(struct i915_fence_reg *fence,
 169                                  struct i915_vma *vma)
 170 {
 171         u32 val;
 172
 173         val = 0;
 174         if (vma) {
 175                 unsigned int stride = i915_gem_object_get_stride(vma->obj);
 176
 177                 GEM_BUG_ON(!i915_vma_is_map_and_fenceable(vma));
 178                 GEM_BUG_ON(vma->node.start & ~I830_FENCE_START_MASK);
 179                 GEM_BUG_ON(!is_power_of_2(vma->fence_size));
 180                 GEM_BUG_ON(!is_power_of_2(stride / 128));
 181                 GEM_BUG_ON(!IS_ALIGNED(vma->node.start, vma->fence_size));
 182
 183                 val = vma->node.start;
 184                 if (i915_gem_object_get_tiling(vma->obj) == I915_TILING_Y)
 185                         val |= BIT(I830_FENCE_TILING_Y_SHIFT);
 186                 val |= I830_FENCE_SIZE_BITS(vma->fence_size);
 187                 val |= ilog2(stride / 128) << I830_FENCE_PITCH_SHIFT;
 188                 val |= I830_FENCE_REG_VALID;
 189         }
 190
 191         if (!pipelined) {
 192                 struct intel_uncore *uncore = fence_to_uncore(fence);
 193                 i915_reg_t reg = FENCE_REG(fence->id);
 194
 195                 intel_uncore_write_fw(uncore, reg, val);
 196                 intel_uncore_posting_read_fw(uncore, reg);
 197         }
 198 }
 199
 200 static void fence_write(struct i915_fence_reg *fence,
 201                         struct i915_vma *vma)
 202 {
 203         struct drm_i915_private *i915 = fence_to_i915(fence);
 204
 205         /*
 206          * Previous access through the fence register is marshalled by
 207          * the mb() inside the fault handlers (i915_gem_release_mmaps)
 208          * and explicitly managed for internal users.
 209          */
 210
 211         if (IS_GEN(i915, 2))
 212                 i830_write_fence_reg(fence, vma);
 213         else if (IS_GEN(i915, 3))
 214                 i915_write_fence_reg(fence, vma);
 215         else
 216                 i965_write_fence_reg(fence, vma);
 217
 218         /*
 219          * Access through the fenced region afterwards is
 220          * ordered by the posting reads whilst writing the registers.
 221          */
 222
 223         fence->dirty = false;
 224 }
 225
 226 static int fence_update(struct i915_fence_reg *fence,
 227                         struct i915_vma *vma)
 228 {
 229         struct i915_ggtt *ggtt = fence->ggtt;
 230         struct intel_uncore *uncore = fence_to_uncore(fence);
 231         intel_wakeref_t wakeref;
 232         struct i915_vma *old;
 233         int ret;
 234
 235         if (vma) {
 236                 if (!i915_vma_is_map_and_fenceable(vma))
 237                         return -EINVAL;
 238
 239                 if (drm_WARN(&uncore->i915->drm,
 240                              !i915_gem_object_get_stride(vma->obj) ||
 241                              !i915_gem_object_get_tiling(vma->obj),
 242                              "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
 243                              i915_gem_object_get_stride(vma->obj),
 244                              i915_gem_object_get_tiling(vma->obj)))
 245                         return -EINVAL;
 246
 247                 ret = i915_vma_sync(vma);
 248                 if (ret)
 249                         return ret;
 250         }
 251
 252         old = xchg(&fence->vma, NULL);
 253         if (old) {
 254                 /* XXX Ideally we would move the waiting to outside the mutex */
 255                 ret = i915_vma_sync(old);
 256                 if (ret) {
 257                         fence->vma = old;
 258                         return ret;
 259                 }
 260
 261                 i915_vma_flush_writes(old);
 262
 263                 /*
 264                  * Ensure that all userspace CPU access is completed before
 265                  * stealing the fence.
 266                  */
 267                 if (old != vma) {
 268                         GEM_BUG_ON(old->fence != fence);
 269                         i915_vma_revoke_mmap(old);
 270                         old->fence = NULL;
 271                 }
 272
 273                 list_move(&fence->link, &ggtt->fence_list);
 274         }
 275
 276         /*
 277          * We only need to update the register itself if the device is awake.
 278          * If the device is currently powered down, we will defer the write
 279          * to the runtime resume, see i915_gem_restore_fences().
 280          *
 281          * This only works for removing the fence register, on acquisition
 282          * the caller must hold the rpm wakeref. The fence register must
 283          * be cleared before we can use any other fences to ensure that
 284          * the new fences do not overlap the elided clears, confusing HW.
 285          */
 286         wakeref = intel_runtime_pm_get_if_in_use(uncore->rpm);
 287         if (!wakeref) {
 288                 GEM_BUG_ON(vma);
 289                 return 0;
 290         }
 291
 292         WRITE_ONCE(fence->vma, vma);
 293         fence_write(fence, vma);
 294
 295         if (vma) {
 296                 vma->fence = fence;
 297                 list_move_tail(&fence->link, &ggtt->fence_list);
 298         }
 299
 300         intel_runtime_pm_put(uncore->rpm, wakeref);
 301         return 0;
 302 }
 303
 304 /**
 305  * i915_vma_revoke_fence - force-remove fence for a VMA
 306  * @vma: vma to map linearly (not through a fence reg)
 307  *
 308  * This function force-removes any fence from the given object, which is useful
 309  * if the kernel wants to do untiled GTT access.
 310  *
 311  * Returns:
 312  *
 313  * 0 on success, negative error code on failure.
 314  */
 315 int i915_vma_revoke_fence(struct i915_vma *vma)
 316 {
 317         struct i915_fence_reg *fence = vma->fence;
 318
 319         lockdep_assert_held(&vma->vm->mutex);
 320         if (!fence)
 321                 return 0;
 322
 323         if (atomic_read(&fence->pin_count))
 324                 return -EBUSY;
 325
 326         return fence_update(fence, NULL);
 327 }
 328
 329 static struct i915_fence_reg *fence_find(struct i915_ggtt *ggtt)
 330 {
 331         struct i915_fence_reg *fence;
 332
 333         list_for_each_entry(fence, &ggtt->fence_list, link) {
 334                 GEM_BUG_ON(fence->vma && fence->vma->fence != fence);
 335
 336                 if (atomic_read(&fence->pin_count))
 337                         continue;
 338
 339                 return fence;
 340         }
 341
 342         /* Wait for completion of pending flips which consume fences */
 343         if (intel_has_pending_fb_unpin(ggtt->vm.i915))
 344                 return ERR_PTR(-EAGAIN);
 345
 346         return ERR_PTR(-EDEADLK);
 347 }
 348
 349 int __i915_vma_pin_fence(struct i915_vma *vma)
 350 {
 351         struct i915_ggtt *ggtt = i915_vm_to_ggtt(vma->vm);
 352         struct i915_fence_reg *fence;
 353         struct i915_vma *set = i915_gem_object_is_tiled(vma->obj) ? vma : NULL;
 354         int err;
 355
 356         lockdep_assert_held(&vma->vm->mutex);
 357
 358         /* Just update our place in the LRU if our fence is getting reused. */
 359         if (vma->fence) {
 360                 fence = vma->fence;
 361                 GEM_BUG_ON(fence->vma != vma);
 362                 atomic_inc(&fence->pin_count);
 363                 if (!fence->dirty) {
 364                         list_move_tail(&fence->link, &ggtt->fence_list);
 365                         return 0;
 366                 }
 367         } else if (set) {
 368                 fence = fence_find(ggtt);
 369                 if (IS_ERR(fence))
 370                         return PTR_ERR(fence);
 371
 372                 GEM_BUG_ON(atomic_read(&fence->pin_count));
 373                 atomic_inc(&fence->pin_count);
 374         } else {
 375                 return 0;
 376         }
 377
 378         err = fence_update(fence, set);
 379         if (err)
 380                 goto out_unpin;
 381
 382         GEM_BUG_ON(fence->vma != set);
 383         GEM_BUG_ON(vma->fence != (set ? fence : NULL));
 384
 385         if (set)
 386                 return 0;
 387
 388 out_unpin:
 389         atomic_dec(&fence->pin_count);
 390         return err;
 391 }
 392
 393 /**
 394  * i915_vma_pin_fence - set up fencing for a vma
 395  * @vma: vma to map through a fence reg
 396  *
 397  * When mapping objects through the GTT, userspace wants to be able to write
 398  * to them without having to worry about swizzling if the object is tiled.
 399  * This function walks the fence regs looking for a free one for @obj,
 400  * stealing one if it can't find any.
 401  *
 402  * It then sets up the reg based on the object's properties: address, pitch
 403  * and tiling format.
 404  *
 405  * For an untiled surface, this removes any existing fence.
 406  *
 407  * Returns:
 408  *
 409  * 0 on success, negative error code on failure.
 410  */
 411 int i915_vma_pin_fence(struct i915_vma *vma)
 412 {
 413         int err;
 414
 415         if (!vma->fence && !i915_gem_object_is_tiled(vma->obj))
 416                 return 0;
 417
 418         /*
 419          * Note that we revoke fences on runtime suspend. Therefore the user
 420          * must keep the device awake whilst using the fence.
 421          */
 422         assert_rpm_wakelock_held(vma->vm->gt->uncore->rpm);
 423         GEM_BUG_ON(!i915_vma_is_pinned(vma));
 424         GEM_BUG_ON(!i915_vma_is_ggtt(vma));
 425
 426         err = mutex_lock_interruptible(&vma->vm->mutex);
 427         if (err)
 428                 return err;
 429
 430         err = __i915_vma_pin_fence(vma);
 431         mutex_unlock(&vma->vm->mutex);
 432
 433         return err;
 434 }
 435
 436 /**
 437  * i915_reserve_fence - Reserve a fence for vGPU
 438  * @ggtt: Global GTT
 439  *
 440  * This function walks the fence regs looking for a free one and remove
 441  * it from the fence_list. It is used to reserve fence for vGPU to use.
 442  */
 443 struct i915_fence_reg *i915_reserve_fence(struct i915_ggtt *ggtt)
 444 {
 445         struct i915_fence_reg *fence;
 446         int count;
 447         int ret;
 448
 449         lockdep_assert_held(&ggtt->vm.mutex);
 450
 451         /* Keep at least one fence available for the display engine. */
 452         count = 0;
 453         list_for_each_entry(fence, &ggtt->fence_list, link)
 454                 count += !atomic_read(&fence->pin_count);
 455         if (count <= 1)
 456                 return ERR_PTR(-ENOSPC);
 457
 458         fence = fence_find(ggtt);
 459         if (IS_ERR(fence))
 460                 return fence;
 461
 462         if (fence->vma) {
 463                 /* Force-remove fence from VMA */
 464                 ret = fence_update(fence, NULL);
 465                 if (ret)
 466                         return ERR_PTR(ret);
 467         }
 468
 469         list_del(&fence->link);
 470
 471         return fence;
 472 }
 473
 474 /**
 475  * i915_unreserve_fence - Reclaim a reserved fence
 476  * @fence: the fence reg
 477  *
 478  * This function add a reserved fence register from vGPU to the fence_list.
 479  */
 480 void i915_unreserve_fence(struct i915_fence_reg *fence)
 481 {
 482         struct i915_ggtt *ggtt = fence->ggtt;
 483
 484         lockdep_assert_held(&ggtt->vm.mutex);
 485
 486         list_add(&fence->link, &ggtt->fence_list);
 487 }
 488
 489 /**
 490  * i915_gem_restore_fences - restore fence state
 491  * @ggtt: Global GTT
 492  *
 493  * Restore the hw fence state to match the software tracking again, to be called
 494  * after a gpu reset and on resume. Note that on runtime suspend we only cancel
 495  * the fences, to be reacquired by the user later.
 496  */
 497 void i915_gem_restore_fences(struct i915_ggtt *ggtt)
 498 {
 499         int i;
 500
 501         rcu_read_lock(); /* keep obj alive as we dereference */
 502         for (i = 0; i < ggtt->num_fences; i++) {
 503                 struct i915_fence_reg *reg = &ggtt->fence_regs[i];
 504                 struct i915_vma *vma = READ_ONCE(reg->vma);
 505
 506                 GEM_BUG_ON(vma && vma->fence != reg);
 507
 508                 /*
 509                  * Commit delayed tiling changes if we have an object still
 510                  * attached to the fence, otherwise just clear the fence.
 511                  */
 512                 if (vma && !i915_gem_object_is_tiled(vma->obj))
 513                         vma = NULL;
 514
 515                 fence_write(reg, vma);
 516         }
 517         rcu_read_unlock();
 518 }
 519
 520 /**
 521  * DOC: tiling swizzling details
 522  *
 523  * The idea behind tiling is to increase cache hit rates by rearranging
 524  * pixel data so that a group of pixel accesses are in the same cacheline.
 525  * Performance improvement from doing this on the back/depth buffer are on
 526  * the order of 30%.
 527  *
 528  * Intel architectures make this somewhat more complicated, though, by
 529  * adjustments made to addressing of data when the memory is in interleaved
 530  * mode (matched pairs of DIMMS) to improve memory bandwidth.
 531  * For interleaved memory, the CPU sends every sequential 64 bytes
 532  * to an alternate memory channel so it can get the bandwidth from both.
 533  *
 534  * The GPU also rearranges its accesses for increased bandwidth to interleaved
 535  * memory, and it matches what the CPU does for non-tiled.  However, when tiled
 536  * it does it a little differently, since one walks addresses not just in the
 537  * X direction but also Y.  So, along with alternating channels when bit
 538  * 6 of the address flips, it also alternates when other bits flip --  Bits 9
 539  * (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines)
 540  * are common to both the 915 and 965-class hardware.
 541  *
 542  * The CPU also sometimes XORs in higher bits as well, to improve
 543  * bandwidth doing strided access like we do so frequently in graphics.  This
 544  * is called "Channel XOR Randomization" in the MCH documentation.  The result
 545  * is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address
 546  * decode.
 547  *
 548  * All of this bit 6 XORing has an effect on our memory management,
 549  * as we need to make sure that the 3d driver can correctly address object
 550  * contents.
 551  *
 552  * If we don't have interleaved memory, all tiling is safe and no swizzling is
 553  * required.
 554  *
 555  * When bit 17 is XORed in, we simply refuse to tile at all.  Bit
 556  * 17 is not just a page offset, so as we page an object out and back in,
 557  * individual pages in it will have different bit 17 addresses, resulting in
 558  * each 64 bytes being swapped with its neighbor!
 559  *
 560  * Otherwise, if interleaved, we have to tell the 3d driver what the address
 561  * swizzling it needs to do is, since it's writing with the CPU to the pages
 562  * (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the
 563  * pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling
 564  * required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order
 565  * to match what the GPU expects.
 566  */
 567
 568 /**
 569  * detect_bit_6_swizzle - detect bit 6 swizzling pattern
 570  * @ggtt: Global GGTT
 571  *
 572  * Detects bit 6 swizzling of address lookup between IGD access and CPU
 573  * access through main memory.
 574  */
 575 static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
 576 {
 577         struct intel_uncore *uncore = ggtt->vm.gt->uncore;
 578         struct drm_i915_private *i915 = ggtt->vm.i915;
 579         u32 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
 580         u32 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
 581
 582         if (INTEL_GEN(i915) >= 8 || IS_VALLEYVIEW(i915)) {
 583                 /*
 584                  * On BDW+, swizzling is not used. We leave the CPU memory
 585                  * controller in charge of optimizing memory accesses without
 586                  * the extra address manipulation GPU side.
 587                  *
 588                  * VLV and CHV don't have GPU swizzling.
 589                  */
 590                 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
 591                 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
 592         } else if (INTEL_GEN(i915) >= 6) {
 593                 if (i915->preserve_bios_swizzle) {
 594                         if (intel_uncore_read(uncore, DISP_ARB_CTL) &
 595                             DISP_TILE_SURFACE_SWIZZLING) {
 596                                 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
 597                                 swizzle_y = I915_BIT_6_SWIZZLE_9;
 598                         } else {
 599                                 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
 600                                 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
 601                         }
 602                 } else {
 603                         u32 dimm_c0, dimm_c1;
 604                         dimm_c0 = intel_uncore_read(uncore, MAD_DIMM_C0);
 605                         dimm_c1 = intel_uncore_read(uncore, MAD_DIMM_C1);
 606                         dimm_c0 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK;
 607                         dimm_c1 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK;
 608                         /*
 609                          * Enable swizzling when the channels are populated
 610                          * with identically sized dimms. We don't need to check
 611                          * the 3rd channel because no cpu with gpu attached
 612                          * ships in that configuration. Also, swizzling only
 613                          * makes sense for 2 channels anyway.
 614                          */
 615                         if (dimm_c0 == dimm_c1) {
 616                                 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
 617                                 swizzle_y = I915_BIT_6_SWIZZLE_9;
 618                         } else {
 619                                 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
 620                                 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
 621                         }
 622                 }
 623         } else if (IS_GEN(i915, 5)) {
 624                 /*
 625                  * On Ironlake whatever DRAM config, GPU always do
 626                  * same swizzling setup.
 627                  */
 628                 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
 629                 swizzle_y = I915_BIT_6_SWIZZLE_9;
 630         } else if (IS_GEN(i915, 2)) {
 631                 /*
 632                  * As far as we know, the 865 doesn't have these bit 6
 633                  * swizzling issues.
 634                  */
 635                 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
 636                 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
 637         } else if (IS_G45(i915) || IS_I965G(i915) || IS_G33(i915)) {
 638                 /*
 639                  * The 965, G33, and newer, have a very flexible memory
 640                  * configuration.  It will enable dual-channel mode
 641                  * (interleaving) on as much memory as it can, and the GPU
 642                  * will additionally sometimes enable different bit 6
 643                  * swizzling for tiled objects from the CPU.
 644                  *
 645                  * Here's what I found on the G965:
 646                  *    slot fill         memory size  swizzling
 647                  * 0A   0B   1A   1B    1-ch   2-ch
 648                  * 512  0    0    0     512    0     O
 649                  * 512  0    512  0     16     1008  X
 650                  * 512  0    0    512   16     1008  X
 651                  * 0    512  0    512   16     1008  X
 652                  * 1024 1024 1024 0     2048   1024  O
 653                  *
 654                  * We could probably detect this based on either the DRB
 655                  * matching, which was the case for the swizzling required in
 656                  * the table above, or from the 1-ch value being less than
 657                  * the minimum size of a rank.
 658                  *
 659                  * Reports indicate that the swizzling actually
 660                  * varies depending upon page placement inside the
 661                  * channels, i.e. we see swizzled pages where the
 662                  * banks of memory are paired and unswizzled on the
 663                  * uneven portion, so leave that as unknown.
 664                  */
 665                 if (intel_uncore_read(uncore, C0DRB3) ==
 666                     intel_uncore_read(uncore, C1DRB3)) {
 667                         swizzle_x = I915_BIT_6_SWIZZLE_9_10;
 668                         swizzle_y = I915_BIT_6_SWIZZLE_9;
 669                 }
 670         } else {
 671                 u32 dcc = intel_uncore_read(uncore, DCC);
 672
 673                 /*
 674                  * On 9xx chipsets, channel interleave by the CPU is
 675                  * determined by DCC.  For single-channel, neither the CPU
 676                  * nor the GPU do swizzling.  For dual channel interleaved,
 677                  * the GPU's interleave is bit 9 and 10 for X tiled, and bit
 678                  * 9 for Y tiled.  The CPU's interleave is independent, and
 679                  * can be based on either bit 11 (haven't seen this yet) or
 680                  * bit 17 (common).
 681                  */
 682                 switch (dcc & DCC_ADDRESSING_MODE_MASK) {
 683                 case DCC_ADDRESSING_MODE_SINGLE_CHANNEL:
 684                 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC:
 685                         swizzle_x = I915_BIT_6_SWIZZLE_NONE;
 686                         swizzle_y = I915_BIT_6_SWIZZLE_NONE;
 687                         break;
 688                 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED:
 689                         if (dcc & DCC_CHANNEL_XOR_DISABLE) {
 690                                 /*
 691                                  * This is the base swizzling by the GPU for
 692                                  * tiled buffers.
 693                                  */
 694                                 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
 695                                 swizzle_y = I915_BIT_6_SWIZZLE_9;
 696                         } else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) {
 697                                 /* Bit 11 swizzling by the CPU in addition. */
 698                                 swizzle_x = I915_BIT_6_SWIZZLE_9_10_11;
 699                                 swizzle_y = I915_BIT_6_SWIZZLE_9_11;
 700                         } else {
 701                                 /* Bit 17 swizzling by the CPU in addition. */
 702                                 swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;
 703                                 swizzle_y = I915_BIT_6_SWIZZLE_9_17;
 704                         }
 705                         break;
 706                 }
 707
 708                 /* check for L-shaped memory aka modified enhanced addressing */
 709                 if (IS_GEN(i915, 4) &&
 710                     !(intel_uncore_read(uncore, DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) {
 711                         swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
 712                         swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
 713                 }
 714
 715                 if (dcc == 0xffffffff) {
 716                         drm_err(&i915->drm, "Couldn't read from MCHBAR.  "
 717                                   "Disabling tiling.\n");
 718                         swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
 719                         swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
 720                 }
 721         }
 722
 723         if (swizzle_x == I915_BIT_6_SWIZZLE_UNKNOWN ||
 724             swizzle_y == I915_BIT_6_SWIZZLE_UNKNOWN) {
 725                 /*
 726                  * Userspace likes to explode if it sees unknown swizzling,
 727                  * so lie. We will finish the lie when reporting through
 728                  * the get-tiling-ioctl by reporting the physical swizzle
 729                  * mode as unknown instead.
 730                  *
 731                  * As we don't strictly know what the swizzling is, it may be
 732                  * bit17 dependent, and so we need to also prevent the pages
 733                  * from being moved.
 734                  */
 735                 i915->quirks |= QUIRK_PIN_SWIZZLED_PAGES;
 736                 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
 737                 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
 738         }
 739
 740         i915->ggtt.bit_6_swizzle_x = swizzle_x;
 741         i915->ggtt.bit_6_swizzle_y = swizzle_y;
 742 }
 743
 744 /*
 745  * Swap every 64 bytes of this page around, to account for it having a new
 746  * bit 17 of its physical address and therefore being interpreted differently
 747  * by the GPU.
 748  */
 749 static void i915_gem_swizzle_page(struct page *page)
 750 {
 751         char temp[64];
 752         char *vaddr;
 753         int i;
 754
 755         vaddr = kmap(page);
 756
 757         for (i = 0; i < PAGE_SIZE; i += 128) {
 758                 memcpy(temp, &vaddr[i], 64);
 759                 memcpy(&vaddr[i], &vaddr[i + 64], 64);
 760                 memcpy(&vaddr[i + 64], temp, 64);
 761         }
 762
 763         kunmap(page);
 764 }
 765
 766 /**
 767  * i915_gem_object_do_bit_17_swizzle - fixup bit 17 swizzling
 768  * @obj: i915 GEM buffer object
 769  * @pages: the scattergather list of physical pages
 770  *
 771  * This function fixes up the swizzling in case any page frame number for this
 772  * object has changed in bit 17 since that state has been saved with
 773  * i915_gem_object_save_bit_17_swizzle().
 774  *
 775  * This is called when pinning backing storage again, since the kernel is free
 776  * to move unpinned backing storage around (either by directly moving pages or
 777  * by swapping them out and back in again).
 778  */
 779 void
 780 i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
 781                                   struct sg_table *pages)
 782 {
 783         struct sgt_iter sgt_iter;
 784         struct page *page;
 785         int i;
 786
 787         if (obj->bit_17 == NULL)
 788                 return;
 789
 790         i = 0;
 791         for_each_sgt_page(page, sgt_iter, pages) {
 792                 char new_bit_17 = page_to_phys(page) >> 17;
 793                 if ((new_bit_17 & 0x1) != (test_bit(i, obj->bit_17) != 0)) {
 794                         i915_gem_swizzle_page(page);
 795                         set_page_dirty(page);
 796                 }
 797                 i++;
 798         }
 799 }
 800
 801 /**
 802  * i915_gem_object_save_bit_17_swizzle - save bit 17 swizzling
 803  * @obj: i915 GEM buffer object
 804  * @pages: the scattergather list of physical pages
 805  *
 806  * This function saves the bit 17 of each page frame number so that swizzling
 807  * can be fixed up later on with i915_gem_object_do_bit_17_swizzle(). This must
 808  * be called before the backing storage can be unpinned.
 809  */
 810 void
 811 i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
 812                                     struct sg_table *pages)
 813 {
 814         const unsigned int page_count = obj->base.size >> PAGE_SHIFT;
 815         struct sgt_iter sgt_iter;
 816         struct page *page;
 817         int i;
 818
 819         if (obj->bit_17 == NULL) {
 820                 obj->bit_17 = bitmap_zalloc(page_count, GFP_KERNEL);
 821                 if (obj->bit_17 == NULL) {
 822                         DRM_ERROR("Failed to allocate memory for bit 17 "
 823                                   "record\n");
 824                         return;
 825                 }
 826         }
 827
 828         i = 0;
 829
 830         for_each_sgt_page(page, sgt_iter, pages) {
 831                 if (page_to_phys(page) & (1 << 17))
 832                         __set_bit(i, obj->bit_17);
 833                 else
 834                         __clear_bit(i, obj->bit_17);
 835                 i++;
 836         }
 837 }
 838
 839 void i915_ggtt_init_fences(struct i915_ggtt *ggtt)
 840 {
 841         struct drm_i915_private *i915 = ggtt->vm.i915;
 842         struct intel_uncore *uncore = ggtt->vm.gt->uncore;
 843         int num_fences;
 844         int i;
 845
 846         INIT_LIST_HEAD(&ggtt->fence_list);
 847         INIT_LIST_HEAD(&ggtt->userfault_list);
 848         intel_wakeref_auto_init(&ggtt->userfault_wakeref, uncore->rpm);
 849
 850         detect_bit_6_swizzle(ggtt);
 851
 852         if (!i915_ggtt_has_aperture(ggtt))
 853                 num_fences = 0;
 854         else if (INTEL_GEN(i915) >= 7 &&
 855                  !(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)))
 856                 num_fences = 32;
 857         else if (INTEL_GEN(i915) >= 4 ||
 858                  IS_I945G(i915) || IS_I945GM(i915) ||
 859                  IS_G33(i915) || IS_PINEVIEW(i915))
 860                 num_fences = 16;
 861         else
 862                 num_fences = 8;
 863
 864         if (intel_vgpu_active(i915))
 865                 num_fences = intel_uncore_read(uncore,
 866                                                vgtif_reg(avail_rs.fence_num));
 867
 868         /* Initialize fence registers to zero */
 869         for (i = 0; i < num_fences; i++) {
 870                 struct i915_fence_reg *fence = &ggtt->fence_regs[i];
 871
 872                 fence->ggtt = ggtt;
 873                 fence->id = i;
 874                 list_add_tail(&fence->link, &ggtt->fence_list);
 875         }
 876         ggtt->num_fences = num_fences;
 877
 878         i915_gem_restore_fences(ggtt);
 879 }
 880
 881 void intel_gt_init_swizzling(struct intel_gt *gt)
 882 {
 883         struct drm_i915_private *i915 = gt->i915;
 884         struct intel_uncore *uncore = gt->uncore;
 885
 886         if (INTEL_GEN(i915) < 5 ||
 887             i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
 888                 return;
 889
 890         intel_uncore_rmw(uncore, DISP_ARB_CTL, 0, DISP_TILE_SURFACE_SWIZZLING);
 891
 892         if (IS_GEN(i915, 5))
 893                 return;
 894
 895         intel_uncore_rmw(uncore, TILECTL, 0, TILECTL_SWZCTL);
 896
 897         if (IS_GEN(i915, 6))
 898                 intel_uncore_write(uncore,
 899                                    ARB_MODE,
 900                                    _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
 901         else if (IS_GEN(i915, 7))
 902                 intel_uncore_write(uncore,
 903                                    ARB_MODE,
 904                                    _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
 905         else if (IS_GEN(i915, 8))
 906                 intel_uncore_write(uncore,
 907                                    GAMTARBMODE,
 908                                    _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
 909         else
 910                 MISSING_CASE(INTEL_GEN(i915));
 911 }