2 * Copyright © 2008,2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include <linux/dma_remapping.h>
39 struct hlist_head buckets[0];
42 static struct eb_objects *
45 struct eb_objects *eb;
46 int count = PAGE_SIZE / sizeof(struct hlist_head) / 2;
49 eb = kzalloc(count*sizeof(struct hlist_head) +
50 sizeof(struct eb_objects),
60 eb_reset(struct eb_objects *eb)
62 memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head));
66 eb_add_object(struct eb_objects *eb, struct drm_i915_gem_object *obj)
68 hlist_add_head(&obj->exec_node,
69 &eb->buckets[obj->exec_handle & eb->and]);
72 static struct drm_i915_gem_object *
73 eb_get_object(struct eb_objects *eb, unsigned long handle)
75 struct hlist_head *head;
76 struct hlist_node *node;
77 struct drm_i915_gem_object *obj;
79 head = &eb->buckets[handle & eb->and];
80 hlist_for_each(node, head) {
81 obj = hlist_entry(node, struct drm_i915_gem_object, exec_node);
82 if (obj->exec_handle == handle)
90 eb_destroy(struct eb_objects *eb)
95 static inline int use_cpu_reloc(struct drm_i915_gem_object *obj)
97 return (obj->base.write_domain == I915_GEM_DOMAIN_CPU ||
98 obj->cache_level != I915_CACHE_NONE);
102 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
103 struct eb_objects *eb,
104 struct drm_i915_gem_relocation_entry *reloc)
106 struct drm_device *dev = obj->base.dev;
107 struct drm_gem_object *target_obj;
108 struct drm_i915_gem_object *target_i915_obj;
109 uint32_t target_offset;
112 /* we've already hold a reference to all valid objects */
113 target_obj = &eb_get_object(eb, reloc->target_handle)->base;
114 if (unlikely(target_obj == NULL))
117 target_i915_obj = to_intel_bo(target_obj);
118 target_offset = target_i915_obj->gtt_offset;
120 /* The target buffer should have appeared before us in the
121 * exec_object list, so it should have a GTT space bound by now.
123 if (unlikely(target_offset == 0)) {
124 DRM_DEBUG("No GTT space found for object %d\n",
125 reloc->target_handle);
129 /* Validate that the target is in a valid r/w GPU domain */
130 if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
131 DRM_DEBUG("reloc with multiple write domains: "
132 "obj %p target %d offset %d "
133 "read %08x write %08x",
134 obj, reloc->target_handle,
137 reloc->write_domain);
140 if (unlikely((reloc->write_domain | reloc->read_domains)
141 & ~I915_GEM_GPU_DOMAINS)) {
142 DRM_DEBUG("reloc with read/write non-GPU domains: "
143 "obj %p target %d offset %d "
144 "read %08x write %08x",
145 obj, reloc->target_handle,
148 reloc->write_domain);
151 if (unlikely(reloc->write_domain && target_obj->pending_write_domain &&
152 reloc->write_domain != target_obj->pending_write_domain)) {
153 DRM_DEBUG("Write domain conflict: "
154 "obj %p target %d offset %d "
155 "new %08x old %08x\n",
156 obj, reloc->target_handle,
159 target_obj->pending_write_domain);
163 target_obj->pending_read_domains |= reloc->read_domains;
164 target_obj->pending_write_domain |= reloc->write_domain;
166 /* If the relocation already has the right value in it, no
167 * more work needs to be done.
169 if (target_offset == reloc->presumed_offset)
172 /* Check that the relocation address is valid... */
173 if (unlikely(reloc->offset > obj->base.size - 4)) {
174 DRM_DEBUG("Relocation beyond object bounds: "
175 "obj %p target %d offset %d size %d.\n",
176 obj, reloc->target_handle,
178 (int) obj->base.size);
181 if (unlikely(reloc->offset & 3)) {
182 DRM_DEBUG("Relocation not 4-byte aligned: "
183 "obj %p target %d offset %d.\n",
184 obj, reloc->target_handle,
185 (int) reloc->offset);
189 /* We can't wait for rendering with pagefaults disabled */
190 if (obj->active && in_atomic())
193 reloc->delta += target_offset;
194 if (use_cpu_reloc(obj)) {
195 uint32_t page_offset = reloc->offset & ~PAGE_MASK;
198 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
202 vaddr = kmap_atomic(obj->pages[reloc->offset >> PAGE_SHIFT]);
203 *(uint32_t *)(vaddr + page_offset) = reloc->delta;
204 kunmap_atomic(vaddr);
206 struct drm_i915_private *dev_priv = dev->dev_private;
207 uint32_t __iomem *reloc_entry;
208 void __iomem *reloc_page;
210 ret = i915_gem_object_set_to_gtt_domain(obj, true);
214 ret = i915_gem_object_put_fence(obj);
218 /* Map the page containing the relocation we're going to perform. */
219 reloc->offset += obj->gtt_offset;
220 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
221 reloc->offset & PAGE_MASK);
222 reloc_entry = (uint32_t __iomem *)
223 (reloc_page + (reloc->offset & ~PAGE_MASK));
224 iowrite32(reloc->delta, reloc_entry);
225 io_mapping_unmap_atomic(reloc_page);
228 /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
229 * pipe_control writes because the gpu doesn't properly redirect them
230 * through the ppgtt for non_secure batchbuffers. */
231 if (unlikely(IS_GEN6(dev) &&
232 reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
233 !target_i915_obj->has_global_gtt_mapping)) {
234 i915_gem_gtt_bind_object(target_i915_obj,
235 target_i915_obj->cache_level);
238 /* and update the user's relocation entry */
239 reloc->presumed_offset = target_offset;
245 i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj,
246 struct eb_objects *eb)
248 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
249 struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)];
250 struct drm_i915_gem_relocation_entry __user *user_relocs;
251 struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
254 user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr;
256 remain = entry->relocation_count;
258 struct drm_i915_gem_relocation_entry *r = stack_reloc;
260 if (count > ARRAY_SIZE(stack_reloc))
261 count = ARRAY_SIZE(stack_reloc);
264 if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0])))
268 u64 offset = r->presumed_offset;
270 ret = i915_gem_execbuffer_relocate_entry(obj, eb, r);
274 if (r->presumed_offset != offset &&
275 __copy_to_user_inatomic(&user_relocs->presumed_offset,
277 sizeof(r->presumed_offset))) {
291 i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj,
292 struct eb_objects *eb,
293 struct drm_i915_gem_relocation_entry *relocs)
295 const struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
298 for (i = 0; i < entry->relocation_count; i++) {
299 ret = i915_gem_execbuffer_relocate_entry(obj, eb, &relocs[i]);
308 i915_gem_execbuffer_relocate(struct drm_device *dev,
309 struct eb_objects *eb,
310 struct list_head *objects)
312 struct drm_i915_gem_object *obj;
315 /* This is the fast path and we cannot handle a pagefault whilst
316 * holding the struct mutex lest the user pass in the relocations
317 * contained within a mmaped bo. For in such a case we, the page
318 * fault handler would call i915_gem_fault() and we would try to
319 * acquire the struct mutex again. Obviously this is bad and so
320 * lockdep complains vehemently.
323 list_for_each_entry(obj, objects, exec_list) {
324 ret = i915_gem_execbuffer_relocate_object(obj, eb);
333 #define __EXEC_OBJECT_HAS_FENCE (1<<31)
336 need_reloc_mappable(struct drm_i915_gem_object *obj)
338 struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
339 return entry->relocation_count && !use_cpu_reloc(obj);
343 pin_and_fence_object(struct drm_i915_gem_object *obj,
344 struct intel_ring_buffer *ring)
346 struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
347 bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
348 bool need_fence, need_mappable;
352 has_fenced_gpu_access &&
353 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
354 obj->tiling_mode != I915_TILING_NONE;
355 need_mappable = need_fence || need_reloc_mappable(obj);
357 ret = i915_gem_object_pin(obj, entry->alignment, need_mappable);
361 if (has_fenced_gpu_access) {
362 if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
363 ret = i915_gem_object_get_fence(obj);
367 if (i915_gem_object_pin_fence(obj))
368 entry->flags |= __EXEC_OBJECT_HAS_FENCE;
370 obj->pending_fenced_gpu_access = true;
374 entry->offset = obj->gtt_offset;
378 i915_gem_object_unpin(obj);
383 i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring,
384 struct drm_file *file,
385 struct list_head *objects)
387 drm_i915_private_t *dev_priv = ring->dev->dev_private;
388 struct drm_i915_gem_object *obj;
390 bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
391 struct list_head ordered_objects;
393 INIT_LIST_HEAD(&ordered_objects);
394 while (!list_empty(objects)) {
395 struct drm_i915_gem_exec_object2 *entry;
396 bool need_fence, need_mappable;
398 obj = list_first_entry(objects,
399 struct drm_i915_gem_object,
401 entry = obj->exec_entry;
404 has_fenced_gpu_access &&
405 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
406 obj->tiling_mode != I915_TILING_NONE;
407 need_mappable = need_fence || need_reloc_mappable(obj);
410 list_move(&obj->exec_list, &ordered_objects);
412 list_move_tail(&obj->exec_list, &ordered_objects);
414 obj->base.pending_read_domains = 0;
415 obj->base.pending_write_domain = 0;
416 obj->pending_fenced_gpu_access = false;
418 list_splice(&ordered_objects, objects);
420 /* Attempt to pin all of the buffers into the GTT.
421 * This is done in 3 phases:
423 * 1a. Unbind all objects that do not match the GTT constraints for
424 * the execbuffer (fenceable, mappable, alignment etc).
425 * 1b. Increment pin count for already bound objects.
426 * 2. Bind new objects.
427 * 3. Decrement pin count.
429 * This avoid unnecessary unbinding of later objects in order to makr
430 * room for the earlier objects *unless* we need to defragment.
436 /* Unbind any ill-fitting objects or pin. */
437 list_for_each_entry(obj, objects, exec_list) {
438 struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
439 bool need_fence, need_mappable;
445 has_fenced_gpu_access &&
446 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
447 obj->tiling_mode != I915_TILING_NONE;
448 need_mappable = need_fence || need_reloc_mappable(obj);
450 if ((entry->alignment && obj->gtt_offset & (entry->alignment - 1)) ||
451 (need_mappable && !obj->map_and_fenceable))
452 ret = i915_gem_object_unbind(obj);
454 ret = pin_and_fence_object(obj, ring);
459 /* Bind fresh objects */
460 list_for_each_entry(obj, objects, exec_list) {
464 ret = pin_and_fence_object(obj, ring);
468 /* This can potentially raise a harmless
469 * -EINVAL if we failed to bind in the above
470 * call. It cannot raise -EINTR since we know
471 * that the bo is freshly bound and so will
472 * not need to be flushed or waited upon.
474 ret_ignore = i915_gem_object_unbind(obj);
476 WARN_ON(obj->gtt_space);
481 /* Decrement pin count for bound objects */
482 list_for_each_entry(obj, objects, exec_list) {
483 struct drm_i915_gem_exec_object2 *entry;
488 entry = obj->exec_entry;
489 if (entry->flags & __EXEC_OBJECT_HAS_FENCE) {
490 i915_gem_object_unpin_fence(obj);
491 entry->flags &= ~__EXEC_OBJECT_HAS_FENCE;
494 i915_gem_object_unpin(obj);
496 /* ... and ensure ppgtt mapping exist if needed. */
497 if (dev_priv->mm.aliasing_ppgtt && !obj->has_aliasing_ppgtt_mapping) {
498 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
499 obj, obj->cache_level);
501 obj->has_aliasing_ppgtt_mapping = 1;
505 if (ret != -ENOSPC || retry > 1)
508 /* First attempt, just clear anything that is purgeable.
509 * Second attempt, clear the entire GTT.
511 ret = i915_gem_evict_everything(ring->dev, retry == 0);
519 list_for_each_entry_continue_reverse(obj, objects, exec_list) {
520 struct drm_i915_gem_exec_object2 *entry;
525 entry = obj->exec_entry;
526 if (entry->flags & __EXEC_OBJECT_HAS_FENCE) {
527 i915_gem_object_unpin_fence(obj);
528 entry->flags &= ~__EXEC_OBJECT_HAS_FENCE;
531 i915_gem_object_unpin(obj);
538 i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
539 struct drm_file *file,
540 struct intel_ring_buffer *ring,
541 struct list_head *objects,
542 struct eb_objects *eb,
543 struct drm_i915_gem_exec_object2 *exec,
546 struct drm_i915_gem_relocation_entry *reloc;
547 struct drm_i915_gem_object *obj;
551 /* We may process another execbuffer during the unlock... */
552 while (!list_empty(objects)) {
553 obj = list_first_entry(objects,
554 struct drm_i915_gem_object,
556 list_del_init(&obj->exec_list);
557 drm_gem_object_unreference(&obj->base);
560 mutex_unlock(&dev->struct_mutex);
563 for (i = 0; i < count; i++)
564 total += exec[i].relocation_count;
566 reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset));
567 reloc = drm_malloc_ab(total, sizeof(*reloc));
568 if (reloc == NULL || reloc_offset == NULL) {
569 drm_free_large(reloc);
570 drm_free_large(reloc_offset);
571 mutex_lock(&dev->struct_mutex);
576 for (i = 0; i < count; i++) {
577 struct drm_i915_gem_relocation_entry __user *user_relocs;
579 user_relocs = (void __user *)(uintptr_t)exec[i].relocs_ptr;
581 if (copy_from_user(reloc+total, user_relocs,
582 exec[i].relocation_count * sizeof(*reloc))) {
584 mutex_lock(&dev->struct_mutex);
588 reloc_offset[i] = total;
589 total += exec[i].relocation_count;
592 ret = i915_mutex_lock_interruptible(dev);
594 mutex_lock(&dev->struct_mutex);
598 /* reacquire the objects */
600 for (i = 0; i < count; i++) {
601 obj = to_intel_bo(drm_gem_object_lookup(dev, file,
603 if (&obj->base == NULL) {
604 DRM_DEBUG("Invalid object handle %d at index %d\n",
610 list_add_tail(&obj->exec_list, objects);
611 obj->exec_handle = exec[i].handle;
612 obj->exec_entry = &exec[i];
613 eb_add_object(eb, obj);
616 ret = i915_gem_execbuffer_reserve(ring, file, objects);
620 list_for_each_entry(obj, objects, exec_list) {
621 int offset = obj->exec_entry - exec;
622 ret = i915_gem_execbuffer_relocate_object_slow(obj, eb,
623 reloc + reloc_offset[offset]);
628 /* Leave the user relocations as are, this is the painfully slow path,
629 * and we want to avoid the complication of dropping the lock whilst
630 * having buffers reserved in the aperture and so causing spurious
631 * ENOSPC for random operations.
635 drm_free_large(reloc);
636 drm_free_large(reloc_offset);
641 i915_gem_execbuffer_wait_for_flips(struct intel_ring_buffer *ring, u32 flips)
643 u32 plane, flip_mask;
646 /* Check for any pending flips. As we only maintain a flip queue depth
647 * of 1, we can simply insert a WAIT for the next display flip prior
648 * to executing the batch and avoid stalling the CPU.
651 for (plane = 0; flips >> plane; plane++) {
652 if (((flips >> plane) & 1) == 0)
656 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
658 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
660 ret = intel_ring_begin(ring, 2);
664 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
665 intel_ring_emit(ring, MI_NOOP);
666 intel_ring_advance(ring);
673 i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring,
674 struct list_head *objects)
676 struct drm_i915_gem_object *obj;
677 uint32_t flush_domains = 0;
681 list_for_each_entry(obj, objects, exec_list) {
682 ret = i915_gem_object_sync(obj, ring);
686 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
687 i915_gem_clflush_object(obj);
689 if (obj->base.pending_write_domain)
690 flips |= atomic_read(&obj->pending_flip);
692 flush_domains |= obj->base.write_domain;
696 ret = i915_gem_execbuffer_wait_for_flips(ring, flips);
701 if (flush_domains & I915_GEM_DOMAIN_CPU)
702 intel_gtt_chipset_flush();
704 if (flush_domains & I915_GEM_DOMAIN_GTT)
707 /* Unconditionally invalidate gpu caches and ensure that we do flush
708 * any residual writes from the previous batch.
710 return intel_ring_invalidate_all_caches(ring);
714 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
716 return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0;
720 validate_exec_list(struct drm_i915_gem_exec_object2 *exec,
725 for (i = 0; i < count; i++) {
726 char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr;
727 int length; /* limited by fault_in_pages_readable() */
729 /* First check for malicious input causing overflow */
730 if (exec[i].relocation_count >
731 INT_MAX / sizeof(struct drm_i915_gem_relocation_entry))
734 length = exec[i].relocation_count *
735 sizeof(struct drm_i915_gem_relocation_entry);
736 if (!access_ok(VERIFY_READ, ptr, length))
739 /* we may also need to update the presumed offsets */
740 if (!access_ok(VERIFY_WRITE, ptr, length))
743 if (fault_in_multipages_readable(ptr, length))
751 i915_gem_execbuffer_move_to_active(struct list_head *objects,
752 struct intel_ring_buffer *ring,
755 struct drm_i915_gem_object *obj;
757 list_for_each_entry(obj, objects, exec_list) {
758 u32 old_read = obj->base.read_domains;
759 u32 old_write = obj->base.write_domain;
761 obj->base.read_domains = obj->base.pending_read_domains;
762 obj->base.write_domain = obj->base.pending_write_domain;
763 obj->fenced_gpu_access = obj->pending_fenced_gpu_access;
765 i915_gem_object_move_to_active(obj, ring, seqno);
766 if (obj->base.write_domain) {
768 obj->last_write_seqno = seqno;
769 if (obj->pin_count) /* check for potential scanout */
770 intel_mark_fb_busy(obj);
773 trace_i915_gem_object_change_domain(obj, old_read, old_write);
778 i915_gem_execbuffer_retire_commands(struct drm_device *dev,
779 struct drm_file *file,
780 struct intel_ring_buffer *ring)
782 /* Unconditionally force add_request to emit a full flush. */
783 ring->gpu_caches_dirty = true;
785 /* Add a breadcrumb for the completion of the batch buffer */
786 (void)i915_add_request(ring, file, NULL);
790 i915_reset_gen7_sol_offsets(struct drm_device *dev,
791 struct intel_ring_buffer *ring)
793 drm_i915_private_t *dev_priv = dev->dev_private;
796 if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS])
799 ret = intel_ring_begin(ring, 4 * 3);
803 for (i = 0; i < 4; i++) {
804 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
805 intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i));
806 intel_ring_emit(ring, 0);
809 intel_ring_advance(ring);
815 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
816 struct drm_file *file,
817 struct drm_i915_gem_execbuffer2 *args,
818 struct drm_i915_gem_exec_object2 *exec)
820 drm_i915_private_t *dev_priv = dev->dev_private;
821 struct list_head objects;
822 struct eb_objects *eb;
823 struct drm_i915_gem_object *batch_obj;
824 struct drm_clip_rect *cliprects = NULL;
825 struct intel_ring_buffer *ring;
826 u32 ctx_id = i915_execbuffer2_get_context_id(*args);
827 u32 exec_start, exec_len;
832 if (!i915_gem_check_execbuffer(args)) {
833 DRM_DEBUG("execbuf with invalid offset/length\n");
837 ret = validate_exec_list(exec, args->buffer_count);
841 switch (args->flags & I915_EXEC_RING_MASK) {
842 case I915_EXEC_DEFAULT:
843 case I915_EXEC_RENDER:
844 ring = &dev_priv->ring[RCS];
847 ring = &dev_priv->ring[VCS];
849 DRM_DEBUG("Ring %s doesn't support contexts\n",
855 ring = &dev_priv->ring[BCS];
857 DRM_DEBUG("Ring %s doesn't support contexts\n",
863 DRM_DEBUG("execbuf with unknown ring: %d\n",
864 (int)(args->flags & I915_EXEC_RING_MASK));
867 if (!intel_ring_initialized(ring)) {
868 DRM_DEBUG("execbuf with invalid ring: %d\n",
869 (int)(args->flags & I915_EXEC_RING_MASK));
873 mode = args->flags & I915_EXEC_CONSTANTS_MASK;
874 mask = I915_EXEC_CONSTANTS_MASK;
876 case I915_EXEC_CONSTANTS_REL_GENERAL:
877 case I915_EXEC_CONSTANTS_ABSOLUTE:
878 case I915_EXEC_CONSTANTS_REL_SURFACE:
879 if (ring == &dev_priv->ring[RCS] &&
880 mode != dev_priv->relative_constants_mode) {
881 if (INTEL_INFO(dev)->gen < 4)
884 if (INTEL_INFO(dev)->gen > 5 &&
885 mode == I915_EXEC_CONSTANTS_REL_SURFACE)
888 /* The HW changed the meaning on this bit on gen6 */
889 if (INTEL_INFO(dev)->gen >= 6)
890 mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
894 DRM_DEBUG("execbuf with unknown constants: %d\n", mode);
898 if (args->buffer_count < 1) {
899 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
903 if (args->num_cliprects != 0) {
904 if (ring != &dev_priv->ring[RCS]) {
905 DRM_DEBUG("clip rectangles are only valid with the render ring\n");
909 if (INTEL_INFO(dev)->gen >= 5) {
910 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
914 if (args->num_cliprects > UINT_MAX / sizeof(*cliprects)) {
915 DRM_DEBUG("execbuf with %u cliprects\n",
916 args->num_cliprects);
920 cliprects = kmalloc(args->num_cliprects * sizeof(*cliprects),
922 if (cliprects == NULL) {
927 if (copy_from_user(cliprects,
928 (struct drm_clip_rect __user *)(uintptr_t)
930 sizeof(*cliprects)*args->num_cliprects)) {
936 ret = i915_mutex_lock_interruptible(dev);
940 if (dev_priv->mm.suspended) {
941 mutex_unlock(&dev->struct_mutex);
946 eb = eb_create(args->buffer_count);
948 mutex_unlock(&dev->struct_mutex);
953 /* Look up object handles */
954 INIT_LIST_HEAD(&objects);
955 for (i = 0; i < args->buffer_count; i++) {
956 struct drm_i915_gem_object *obj;
958 obj = to_intel_bo(drm_gem_object_lookup(dev, file,
960 if (&obj->base == NULL) {
961 DRM_DEBUG("Invalid object handle %d at index %d\n",
963 /* prevent error path from reading uninitialized data */
968 if (!list_empty(&obj->exec_list)) {
969 DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
970 obj, exec[i].handle, i);
975 list_add_tail(&obj->exec_list, &objects);
976 obj->exec_handle = exec[i].handle;
977 obj->exec_entry = &exec[i];
978 eb_add_object(eb, obj);
981 /* take note of the batch buffer before we might reorder the lists */
982 batch_obj = list_entry(objects.prev,
983 struct drm_i915_gem_object,
986 /* Move the objects en-masse into the GTT, evicting if necessary. */
987 ret = i915_gem_execbuffer_reserve(ring, file, &objects);
991 /* The objects are in their final locations, apply the relocations. */
992 ret = i915_gem_execbuffer_relocate(dev, eb, &objects);
994 if (ret == -EFAULT) {
995 ret = i915_gem_execbuffer_relocate_slow(dev, file, ring,
999 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1005 /* Set the pending read domains for the batch buffer to COMMAND */
1006 if (batch_obj->base.pending_write_domain) {
1007 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
1011 batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
1013 ret = i915_gem_execbuffer_move_to_gpu(ring, &objects);
1017 seqno = i915_gem_next_request_seqno(ring);
1018 for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) {
1019 if (seqno < ring->sync_seqno[i]) {
1020 /* The GPU can not handle its semaphore value wrapping,
1021 * so every billion or so execbuffers, we need to stall
1022 * the GPU in order to reset the counters.
1024 ret = i915_gpu_idle(dev);
1027 i915_gem_retire_requests(dev);
1029 BUG_ON(ring->sync_seqno[i]);
1033 ret = i915_switch_context(ring, file, ctx_id);
1037 if (ring == &dev_priv->ring[RCS] &&
1038 mode != dev_priv->relative_constants_mode) {
1039 ret = intel_ring_begin(ring, 4);
1043 intel_ring_emit(ring, MI_NOOP);
1044 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1045 intel_ring_emit(ring, INSTPM);
1046 intel_ring_emit(ring, mask << 16 | mode);
1047 intel_ring_advance(ring);
1049 dev_priv->relative_constants_mode = mode;
1052 if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
1053 ret = i915_reset_gen7_sol_offsets(dev, ring);
1058 trace_i915_gem_ring_dispatch(ring, seqno);
1060 exec_start = batch_obj->gtt_offset + args->batch_start_offset;
1061 exec_len = args->batch_len;
1063 for (i = 0; i < args->num_cliprects; i++) {
1064 ret = i915_emit_box(dev, &cliprects[i],
1065 args->DR1, args->DR4);
1069 ret = ring->dispatch_execbuffer(ring,
1070 exec_start, exec_len);
1075 ret = ring->dispatch_execbuffer(ring, exec_start, exec_len);
1080 i915_gem_execbuffer_move_to_active(&objects, ring, seqno);
1081 i915_gem_execbuffer_retire_commands(dev, file, ring);
1085 while (!list_empty(&objects)) {
1086 struct drm_i915_gem_object *obj;
1088 obj = list_first_entry(&objects,
1089 struct drm_i915_gem_object,
1091 list_del_init(&obj->exec_list);
1092 drm_gem_object_unreference(&obj->base);
1095 mutex_unlock(&dev->struct_mutex);
1103 * Legacy execbuffer just creates an exec2 list from the original exec object
1104 * list array and passes it to the real function.
1107 i915_gem_execbuffer(struct drm_device *dev, void *data,
1108 struct drm_file *file)
1110 struct drm_i915_gem_execbuffer *args = data;
1111 struct drm_i915_gem_execbuffer2 exec2;
1112 struct drm_i915_gem_exec_object *exec_list = NULL;
1113 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1116 if (args->buffer_count < 1) {
1117 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1121 /* Copy in the exec list from userland */
1122 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
1123 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
1124 if (exec_list == NULL || exec2_list == NULL) {
1125 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1126 args->buffer_count);
1127 drm_free_large(exec_list);
1128 drm_free_large(exec2_list);
1131 ret = copy_from_user(exec_list,
1132 (struct drm_i915_relocation_entry __user *)
1133 (uintptr_t) args->buffers_ptr,
1134 sizeof(*exec_list) * args->buffer_count);
1136 DRM_DEBUG("copy %d exec entries failed %d\n",
1137 args->buffer_count, ret);
1138 drm_free_large(exec_list);
1139 drm_free_large(exec2_list);
1143 for (i = 0; i < args->buffer_count; i++) {
1144 exec2_list[i].handle = exec_list[i].handle;
1145 exec2_list[i].relocation_count = exec_list[i].relocation_count;
1146 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
1147 exec2_list[i].alignment = exec_list[i].alignment;
1148 exec2_list[i].offset = exec_list[i].offset;
1149 if (INTEL_INFO(dev)->gen < 4)
1150 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
1152 exec2_list[i].flags = 0;
1155 exec2.buffers_ptr = args->buffers_ptr;
1156 exec2.buffer_count = args->buffer_count;
1157 exec2.batch_start_offset = args->batch_start_offset;
1158 exec2.batch_len = args->batch_len;
1159 exec2.DR1 = args->DR1;
1160 exec2.DR4 = args->DR4;
1161 exec2.num_cliprects = args->num_cliprects;
1162 exec2.cliprects_ptr = args->cliprects_ptr;
1163 exec2.flags = I915_EXEC_RENDER;
1164 i915_execbuffer2_set_context_id(exec2, 0);
1166 ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list);
1168 /* Copy the new buffer offsets back to the user's exec list. */
1169 for (i = 0; i < args->buffer_count; i++)
1170 exec_list[i].offset = exec2_list[i].offset;
1171 /* ... and back out to userspace */
1172 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
1173 (uintptr_t) args->buffers_ptr,
1175 sizeof(*exec_list) * args->buffer_count);
1178 DRM_DEBUG("failed to copy %d exec entries "
1179 "back to user (%d)\n",
1180 args->buffer_count, ret);
1184 drm_free_large(exec_list);
1185 drm_free_large(exec2_list);
1190 i915_gem_execbuffer2(struct drm_device *dev, void *data,
1191 struct drm_file *file)
1193 struct drm_i915_gem_execbuffer2 *args = data;
1194 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1197 if (args->buffer_count < 1 ||
1198 args->buffer_count > UINT_MAX / sizeof(*exec2_list)) {
1199 DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count);
1203 exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count,
1204 GFP_KERNEL | __GFP_NOWARN | __GFP_NORETRY);
1205 if (exec2_list == NULL)
1206 exec2_list = drm_malloc_ab(sizeof(*exec2_list),
1207 args->buffer_count);
1208 if (exec2_list == NULL) {
1209 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1210 args->buffer_count);
1213 ret = copy_from_user(exec2_list,
1214 (struct drm_i915_relocation_entry __user *)
1215 (uintptr_t) args->buffers_ptr,
1216 sizeof(*exec2_list) * args->buffer_count);
1218 DRM_DEBUG("copy %d exec entries failed %d\n",
1219 args->buffer_count, ret);
1220 drm_free_large(exec2_list);
1224 ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list);
1226 /* Copy the new buffer offsets back to the user's exec list. */
1227 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
1228 (uintptr_t) args->buffers_ptr,
1230 sizeof(*exec2_list) * args->buffer_count);
1233 DRM_DEBUG("failed to copy %d exec entries "
1234 "back to user (%d)\n",
1235 args->buffer_count, ret);
1239 drm_free_large(exec2_list);