2 * Copyright © 2011-2012 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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11 * The above copyright notice and this permission notice (including the next
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
29 * This file implements HW context support. On gen5+ a HW context consists of an
30 * opaque GPU object which is referenced at times of context saves and restores.
31 * With RC6 enabled, the context is also referenced as the GPU enters and exists
32 * from RC6 (GPU has it's own internal power context, except on gen5). Though
33 * something like a context does exist for the media ring, the code only
34 * supports contexts for the render ring.
36 * In software, there is a distinction between contexts created by the user,
37 * and the default HW context. The default HW context is used by GPU clients
38 * that do not request setup of their own hardware context. The default
39 * context's state is never restored to help prevent programming errors. This
40 * would happen if a client ran and piggy-backed off another clients GPU state.
41 * The default context only exists to give the GPU some offset to load as the
42 * current to invoke a save of the context we actually care about. In fact, the
43 * code could likely be constructed, albeit in a more complicated fashion, to
44 * never use the default context, though that limits the driver's ability to
45 * swap out, and/or destroy other contexts.
47 * All other contexts are created as a request by the GPU client. These contexts
48 * store GPU state, and thus allow GPU clients to not re-emit state (and
49 * potentially query certain state) at any time. The kernel driver makes
50 * certain that the appropriate commands are inserted.
52 * The context life cycle is semi-complicated in that context BOs may live
53 * longer than the context itself because of the way the hardware, and object
54 * tracking works. Below is a very crude representation of the state machine
55 * describing the context life.
56 * refcount pincount active
57 * S0: initial state 0 0 0
58 * S1: context created 1 0 0
59 * S2: context is currently running 2 1 X
60 * S3: GPU referenced, but not current 2 0 1
61 * S4: context is current, but destroyed 1 1 0
62 * S5: like S3, but destroyed 1 0 1
64 * The most common (but not all) transitions:
65 * S0->S1: client creates a context
66 * S1->S2: client submits execbuf with context
67 * S2->S3: other clients submits execbuf with context
68 * S3->S1: context object was retired
69 * S3->S2: clients submits another execbuf
70 * S2->S4: context destroy called with current context
71 * S3->S5->S0: destroy path
72 * S4->S5->S0: destroy path on current context
74 * There are two confusing terms used above:
75 * The "current context" means the context which is currently running on the
76 * GPU. The GPU has loaded its state already and has stored away the gtt
77 * offset of the BO. The GPU is not actively referencing the data at this
78 * offset, but it will on the next context switch. The only way to avoid this
79 * is to do a GPU reset.
81 * An "active context' is one which was previously the "current context" and is
82 * on the active list waiting for the next context switch to occur. Until this
83 * happens, the object must remain at the same gtt offset. It is therefore
84 * possible to destroy a context, but it is still active.
89 #include <drm/i915_drm.h>
92 /* This is a HW constraint. The value below is the largest known requirement
93 * I've seen in a spec to date, and that was a workaround for a non-shipping
94 * part. It should be safe to decrease this, but it's more future proof as is.
96 #define GEN6_CONTEXT_ALIGN (64<<10)
97 #define GEN7_CONTEXT_ALIGN 4096
99 static int do_switch(struct intel_ring_buffer *ring,
100 struct i915_hw_context *to);
102 static size_t get_context_alignment(struct drm_device *dev)
105 return GEN6_CONTEXT_ALIGN;
107 return GEN7_CONTEXT_ALIGN;
110 static int get_context_size(struct drm_device *dev)
112 struct drm_i915_private *dev_priv = dev->dev_private;
116 switch (INTEL_INFO(dev)->gen) {
118 reg = I915_READ(CXT_SIZE);
119 ret = GEN6_CXT_TOTAL_SIZE(reg) * 64;
122 reg = I915_READ(GEN7_CXT_SIZE);
124 ret = HSW_CXT_TOTAL_SIZE;
126 ret = GEN7_CXT_TOTAL_SIZE(reg) * 64;
129 ret = GEN8_CXT_TOTAL_SIZE;
138 void i915_gem_context_free(struct kref *ctx_ref)
140 struct i915_hw_context *ctx = container_of(ctx_ref,
142 struct i915_hw_ppgtt *ppgtt = NULL;
144 /* We refcount even the aliasing PPGTT to keep the code symmetric */
145 if (USES_ALIASING_PPGTT(ctx->obj->base.dev))
146 ppgtt = ctx_to_ppgtt(ctx);
148 /* XXX: Free up the object before tearing down the address space, in
149 * case we're bound in the PPGTT */
150 drm_gem_object_unreference(&ctx->obj->base);
153 kref_put(&ppgtt->ref, ppgtt_release);
154 list_del(&ctx->link);
158 static struct i915_hw_ppgtt *
159 create_vm_for_ctx(struct drm_device *dev, struct i915_hw_context *ctx)
161 struct i915_hw_ppgtt *ppgtt;
164 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
166 return ERR_PTR(-ENOMEM);
168 ret = i915_gem_init_ppgtt(dev, ppgtt);
177 static struct i915_hw_context *
178 __create_hw_context(struct drm_device *dev,
179 struct drm_i915_file_private *file_priv)
181 struct drm_i915_private *dev_priv = dev->dev_private;
182 struct i915_hw_context *ctx;
185 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
187 return ERR_PTR(-ENOMEM);
189 kref_init(&ctx->ref);
190 ctx->obj = i915_gem_alloc_object(dev, dev_priv->hw_context_size);
191 INIT_LIST_HEAD(&ctx->link);
192 if (ctx->obj == NULL) {
194 DRM_DEBUG_DRIVER("Context object allocated failed\n");
195 return ERR_PTR(-ENOMEM);
198 if (INTEL_INFO(dev)->gen >= 7) {
199 ret = i915_gem_object_set_cache_level(ctx->obj,
201 /* Failure shouldn't ever happen this early */
206 list_add_tail(&ctx->link, &dev_priv->context_list);
208 /* Default context will never have a file_priv */
209 if (file_priv == NULL)
212 ret = idr_alloc(&file_priv->context_idr, ctx, DEFAULT_CONTEXT_ID, 0,
217 ctx->file_priv = file_priv;
219 /* NB: Mark all slices as needing a remap so that when the context first
220 * loads it will restore whatever remap state already exists. If there
221 * is no remap info, it will be a NOP. */
222 ctx->remap_slice = (1 << NUM_L3_SLICES(dev)) - 1;
227 i915_gem_context_unreference(ctx);
231 static inline bool is_default_context(struct i915_hw_context *ctx)
233 return (ctx->id == DEFAULT_CONTEXT_ID);
237 * The default context needs to exist per ring that uses contexts. It stores the
238 * context state of the GPU for applications that don't utilize HW contexts, as
239 * well as an idle case.
241 static struct i915_hw_context *
242 i915_gem_create_context(struct drm_device *dev,
243 struct drm_i915_file_private *file_priv,
246 struct drm_i915_private *dev_priv = dev->dev_private;
247 struct i915_hw_context *ctx;
250 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
252 ctx = __create_hw_context(dev, file_priv);
257 struct i915_hw_ppgtt *ppgtt = create_vm_for_ctx(dev, ctx);
259 if (IS_ERR_OR_NULL(ppgtt)) {
260 DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",
262 ret = PTR_ERR(ppgtt);
265 ctx->vm = &ppgtt->base;
267 /* This case is reserved for the global default context and
268 * should only happen once. */
270 if (WARN_ON(dev_priv->mm.aliasing_ppgtt)) {
275 dev_priv->mm.aliasing_ppgtt = ppgtt;
277 /* We may need to do things with the shrinker which
278 * require us to immediately switch back to the default
279 * context. This can cause a problem as pinning the
280 * default context also requires GTT space which may not
281 * be available. To avoid this we always pin the default
284 ret = i915_gem_obj_ggtt_pin(ctx->obj,
285 get_context_alignment(dev),
288 DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret);
292 } else if (USES_ALIASING_PPGTT(dev)) {
293 /* For platforms which only have aliasing PPGTT, we fake the
294 * address space and refcounting. */
295 kref_get(&dev_priv->mm.aliasing_ppgtt->ref);
298 /* TODO: Until full ppgtt... */
299 if (USES_ALIASING_PPGTT(dev))
300 ctx->vm = &dev_priv->mm.aliasing_ppgtt->base;
302 ctx->vm = &dev_priv->gtt.base;
307 i915_gem_context_unreference(ctx);
311 void i915_gem_context_reset(struct drm_device *dev)
313 struct drm_i915_private *dev_priv = dev->dev_private;
314 struct intel_ring_buffer *ring;
317 if (!HAS_HW_CONTEXTS(dev))
320 /* Prevent the hardware from restoring the last context (which hung) on
322 for (i = 0; i < I915_NUM_RINGS; i++) {
323 struct i915_hw_context *dctx;
324 if (!(INTEL_INFO(dev)->ring_mask & (1<<i)))
327 /* Do a fake switch to the default context */
328 ring = &dev_priv->ring[i];
329 dctx = ring->default_context;
333 if (!ring->last_context)
336 if (ring->last_context == dctx)
340 WARN_ON(i915_gem_obj_ggtt_pin(dctx->obj,
341 get_context_alignment(dev),
343 /* Fake a finish/inactive */
344 dctx->obj->base.write_domain = 0;
345 dctx->obj->active = 0;
348 i915_gem_context_unreference(ring->last_context);
349 i915_gem_context_reference(dctx);
350 ring->last_context = dctx;
354 int i915_gem_context_init(struct drm_device *dev)
356 struct drm_i915_private *dev_priv = dev->dev_private;
357 struct intel_ring_buffer *ring;
360 if (!HAS_HW_CONTEXTS(dev))
363 /* Init should only be called once per module load. Eventually the
364 * restriction on the context_disabled check can be loosened. */
365 if (WARN_ON(dev_priv->ring[RCS].default_context))
368 dev_priv->hw_context_size = round_up(get_context_size(dev), 4096);
370 if (dev_priv->hw_context_size > (1<<20)) {
371 DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size\n");
375 dev_priv->ring[RCS].default_context =
376 i915_gem_create_context(dev, NULL, USES_ALIASING_PPGTT(dev));
378 if (IS_ERR_OR_NULL(dev_priv->ring[RCS].default_context)) {
379 DRM_DEBUG_DRIVER("Disabling HW Contexts; create failed %ld\n",
380 PTR_ERR(dev_priv->ring[RCS].default_context));
381 return PTR_ERR(dev_priv->ring[RCS].default_context);
384 for (i = RCS + 1; i < I915_NUM_RINGS; i++) {
385 if (!(INTEL_INFO(dev)->ring_mask & (1<<i)))
388 ring = &dev_priv->ring[i];
390 /* NB: RCS will hold a ref for all rings */
391 ring->default_context = dev_priv->ring[RCS].default_context;
394 DRM_DEBUG_DRIVER("HW context support initialized\n");
398 void i915_gem_context_fini(struct drm_device *dev)
400 struct drm_i915_private *dev_priv = dev->dev_private;
401 struct i915_hw_context *dctx = dev_priv->ring[RCS].default_context;
404 if (!HAS_HW_CONTEXTS(dev))
407 /* The only known way to stop the gpu from accessing the hw context is
408 * to reset it. Do this as the very last operation to avoid confusing
409 * other code, leading to spurious errors. */
410 intel_gpu_reset(dev);
412 /* When default context is created and switched to, base object refcount
413 * will be 2 (+1 from object creation and +1 from do_switch()).
414 * i915_gem_context_fini() will be called after gpu_idle() has switched
415 * to default context. So we need to unreference the base object once
416 * to offset the do_switch part, so that i915_gem_context_unreference()
417 * can then free the base object correctly. */
418 WARN_ON(!dev_priv->ring[RCS].last_context);
419 if (dev_priv->ring[RCS].last_context == dctx) {
420 /* Fake switch to NULL context */
421 WARN_ON(dctx->obj->active);
422 i915_gem_object_ggtt_unpin(dctx->obj);
423 i915_gem_context_unreference(dctx);
424 dev_priv->ring[RCS].last_context = NULL;
427 for (i = 0; i < I915_NUM_RINGS; i++) {
428 struct intel_ring_buffer *ring = &dev_priv->ring[i];
429 if (!(INTEL_INFO(dev)->ring_mask & (1<<i)))
432 if (ring->last_context)
433 i915_gem_context_unreference(ring->last_context);
435 ring->default_context = NULL;
436 ring->last_context = NULL;
439 i915_gem_object_ggtt_unpin(dctx->obj);
440 i915_gem_context_unreference(dctx);
441 dev_priv->mm.aliasing_ppgtt = NULL;
444 int i915_gem_context_enable(struct drm_i915_private *dev_priv)
446 struct intel_ring_buffer *ring;
449 if (!HAS_HW_CONTEXTS(dev_priv->dev))
452 /* This is the only place the aliasing PPGTT gets enabled, which means
453 * it has to happen before we bail on reset */
454 if (dev_priv->mm.aliasing_ppgtt) {
455 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
456 ppgtt->enable(ppgtt);
459 /* FIXME: We should make this work, even in reset */
460 if (i915_reset_in_progress(&dev_priv->gpu_error))
463 BUG_ON(!dev_priv->ring[RCS].default_context);
465 for_each_ring(ring, dev_priv, i) {
466 ret = do_switch(ring, ring->default_context);
474 static int context_idr_cleanup(int id, void *p, void *data)
476 struct i915_hw_context *ctx = p;
478 /* Ignore the default context because close will handle it */
479 if (is_default_context(ctx))
482 i915_gem_context_unreference(ctx);
486 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file)
488 struct drm_i915_file_private *file_priv = file->driver_priv;
489 struct drm_i915_private *dev_priv = dev->dev_private;
491 if (!HAS_HW_CONTEXTS(dev)) {
492 /* Cheat for hang stats */
493 file_priv->private_default_ctx =
494 kzalloc(sizeof(struct i915_hw_context), GFP_KERNEL);
495 file_priv->private_default_ctx->vm = &dev_priv->gtt.base;
499 idr_init(&file_priv->context_idr);
501 mutex_lock(&dev->struct_mutex);
502 file_priv->private_default_ctx =
503 i915_gem_create_context(dev, file_priv, false);
504 mutex_unlock(&dev->struct_mutex);
506 if (IS_ERR(file_priv->private_default_ctx)) {
507 idr_destroy(&file_priv->context_idr);
508 return PTR_ERR(file_priv->private_default_ctx);
514 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file)
516 struct drm_i915_file_private *file_priv = file->driver_priv;
518 if (!HAS_HW_CONTEXTS(dev)) {
519 kfree(file_priv->private_default_ctx);
523 idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL);
524 i915_gem_context_unreference(file_priv->private_default_ctx);
525 idr_destroy(&file_priv->context_idr);
528 struct i915_hw_context *
529 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id)
531 if (!HAS_HW_CONTEXTS(file_priv->dev_priv->dev))
532 return file_priv->private_default_ctx;
534 return (struct i915_hw_context *)idr_find(&file_priv->context_idr, id);
538 mi_set_context(struct intel_ring_buffer *ring,
539 struct i915_hw_context *new_context,
544 /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
545 * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value
546 * explicitly, so we rely on the value at ring init, stored in
547 * itlb_before_ctx_switch.
549 if (IS_GEN6(ring->dev) && ring->itlb_before_ctx_switch) {
550 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, 0);
555 ret = intel_ring_begin(ring, 6);
559 /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw */
560 if (IS_GEN7(ring->dev))
561 intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE);
563 intel_ring_emit(ring, MI_NOOP);
565 intel_ring_emit(ring, MI_NOOP);
566 intel_ring_emit(ring, MI_SET_CONTEXT);
567 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(new_context->obj) |
569 MI_SAVE_EXT_STATE_EN |
570 MI_RESTORE_EXT_STATE_EN |
572 /* w/a: MI_SET_CONTEXT must always be followed by MI_NOOP */
573 intel_ring_emit(ring, MI_NOOP);
575 if (IS_GEN7(ring->dev))
576 intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE);
578 intel_ring_emit(ring, MI_NOOP);
580 intel_ring_advance(ring);
585 static int do_switch(struct intel_ring_buffer *ring,
586 struct i915_hw_context *to)
588 struct drm_i915_private *dev_priv = ring->dev->dev_private;
589 struct i915_hw_context *from = ring->last_context;
593 if (from != NULL && ring == &dev_priv->ring[RCS]) {
594 BUG_ON(from->obj == NULL);
595 BUG_ON(!i915_gem_obj_is_pinned(from->obj));
598 if (from == to && from->last_ring == ring && !to->remap_slice)
601 if (ring != &dev_priv->ring[RCS]) {
603 i915_gem_context_unreference(from);
607 ret = i915_gem_obj_ggtt_pin(to->obj, get_context_alignment(ring->dev),
613 * Pin can switch back to the default context if we end up calling into
614 * evict_everything - as a last ditch gtt defrag effort that also
615 * switches to the default context. Hence we need to reload from here.
617 from = ring->last_context;
620 * Clear this page out of any CPU caches for coherent swap-in/out. Note
621 * that thanks to write = false in this call and us not setting any gpu
622 * write domains when putting a context object onto the active list
623 * (when switching away from it), this won't block.
625 * XXX: We need a real interface to do this instead of trickery.
627 ret = i915_gem_object_set_to_gtt_domain(to->obj, false);
629 i915_gem_object_ggtt_unpin(to->obj);
633 if (!to->obj->has_global_gtt_mapping) {
634 struct i915_vma *vma = i915_gem_obj_to_vma(to->obj,
635 &dev_priv->gtt.base);
636 vma->bind_vma(vma, to->obj->cache_level, GLOBAL_BIND);
639 if (!to->is_initialized || is_default_context(to))
640 hw_flags |= MI_RESTORE_INHIBIT;
642 ret = mi_set_context(ring, to, hw_flags);
644 i915_gem_object_ggtt_unpin(to->obj);
648 for (i = 0; i < MAX_L3_SLICES; i++) {
649 if (!(to->remap_slice & (1<<i)))
652 ret = i915_gem_l3_remap(ring, i);
653 /* If it failed, try again next round */
655 DRM_DEBUG_DRIVER("L3 remapping failed\n");
657 to->remap_slice &= ~(1<<i);
660 /* The backing object for the context is done after switching to the
661 * *next* context. Therefore we cannot retire the previous context until
662 * the next context has already started running. In fact, the below code
663 * is a bit suboptimal because the retiring can occur simply after the
664 * MI_SET_CONTEXT instead of when the next seqno has completed.
667 from->obj->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
668 i915_vma_move_to_active(i915_gem_obj_to_ggtt(from->obj), ring);
669 /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the
670 * whole damn pipeline, we don't need to explicitly mark the
671 * object dirty. The only exception is that the context must be
672 * correct in case the object gets swapped out. Ideally we'd be
673 * able to defer doing this until we know the object would be
674 * swapped, but there is no way to do that yet.
676 from->obj->dirty = 1;
677 BUG_ON(from->obj->ring != ring);
679 /* obj is kept alive until the next request by its active ref */
680 i915_gem_object_ggtt_unpin(from->obj);
681 i915_gem_context_unreference(from);
685 i915_gem_context_reference(to);
686 ring->last_context = to;
687 to->is_initialized = true;
688 to->last_ring = ring;
694 * i915_switch_context() - perform a GPU context switch.
695 * @ring: ring for which we'll execute the context switch
696 * @file_priv: file_priv associated with the context, may be NULL
697 * @id: context id number
699 * The context life cycle is simple. The context refcount is incremented and
700 * decremented by 1 and create and destroy. If the context is in use by the GPU,
701 * it will have a refoucnt > 1. This allows us to destroy the context abstract
702 * object while letting the normal object tracking destroy the backing BO.
704 int i915_switch_context(struct intel_ring_buffer *ring,
705 struct drm_file *file,
706 struct i915_hw_context *to)
708 struct drm_i915_private *dev_priv = ring->dev->dev_private;
710 WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
712 BUG_ON(file && to == NULL);
714 /* We have the fake context, but don't supports switching. */
715 if (!HAS_HW_CONTEXTS(ring->dev))
718 return do_switch(ring, to);
721 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
722 struct drm_file *file)
724 struct drm_i915_gem_context_create *args = data;
725 struct drm_i915_file_private *file_priv = file->driver_priv;
726 struct i915_hw_context *ctx;
729 if (!(dev->driver->driver_features & DRIVER_GEM))
732 if (!HAS_HW_CONTEXTS(dev))
735 ret = i915_mutex_lock_interruptible(dev);
739 ctx = i915_gem_create_context(dev, file_priv, false);
740 mutex_unlock(&dev->struct_mutex);
744 args->ctx_id = ctx->id;
745 DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id);
750 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
751 struct drm_file *file)
753 struct drm_i915_gem_context_destroy *args = data;
754 struct drm_i915_file_private *file_priv = file->driver_priv;
755 struct i915_hw_context *ctx;
758 if (!(dev->driver->driver_features & DRIVER_GEM))
761 if (args->ctx_id == DEFAULT_CONTEXT_ID)
764 ret = i915_mutex_lock_interruptible(dev);
768 ctx = i915_gem_context_get(file_priv, args->ctx_id);
770 mutex_unlock(&dev->struct_mutex);
774 idr_remove(&ctx->file_priv->context_idr, ctx->id);
775 i915_gem_context_unreference(ctx);
776 mutex_unlock(&dev->struct_mutex);
778 DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id);