2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_vgpu.h"
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include <linux/shmem_fs.h>
36 #include <linux/slab.h>
37 #include <linux/swap.h>
38 #include <linux/pci.h>
39 #include <linux/dma-buf.h>
41 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
42 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
43 static __must_check int
44 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
47 i915_gem_object_retire(struct drm_i915_gem_object *obj);
49 static void i915_gem_write_fence(struct drm_device *dev, int reg,
50 struct drm_i915_gem_object *obj);
51 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
52 struct drm_i915_fence_reg *fence,
55 static bool cpu_cache_is_coherent(struct drm_device *dev,
56 enum i915_cache_level level)
58 return HAS_LLC(dev) || level != I915_CACHE_NONE;
61 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
63 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
66 return obj->pin_display;
69 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
72 i915_gem_release_mmap(obj);
74 /* As we do not have an associated fence register, we will force
75 * a tiling change if we ever need to acquire one.
77 obj->fence_dirty = false;
78 obj->fence_reg = I915_FENCE_REG_NONE;
81 /* some bookkeeping */
82 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
85 spin_lock(&dev_priv->mm.object_stat_lock);
86 dev_priv->mm.object_count++;
87 dev_priv->mm.object_memory += size;
88 spin_unlock(&dev_priv->mm.object_stat_lock);
91 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
94 spin_lock(&dev_priv->mm.object_stat_lock);
95 dev_priv->mm.object_count--;
96 dev_priv->mm.object_memory -= size;
97 spin_unlock(&dev_priv->mm.object_stat_lock);
101 i915_gem_wait_for_error(struct i915_gpu_error *error)
105 #define EXIT_COND (!i915_reset_in_progress(error) || \
106 i915_terminally_wedged(error))
111 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
112 * userspace. If it takes that long something really bad is going on and
113 * we should simply try to bail out and fail as gracefully as possible.
115 ret = wait_event_interruptible_timeout(error->reset_queue,
119 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
121 } else if (ret < 0) {
129 int i915_mutex_lock_interruptible(struct drm_device *dev)
131 struct drm_i915_private *dev_priv = dev->dev_private;
134 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
138 ret = mutex_lock_interruptible(&dev->struct_mutex);
142 WARN_ON(i915_verify_lists(dev));
147 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
148 struct drm_file *file)
150 struct drm_i915_private *dev_priv = dev->dev_private;
151 struct drm_i915_gem_get_aperture *args = data;
152 struct drm_i915_gem_object *obj;
156 mutex_lock(&dev->struct_mutex);
157 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
158 if (i915_gem_obj_is_pinned(obj))
159 pinned += i915_gem_obj_ggtt_size(obj);
160 mutex_unlock(&dev->struct_mutex);
162 args->aper_size = dev_priv->gtt.base.total;
163 args->aper_available_size = args->aper_size - pinned;
169 i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
171 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
172 char *vaddr = obj->phys_handle->vaddr;
174 struct scatterlist *sg;
177 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
180 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
184 page = shmem_read_mapping_page(mapping, i);
186 return PTR_ERR(page);
188 src = kmap_atomic(page);
189 memcpy(vaddr, src, PAGE_SIZE);
190 drm_clflush_virt_range(vaddr, PAGE_SIZE);
193 page_cache_release(page);
197 i915_gem_chipset_flush(obj->base.dev);
199 st = kmalloc(sizeof(*st), GFP_KERNEL);
203 if (sg_alloc_table(st, 1, GFP_KERNEL)) {
210 sg->length = obj->base.size;
212 sg_dma_address(sg) = obj->phys_handle->busaddr;
213 sg_dma_len(sg) = obj->base.size;
216 obj->has_dma_mapping = true;
221 i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj)
225 BUG_ON(obj->madv == __I915_MADV_PURGED);
227 ret = i915_gem_object_set_to_cpu_domain(obj, true);
229 /* In the event of a disaster, abandon all caches and
232 WARN_ON(ret != -EIO);
233 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
236 if (obj->madv == I915_MADV_DONTNEED)
240 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
241 char *vaddr = obj->phys_handle->vaddr;
244 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
248 page = shmem_read_mapping_page(mapping, i);
252 dst = kmap_atomic(page);
253 drm_clflush_virt_range(vaddr, PAGE_SIZE);
254 memcpy(dst, vaddr, PAGE_SIZE);
257 set_page_dirty(page);
258 if (obj->madv == I915_MADV_WILLNEED)
259 mark_page_accessed(page);
260 page_cache_release(page);
266 sg_free_table(obj->pages);
269 obj->has_dma_mapping = false;
273 i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
275 drm_pci_free(obj->base.dev, obj->phys_handle);
278 static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
279 .get_pages = i915_gem_object_get_pages_phys,
280 .put_pages = i915_gem_object_put_pages_phys,
281 .release = i915_gem_object_release_phys,
285 drop_pages(struct drm_i915_gem_object *obj)
287 struct i915_vma *vma, *next;
290 drm_gem_object_reference(&obj->base);
291 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link)
292 if (i915_vma_unbind(vma))
295 ret = i915_gem_object_put_pages(obj);
296 drm_gem_object_unreference(&obj->base);
302 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
305 drm_dma_handle_t *phys;
308 if (obj->phys_handle) {
309 if ((unsigned long)obj->phys_handle->vaddr & (align -1))
315 if (obj->madv != I915_MADV_WILLNEED)
318 if (obj->base.filp == NULL)
321 ret = drop_pages(obj);
325 /* create a new object */
326 phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
330 obj->phys_handle = phys;
331 obj->ops = &i915_gem_phys_ops;
333 return i915_gem_object_get_pages(obj);
337 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
338 struct drm_i915_gem_pwrite *args,
339 struct drm_file *file_priv)
341 struct drm_device *dev = obj->base.dev;
342 void *vaddr = obj->phys_handle->vaddr + args->offset;
343 char __user *user_data = to_user_ptr(args->data_ptr);
346 /* We manually control the domain here and pretend that it
347 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
349 ret = i915_gem_object_wait_rendering(obj, false);
353 intel_fb_obj_invalidate(obj, NULL, ORIGIN_CPU);
354 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
355 unsigned long unwritten;
357 /* The physical object once assigned is fixed for the lifetime
358 * of the obj, so we can safely drop the lock and continue
361 mutex_unlock(&dev->struct_mutex);
362 unwritten = copy_from_user(vaddr, user_data, args->size);
363 mutex_lock(&dev->struct_mutex);
370 drm_clflush_virt_range(vaddr, args->size);
371 i915_gem_chipset_flush(dev);
374 intel_fb_obj_flush(obj, false);
378 void *i915_gem_object_alloc(struct drm_device *dev)
380 struct drm_i915_private *dev_priv = dev->dev_private;
381 return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL);
384 void i915_gem_object_free(struct drm_i915_gem_object *obj)
386 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
387 kmem_cache_free(dev_priv->objects, obj);
391 i915_gem_create(struct drm_file *file,
392 struct drm_device *dev,
396 struct drm_i915_gem_object *obj;
400 size = roundup(size, PAGE_SIZE);
404 /* Allocate the new object */
405 obj = i915_gem_alloc_object(dev, size);
409 ret = drm_gem_handle_create(file, &obj->base, &handle);
410 /* drop reference from allocate - handle holds it now */
411 drm_gem_object_unreference_unlocked(&obj->base);
420 i915_gem_dumb_create(struct drm_file *file,
421 struct drm_device *dev,
422 struct drm_mode_create_dumb *args)
424 /* have to work out size/pitch and return them */
425 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
426 args->size = args->pitch * args->height;
427 return i915_gem_create(file, dev,
428 args->size, &args->handle);
432 * Creates a new mm object and returns a handle to it.
435 i915_gem_create_ioctl(struct drm_device *dev, void *data,
436 struct drm_file *file)
438 struct drm_i915_gem_create *args = data;
440 return i915_gem_create(file, dev,
441 args->size, &args->handle);
445 __copy_to_user_swizzled(char __user *cpu_vaddr,
446 const char *gpu_vaddr, int gpu_offset,
449 int ret, cpu_offset = 0;
452 int cacheline_end = ALIGN(gpu_offset + 1, 64);
453 int this_length = min(cacheline_end - gpu_offset, length);
454 int swizzled_gpu_offset = gpu_offset ^ 64;
456 ret = __copy_to_user(cpu_vaddr + cpu_offset,
457 gpu_vaddr + swizzled_gpu_offset,
462 cpu_offset += this_length;
463 gpu_offset += this_length;
464 length -= this_length;
471 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
472 const char __user *cpu_vaddr,
475 int ret, cpu_offset = 0;
478 int cacheline_end = ALIGN(gpu_offset + 1, 64);
479 int this_length = min(cacheline_end - gpu_offset, length);
480 int swizzled_gpu_offset = gpu_offset ^ 64;
482 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
483 cpu_vaddr + cpu_offset,
488 cpu_offset += this_length;
489 gpu_offset += this_length;
490 length -= this_length;
497 * Pins the specified object's pages and synchronizes the object with
498 * GPU accesses. Sets needs_clflush to non-zero if the caller should
499 * flush the object from the CPU cache.
501 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
511 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
512 /* If we're not in the cpu read domain, set ourself into the gtt
513 * read domain and manually flush cachelines (if required). This
514 * optimizes for the case when the gpu will dirty the data
515 * anyway again before the next pread happens. */
516 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
518 ret = i915_gem_object_wait_rendering(obj, true);
522 i915_gem_object_retire(obj);
525 ret = i915_gem_object_get_pages(obj);
529 i915_gem_object_pin_pages(obj);
534 /* Per-page copy function for the shmem pread fastpath.
535 * Flushes invalid cachelines before reading the target if
536 * needs_clflush is set. */
538 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
539 char __user *user_data,
540 bool page_do_bit17_swizzling, bool needs_clflush)
545 if (unlikely(page_do_bit17_swizzling))
548 vaddr = kmap_atomic(page);
550 drm_clflush_virt_range(vaddr + shmem_page_offset,
552 ret = __copy_to_user_inatomic(user_data,
553 vaddr + shmem_page_offset,
555 kunmap_atomic(vaddr);
557 return ret ? -EFAULT : 0;
561 shmem_clflush_swizzled_range(char *addr, unsigned long length,
564 if (unlikely(swizzled)) {
565 unsigned long start = (unsigned long) addr;
566 unsigned long end = (unsigned long) addr + length;
568 /* For swizzling simply ensure that we always flush both
569 * channels. Lame, but simple and it works. Swizzled
570 * pwrite/pread is far from a hotpath - current userspace
571 * doesn't use it at all. */
572 start = round_down(start, 128);
573 end = round_up(end, 128);
575 drm_clflush_virt_range((void *)start, end - start);
577 drm_clflush_virt_range(addr, length);
582 /* Only difference to the fast-path function is that this can handle bit17
583 * and uses non-atomic copy and kmap functions. */
585 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
586 char __user *user_data,
587 bool page_do_bit17_swizzling, bool needs_clflush)
594 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
596 page_do_bit17_swizzling);
598 if (page_do_bit17_swizzling)
599 ret = __copy_to_user_swizzled(user_data,
600 vaddr, shmem_page_offset,
603 ret = __copy_to_user(user_data,
604 vaddr + shmem_page_offset,
608 return ret ? - EFAULT : 0;
612 i915_gem_shmem_pread(struct drm_device *dev,
613 struct drm_i915_gem_object *obj,
614 struct drm_i915_gem_pread *args,
615 struct drm_file *file)
617 char __user *user_data;
620 int shmem_page_offset, page_length, ret = 0;
621 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
623 int needs_clflush = 0;
624 struct sg_page_iter sg_iter;
626 user_data = to_user_ptr(args->data_ptr);
629 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
631 ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
635 offset = args->offset;
637 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
638 offset >> PAGE_SHIFT) {
639 struct page *page = sg_page_iter_page(&sg_iter);
644 /* Operation in this page
646 * shmem_page_offset = offset within page in shmem file
647 * page_length = bytes to copy for this page
649 shmem_page_offset = offset_in_page(offset);
650 page_length = remain;
651 if ((shmem_page_offset + page_length) > PAGE_SIZE)
652 page_length = PAGE_SIZE - shmem_page_offset;
654 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
655 (page_to_phys(page) & (1 << 17)) != 0;
657 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
658 user_data, page_do_bit17_swizzling,
663 mutex_unlock(&dev->struct_mutex);
665 if (likely(!i915.prefault_disable) && !prefaulted) {
666 ret = fault_in_multipages_writeable(user_data, remain);
667 /* Userspace is tricking us, but we've already clobbered
668 * its pages with the prefault and promised to write the
669 * data up to the first fault. Hence ignore any errors
670 * and just continue. */
675 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
676 user_data, page_do_bit17_swizzling,
679 mutex_lock(&dev->struct_mutex);
685 remain -= page_length;
686 user_data += page_length;
687 offset += page_length;
691 i915_gem_object_unpin_pages(obj);
697 * Reads data from the object referenced by handle.
699 * On error, the contents of *data are undefined.
702 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
703 struct drm_file *file)
705 struct drm_i915_gem_pread *args = data;
706 struct drm_i915_gem_object *obj;
712 if (!access_ok(VERIFY_WRITE,
713 to_user_ptr(args->data_ptr),
717 ret = i915_mutex_lock_interruptible(dev);
721 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
722 if (&obj->base == NULL) {
727 /* Bounds check source. */
728 if (args->offset > obj->base.size ||
729 args->size > obj->base.size - args->offset) {
734 /* prime objects have no backing filp to GEM pread/pwrite
737 if (!obj->base.filp) {
742 trace_i915_gem_object_pread(obj, args->offset, args->size);
744 ret = i915_gem_shmem_pread(dev, obj, args, file);
747 drm_gem_object_unreference(&obj->base);
749 mutex_unlock(&dev->struct_mutex);
753 /* This is the fast write path which cannot handle
754 * page faults in the source data
758 fast_user_write(struct io_mapping *mapping,
759 loff_t page_base, int page_offset,
760 char __user *user_data,
763 void __iomem *vaddr_atomic;
765 unsigned long unwritten;
767 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
768 /* We can use the cpu mem copy function because this is X86. */
769 vaddr = (void __force*)vaddr_atomic + page_offset;
770 unwritten = __copy_from_user_inatomic_nocache(vaddr,
772 io_mapping_unmap_atomic(vaddr_atomic);
777 * This is the fast pwrite path, where we copy the data directly from the
778 * user into the GTT, uncached.
781 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
782 struct drm_i915_gem_object *obj,
783 struct drm_i915_gem_pwrite *args,
784 struct drm_file *file)
786 struct drm_i915_private *dev_priv = dev->dev_private;
788 loff_t offset, page_base;
789 char __user *user_data;
790 int page_offset, page_length, ret;
792 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
796 ret = i915_gem_object_set_to_gtt_domain(obj, true);
800 ret = i915_gem_object_put_fence(obj);
804 user_data = to_user_ptr(args->data_ptr);
807 offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
809 intel_fb_obj_invalidate(obj, NULL, ORIGIN_GTT);
812 /* Operation in this page
814 * page_base = page offset within aperture
815 * page_offset = offset within page
816 * page_length = bytes to copy for this page
818 page_base = offset & PAGE_MASK;
819 page_offset = offset_in_page(offset);
820 page_length = remain;
821 if ((page_offset + remain) > PAGE_SIZE)
822 page_length = PAGE_SIZE - page_offset;
824 /* If we get a fault while copying data, then (presumably) our
825 * source page isn't available. Return the error and we'll
826 * retry in the slow path.
828 if (fast_user_write(dev_priv->gtt.mappable, page_base,
829 page_offset, user_data, page_length)) {
834 remain -= page_length;
835 user_data += page_length;
836 offset += page_length;
840 intel_fb_obj_flush(obj, false);
842 i915_gem_object_ggtt_unpin(obj);
847 /* Per-page copy function for the shmem pwrite fastpath.
848 * Flushes invalid cachelines before writing to the target if
849 * needs_clflush_before is set and flushes out any written cachelines after
850 * writing if needs_clflush is set. */
852 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
853 char __user *user_data,
854 bool page_do_bit17_swizzling,
855 bool needs_clflush_before,
856 bool needs_clflush_after)
861 if (unlikely(page_do_bit17_swizzling))
864 vaddr = kmap_atomic(page);
865 if (needs_clflush_before)
866 drm_clflush_virt_range(vaddr + shmem_page_offset,
868 ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
869 user_data, page_length);
870 if (needs_clflush_after)
871 drm_clflush_virt_range(vaddr + shmem_page_offset,
873 kunmap_atomic(vaddr);
875 return ret ? -EFAULT : 0;
878 /* Only difference to the fast-path function is that this can handle bit17
879 * and uses non-atomic copy and kmap functions. */
881 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
882 char __user *user_data,
883 bool page_do_bit17_swizzling,
884 bool needs_clflush_before,
885 bool needs_clflush_after)
891 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
892 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
894 page_do_bit17_swizzling);
895 if (page_do_bit17_swizzling)
896 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
900 ret = __copy_from_user(vaddr + shmem_page_offset,
903 if (needs_clflush_after)
904 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
906 page_do_bit17_swizzling);
909 return ret ? -EFAULT : 0;
913 i915_gem_shmem_pwrite(struct drm_device *dev,
914 struct drm_i915_gem_object *obj,
915 struct drm_i915_gem_pwrite *args,
916 struct drm_file *file)
920 char __user *user_data;
921 int shmem_page_offset, page_length, ret = 0;
922 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
923 int hit_slowpath = 0;
924 int needs_clflush_after = 0;
925 int needs_clflush_before = 0;
926 struct sg_page_iter sg_iter;
928 user_data = to_user_ptr(args->data_ptr);
931 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
933 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
934 /* If we're not in the cpu write domain, set ourself into the gtt
935 * write domain and manually flush cachelines (if required). This
936 * optimizes for the case when the gpu will use the data
937 * right away and we therefore have to clflush anyway. */
938 needs_clflush_after = cpu_write_needs_clflush(obj);
939 ret = i915_gem_object_wait_rendering(obj, false);
943 i915_gem_object_retire(obj);
945 /* Same trick applies to invalidate partially written cachelines read
947 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
948 needs_clflush_before =
949 !cpu_cache_is_coherent(dev, obj->cache_level);
951 ret = i915_gem_object_get_pages(obj);
955 intel_fb_obj_invalidate(obj, NULL, ORIGIN_CPU);
957 i915_gem_object_pin_pages(obj);
959 offset = args->offset;
962 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
963 offset >> PAGE_SHIFT) {
964 struct page *page = sg_page_iter_page(&sg_iter);
965 int partial_cacheline_write;
970 /* Operation in this page
972 * shmem_page_offset = offset within page in shmem file
973 * page_length = bytes to copy for this page
975 shmem_page_offset = offset_in_page(offset);
977 page_length = remain;
978 if ((shmem_page_offset + page_length) > PAGE_SIZE)
979 page_length = PAGE_SIZE - shmem_page_offset;
981 /* If we don't overwrite a cacheline completely we need to be
982 * careful to have up-to-date data by first clflushing. Don't
983 * overcomplicate things and flush the entire patch. */
984 partial_cacheline_write = needs_clflush_before &&
985 ((shmem_page_offset | page_length)
986 & (boot_cpu_data.x86_clflush_size - 1));
988 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
989 (page_to_phys(page) & (1 << 17)) != 0;
991 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
992 user_data, page_do_bit17_swizzling,
993 partial_cacheline_write,
994 needs_clflush_after);
999 mutex_unlock(&dev->struct_mutex);
1000 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
1001 user_data, page_do_bit17_swizzling,
1002 partial_cacheline_write,
1003 needs_clflush_after);
1005 mutex_lock(&dev->struct_mutex);
1011 remain -= page_length;
1012 user_data += page_length;
1013 offset += page_length;
1017 i915_gem_object_unpin_pages(obj);
1021 * Fixup: Flush cpu caches in case we didn't flush the dirty
1022 * cachelines in-line while writing and the object moved
1023 * out of the cpu write domain while we've dropped the lock.
1025 if (!needs_clflush_after &&
1026 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1027 if (i915_gem_clflush_object(obj, obj->pin_display))
1028 i915_gem_chipset_flush(dev);
1032 if (needs_clflush_after)
1033 i915_gem_chipset_flush(dev);
1035 intel_fb_obj_flush(obj, false);
1040 * Writes data to the object referenced by handle.
1042 * On error, the contents of the buffer that were to be modified are undefined.
1045 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1046 struct drm_file *file)
1048 struct drm_i915_private *dev_priv = dev->dev_private;
1049 struct drm_i915_gem_pwrite *args = data;
1050 struct drm_i915_gem_object *obj;
1053 if (args->size == 0)
1056 if (!access_ok(VERIFY_READ,
1057 to_user_ptr(args->data_ptr),
1061 if (likely(!i915.prefault_disable)) {
1062 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
1068 intel_runtime_pm_get(dev_priv);
1070 ret = i915_mutex_lock_interruptible(dev);
1074 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1075 if (&obj->base == NULL) {
1080 /* Bounds check destination. */
1081 if (args->offset > obj->base.size ||
1082 args->size > obj->base.size - args->offset) {
1087 /* prime objects have no backing filp to GEM pread/pwrite
1090 if (!obj->base.filp) {
1095 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1098 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1099 * it would end up going through the fenced access, and we'll get
1100 * different detiling behavior between reading and writing.
1101 * pread/pwrite currently are reading and writing from the CPU
1102 * perspective, requiring manual detiling by the client.
1104 if (obj->tiling_mode == I915_TILING_NONE &&
1105 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
1106 cpu_write_needs_clflush(obj)) {
1107 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1108 /* Note that the gtt paths might fail with non-page-backed user
1109 * pointers (e.g. gtt mappings when moving data between
1110 * textures). Fallback to the shmem path in that case. */
1113 if (ret == -EFAULT || ret == -ENOSPC) {
1114 if (obj->phys_handle)
1115 ret = i915_gem_phys_pwrite(obj, args, file);
1117 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1121 drm_gem_object_unreference(&obj->base);
1123 mutex_unlock(&dev->struct_mutex);
1125 intel_runtime_pm_put(dev_priv);
1131 i915_gem_check_wedge(struct i915_gpu_error *error,
1134 if (i915_reset_in_progress(error)) {
1135 /* Non-interruptible callers can't handle -EAGAIN, hence return
1136 * -EIO unconditionally for these. */
1140 /* Recovery complete, but the reset failed ... */
1141 if (i915_terminally_wedged(error))
1145 * Check if GPU Reset is in progress - we need intel_ring_begin
1146 * to work properly to reinit the hw state while the gpu is
1147 * still marked as reset-in-progress. Handle this with a flag.
1149 if (!error->reload_in_reset)
1157 * Compare arbitrary request against outstanding lazy request. Emit on match.
1160 i915_gem_check_olr(struct drm_i915_gem_request *req)
1164 WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
1167 if (req == req->ring->outstanding_lazy_request)
1168 ret = i915_add_request(req->ring);
1173 static void fake_irq(unsigned long data)
1175 wake_up_process((struct task_struct *)data);
1178 static bool missed_irq(struct drm_i915_private *dev_priv,
1179 struct intel_engine_cs *ring)
1181 return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
1184 static int __i915_spin_request(struct drm_i915_gem_request *rq)
1186 unsigned long timeout;
1188 if (i915_gem_request_get_ring(rq)->irq_refcount)
1191 timeout = jiffies + 1;
1192 while (!need_resched()) {
1193 if (i915_gem_request_completed(rq, true))
1196 if (time_after_eq(jiffies, timeout))
1199 cpu_relax_lowlatency();
1201 if (i915_gem_request_completed(rq, false))
1208 * __i915_wait_request - wait until execution of request has finished
1210 * @reset_counter: reset sequence associated with the given request
1211 * @interruptible: do an interruptible wait (normally yes)
1212 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1214 * Note: It is of utmost importance that the passed in seqno and reset_counter
1215 * values have been read by the caller in an smp safe manner. Where read-side
1216 * locks are involved, it is sufficient to read the reset_counter before
1217 * unlocking the lock that protects the seqno. For lockless tricks, the
1218 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1221 * Returns 0 if the request was found within the alloted time. Else returns the
1222 * errno with remaining time filled in timeout argument.
1224 int __i915_wait_request(struct drm_i915_gem_request *req,
1225 unsigned reset_counter,
1228 struct drm_i915_file_private *file_priv)
1230 struct intel_engine_cs *ring = i915_gem_request_get_ring(req);
1231 struct drm_device *dev = ring->dev;
1232 struct drm_i915_private *dev_priv = dev->dev_private;
1233 const bool irq_test_in_progress =
1234 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
1236 unsigned long timeout_expire;
1240 WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled");
1242 if (i915_gem_request_completed(req, true))
1245 timeout_expire = timeout ?
1246 jiffies + nsecs_to_jiffies_timeout((u64)*timeout) : 0;
1248 if (INTEL_INFO(dev)->gen >= 6)
1249 gen6_rps_boost(dev_priv, file_priv);
1251 /* Record current time in case interrupted by signal, or wedged */
1252 trace_i915_gem_request_wait_begin(req);
1253 before = ktime_get_raw_ns();
1255 /* Optimistic spin for the next jiffie before touching IRQs */
1256 ret = __i915_spin_request(req);
1260 if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring))) {
1266 struct timer_list timer;
1268 prepare_to_wait(&ring->irq_queue, &wait,
1269 interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
1271 /* We need to check whether any gpu reset happened in between
1272 * the caller grabbing the seqno and now ... */
1273 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
1274 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1275 * is truely gone. */
1276 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1282 if (i915_gem_request_completed(req, false)) {
1287 if (interruptible && signal_pending(current)) {
1292 if (timeout && time_after_eq(jiffies, timeout_expire)) {
1297 timer.function = NULL;
1298 if (timeout || missed_irq(dev_priv, ring)) {
1299 unsigned long expire;
1301 setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
1302 expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire;
1303 mod_timer(&timer, expire);
1308 if (timer.function) {
1309 del_singleshot_timer_sync(&timer);
1310 destroy_timer_on_stack(&timer);
1313 if (!irq_test_in_progress)
1314 ring->irq_put(ring);
1316 finish_wait(&ring->irq_queue, &wait);
1319 now = ktime_get_raw_ns();
1320 trace_i915_gem_request_wait_end(req);
1323 s64 tres = *timeout - (now - before);
1325 *timeout = tres < 0 ? 0 : tres;
1328 * Apparently ktime isn't accurate enough and occasionally has a
1329 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1330 * things up to make the test happy. We allow up to 1 jiffy.
1332 * This is a regrssion from the timespec->ktime conversion.
1334 if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000)
1342 * Waits for a request to be signaled, and cleans up the
1343 * request and object lists appropriately for that event.
1346 i915_wait_request(struct drm_i915_gem_request *req)
1348 struct drm_device *dev;
1349 struct drm_i915_private *dev_priv;
1351 unsigned reset_counter;
1354 BUG_ON(req == NULL);
1356 dev = req->ring->dev;
1357 dev_priv = dev->dev_private;
1358 interruptible = dev_priv->mm.interruptible;
1360 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1362 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1366 ret = i915_gem_check_olr(req);
1370 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1371 i915_gem_request_reference(req);
1372 ret = __i915_wait_request(req, reset_counter,
1373 interruptible, NULL, NULL);
1374 i915_gem_request_unreference(req);
1379 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj)
1384 /* Manually manage the write flush as we may have not yet
1385 * retired the buffer.
1387 * Note that the last_write_req is always the earlier of
1388 * the two (read/write) requests, so if we haved successfully waited,
1389 * we know we have passed the last write.
1391 i915_gem_request_assign(&obj->last_write_req, NULL);
1397 * Ensures that all rendering to the object has completed and the object is
1398 * safe to unbind from the GTT or access from the CPU.
1400 static __must_check int
1401 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1404 struct drm_i915_gem_request *req;
1407 req = readonly ? obj->last_write_req : obj->last_read_req;
1411 ret = i915_wait_request(req);
1415 return i915_gem_object_wait_rendering__tail(obj);
1418 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1419 * as the object state may change during this call.
1421 static __must_check int
1422 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1423 struct drm_i915_file_private *file_priv,
1426 struct drm_i915_gem_request *req;
1427 struct drm_device *dev = obj->base.dev;
1428 struct drm_i915_private *dev_priv = dev->dev_private;
1429 unsigned reset_counter;
1432 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1433 BUG_ON(!dev_priv->mm.interruptible);
1435 req = readonly ? obj->last_write_req : obj->last_read_req;
1439 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1443 ret = i915_gem_check_olr(req);
1447 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1448 i915_gem_request_reference(req);
1449 mutex_unlock(&dev->struct_mutex);
1450 ret = __i915_wait_request(req, reset_counter, true, NULL, file_priv);
1451 mutex_lock(&dev->struct_mutex);
1452 i915_gem_request_unreference(req);
1456 return i915_gem_object_wait_rendering__tail(obj);
1460 * Called when user space prepares to use an object with the CPU, either
1461 * through the mmap ioctl's mapping or a GTT mapping.
1464 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1465 struct drm_file *file)
1467 struct drm_i915_gem_set_domain *args = data;
1468 struct drm_i915_gem_object *obj;
1469 uint32_t read_domains = args->read_domains;
1470 uint32_t write_domain = args->write_domain;
1473 /* Only handle setting domains to types used by the CPU. */
1474 if (write_domain & I915_GEM_GPU_DOMAINS)
1477 if (read_domains & I915_GEM_GPU_DOMAINS)
1480 /* Having something in the write domain implies it's in the read
1481 * domain, and only that read domain. Enforce that in the request.
1483 if (write_domain != 0 && read_domains != write_domain)
1486 ret = i915_mutex_lock_interruptible(dev);
1490 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1491 if (&obj->base == NULL) {
1496 /* Try to flush the object off the GPU without holding the lock.
1497 * We will repeat the flush holding the lock in the normal manner
1498 * to catch cases where we are gazumped.
1500 ret = i915_gem_object_wait_rendering__nonblocking(obj,
1506 if (read_domains & I915_GEM_DOMAIN_GTT)
1507 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1509 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1512 drm_gem_object_unreference(&obj->base);
1514 mutex_unlock(&dev->struct_mutex);
1519 * Called when user space has done writes to this buffer
1522 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1523 struct drm_file *file)
1525 struct drm_i915_gem_sw_finish *args = data;
1526 struct drm_i915_gem_object *obj;
1529 ret = i915_mutex_lock_interruptible(dev);
1533 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1534 if (&obj->base == NULL) {
1539 /* Pinned buffers may be scanout, so flush the cache */
1540 if (obj->pin_display)
1541 i915_gem_object_flush_cpu_write_domain(obj);
1543 drm_gem_object_unreference(&obj->base);
1545 mutex_unlock(&dev->struct_mutex);
1550 * Maps the contents of an object, returning the address it is mapped
1553 * While the mapping holds a reference on the contents of the object, it doesn't
1554 * imply a ref on the object itself.
1558 * DRM driver writers who look a this function as an example for how to do GEM
1559 * mmap support, please don't implement mmap support like here. The modern way
1560 * to implement DRM mmap support is with an mmap offset ioctl (like
1561 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1562 * That way debug tooling like valgrind will understand what's going on, hiding
1563 * the mmap call in a driver private ioctl will break that. The i915 driver only
1564 * does cpu mmaps this way because we didn't know better.
1567 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1568 struct drm_file *file)
1570 struct drm_i915_gem_mmap *args = data;
1571 struct drm_gem_object *obj;
1574 if (args->flags & ~(I915_MMAP_WC))
1577 if (args->flags & I915_MMAP_WC && !cpu_has_pat)
1580 obj = drm_gem_object_lookup(dev, file, args->handle);
1584 /* prime objects have no backing filp to GEM mmap
1588 drm_gem_object_unreference_unlocked(obj);
1592 addr = vm_mmap(obj->filp, 0, args->size,
1593 PROT_READ | PROT_WRITE, MAP_SHARED,
1595 if (args->flags & I915_MMAP_WC) {
1596 struct mm_struct *mm = current->mm;
1597 struct vm_area_struct *vma;
1599 down_write(&mm->mmap_sem);
1600 vma = find_vma(mm, addr);
1603 pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
1606 up_write(&mm->mmap_sem);
1608 drm_gem_object_unreference_unlocked(obj);
1609 if (IS_ERR((void *)addr))
1612 args->addr_ptr = (uint64_t) addr;
1618 * i915_gem_fault - fault a page into the GTT
1619 * vma: VMA in question
1622 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1623 * from userspace. The fault handler takes care of binding the object to
1624 * the GTT (if needed), allocating and programming a fence register (again,
1625 * only if needed based on whether the old reg is still valid or the object
1626 * is tiled) and inserting a new PTE into the faulting process.
1628 * Note that the faulting process may involve evicting existing objects
1629 * from the GTT and/or fence registers to make room. So performance may
1630 * suffer if the GTT working set is large or there are few fence registers
1633 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1635 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1636 struct drm_device *dev = obj->base.dev;
1637 struct drm_i915_private *dev_priv = dev->dev_private;
1638 struct i915_ggtt_view view = i915_ggtt_view_normal;
1639 pgoff_t page_offset;
1642 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1644 intel_runtime_pm_get(dev_priv);
1646 /* We don't use vmf->pgoff since that has the fake offset */
1647 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1650 ret = i915_mutex_lock_interruptible(dev);
1654 trace_i915_gem_object_fault(obj, page_offset, true, write);
1656 /* Try to flush the object off the GPU first without holding the lock.
1657 * Upon reacquiring the lock, we will perform our sanity checks and then
1658 * repeat the flush holding the lock in the normal manner to catch cases
1659 * where we are gazumped.
1661 ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
1665 /* Access to snoopable pages through the GTT is incoherent. */
1666 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1671 /* Use a partial view if the object is bigger than the aperture. */
1672 if (obj->base.size >= dev_priv->gtt.mappable_end &&
1673 obj->tiling_mode == I915_TILING_NONE) {
1674 static const unsigned int chunk_size = 256; // 1 MiB
1676 memset(&view, 0, sizeof(view));
1677 view.type = I915_GGTT_VIEW_PARTIAL;
1678 view.params.partial.offset = rounddown(page_offset, chunk_size);
1679 view.params.partial.size =
1682 (vma->vm_end - vma->vm_start)/PAGE_SIZE -
1683 view.params.partial.offset);
1686 /* Now pin it into the GTT if needed */
1687 ret = i915_gem_object_ggtt_pin(obj, &view, 0, PIN_MAPPABLE);
1691 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1695 ret = i915_gem_object_get_fence(obj);
1699 /* Finally, remap it using the new GTT offset */
1700 pfn = dev_priv->gtt.mappable_base +
1701 i915_gem_obj_ggtt_offset_view(obj, &view);
1704 if (unlikely(view.type == I915_GGTT_VIEW_PARTIAL)) {
1705 /* Overriding existing pages in partial view does not cause
1706 * us any trouble as TLBs are still valid because the fault
1707 * is due to userspace losing part of the mapping or never
1708 * having accessed it before (at this partials' range).
1710 unsigned long base = vma->vm_start +
1711 (view.params.partial.offset << PAGE_SHIFT);
1714 for (i = 0; i < view.params.partial.size; i++) {
1715 ret = vm_insert_pfn(vma, base + i * PAGE_SIZE, pfn + i);
1720 obj->fault_mappable = true;
1722 if (!obj->fault_mappable) {
1723 unsigned long size = min_t(unsigned long,
1724 vma->vm_end - vma->vm_start,
1728 for (i = 0; i < size >> PAGE_SHIFT; i++) {
1729 ret = vm_insert_pfn(vma,
1730 (unsigned long)vma->vm_start + i * PAGE_SIZE,
1736 obj->fault_mappable = true;
1738 ret = vm_insert_pfn(vma,
1739 (unsigned long)vmf->virtual_address,
1743 i915_gem_object_ggtt_unpin_view(obj, &view);
1745 mutex_unlock(&dev->struct_mutex);
1750 * We eat errors when the gpu is terminally wedged to avoid
1751 * userspace unduly crashing (gl has no provisions for mmaps to
1752 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1753 * and so needs to be reported.
1755 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1756 ret = VM_FAULT_SIGBUS;
1761 * EAGAIN means the gpu is hung and we'll wait for the error
1762 * handler to reset everything when re-faulting in
1763 * i915_mutex_lock_interruptible.
1770 * EBUSY is ok: this just means that another thread
1771 * already did the job.
1773 ret = VM_FAULT_NOPAGE;
1780 ret = VM_FAULT_SIGBUS;
1783 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1784 ret = VM_FAULT_SIGBUS;
1788 intel_runtime_pm_put(dev_priv);
1793 * i915_gem_release_mmap - remove physical page mappings
1794 * @obj: obj in question
1796 * Preserve the reservation of the mmapping with the DRM core code, but
1797 * relinquish ownership of the pages back to the system.
1799 * It is vital that we remove the page mapping if we have mapped a tiled
1800 * object through the GTT and then lose the fence register due to
1801 * resource pressure. Similarly if the object has been moved out of the
1802 * aperture, than pages mapped into userspace must be revoked. Removing the
1803 * mapping will then trigger a page fault on the next user access, allowing
1804 * fixup by i915_gem_fault().
1807 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1809 if (!obj->fault_mappable)
1812 drm_vma_node_unmap(&obj->base.vma_node,
1813 obj->base.dev->anon_inode->i_mapping);
1814 obj->fault_mappable = false;
1818 i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1820 struct drm_i915_gem_object *obj;
1822 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1823 i915_gem_release_mmap(obj);
1827 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1831 if (INTEL_INFO(dev)->gen >= 4 ||
1832 tiling_mode == I915_TILING_NONE)
1835 /* Previous chips need a power-of-two fence region when tiling */
1836 if (INTEL_INFO(dev)->gen == 3)
1837 gtt_size = 1024*1024;
1839 gtt_size = 512*1024;
1841 while (gtt_size < size)
1848 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1849 * @obj: object to check
1851 * Return the required GTT alignment for an object, taking into account
1852 * potential fence register mapping.
1855 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1856 int tiling_mode, bool fenced)
1859 * Minimum alignment is 4k (GTT page size), but might be greater
1860 * if a fence register is needed for the object.
1862 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1863 tiling_mode == I915_TILING_NONE)
1867 * Previous chips need to be aligned to the size of the smallest
1868 * fence register that can contain the object.
1870 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1873 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1875 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1878 if (drm_vma_node_has_offset(&obj->base.vma_node))
1881 dev_priv->mm.shrinker_no_lock_stealing = true;
1883 ret = drm_gem_create_mmap_offset(&obj->base);
1887 /* Badly fragmented mmap space? The only way we can recover
1888 * space is by destroying unwanted objects. We can't randomly release
1889 * mmap_offsets as userspace expects them to be persistent for the
1890 * lifetime of the objects. The closest we can is to release the
1891 * offsets on purgeable objects by truncating it and marking it purged,
1892 * which prevents userspace from ever using that object again.
1894 i915_gem_shrink(dev_priv,
1895 obj->base.size >> PAGE_SHIFT,
1897 I915_SHRINK_UNBOUND |
1898 I915_SHRINK_PURGEABLE);
1899 ret = drm_gem_create_mmap_offset(&obj->base);
1903 i915_gem_shrink_all(dev_priv);
1904 ret = drm_gem_create_mmap_offset(&obj->base);
1906 dev_priv->mm.shrinker_no_lock_stealing = false;
1911 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1913 drm_gem_free_mmap_offset(&obj->base);
1917 i915_gem_mmap_gtt(struct drm_file *file,
1918 struct drm_device *dev,
1922 struct drm_i915_gem_object *obj;
1925 ret = i915_mutex_lock_interruptible(dev);
1929 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1930 if (&obj->base == NULL) {
1935 if (obj->madv != I915_MADV_WILLNEED) {
1936 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
1941 ret = i915_gem_object_create_mmap_offset(obj);
1945 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
1948 drm_gem_object_unreference(&obj->base);
1950 mutex_unlock(&dev->struct_mutex);
1955 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1957 * @data: GTT mapping ioctl data
1958 * @file: GEM object info
1960 * Simply returns the fake offset to userspace so it can mmap it.
1961 * The mmap call will end up in drm_gem_mmap(), which will set things
1962 * up so we can get faults in the handler above.
1964 * The fault handler will take care of binding the object into the GTT
1965 * (since it may have been evicted to make room for something), allocating
1966 * a fence register, and mapping the appropriate aperture address into
1970 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1971 struct drm_file *file)
1973 struct drm_i915_gem_mmap_gtt *args = data;
1975 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1978 /* Immediately discard the backing storage */
1980 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1982 i915_gem_object_free_mmap_offset(obj);
1984 if (obj->base.filp == NULL)
1987 /* Our goal here is to return as much of the memory as
1988 * is possible back to the system as we are called from OOM.
1989 * To do this we must instruct the shmfs to drop all of its
1990 * backing pages, *now*.
1992 shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
1993 obj->madv = __I915_MADV_PURGED;
1996 /* Try to discard unwanted pages */
1998 i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
2000 struct address_space *mapping;
2002 switch (obj->madv) {
2003 case I915_MADV_DONTNEED:
2004 i915_gem_object_truncate(obj);
2005 case __I915_MADV_PURGED:
2009 if (obj->base.filp == NULL)
2012 mapping = file_inode(obj->base.filp)->i_mapping,
2013 invalidate_mapping_pages(mapping, 0, (loff_t)-1);
2017 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
2019 struct sg_page_iter sg_iter;
2022 BUG_ON(obj->madv == __I915_MADV_PURGED);
2024 ret = i915_gem_object_set_to_cpu_domain(obj, true);
2026 /* In the event of a disaster, abandon all caches and
2027 * hope for the best.
2029 WARN_ON(ret != -EIO);
2030 i915_gem_clflush_object(obj, true);
2031 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2034 if (i915_gem_object_needs_bit17_swizzle(obj))
2035 i915_gem_object_save_bit_17_swizzle(obj);
2037 if (obj->madv == I915_MADV_DONTNEED)
2040 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
2041 struct page *page = sg_page_iter_page(&sg_iter);
2044 set_page_dirty(page);
2046 if (obj->madv == I915_MADV_WILLNEED)
2047 mark_page_accessed(page);
2049 page_cache_release(page);
2053 sg_free_table(obj->pages);
2058 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
2060 const struct drm_i915_gem_object_ops *ops = obj->ops;
2062 if (obj->pages == NULL)
2065 if (obj->pages_pin_count)
2068 BUG_ON(i915_gem_obj_bound_any(obj));
2070 /* ->put_pages might need to allocate memory for the bit17 swizzle
2071 * array, hence protect them from being reaped by removing them from gtt
2073 list_del(&obj->global_list);
2075 ops->put_pages(obj);
2078 i915_gem_object_invalidate(obj);
2084 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2086 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2088 struct address_space *mapping;
2089 struct sg_table *st;
2090 struct scatterlist *sg;
2091 struct sg_page_iter sg_iter;
2093 unsigned long last_pfn = 0; /* suppress gcc warning */
2096 /* Assert that the object is not currently in any GPU domain. As it
2097 * wasn't in the GTT, there shouldn't be any way it could have been in
2100 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2101 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2103 st = kmalloc(sizeof(*st), GFP_KERNEL);
2107 page_count = obj->base.size / PAGE_SIZE;
2108 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2113 /* Get the list of pages out of our struct file. They'll be pinned
2114 * at this point until we release them.
2116 * Fail silently without starting the shrinker
2118 mapping = file_inode(obj->base.filp)->i_mapping;
2119 gfp = mapping_gfp_mask(mapping);
2120 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
2121 gfp &= ~(__GFP_IO | __GFP_WAIT);
2124 for (i = 0; i < page_count; i++) {
2125 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2127 i915_gem_shrink(dev_priv,
2130 I915_SHRINK_UNBOUND |
2131 I915_SHRINK_PURGEABLE);
2132 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2135 /* We've tried hard to allocate the memory by reaping
2136 * our own buffer, now let the real VM do its job and
2137 * go down in flames if truly OOM.
2139 i915_gem_shrink_all(dev_priv);
2140 page = shmem_read_mapping_page(mapping, i);
2144 #ifdef CONFIG_SWIOTLB
2145 if (swiotlb_nr_tbl()) {
2147 sg_set_page(sg, page, PAGE_SIZE, 0);
2152 if (!i || page_to_pfn(page) != last_pfn + 1) {
2156 sg_set_page(sg, page, PAGE_SIZE, 0);
2158 sg->length += PAGE_SIZE;
2160 last_pfn = page_to_pfn(page);
2162 /* Check that the i965g/gm workaround works. */
2163 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2165 #ifdef CONFIG_SWIOTLB
2166 if (!swiotlb_nr_tbl())
2171 if (i915_gem_object_needs_bit17_swizzle(obj))
2172 i915_gem_object_do_bit_17_swizzle(obj);
2174 if (obj->tiling_mode != I915_TILING_NONE &&
2175 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2176 i915_gem_object_pin_pages(obj);
2182 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
2183 page_cache_release(sg_page_iter_page(&sg_iter));
2187 /* shmemfs first checks if there is enough memory to allocate the page
2188 * and reports ENOSPC should there be insufficient, along with the usual
2189 * ENOMEM for a genuine allocation failure.
2191 * We use ENOSPC in our driver to mean that we have run out of aperture
2192 * space and so want to translate the error from shmemfs back to our
2193 * usual understanding of ENOMEM.
2195 if (PTR_ERR(page) == -ENOSPC)
2198 return PTR_ERR(page);
2201 /* Ensure that the associated pages are gathered from the backing storage
2202 * and pinned into our object. i915_gem_object_get_pages() may be called
2203 * multiple times before they are released by a single call to
2204 * i915_gem_object_put_pages() - once the pages are no longer referenced
2205 * either as a result of memory pressure (reaping pages under the shrinker)
2206 * or as the object is itself released.
2209 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2211 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2212 const struct drm_i915_gem_object_ops *ops = obj->ops;
2218 if (obj->madv != I915_MADV_WILLNEED) {
2219 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2223 BUG_ON(obj->pages_pin_count);
2225 ret = ops->get_pages(obj);
2229 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2231 obj->get_page.sg = obj->pages->sgl;
2232 obj->get_page.last = 0;
2238 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
2239 struct intel_engine_cs *ring)
2241 struct drm_i915_gem_request *req;
2242 struct intel_engine_cs *old_ring;
2244 BUG_ON(ring == NULL);
2246 req = intel_ring_get_request(ring);
2247 old_ring = i915_gem_request_get_ring(obj->last_read_req);
2249 if (old_ring != ring && obj->last_write_req) {
2250 /* Keep the request relative to the current ring */
2251 i915_gem_request_assign(&obj->last_write_req, req);
2254 /* Add a reference if we're newly entering the active list. */
2256 drm_gem_object_reference(&obj->base);
2260 list_move_tail(&obj->ring_list, &ring->active_list);
2262 i915_gem_request_assign(&obj->last_read_req, req);
2265 void i915_vma_move_to_active(struct i915_vma *vma,
2266 struct intel_engine_cs *ring)
2268 list_move_tail(&vma->mm_list, &vma->vm->active_list);
2269 return i915_gem_object_move_to_active(vma->obj, ring);
2273 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2275 struct i915_vma *vma;
2277 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
2278 BUG_ON(!obj->active);
2280 list_for_each_entry(vma, &obj->vma_list, vma_link) {
2281 if (!list_empty(&vma->mm_list))
2282 list_move_tail(&vma->mm_list, &vma->vm->inactive_list);
2285 intel_fb_obj_flush(obj, true);
2287 list_del_init(&obj->ring_list);
2289 i915_gem_request_assign(&obj->last_read_req, NULL);
2290 i915_gem_request_assign(&obj->last_write_req, NULL);
2291 obj->base.write_domain = 0;
2293 i915_gem_request_assign(&obj->last_fenced_req, NULL);
2296 drm_gem_object_unreference(&obj->base);
2298 WARN_ON(i915_verify_lists(dev));
2302 i915_gem_object_retire(struct drm_i915_gem_object *obj)
2304 if (obj->last_read_req == NULL)
2307 if (i915_gem_request_completed(obj->last_read_req, true))
2308 i915_gem_object_move_to_inactive(obj);
2312 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2314 struct drm_i915_private *dev_priv = dev->dev_private;
2315 struct intel_engine_cs *ring;
2318 /* Carefully retire all requests without writing to the rings */
2319 for_each_ring(ring, dev_priv, i) {
2320 ret = intel_ring_idle(ring);
2324 i915_gem_retire_requests(dev);
2326 /* Finally reset hw state */
2327 for_each_ring(ring, dev_priv, i) {
2328 intel_ring_init_seqno(ring, seqno);
2330 for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++)
2331 ring->semaphore.sync_seqno[j] = 0;
2337 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2339 struct drm_i915_private *dev_priv = dev->dev_private;
2345 /* HWS page needs to be set less than what we
2346 * will inject to ring
2348 ret = i915_gem_init_seqno(dev, seqno - 1);
2352 /* Carefully set the last_seqno value so that wrap
2353 * detection still works
2355 dev_priv->next_seqno = seqno;
2356 dev_priv->last_seqno = seqno - 1;
2357 if (dev_priv->last_seqno == 0)
2358 dev_priv->last_seqno--;
2364 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2366 struct drm_i915_private *dev_priv = dev->dev_private;
2368 /* reserve 0 for non-seqno */
2369 if (dev_priv->next_seqno == 0) {
2370 int ret = i915_gem_init_seqno(dev, 0);
2374 dev_priv->next_seqno = 1;
2377 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2381 int __i915_add_request(struct intel_engine_cs *ring,
2382 struct drm_file *file,
2383 struct drm_i915_gem_object *obj)
2385 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2386 struct drm_i915_gem_request *request;
2387 struct intel_ringbuffer *ringbuf;
2391 request = ring->outstanding_lazy_request;
2392 if (WARN_ON(request == NULL))
2395 if (i915.enable_execlists) {
2396 ringbuf = request->ctx->engine[ring->id].ringbuf;
2398 ringbuf = ring->buffer;
2400 request_start = intel_ring_get_tail(ringbuf);
2402 * Emit any outstanding flushes - execbuf can fail to emit the flush
2403 * after having emitted the batchbuffer command. Hence we need to fix
2404 * things up similar to emitting the lazy request. The difference here
2405 * is that the flush _must_ happen before the next request, no matter
2408 if (i915.enable_execlists) {
2409 ret = logical_ring_flush_all_caches(ringbuf, request->ctx);
2413 ret = intel_ring_flush_all_caches(ring);
2418 /* Record the position of the start of the request so that
2419 * should we detect the updated seqno part-way through the
2420 * GPU processing the request, we never over-estimate the
2421 * position of the head.
2423 request->postfix = intel_ring_get_tail(ringbuf);
2425 if (i915.enable_execlists) {
2426 ret = ring->emit_request(ringbuf, request);
2430 ret = ring->add_request(ring);
2434 request->tail = intel_ring_get_tail(ringbuf);
2437 request->head = request_start;
2439 /* Whilst this request exists, batch_obj will be on the
2440 * active_list, and so will hold the active reference. Only when this
2441 * request is retired will the the batch_obj be moved onto the
2442 * inactive_list and lose its active reference. Hence we do not need
2443 * to explicitly hold another reference here.
2445 request->batch_obj = obj;
2447 if (!i915.enable_execlists) {
2448 /* Hold a reference to the current context so that we can inspect
2449 * it later in case a hangcheck error event fires.
2451 request->ctx = ring->last_context;
2453 i915_gem_context_reference(request->ctx);
2456 request->emitted_jiffies = jiffies;
2457 list_add_tail(&request->list, &ring->request_list);
2458 request->file_priv = NULL;
2461 struct drm_i915_file_private *file_priv = file->driver_priv;
2463 spin_lock(&file_priv->mm.lock);
2464 request->file_priv = file_priv;
2465 list_add_tail(&request->client_list,
2466 &file_priv->mm.request_list);
2467 spin_unlock(&file_priv->mm.lock);
2469 request->pid = get_pid(task_pid(current));
2472 trace_i915_gem_request_add(request);
2473 ring->outstanding_lazy_request = NULL;
2475 i915_queue_hangcheck(ring->dev);
2477 queue_delayed_work(dev_priv->wq,
2478 &dev_priv->mm.retire_work,
2479 round_jiffies_up_relative(HZ));
2480 intel_mark_busy(dev_priv->dev);
2486 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2488 struct drm_i915_file_private *file_priv = request->file_priv;
2493 spin_lock(&file_priv->mm.lock);
2494 list_del(&request->client_list);
2495 request->file_priv = NULL;
2496 spin_unlock(&file_priv->mm.lock);
2499 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2500 const struct intel_context *ctx)
2502 unsigned long elapsed;
2504 elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2506 if (ctx->hang_stats.banned)
2509 if (ctx->hang_stats.ban_period_seconds &&
2510 elapsed <= ctx->hang_stats.ban_period_seconds) {
2511 if (!i915_gem_context_is_default(ctx)) {
2512 DRM_DEBUG("context hanging too fast, banning!\n");
2514 } else if (i915_stop_ring_allow_ban(dev_priv)) {
2515 if (i915_stop_ring_allow_warn(dev_priv))
2516 DRM_ERROR("gpu hanging too fast, banning!\n");
2524 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2525 struct intel_context *ctx,
2528 struct i915_ctx_hang_stats *hs;
2533 hs = &ctx->hang_stats;
2536 hs->banned = i915_context_is_banned(dev_priv, ctx);
2538 hs->guilty_ts = get_seconds();
2540 hs->batch_pending++;
2544 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2546 list_del(&request->list);
2547 i915_gem_request_remove_from_client(request);
2549 put_pid(request->pid);
2551 i915_gem_request_unreference(request);
2554 void i915_gem_request_free(struct kref *req_ref)
2556 struct drm_i915_gem_request *req = container_of(req_ref,
2558 struct intel_context *ctx = req->ctx;
2561 if (i915.enable_execlists) {
2562 struct intel_engine_cs *ring = req->ring;
2564 if (ctx != ring->default_context)
2565 intel_lr_context_unpin(ring, ctx);
2568 i915_gem_context_unreference(ctx);
2571 kmem_cache_free(req->i915->requests, req);
2574 int i915_gem_request_alloc(struct intel_engine_cs *ring,
2575 struct intel_context *ctx)
2577 struct drm_i915_private *dev_priv = to_i915(ring->dev);
2578 struct drm_i915_gem_request *rq;
2581 if (ring->outstanding_lazy_request)
2584 rq = kmem_cache_zalloc(dev_priv->requests, GFP_KERNEL);
2588 kref_init(&rq->ref);
2589 rq->i915 = dev_priv;
2591 ret = i915_gem_get_seqno(ring->dev, &rq->seqno);
2599 if (i915.enable_execlists)
2600 ret = intel_logical_ring_alloc_request_extras(rq, ctx);
2602 ret = intel_ring_alloc_request_extras(rq);
2608 ring->outstanding_lazy_request = rq;
2612 struct drm_i915_gem_request *
2613 i915_gem_find_active_request(struct intel_engine_cs *ring)
2615 struct drm_i915_gem_request *request;
2617 list_for_each_entry(request, &ring->request_list, list) {
2618 if (i915_gem_request_completed(request, false))
2627 static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
2628 struct intel_engine_cs *ring)
2630 struct drm_i915_gem_request *request;
2633 request = i915_gem_find_active_request(ring);
2635 if (request == NULL)
2638 ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2640 i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2642 list_for_each_entry_continue(request, &ring->request_list, list)
2643 i915_set_reset_status(dev_priv, request->ctx, false);
2646 static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2647 struct intel_engine_cs *ring)
2649 while (!list_empty(&ring->active_list)) {
2650 struct drm_i915_gem_object *obj;
2652 obj = list_first_entry(&ring->active_list,
2653 struct drm_i915_gem_object,
2656 i915_gem_object_move_to_inactive(obj);
2660 * Clear the execlists queue up before freeing the requests, as those
2661 * are the ones that keep the context and ringbuffer backing objects
2664 while (!list_empty(&ring->execlist_queue)) {
2665 struct drm_i915_gem_request *submit_req;
2667 submit_req = list_first_entry(&ring->execlist_queue,
2668 struct drm_i915_gem_request,
2670 list_del(&submit_req->execlist_link);
2672 if (submit_req->ctx != ring->default_context)
2673 intel_lr_context_unpin(ring, submit_req->ctx);
2675 i915_gem_request_unreference(submit_req);
2679 * We must free the requests after all the corresponding objects have
2680 * been moved off active lists. Which is the same order as the normal
2681 * retire_requests function does. This is important if object hold
2682 * implicit references on things like e.g. ppgtt address spaces through
2685 while (!list_empty(&ring->request_list)) {
2686 struct drm_i915_gem_request *request;
2688 request = list_first_entry(&ring->request_list,
2689 struct drm_i915_gem_request,
2692 i915_gem_free_request(request);
2695 /* This may not have been flushed before the reset, so clean it now */
2696 i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
2699 void i915_gem_restore_fences(struct drm_device *dev)
2701 struct drm_i915_private *dev_priv = dev->dev_private;
2704 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2705 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2708 * Commit delayed tiling changes if we have an object still
2709 * attached to the fence, otherwise just clear the fence.
2712 i915_gem_object_update_fence(reg->obj, reg,
2713 reg->obj->tiling_mode);
2715 i915_gem_write_fence(dev, i, NULL);
2720 void i915_gem_reset(struct drm_device *dev)
2722 struct drm_i915_private *dev_priv = dev->dev_private;
2723 struct intel_engine_cs *ring;
2727 * Before we free the objects from the requests, we need to inspect
2728 * them for finding the guilty party. As the requests only borrow
2729 * their reference to the objects, the inspection must be done first.
2731 for_each_ring(ring, dev_priv, i)
2732 i915_gem_reset_ring_status(dev_priv, ring);
2734 for_each_ring(ring, dev_priv, i)
2735 i915_gem_reset_ring_cleanup(dev_priv, ring);
2737 i915_gem_context_reset(dev);
2739 i915_gem_restore_fences(dev);
2743 * This function clears the request list as sequence numbers are passed.
2746 i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
2748 if (list_empty(&ring->request_list))
2751 WARN_ON(i915_verify_lists(ring->dev));
2753 /* Retire requests first as we use it above for the early return.
2754 * If we retire requests last, we may use a later seqno and so clear
2755 * the requests lists without clearing the active list, leading to
2758 while (!list_empty(&ring->request_list)) {
2759 struct drm_i915_gem_request *request;
2761 request = list_first_entry(&ring->request_list,
2762 struct drm_i915_gem_request,
2765 if (!i915_gem_request_completed(request, true))
2768 trace_i915_gem_request_retire(request);
2770 /* We know the GPU must have read the request to have
2771 * sent us the seqno + interrupt, so use the position
2772 * of tail of the request to update the last known position
2775 request->ringbuf->last_retired_head = request->postfix;
2777 i915_gem_free_request(request);
2780 /* Move any buffers on the active list that are no longer referenced
2781 * by the ringbuffer to the flushing/inactive lists as appropriate,
2782 * before we free the context associated with the requests.
2784 while (!list_empty(&ring->active_list)) {
2785 struct drm_i915_gem_object *obj;
2787 obj = list_first_entry(&ring->active_list,
2788 struct drm_i915_gem_object,
2791 if (!i915_gem_request_completed(obj->last_read_req, true))
2794 i915_gem_object_move_to_inactive(obj);
2797 if (unlikely(ring->trace_irq_req &&
2798 i915_gem_request_completed(ring->trace_irq_req, true))) {
2799 ring->irq_put(ring);
2800 i915_gem_request_assign(&ring->trace_irq_req, NULL);
2803 WARN_ON(i915_verify_lists(ring->dev));
2807 i915_gem_retire_requests(struct drm_device *dev)
2809 struct drm_i915_private *dev_priv = dev->dev_private;
2810 struct intel_engine_cs *ring;
2814 for_each_ring(ring, dev_priv, i) {
2815 i915_gem_retire_requests_ring(ring);
2816 idle &= list_empty(&ring->request_list);
2817 if (i915.enable_execlists) {
2818 unsigned long flags;
2820 spin_lock_irqsave(&ring->execlist_lock, flags);
2821 idle &= list_empty(&ring->execlist_queue);
2822 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2824 intel_execlists_retire_requests(ring);
2829 mod_delayed_work(dev_priv->wq,
2830 &dev_priv->mm.idle_work,
2831 msecs_to_jiffies(100));
2837 i915_gem_retire_work_handler(struct work_struct *work)
2839 struct drm_i915_private *dev_priv =
2840 container_of(work, typeof(*dev_priv), mm.retire_work.work);
2841 struct drm_device *dev = dev_priv->dev;
2844 /* Come back later if the device is busy... */
2846 if (mutex_trylock(&dev->struct_mutex)) {
2847 idle = i915_gem_retire_requests(dev);
2848 mutex_unlock(&dev->struct_mutex);
2851 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2852 round_jiffies_up_relative(HZ));
2856 i915_gem_idle_work_handler(struct work_struct *work)
2858 struct drm_i915_private *dev_priv =
2859 container_of(work, typeof(*dev_priv), mm.idle_work.work);
2860 struct drm_device *dev = dev_priv->dev;
2861 struct intel_engine_cs *ring;
2864 for_each_ring(ring, dev_priv, i)
2865 if (!list_empty(&ring->request_list))
2868 intel_mark_idle(dev);
2870 if (mutex_trylock(&dev->struct_mutex)) {
2871 struct intel_engine_cs *ring;
2874 for_each_ring(ring, dev_priv, i)
2875 i915_gem_batch_pool_fini(&ring->batch_pool);
2877 mutex_unlock(&dev->struct_mutex);
2882 * Ensures that an object will eventually get non-busy by flushing any required
2883 * write domains, emitting any outstanding lazy request and retiring and
2884 * completed requests.
2887 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2889 struct intel_engine_cs *ring;
2893 ring = i915_gem_request_get_ring(obj->last_read_req);
2895 ret = i915_gem_check_olr(obj->last_read_req);
2899 i915_gem_retire_requests_ring(ring);
2906 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2907 * @DRM_IOCTL_ARGS: standard ioctl arguments
2909 * Returns 0 if successful, else an error is returned with the remaining time in
2910 * the timeout parameter.
2911 * -ETIME: object is still busy after timeout
2912 * -ERESTARTSYS: signal interrupted the wait
2913 * -ENONENT: object doesn't exist
2914 * Also possible, but rare:
2915 * -EAGAIN: GPU wedged
2917 * -ENODEV: Internal IRQ fail
2918 * -E?: The add request failed
2920 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2921 * non-zero timeout parameter the wait ioctl will wait for the given number of
2922 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2923 * without holding struct_mutex the object may become re-busied before this
2924 * function completes. A similar but shorter * race condition exists in the busy
2928 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2930 struct drm_i915_private *dev_priv = dev->dev_private;
2931 struct drm_i915_gem_wait *args = data;
2932 struct drm_i915_gem_object *obj;
2933 struct drm_i915_gem_request *req;
2934 unsigned reset_counter;
2937 if (args->flags != 0)
2940 ret = i915_mutex_lock_interruptible(dev);
2944 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2945 if (&obj->base == NULL) {
2946 mutex_unlock(&dev->struct_mutex);
2950 /* Need to make sure the object gets inactive eventually. */
2951 ret = i915_gem_object_flush_active(obj);
2955 if (!obj->active || !obj->last_read_req)
2958 req = obj->last_read_req;
2960 /* Do this after OLR check to make sure we make forward progress polling
2961 * on this IOCTL with a timeout == 0 (like busy ioctl)
2963 if (args->timeout_ns == 0) {
2968 drm_gem_object_unreference(&obj->base);
2969 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2970 i915_gem_request_reference(req);
2971 mutex_unlock(&dev->struct_mutex);
2973 ret = __i915_wait_request(req, reset_counter, true,
2974 args->timeout_ns > 0 ? &args->timeout_ns : NULL,
2976 i915_gem_request_unreference__unlocked(req);
2980 drm_gem_object_unreference(&obj->base);
2981 mutex_unlock(&dev->struct_mutex);
2986 * i915_gem_object_sync - sync an object to a ring.
2988 * @obj: object which may be in use on another ring.
2989 * @to: ring we wish to use the object on. May be NULL.
2991 * This code is meant to abstract object synchronization with the GPU.
2992 * Calling with NULL implies synchronizing the object with the CPU
2993 * rather than a particular GPU ring.
2995 * Returns 0 if successful, else propagates up the lower layer error.
2998 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2999 struct intel_engine_cs *to)
3001 struct intel_engine_cs *from;
3005 from = i915_gem_request_get_ring(obj->last_read_req);
3007 if (from == NULL || to == from)
3010 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
3011 return i915_gem_object_wait_rendering(obj, false);
3013 idx = intel_ring_sync_index(from, to);
3015 seqno = i915_gem_request_get_seqno(obj->last_read_req);
3016 /* Optimization: Avoid semaphore sync when we are sure we already
3017 * waited for an object with higher seqno */
3018 if (seqno <= from->semaphore.sync_seqno[idx])
3021 ret = i915_gem_check_olr(obj->last_read_req);
3025 trace_i915_gem_ring_sync_to(from, to, obj->last_read_req);
3026 ret = to->semaphore.sync_to(to, from, seqno);
3028 /* We use last_read_req because sync_to()
3029 * might have just caused seqno wrap under
3032 from->semaphore.sync_seqno[idx] =
3033 i915_gem_request_get_seqno(obj->last_read_req);
3038 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
3040 u32 old_write_domain, old_read_domains;
3042 /* Force a pagefault for domain tracking on next user access */
3043 i915_gem_release_mmap(obj);
3045 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3048 /* Wait for any direct GTT access to complete */
3051 old_read_domains = obj->base.read_domains;
3052 old_write_domain = obj->base.write_domain;
3054 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
3055 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
3057 trace_i915_gem_object_change_domain(obj,
3062 int i915_vma_unbind(struct i915_vma *vma)
3064 struct drm_i915_gem_object *obj = vma->obj;
3065 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3068 if (list_empty(&vma->vma_link))
3071 if (!drm_mm_node_allocated(&vma->node)) {
3072 i915_gem_vma_destroy(vma);
3079 BUG_ON(obj->pages == NULL);
3081 ret = i915_gem_object_finish_gpu(obj);
3084 /* Continue on if we fail due to EIO, the GPU is hung so we
3085 * should be safe and we need to cleanup or else we might
3086 * cause memory corruption through use-after-free.
3089 if (i915_is_ggtt(vma->vm) &&
3090 vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3091 i915_gem_object_finish_gtt(obj);
3093 /* release the fence reg _after_ flushing */
3094 ret = i915_gem_object_put_fence(obj);
3099 trace_i915_vma_unbind(vma);
3101 vma->vm->unbind_vma(vma);
3104 list_del_init(&vma->mm_list);
3105 if (i915_is_ggtt(vma->vm)) {
3106 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3107 obj->map_and_fenceable = false;
3108 } else if (vma->ggtt_view.pages) {
3109 sg_free_table(vma->ggtt_view.pages);
3110 kfree(vma->ggtt_view.pages);
3111 vma->ggtt_view.pages = NULL;
3115 drm_mm_remove_node(&vma->node);
3116 i915_gem_vma_destroy(vma);
3118 /* Since the unbound list is global, only move to that list if
3119 * no more VMAs exist. */
3120 if (list_empty(&obj->vma_list)) {
3121 /* Throw away the active reference before
3122 * moving to the unbound list. */
3123 i915_gem_object_retire(obj);
3125 i915_gem_gtt_finish_object(obj);
3126 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
3129 /* And finally now the object is completely decoupled from this vma,
3130 * we can drop its hold on the backing storage and allow it to be
3131 * reaped by the shrinker.
3133 i915_gem_object_unpin_pages(obj);
3138 int i915_gpu_idle(struct drm_device *dev)
3140 struct drm_i915_private *dev_priv = dev->dev_private;
3141 struct intel_engine_cs *ring;
3144 /* Flush everything onto the inactive list. */
3145 for_each_ring(ring, dev_priv, i) {
3146 if (!i915.enable_execlists) {
3147 ret = i915_switch_context(ring, ring->default_context);
3152 ret = intel_ring_idle(ring);
3160 static void i965_write_fence_reg(struct drm_device *dev, int reg,
3161 struct drm_i915_gem_object *obj)
3163 struct drm_i915_private *dev_priv = dev->dev_private;
3165 int fence_pitch_shift;
3167 if (INTEL_INFO(dev)->gen >= 6) {
3168 fence_reg = FENCE_REG_SANDYBRIDGE_0;
3169 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
3171 fence_reg = FENCE_REG_965_0;
3172 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
3175 fence_reg += reg * 8;
3177 /* To w/a incoherency with non-atomic 64-bit register updates,
3178 * we split the 64-bit update into two 32-bit writes. In order
3179 * for a partial fence not to be evaluated between writes, we
3180 * precede the update with write to turn off the fence register,
3181 * and only enable the fence as the last step.
3183 * For extra levels of paranoia, we make sure each step lands
3184 * before applying the next step.
3186 I915_WRITE(fence_reg, 0);
3187 POSTING_READ(fence_reg);
3190 u32 size = i915_gem_obj_ggtt_size(obj);
3193 /* Adjust fence size to match tiled area */
3194 if (obj->tiling_mode != I915_TILING_NONE) {
3195 uint32_t row_size = obj->stride *
3196 (obj->tiling_mode == I915_TILING_Y ? 32 : 8);
3197 size = (size / row_size) * row_size;
3200 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
3202 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
3203 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
3204 if (obj->tiling_mode == I915_TILING_Y)
3205 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
3206 val |= I965_FENCE_REG_VALID;
3208 I915_WRITE(fence_reg + 4, val >> 32);
3209 POSTING_READ(fence_reg + 4);
3211 I915_WRITE(fence_reg + 0, val);
3212 POSTING_READ(fence_reg);
3214 I915_WRITE(fence_reg + 4, 0);
3215 POSTING_READ(fence_reg + 4);
3219 static void i915_write_fence_reg(struct drm_device *dev, int reg,
3220 struct drm_i915_gem_object *obj)
3222 struct drm_i915_private *dev_priv = dev->dev_private;
3226 u32 size = i915_gem_obj_ggtt_size(obj);
3230 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
3231 (size & -size) != size ||
3232 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3233 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3234 i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
3236 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
3241 /* Note: pitch better be a power of two tile widths */
3242 pitch_val = obj->stride / tile_width;
3243 pitch_val = ffs(pitch_val) - 1;
3245 val = i915_gem_obj_ggtt_offset(obj);
3246 if (obj->tiling_mode == I915_TILING_Y)
3247 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3248 val |= I915_FENCE_SIZE_BITS(size);
3249 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3250 val |= I830_FENCE_REG_VALID;
3255 reg = FENCE_REG_830_0 + reg * 4;
3257 reg = FENCE_REG_945_8 + (reg - 8) * 4;
3259 I915_WRITE(reg, val);
3263 static void i830_write_fence_reg(struct drm_device *dev, int reg,
3264 struct drm_i915_gem_object *obj)
3266 struct drm_i915_private *dev_priv = dev->dev_private;
3270 u32 size = i915_gem_obj_ggtt_size(obj);
3273 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
3274 (size & -size) != size ||
3275 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3276 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3277 i915_gem_obj_ggtt_offset(obj), size);
3279 pitch_val = obj->stride / 128;
3280 pitch_val = ffs(pitch_val) - 1;
3282 val = i915_gem_obj_ggtt_offset(obj);
3283 if (obj->tiling_mode == I915_TILING_Y)
3284 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3285 val |= I830_FENCE_SIZE_BITS(size);
3286 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3287 val |= I830_FENCE_REG_VALID;
3291 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
3292 POSTING_READ(FENCE_REG_830_0 + reg * 4);
3295 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
3297 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
3300 static void i915_gem_write_fence(struct drm_device *dev, int reg,
3301 struct drm_i915_gem_object *obj)
3303 struct drm_i915_private *dev_priv = dev->dev_private;
3305 /* Ensure that all CPU reads are completed before installing a fence
3306 * and all writes before removing the fence.
3308 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
3311 WARN(obj && (!obj->stride || !obj->tiling_mode),
3312 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3313 obj->stride, obj->tiling_mode);
3316 i830_write_fence_reg(dev, reg, obj);
3317 else if (IS_GEN3(dev))
3318 i915_write_fence_reg(dev, reg, obj);
3319 else if (INTEL_INFO(dev)->gen >= 4)
3320 i965_write_fence_reg(dev, reg, obj);
3322 /* And similarly be paranoid that no direct access to this region
3323 * is reordered to before the fence is installed.
3325 if (i915_gem_object_needs_mb(obj))
3329 static inline int fence_number(struct drm_i915_private *dev_priv,
3330 struct drm_i915_fence_reg *fence)
3332 return fence - dev_priv->fence_regs;
3335 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
3336 struct drm_i915_fence_reg *fence,
3339 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3340 int reg = fence_number(dev_priv, fence);
3342 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
3345 obj->fence_reg = reg;
3347 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
3349 obj->fence_reg = I915_FENCE_REG_NONE;
3351 list_del_init(&fence->lru_list);
3353 obj->fence_dirty = false;
3357 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
3359 if (obj->last_fenced_req) {
3360 int ret = i915_wait_request(obj->last_fenced_req);
3364 i915_gem_request_assign(&obj->last_fenced_req, NULL);
3371 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3373 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3374 struct drm_i915_fence_reg *fence;
3377 ret = i915_gem_object_wait_fence(obj);
3381 if (obj->fence_reg == I915_FENCE_REG_NONE)
3384 fence = &dev_priv->fence_regs[obj->fence_reg];
3386 if (WARN_ON(fence->pin_count))
3389 i915_gem_object_fence_lost(obj);
3390 i915_gem_object_update_fence(obj, fence, false);
3395 static struct drm_i915_fence_reg *
3396 i915_find_fence_reg(struct drm_device *dev)
3398 struct drm_i915_private *dev_priv = dev->dev_private;
3399 struct drm_i915_fence_reg *reg, *avail;
3402 /* First try to find a free reg */
3404 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3405 reg = &dev_priv->fence_regs[i];
3409 if (!reg->pin_count)
3416 /* None available, try to steal one or wait for a user to finish */
3417 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3425 /* Wait for completion of pending flips which consume fences */
3426 if (intel_has_pending_fb_unpin(dev))
3427 return ERR_PTR(-EAGAIN);
3429 return ERR_PTR(-EDEADLK);
3433 * i915_gem_object_get_fence - set up fencing for an object
3434 * @obj: object to map through a fence reg
3436 * When mapping objects through the GTT, userspace wants to be able to write
3437 * to them without having to worry about swizzling if the object is tiled.
3438 * This function walks the fence regs looking for a free one for @obj,
3439 * stealing one if it can't find any.
3441 * It then sets up the reg based on the object's properties: address, pitch
3442 * and tiling format.
3444 * For an untiled surface, this removes any existing fence.
3447 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3449 struct drm_device *dev = obj->base.dev;
3450 struct drm_i915_private *dev_priv = dev->dev_private;
3451 bool enable = obj->tiling_mode != I915_TILING_NONE;
3452 struct drm_i915_fence_reg *reg;
3455 /* Have we updated the tiling parameters upon the object and so
3456 * will need to serialise the write to the associated fence register?
3458 if (obj->fence_dirty) {
3459 ret = i915_gem_object_wait_fence(obj);
3464 /* Just update our place in the LRU if our fence is getting reused. */
3465 if (obj->fence_reg != I915_FENCE_REG_NONE) {
3466 reg = &dev_priv->fence_regs[obj->fence_reg];
3467 if (!obj->fence_dirty) {
3468 list_move_tail(®->lru_list,
3469 &dev_priv->mm.fence_list);
3472 } else if (enable) {
3473 if (WARN_ON(!obj->map_and_fenceable))
3476 reg = i915_find_fence_reg(dev);
3478 return PTR_ERR(reg);
3481 struct drm_i915_gem_object *old = reg->obj;
3483 ret = i915_gem_object_wait_fence(old);
3487 i915_gem_object_fence_lost(old);
3492 i915_gem_object_update_fence(obj, reg, enable);
3497 static bool i915_gem_valid_gtt_space(struct i915_vma *vma,
3498 unsigned long cache_level)
3500 struct drm_mm_node *gtt_space = &vma->node;
3501 struct drm_mm_node *other;
3504 * On some machines we have to be careful when putting differing types
3505 * of snoopable memory together to avoid the prefetcher crossing memory
3506 * domains and dying. During vm initialisation, we decide whether or not
3507 * these constraints apply and set the drm_mm.color_adjust
3510 if (vma->vm->mm.color_adjust == NULL)
3513 if (!drm_mm_node_allocated(gtt_space))
3516 if (list_empty(>t_space->node_list))
3519 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3520 if (other->allocated && !other->hole_follows && other->color != cache_level)
3523 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3524 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3531 * Finds free space in the GTT aperture and binds the object or a view of it
3534 static struct i915_vma *
3535 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3536 struct i915_address_space *vm,
3537 const struct i915_ggtt_view *ggtt_view,
3541 struct drm_device *dev = obj->base.dev;
3542 struct drm_i915_private *dev_priv = dev->dev_private;
3543 u32 size, fence_size, fence_alignment, unfenced_alignment;
3544 unsigned long start =
3545 flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
3547 flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total;
3548 struct i915_vma *vma;
3551 if (i915_is_ggtt(vm)) {
3554 if (WARN_ON(!ggtt_view))
3555 return ERR_PTR(-EINVAL);
3557 view_size = i915_ggtt_view_size(obj, ggtt_view);
3559 fence_size = i915_gem_get_gtt_size(dev,
3562 fence_alignment = i915_gem_get_gtt_alignment(dev,
3566 unfenced_alignment = i915_gem_get_gtt_alignment(dev,
3570 size = flags & PIN_MAPPABLE ? fence_size : view_size;
3572 fence_size = i915_gem_get_gtt_size(dev,
3575 fence_alignment = i915_gem_get_gtt_alignment(dev,
3579 unfenced_alignment =
3580 i915_gem_get_gtt_alignment(dev,
3584 size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3588 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3590 if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3591 DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n",
3592 ggtt_view ? ggtt_view->type : 0,
3594 return ERR_PTR(-EINVAL);
3597 /* If binding the object/GGTT view requires more space than the entire
3598 * aperture has, reject it early before evicting everything in a vain
3599 * attempt to find space.
3602 DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%u > %s aperture=%lu\n",
3603 ggtt_view ? ggtt_view->type : 0,
3605 flags & PIN_MAPPABLE ? "mappable" : "total",
3607 return ERR_PTR(-E2BIG);
3610 ret = i915_gem_object_get_pages(obj);
3612 return ERR_PTR(ret);
3614 i915_gem_object_pin_pages(obj);
3616 vma = ggtt_view ? i915_gem_obj_lookup_or_create_ggtt_vma(obj, ggtt_view) :
3617 i915_gem_obj_lookup_or_create_vma(obj, vm);
3623 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3627 DRM_MM_SEARCH_DEFAULT,
3628 DRM_MM_CREATE_DEFAULT);
3630 ret = i915_gem_evict_something(dev, vm, size, alignment,
3639 if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) {
3641 goto err_remove_node;
3644 ret = i915_gem_gtt_prepare_object(obj);
3646 goto err_remove_node;
3648 trace_i915_vma_bind(vma, flags);
3649 ret = i915_vma_bind(vma, obj->cache_level, flags);
3651 goto err_finish_gtt;
3653 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3654 list_add_tail(&vma->mm_list, &vm->inactive_list);
3659 i915_gem_gtt_finish_object(obj);
3661 drm_mm_remove_node(&vma->node);
3663 i915_gem_vma_destroy(vma);
3666 i915_gem_object_unpin_pages(obj);
3671 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3674 /* If we don't have a page list set up, then we're not pinned
3675 * to GPU, and we can ignore the cache flush because it'll happen
3676 * again at bind time.
3678 if (obj->pages == NULL)
3682 * Stolen memory is always coherent with the GPU as it is explicitly
3683 * marked as wc by the system, or the system is cache-coherent.
3685 if (obj->stolen || obj->phys_handle)
3688 /* If the GPU is snooping the contents of the CPU cache,
3689 * we do not need to manually clear the CPU cache lines. However,
3690 * the caches are only snooped when the render cache is
3691 * flushed/invalidated. As we always have to emit invalidations
3692 * and flushes when moving into and out of the RENDER domain, correct
3693 * snooping behaviour occurs naturally as the result of our domain
3696 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) {
3697 obj->cache_dirty = true;
3701 trace_i915_gem_object_clflush(obj);
3702 drm_clflush_sg(obj->pages);
3703 obj->cache_dirty = false;
3708 /** Flushes the GTT write domain for the object if it's dirty. */
3710 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3712 uint32_t old_write_domain;
3714 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3717 /* No actual flushing is required for the GTT write domain. Writes
3718 * to it immediately go to main memory as far as we know, so there's
3719 * no chipset flush. It also doesn't land in render cache.
3721 * However, we do have to enforce the order so that all writes through
3722 * the GTT land before any writes to the device, such as updates to
3727 old_write_domain = obj->base.write_domain;
3728 obj->base.write_domain = 0;
3730 intel_fb_obj_flush(obj, false);
3732 trace_i915_gem_object_change_domain(obj,
3733 obj->base.read_domains,
3737 /** Flushes the CPU write domain for the object if it's dirty. */
3739 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3741 uint32_t old_write_domain;
3743 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3746 if (i915_gem_clflush_object(obj, obj->pin_display))
3747 i915_gem_chipset_flush(obj->base.dev);
3749 old_write_domain = obj->base.write_domain;
3750 obj->base.write_domain = 0;
3752 intel_fb_obj_flush(obj, false);
3754 trace_i915_gem_object_change_domain(obj,
3755 obj->base.read_domains,
3760 * Moves a single object to the GTT read, and possibly write domain.
3762 * This function returns when the move is complete, including waiting on
3766 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3768 uint32_t old_write_domain, old_read_domains;
3769 struct i915_vma *vma;
3772 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3775 ret = i915_gem_object_wait_rendering(obj, !write);
3779 i915_gem_object_retire(obj);
3781 /* Flush and acquire obj->pages so that we are coherent through
3782 * direct access in memory with previous cached writes through
3783 * shmemfs and that our cache domain tracking remains valid.
3784 * For example, if the obj->filp was moved to swap without us
3785 * being notified and releasing the pages, we would mistakenly
3786 * continue to assume that the obj remained out of the CPU cached
3789 ret = i915_gem_object_get_pages(obj);
3793 i915_gem_object_flush_cpu_write_domain(obj);
3795 /* Serialise direct access to this object with the barriers for
3796 * coherent writes from the GPU, by effectively invalidating the
3797 * GTT domain upon first access.
3799 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3802 old_write_domain = obj->base.write_domain;
3803 old_read_domains = obj->base.read_domains;
3805 /* It should now be out of any other write domains, and we can update
3806 * the domain values for our changes.
3808 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3809 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3811 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3812 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3817 intel_fb_obj_invalidate(obj, NULL, ORIGIN_GTT);
3819 trace_i915_gem_object_change_domain(obj,
3823 /* And bump the LRU for this access */
3824 vma = i915_gem_obj_to_ggtt(obj);
3825 if (vma && drm_mm_node_allocated(&vma->node) && !obj->active)
3826 list_move_tail(&vma->mm_list,
3827 &to_i915(obj->base.dev)->gtt.base.inactive_list);
3832 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3833 enum i915_cache_level cache_level)
3835 struct drm_device *dev = obj->base.dev;
3836 struct i915_vma *vma, *next;
3839 if (obj->cache_level == cache_level)
3842 if (i915_gem_obj_is_pinned(obj)) {
3843 DRM_DEBUG("can not change the cache level of pinned objects\n");
3847 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
3848 if (!i915_gem_valid_gtt_space(vma, cache_level)) {
3849 ret = i915_vma_unbind(vma);
3855 if (i915_gem_obj_bound_any(obj)) {
3856 ret = i915_gem_object_finish_gpu(obj);
3860 i915_gem_object_finish_gtt(obj);
3862 /* Before SandyBridge, you could not use tiling or fence
3863 * registers with snooped memory, so relinquish any fences
3864 * currently pointing to our region in the aperture.
3866 if (INTEL_INFO(dev)->gen < 6) {
3867 ret = i915_gem_object_put_fence(obj);
3872 list_for_each_entry(vma, &obj->vma_list, vma_link)
3873 if (drm_mm_node_allocated(&vma->node)) {
3874 ret = i915_vma_bind(vma, cache_level,
3881 list_for_each_entry(vma, &obj->vma_list, vma_link)
3882 vma->node.color = cache_level;
3883 obj->cache_level = cache_level;
3885 if (obj->cache_dirty &&
3886 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
3887 cpu_write_needs_clflush(obj)) {
3888 if (i915_gem_clflush_object(obj, true))
3889 i915_gem_chipset_flush(obj->base.dev);
3895 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3896 struct drm_file *file)
3898 struct drm_i915_gem_caching *args = data;
3899 struct drm_i915_gem_object *obj;
3901 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3902 if (&obj->base == NULL)
3905 switch (obj->cache_level) {
3906 case I915_CACHE_LLC:
3907 case I915_CACHE_L3_LLC:
3908 args->caching = I915_CACHING_CACHED;
3912 args->caching = I915_CACHING_DISPLAY;
3916 args->caching = I915_CACHING_NONE;
3920 drm_gem_object_unreference_unlocked(&obj->base);
3924 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3925 struct drm_file *file)
3927 struct drm_i915_gem_caching *args = data;
3928 struct drm_i915_gem_object *obj;
3929 enum i915_cache_level level;
3932 switch (args->caching) {
3933 case I915_CACHING_NONE:
3934 level = I915_CACHE_NONE;
3936 case I915_CACHING_CACHED:
3937 level = I915_CACHE_LLC;
3939 case I915_CACHING_DISPLAY:
3940 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3946 ret = i915_mutex_lock_interruptible(dev);
3950 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3951 if (&obj->base == NULL) {
3956 ret = i915_gem_object_set_cache_level(obj, level);
3958 drm_gem_object_unreference(&obj->base);
3960 mutex_unlock(&dev->struct_mutex);
3965 * Prepare buffer for display plane (scanout, cursors, etc).
3966 * Can be called from an uninterruptible phase (modesetting) and allows
3967 * any flushes to be pipelined (for pageflips).
3970 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3972 struct intel_engine_cs *pipelined,
3973 const struct i915_ggtt_view *view)
3975 u32 old_read_domains, old_write_domain;
3978 if (pipelined != i915_gem_request_get_ring(obj->last_read_req)) {
3979 ret = i915_gem_object_sync(obj, pipelined);
3984 /* Mark the pin_display early so that we account for the
3985 * display coherency whilst setting up the cache domains.
3989 /* The display engine is not coherent with the LLC cache on gen6. As
3990 * a result, we make sure that the pinning that is about to occur is
3991 * done with uncached PTEs. This is lowest common denominator for all
3994 * However for gen6+, we could do better by using the GFDT bit instead
3995 * of uncaching, which would allow us to flush all the LLC-cached data
3996 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3998 ret = i915_gem_object_set_cache_level(obj,
3999 HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
4001 goto err_unpin_display;
4003 /* As the user may map the buffer once pinned in the display plane
4004 * (e.g. libkms for the bootup splash), we have to ensure that we
4005 * always use map_and_fenceable for all scanout buffers.
4007 ret = i915_gem_object_ggtt_pin(obj, view, alignment,
4008 view->type == I915_GGTT_VIEW_NORMAL ?
4011 goto err_unpin_display;
4013 i915_gem_object_flush_cpu_write_domain(obj);
4015 old_write_domain = obj->base.write_domain;
4016 old_read_domains = obj->base.read_domains;
4018 /* It should now be out of any other write domains, and we can update
4019 * the domain values for our changes.
4021 obj->base.write_domain = 0;
4022 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
4024 trace_i915_gem_object_change_domain(obj,
4036 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
4037 const struct i915_ggtt_view *view)
4039 if (WARN_ON(obj->pin_display == 0))
4042 i915_gem_object_ggtt_unpin_view(obj, view);
4048 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
4052 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
4055 ret = i915_gem_object_wait_rendering(obj, false);
4059 /* Ensure that we invalidate the GPU's caches and TLBs. */
4060 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
4065 * Moves a single object to the CPU read, and possibly write domain.
4067 * This function returns when the move is complete, including waiting on
4071 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
4073 uint32_t old_write_domain, old_read_domains;
4076 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
4079 ret = i915_gem_object_wait_rendering(obj, !write);
4083 i915_gem_object_retire(obj);
4084 i915_gem_object_flush_gtt_write_domain(obj);
4086 old_write_domain = obj->base.write_domain;
4087 old_read_domains = obj->base.read_domains;
4089 /* Flush the CPU cache if it's still invalid. */
4090 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
4091 i915_gem_clflush_object(obj, false);
4093 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
4096 /* It should now be out of any other write domains, and we can update
4097 * the domain values for our changes.
4099 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
4101 /* If we're writing through the CPU, then the GPU read domains will
4102 * need to be invalidated at next use.
4105 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4106 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4110 intel_fb_obj_invalidate(obj, NULL, ORIGIN_CPU);
4112 trace_i915_gem_object_change_domain(obj,
4119 /* Throttle our rendering by waiting until the ring has completed our requests
4120 * emitted over 20 msec ago.
4122 * Note that if we were to use the current jiffies each time around the loop,
4123 * we wouldn't escape the function with any frames outstanding if the time to
4124 * render a frame was over 20ms.
4126 * This should get us reasonable parallelism between CPU and GPU but also
4127 * relatively low latency when blocking on a particular request to finish.
4130 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
4132 struct drm_i915_private *dev_priv = dev->dev_private;
4133 struct drm_i915_file_private *file_priv = file->driver_priv;
4134 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
4135 struct drm_i915_gem_request *request, *target = NULL;
4136 unsigned reset_counter;
4139 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
4143 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
4147 spin_lock(&file_priv->mm.lock);
4148 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
4149 if (time_after_eq(request->emitted_jiffies, recent_enough))
4154 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
4156 i915_gem_request_reference(target);
4157 spin_unlock(&file_priv->mm.lock);
4162 ret = __i915_wait_request(target, reset_counter, true, NULL, NULL);
4164 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
4166 i915_gem_request_unreference__unlocked(target);
4172 i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
4174 struct drm_i915_gem_object *obj = vma->obj;
4177 vma->node.start & (alignment - 1))
4180 if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
4183 if (flags & PIN_OFFSET_BIAS &&
4184 vma->node.start < (flags & PIN_OFFSET_MASK))
4191 i915_gem_object_do_pin(struct drm_i915_gem_object *obj,
4192 struct i915_address_space *vm,
4193 const struct i915_ggtt_view *ggtt_view,
4197 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4198 struct i915_vma *vma;
4202 if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
4205 if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
4208 if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE))
4211 if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
4214 vma = ggtt_view ? i915_gem_obj_to_ggtt_view(obj, ggtt_view) :
4215 i915_gem_obj_to_vma(obj, vm);
4218 return PTR_ERR(vma);
4221 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
4224 if (i915_vma_misplaced(vma, alignment, flags)) {
4225 unsigned long offset;
4226 offset = ggtt_view ? i915_gem_obj_ggtt_offset_view(obj, ggtt_view) :
4227 i915_gem_obj_offset(obj, vm);
4228 WARN(vma->pin_count,
4229 "bo is already pinned in %s with incorrect alignment:"
4230 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4231 " obj->map_and_fenceable=%d\n",
4232 ggtt_view ? "ggtt" : "ppgtt",
4235 !!(flags & PIN_MAPPABLE),
4236 obj->map_and_fenceable);
4237 ret = i915_vma_unbind(vma);
4245 bound = vma ? vma->bound : 0;
4246 if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
4247 vma = i915_gem_object_bind_to_vm(obj, vm, ggtt_view, alignment,
4250 return PTR_ERR(vma);
4252 ret = i915_vma_bind(vma, obj->cache_level, flags);
4257 if (ggtt_view && ggtt_view->type == I915_GGTT_VIEW_NORMAL &&
4258 (bound ^ vma->bound) & GLOBAL_BIND) {
4259 bool mappable, fenceable;
4260 u32 fence_size, fence_alignment;
4262 fence_size = i915_gem_get_gtt_size(obj->base.dev,
4265 fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev,
4270 fenceable = (vma->node.size == fence_size &&
4271 (vma->node.start & (fence_alignment - 1)) == 0);
4273 mappable = (vma->node.start + fence_size <=
4274 dev_priv->gtt.mappable_end);
4276 obj->map_and_fenceable = mappable && fenceable;
4278 WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
4286 i915_gem_object_pin(struct drm_i915_gem_object *obj,
4287 struct i915_address_space *vm,
4291 return i915_gem_object_do_pin(obj, vm,
4292 i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL,
4297 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
4298 const struct i915_ggtt_view *view,
4302 if (WARN_ONCE(!view, "no view specified"))
4305 return i915_gem_object_do_pin(obj, i915_obj_to_ggtt(obj), view,
4306 alignment, flags | PIN_GLOBAL);
4310 i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
4311 const struct i915_ggtt_view *view)
4313 struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view);
4316 WARN_ON(vma->pin_count == 0);
4317 WARN_ON(!i915_gem_obj_ggtt_bound_view(obj, view));
4323 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
4325 if (obj->fence_reg != I915_FENCE_REG_NONE) {
4326 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4327 struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj);
4329 WARN_ON(!ggtt_vma ||
4330 dev_priv->fence_regs[obj->fence_reg].pin_count >
4331 ggtt_vma->pin_count);
4332 dev_priv->fence_regs[obj->fence_reg].pin_count++;
4339 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
4341 if (obj->fence_reg != I915_FENCE_REG_NONE) {
4342 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4343 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
4344 dev_priv->fence_regs[obj->fence_reg].pin_count--;
4349 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4350 struct drm_file *file)
4352 struct drm_i915_gem_busy *args = data;
4353 struct drm_i915_gem_object *obj;
4356 ret = i915_mutex_lock_interruptible(dev);
4360 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4361 if (&obj->base == NULL) {
4366 /* Count all active objects as busy, even if they are currently not used
4367 * by the gpu. Users of this interface expect objects to eventually
4368 * become non-busy without any further actions, therefore emit any
4369 * necessary flushes here.
4371 ret = i915_gem_object_flush_active(obj);
4373 args->busy = obj->active;
4374 if (obj->last_read_req) {
4375 struct intel_engine_cs *ring;
4376 BUILD_BUG_ON(I915_NUM_RINGS > 16);
4377 ring = i915_gem_request_get_ring(obj->last_read_req);
4378 args->busy |= intel_ring_flag(ring) << 16;
4381 drm_gem_object_unreference(&obj->base);
4383 mutex_unlock(&dev->struct_mutex);
4388 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4389 struct drm_file *file_priv)
4391 return i915_gem_ring_throttle(dev, file_priv);
4395 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4396 struct drm_file *file_priv)
4398 struct drm_i915_private *dev_priv = dev->dev_private;
4399 struct drm_i915_gem_madvise *args = data;
4400 struct drm_i915_gem_object *obj;
4403 switch (args->madv) {
4404 case I915_MADV_DONTNEED:
4405 case I915_MADV_WILLNEED:
4411 ret = i915_mutex_lock_interruptible(dev);
4415 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4416 if (&obj->base == NULL) {
4421 if (i915_gem_obj_is_pinned(obj)) {
4427 obj->tiling_mode != I915_TILING_NONE &&
4428 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
4429 if (obj->madv == I915_MADV_WILLNEED)
4430 i915_gem_object_unpin_pages(obj);
4431 if (args->madv == I915_MADV_WILLNEED)
4432 i915_gem_object_pin_pages(obj);
4435 if (obj->madv != __I915_MADV_PURGED)
4436 obj->madv = args->madv;
4438 /* if the object is no longer attached, discard its backing storage */
4439 if (obj->madv == I915_MADV_DONTNEED && obj->pages == NULL)
4440 i915_gem_object_truncate(obj);
4442 args->retained = obj->madv != __I915_MADV_PURGED;
4445 drm_gem_object_unreference(&obj->base);
4447 mutex_unlock(&dev->struct_mutex);
4451 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4452 const struct drm_i915_gem_object_ops *ops)
4454 INIT_LIST_HEAD(&obj->global_list);
4455 INIT_LIST_HEAD(&obj->ring_list);
4456 INIT_LIST_HEAD(&obj->obj_exec_link);
4457 INIT_LIST_HEAD(&obj->vma_list);
4458 INIT_LIST_HEAD(&obj->batch_pool_link);
4462 obj->fence_reg = I915_FENCE_REG_NONE;
4463 obj->madv = I915_MADV_WILLNEED;
4465 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4468 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4469 .get_pages = i915_gem_object_get_pages_gtt,
4470 .put_pages = i915_gem_object_put_pages_gtt,
4473 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4476 struct drm_i915_gem_object *obj;
4477 struct address_space *mapping;
4480 obj = i915_gem_object_alloc(dev);
4484 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4485 i915_gem_object_free(obj);
4489 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4490 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4491 /* 965gm cannot relocate objects above 4GiB. */
4492 mask &= ~__GFP_HIGHMEM;
4493 mask |= __GFP_DMA32;
4496 mapping = file_inode(obj->base.filp)->i_mapping;
4497 mapping_set_gfp_mask(mapping, mask);
4499 i915_gem_object_init(obj, &i915_gem_object_ops);
4501 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4502 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4505 /* On some devices, we can have the GPU use the LLC (the CPU
4506 * cache) for about a 10% performance improvement
4507 * compared to uncached. Graphics requests other than
4508 * display scanout are coherent with the CPU in
4509 * accessing this cache. This means in this mode we
4510 * don't need to clflush on the CPU side, and on the
4511 * GPU side we only need to flush internal caches to
4512 * get data visible to the CPU.
4514 * However, we maintain the display planes as UC, and so
4515 * need to rebind when first used as such.
4517 obj->cache_level = I915_CACHE_LLC;
4519 obj->cache_level = I915_CACHE_NONE;
4521 trace_i915_gem_object_create(obj);
4526 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4528 /* If we are the last user of the backing storage (be it shmemfs
4529 * pages or stolen etc), we know that the pages are going to be
4530 * immediately released. In this case, we can then skip copying
4531 * back the contents from the GPU.
4534 if (obj->madv != I915_MADV_WILLNEED)
4537 if (obj->base.filp == NULL)
4540 /* At first glance, this looks racy, but then again so would be
4541 * userspace racing mmap against close. However, the first external
4542 * reference to the filp can only be obtained through the
4543 * i915_gem_mmap_ioctl() which safeguards us against the user
4544 * acquiring such a reference whilst we are in the middle of
4545 * freeing the object.
4547 return atomic_long_read(&obj->base.filp->f_count) == 1;
4550 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4552 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4553 struct drm_device *dev = obj->base.dev;
4554 struct drm_i915_private *dev_priv = dev->dev_private;
4555 struct i915_vma *vma, *next;
4557 intel_runtime_pm_get(dev_priv);
4559 trace_i915_gem_object_destroy(obj);
4561 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4565 ret = i915_vma_unbind(vma);
4566 if (WARN_ON(ret == -ERESTARTSYS)) {
4567 bool was_interruptible;
4569 was_interruptible = dev_priv->mm.interruptible;
4570 dev_priv->mm.interruptible = false;
4572 WARN_ON(i915_vma_unbind(vma));
4574 dev_priv->mm.interruptible = was_interruptible;
4578 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4579 * before progressing. */
4581 i915_gem_object_unpin_pages(obj);
4583 WARN_ON(obj->frontbuffer_bits);
4585 if (obj->pages && obj->madv == I915_MADV_WILLNEED &&
4586 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES &&
4587 obj->tiling_mode != I915_TILING_NONE)
4588 i915_gem_object_unpin_pages(obj);
4590 if (WARN_ON(obj->pages_pin_count))
4591 obj->pages_pin_count = 0;
4592 if (discard_backing_storage(obj))
4593 obj->madv = I915_MADV_DONTNEED;
4594 i915_gem_object_put_pages(obj);
4595 i915_gem_object_free_mmap_offset(obj);
4599 if (obj->base.import_attach)
4600 drm_prime_gem_destroy(&obj->base, NULL);
4602 if (obj->ops->release)
4603 obj->ops->release(obj);
4605 drm_gem_object_release(&obj->base);
4606 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4609 i915_gem_object_free(obj);
4611 intel_runtime_pm_put(dev_priv);
4614 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4615 struct i915_address_space *vm)
4617 struct i915_vma *vma;
4618 list_for_each_entry(vma, &obj->vma_list, vma_link) {
4619 if (i915_is_ggtt(vma->vm) &&
4620 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
4628 struct i915_vma *i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
4629 const struct i915_ggtt_view *view)
4631 struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
4632 struct i915_vma *vma;
4634 if (WARN_ONCE(!view, "no view specified"))
4635 return ERR_PTR(-EINVAL);
4637 list_for_each_entry(vma, &obj->vma_list, vma_link)
4638 if (vma->vm == ggtt &&
4639 i915_ggtt_view_equal(&vma->ggtt_view, view))
4644 void i915_gem_vma_destroy(struct i915_vma *vma)
4646 struct i915_address_space *vm = NULL;
4647 WARN_ON(vma->node.allocated);
4649 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4650 if (!list_empty(&vma->exec_list))
4655 if (!i915_is_ggtt(vm))
4656 i915_ppgtt_put(i915_vm_to_ppgtt(vm));
4658 list_del(&vma->vma_link);
4660 kmem_cache_free(to_i915(vma->obj->base.dev)->vmas, vma);
4664 i915_gem_stop_ringbuffers(struct drm_device *dev)
4666 struct drm_i915_private *dev_priv = dev->dev_private;
4667 struct intel_engine_cs *ring;
4670 for_each_ring(ring, dev_priv, i)
4671 dev_priv->gt.stop_ring(ring);
4675 i915_gem_suspend(struct drm_device *dev)
4677 struct drm_i915_private *dev_priv = dev->dev_private;
4680 mutex_lock(&dev->struct_mutex);
4681 ret = i915_gpu_idle(dev);
4685 i915_gem_retire_requests(dev);
4687 i915_gem_stop_ringbuffers(dev);
4688 mutex_unlock(&dev->struct_mutex);
4690 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
4691 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4692 flush_delayed_work(&dev_priv->mm.idle_work);
4694 /* Assert that we sucessfully flushed all the work and
4695 * reset the GPU back to its idle, low power state.
4697 WARN_ON(dev_priv->mm.busy);
4702 mutex_unlock(&dev->struct_mutex);
4706 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice)
4708 struct drm_device *dev = ring->dev;
4709 struct drm_i915_private *dev_priv = dev->dev_private;
4710 u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4711 u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4714 if (!HAS_L3_DPF(dev) || !remap_info)
4717 ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
4722 * Note: We do not worry about the concurrent register cacheline hang
4723 * here because no other code should access these registers other than
4724 * at initialization time.
4726 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4727 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4728 intel_ring_emit(ring, reg_base + i);
4729 intel_ring_emit(ring, remap_info[i/4]);
4732 intel_ring_advance(ring);
4737 void i915_gem_init_swizzling(struct drm_device *dev)
4739 struct drm_i915_private *dev_priv = dev->dev_private;
4741 if (INTEL_INFO(dev)->gen < 5 ||
4742 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4745 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4746 DISP_TILE_SURFACE_SWIZZLING);
4751 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4753 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4754 else if (IS_GEN7(dev))
4755 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4756 else if (IS_GEN8(dev))
4757 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4763 intel_enable_blt(struct drm_device *dev)
4768 /* The blitter was dysfunctional on early prototypes */
4769 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4770 DRM_INFO("BLT not supported on this pre-production hardware;"
4771 " graphics performance will be degraded.\n");
4778 static void init_unused_ring(struct drm_device *dev, u32 base)
4780 struct drm_i915_private *dev_priv = dev->dev_private;
4782 I915_WRITE(RING_CTL(base), 0);
4783 I915_WRITE(RING_HEAD(base), 0);
4784 I915_WRITE(RING_TAIL(base), 0);
4785 I915_WRITE(RING_START(base), 0);
4788 static void init_unused_rings(struct drm_device *dev)
4791 init_unused_ring(dev, PRB1_BASE);
4792 init_unused_ring(dev, SRB0_BASE);
4793 init_unused_ring(dev, SRB1_BASE);
4794 init_unused_ring(dev, SRB2_BASE);
4795 init_unused_ring(dev, SRB3_BASE);
4796 } else if (IS_GEN2(dev)) {
4797 init_unused_ring(dev, SRB0_BASE);
4798 init_unused_ring(dev, SRB1_BASE);
4799 } else if (IS_GEN3(dev)) {
4800 init_unused_ring(dev, PRB1_BASE);
4801 init_unused_ring(dev, PRB2_BASE);
4805 int i915_gem_init_rings(struct drm_device *dev)
4807 struct drm_i915_private *dev_priv = dev->dev_private;
4810 ret = intel_init_render_ring_buffer(dev);
4815 ret = intel_init_bsd_ring_buffer(dev);
4817 goto cleanup_render_ring;
4820 if (intel_enable_blt(dev)) {
4821 ret = intel_init_blt_ring_buffer(dev);
4823 goto cleanup_bsd_ring;
4826 if (HAS_VEBOX(dev)) {
4827 ret = intel_init_vebox_ring_buffer(dev);
4829 goto cleanup_blt_ring;
4832 if (HAS_BSD2(dev)) {
4833 ret = intel_init_bsd2_ring_buffer(dev);
4835 goto cleanup_vebox_ring;
4838 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4840 goto cleanup_bsd2_ring;
4845 intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]);
4847 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4849 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4851 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4852 cleanup_render_ring:
4853 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4859 i915_gem_init_hw(struct drm_device *dev)
4861 struct drm_i915_private *dev_priv = dev->dev_private;
4862 struct intel_engine_cs *ring;
4865 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4868 /* Double layer security blanket, see i915_gem_init() */
4869 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4871 if (dev_priv->ellc_size)
4872 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4874 if (IS_HASWELL(dev))
4875 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4876 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4878 if (HAS_PCH_NOP(dev)) {
4879 if (IS_IVYBRIDGE(dev)) {
4880 u32 temp = I915_READ(GEN7_MSG_CTL);
4881 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4882 I915_WRITE(GEN7_MSG_CTL, temp);
4883 } else if (INTEL_INFO(dev)->gen >= 7) {
4884 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4885 temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4886 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4890 i915_gem_init_swizzling(dev);
4893 * At least 830 can leave some of the unused rings
4894 * "active" (ie. head != tail) after resume which
4895 * will prevent c3 entry. Makes sure all unused rings
4898 init_unused_rings(dev);
4900 for_each_ring(ring, dev_priv, i) {
4901 ret = ring->init_hw(ring);
4906 for (i = 0; i < NUM_L3_SLICES(dev); i++)
4907 i915_gem_l3_remap(&dev_priv->ring[RCS], i);
4909 ret = i915_ppgtt_init_hw(dev);
4910 if (ret && ret != -EIO) {
4911 DRM_ERROR("PPGTT enable failed %d\n", ret);
4912 i915_gem_cleanup_ringbuffer(dev);
4915 ret = i915_gem_context_enable(dev_priv);
4916 if (ret && ret != -EIO) {
4917 DRM_ERROR("Context enable failed %d\n", ret);
4918 i915_gem_cleanup_ringbuffer(dev);
4924 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4928 int i915_gem_init(struct drm_device *dev)
4930 struct drm_i915_private *dev_priv = dev->dev_private;
4933 i915.enable_execlists = intel_sanitize_enable_execlists(dev,
4934 i915.enable_execlists);
4936 mutex_lock(&dev->struct_mutex);
4938 if (IS_VALLEYVIEW(dev)) {
4939 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4940 I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
4941 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
4942 VLV_GTLC_ALLOWWAKEACK), 10))
4943 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4946 if (!i915.enable_execlists) {
4947 dev_priv->gt.execbuf_submit = i915_gem_ringbuffer_submission;
4948 dev_priv->gt.init_rings = i915_gem_init_rings;
4949 dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer;
4950 dev_priv->gt.stop_ring = intel_stop_ring_buffer;
4952 dev_priv->gt.execbuf_submit = intel_execlists_submission;
4953 dev_priv->gt.init_rings = intel_logical_rings_init;
4954 dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup;
4955 dev_priv->gt.stop_ring = intel_logical_ring_stop;
4958 /* This is just a security blanket to placate dragons.
4959 * On some systems, we very sporadically observe that the first TLBs
4960 * used by the CS may be stale, despite us poking the TLB reset. If
4961 * we hold the forcewake during initialisation these problems
4962 * just magically go away.
4964 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4966 ret = i915_gem_init_userptr(dev);
4970 i915_gem_init_global_gtt(dev);
4972 ret = i915_gem_context_init(dev);
4976 ret = dev_priv->gt.init_rings(dev);
4980 ret = i915_gem_init_hw(dev);
4982 /* Allow ring initialisation to fail by marking the GPU as
4983 * wedged. But we only want to do this where the GPU is angry,
4984 * for all other failure, such as an allocation failure, bail.
4986 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4987 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
4992 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4993 mutex_unlock(&dev->struct_mutex);
4999 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
5001 struct drm_i915_private *dev_priv = dev->dev_private;
5002 struct intel_engine_cs *ring;
5005 for_each_ring(ring, dev_priv, i)
5006 dev_priv->gt.cleanup_ring(ring);
5010 init_ring_lists(struct intel_engine_cs *ring)
5012 INIT_LIST_HEAD(&ring->active_list);
5013 INIT_LIST_HEAD(&ring->request_list);
5016 void i915_init_vm(struct drm_i915_private *dev_priv,
5017 struct i915_address_space *vm)
5019 if (!i915_is_ggtt(vm))
5020 drm_mm_init(&vm->mm, vm->start, vm->total);
5021 vm->dev = dev_priv->dev;
5022 INIT_LIST_HEAD(&vm->active_list);
5023 INIT_LIST_HEAD(&vm->inactive_list);
5024 INIT_LIST_HEAD(&vm->global_link);
5025 list_add_tail(&vm->global_link, &dev_priv->vm_list);
5029 i915_gem_load(struct drm_device *dev)
5031 struct drm_i915_private *dev_priv = dev->dev_private;
5035 kmem_cache_create("i915_gem_object",
5036 sizeof(struct drm_i915_gem_object), 0,
5040 kmem_cache_create("i915_gem_vma",
5041 sizeof(struct i915_vma), 0,
5044 dev_priv->requests =
5045 kmem_cache_create("i915_gem_request",
5046 sizeof(struct drm_i915_gem_request), 0,
5050 INIT_LIST_HEAD(&dev_priv->vm_list);
5051 i915_init_vm(dev_priv, &dev_priv->gtt.base);
5053 INIT_LIST_HEAD(&dev_priv->context_list);
5054 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
5055 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
5056 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5057 for (i = 0; i < I915_NUM_RINGS; i++)
5058 init_ring_lists(&dev_priv->ring[i]);
5059 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
5060 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
5061 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
5062 i915_gem_retire_work_handler);
5063 INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
5064 i915_gem_idle_work_handler);
5065 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
5067 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
5069 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
5070 dev_priv->num_fence_regs = 32;
5071 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5072 dev_priv->num_fence_regs = 16;
5074 dev_priv->num_fence_regs = 8;
5076 if (intel_vgpu_active(dev))
5077 dev_priv->num_fence_regs =
5078 I915_READ(vgtif_reg(avail_rs.fence_num));
5080 /* Initialize fence registers to zero */
5081 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5082 i915_gem_restore_fences(dev);
5084 i915_gem_detect_bit_6_swizzle(dev);
5085 init_waitqueue_head(&dev_priv->pending_flip_queue);
5087 dev_priv->mm.interruptible = true;
5089 i915_gem_shrinker_init(dev_priv);
5091 mutex_init(&dev_priv->fb_tracking.lock);
5094 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
5096 struct drm_i915_file_private *file_priv = file->driver_priv;
5098 /* Clean up our request list when the client is going away, so that
5099 * later retire_requests won't dereference our soon-to-be-gone
5102 spin_lock(&file_priv->mm.lock);
5103 while (!list_empty(&file_priv->mm.request_list)) {
5104 struct drm_i915_gem_request *request;
5106 request = list_first_entry(&file_priv->mm.request_list,
5107 struct drm_i915_gem_request,
5109 list_del(&request->client_list);
5110 request->file_priv = NULL;
5112 spin_unlock(&file_priv->mm.lock);
5114 if (!list_empty(&file_priv->rps_boost)) {
5115 mutex_lock(&to_i915(dev)->rps.hw_lock);
5116 list_del(&file_priv->rps_boost);
5117 mutex_unlock(&to_i915(dev)->rps.hw_lock);
5121 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
5123 struct drm_i915_file_private *file_priv;
5126 DRM_DEBUG_DRIVER("\n");
5128 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
5132 file->driver_priv = file_priv;
5133 file_priv->dev_priv = dev->dev_private;
5134 file_priv->file = file;
5135 INIT_LIST_HEAD(&file_priv->rps_boost);
5137 spin_lock_init(&file_priv->mm.lock);
5138 INIT_LIST_HEAD(&file_priv->mm.request_list);
5140 ret = i915_gem_context_open(dev, file);
5148 * i915_gem_track_fb - update frontbuffer tracking
5149 * old: current GEM buffer for the frontbuffer slots
5150 * new: new GEM buffer for the frontbuffer slots
5151 * frontbuffer_bits: bitmask of frontbuffer slots
5153 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5154 * from @old and setting them in @new. Both @old and @new can be NULL.
5156 void i915_gem_track_fb(struct drm_i915_gem_object *old,
5157 struct drm_i915_gem_object *new,
5158 unsigned frontbuffer_bits)
5161 WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex));
5162 WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits));
5163 old->frontbuffer_bits &= ~frontbuffer_bits;
5167 WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex));
5168 WARN_ON(new->frontbuffer_bits & frontbuffer_bits);
5169 new->frontbuffer_bits |= frontbuffer_bits;
5173 /* All the new VM stuff */
5175 i915_gem_obj_offset(struct drm_i915_gem_object *o,
5176 struct i915_address_space *vm)
5178 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5179 struct i915_vma *vma;
5181 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5183 list_for_each_entry(vma, &o->vma_list, vma_link) {
5184 if (i915_is_ggtt(vma->vm) &&
5185 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5188 return vma->node.start;
5191 WARN(1, "%s vma for this object not found.\n",
5192 i915_is_ggtt(vm) ? "global" : "ppgtt");
5197 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
5198 const struct i915_ggtt_view *view)
5200 struct i915_address_space *ggtt = i915_obj_to_ggtt(o);
5201 struct i915_vma *vma;
5203 list_for_each_entry(vma, &o->vma_list, vma_link)
5204 if (vma->vm == ggtt &&
5205 i915_ggtt_view_equal(&vma->ggtt_view, view))
5206 return vma->node.start;
5208 WARN(1, "global vma for this object not found. (view=%u)\n", view->type);
5212 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
5213 struct i915_address_space *vm)
5215 struct i915_vma *vma;
5217 list_for_each_entry(vma, &o->vma_list, vma_link) {
5218 if (i915_is_ggtt(vma->vm) &&
5219 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5221 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
5228 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
5229 const struct i915_ggtt_view *view)
5231 struct i915_address_space *ggtt = i915_obj_to_ggtt(o);
5232 struct i915_vma *vma;
5234 list_for_each_entry(vma, &o->vma_list, vma_link)
5235 if (vma->vm == ggtt &&
5236 i915_ggtt_view_equal(&vma->ggtt_view, view) &&
5237 drm_mm_node_allocated(&vma->node))
5243 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5245 struct i915_vma *vma;
5247 list_for_each_entry(vma, &o->vma_list, vma_link)
5248 if (drm_mm_node_allocated(&vma->node))
5254 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5255 struct i915_address_space *vm)
5257 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5258 struct i915_vma *vma;
5260 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5262 BUG_ON(list_empty(&o->vma_list));
5264 list_for_each_entry(vma, &o->vma_list, vma_link) {
5265 if (i915_is_ggtt(vma->vm) &&
5266 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5269 return vma->node.size;
5274 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj)
5276 struct i915_vma *vma;
5277 list_for_each_entry(vma, &obj->vma_list, vma_link)
5278 if (vma->pin_count > 0)