2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/shmem_fs.h>
35 #include <linux/slab.h>
36 #include <linux/swap.h>
37 #include <linux/pci.h>
38 #include <linux/dma-buf.h>
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
43 static __must_check int
44 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
46 static int i915_gem_phys_pwrite(struct drm_device *dev,
47 struct drm_i915_gem_object *obj,
48 struct drm_i915_gem_pwrite *args,
49 struct drm_file *file);
51 static void i915_gem_write_fence(struct drm_device *dev, int reg,
52 struct drm_i915_gem_object *obj);
53 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
54 struct drm_i915_fence_reg *fence,
57 static unsigned long i915_gem_inactive_count(struct shrinker *shrinker,
58 struct shrink_control *sc);
59 static unsigned long i915_gem_inactive_scan(struct shrinker *shrinker,
60 struct shrink_control *sc);
61 static unsigned long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
62 static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
63 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
64 static void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
66 static bool cpu_cache_is_coherent(struct drm_device *dev,
67 enum i915_cache_level level)
69 return HAS_LLC(dev) || level != I915_CACHE_NONE;
72 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
74 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
77 return obj->pin_display;
80 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
83 i915_gem_release_mmap(obj);
85 /* As we do not have an associated fence register, we will force
86 * a tiling change if we ever need to acquire one.
88 obj->fence_dirty = false;
89 obj->fence_reg = I915_FENCE_REG_NONE;
92 /* some bookkeeping */
93 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
96 spin_lock(&dev_priv->mm.object_stat_lock);
97 dev_priv->mm.object_count++;
98 dev_priv->mm.object_memory += size;
99 spin_unlock(&dev_priv->mm.object_stat_lock);
102 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
105 spin_lock(&dev_priv->mm.object_stat_lock);
106 dev_priv->mm.object_count--;
107 dev_priv->mm.object_memory -= size;
108 spin_unlock(&dev_priv->mm.object_stat_lock);
112 i915_gem_wait_for_error(struct i915_gpu_error *error)
116 #define EXIT_COND (!i915_reset_in_progress(error) || \
117 i915_terminally_wedged(error))
122 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
123 * userspace. If it takes that long something really bad is going on and
124 * we should simply try to bail out and fail as gracefully as possible.
126 ret = wait_event_interruptible_timeout(error->reset_queue,
130 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
132 } else if (ret < 0) {
140 int i915_mutex_lock_interruptible(struct drm_device *dev)
142 struct drm_i915_private *dev_priv = dev->dev_private;
145 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
149 ret = mutex_lock_interruptible(&dev->struct_mutex);
153 WARN_ON(i915_verify_lists(dev));
158 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
160 return i915_gem_obj_bound_any(obj) && !obj->active;
164 i915_gem_init_ioctl(struct drm_device *dev, void *data,
165 struct drm_file *file)
167 struct drm_i915_private *dev_priv = dev->dev_private;
168 struct drm_i915_gem_init *args = data;
170 if (drm_core_check_feature(dev, DRIVER_MODESET))
173 if (args->gtt_start >= args->gtt_end ||
174 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
177 /* GEM with user mode setting was never supported on ilk and later. */
178 if (INTEL_INFO(dev)->gen >= 5)
181 mutex_lock(&dev->struct_mutex);
182 i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
184 dev_priv->gtt.mappable_end = args->gtt_end;
185 mutex_unlock(&dev->struct_mutex);
191 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
192 struct drm_file *file)
194 struct drm_i915_private *dev_priv = dev->dev_private;
195 struct drm_i915_gem_get_aperture *args = data;
196 struct drm_i915_gem_object *obj;
200 mutex_lock(&dev->struct_mutex);
201 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
202 if (i915_gem_obj_is_pinned(obj))
203 pinned += i915_gem_obj_ggtt_size(obj);
204 mutex_unlock(&dev->struct_mutex);
206 args->aper_size = dev_priv->gtt.base.total;
207 args->aper_available_size = args->aper_size - pinned;
212 void *i915_gem_object_alloc(struct drm_device *dev)
214 struct drm_i915_private *dev_priv = dev->dev_private;
215 return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL);
218 void i915_gem_object_free(struct drm_i915_gem_object *obj)
220 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
221 kmem_cache_free(dev_priv->slab, obj);
225 i915_gem_create(struct drm_file *file,
226 struct drm_device *dev,
230 struct drm_i915_gem_object *obj;
234 size = roundup(size, PAGE_SIZE);
238 /* Allocate the new object */
239 obj = i915_gem_alloc_object(dev, size);
243 ret = drm_gem_handle_create(file, &obj->base, &handle);
244 /* drop reference from allocate - handle holds it now */
245 drm_gem_object_unreference_unlocked(&obj->base);
254 i915_gem_dumb_create(struct drm_file *file,
255 struct drm_device *dev,
256 struct drm_mode_create_dumb *args)
258 /* have to work out size/pitch and return them */
259 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
260 args->size = args->pitch * args->height;
261 return i915_gem_create(file, dev,
262 args->size, &args->handle);
266 * Creates a new mm object and returns a handle to it.
269 i915_gem_create_ioctl(struct drm_device *dev, void *data,
270 struct drm_file *file)
272 struct drm_i915_gem_create *args = data;
274 return i915_gem_create(file, dev,
275 args->size, &args->handle);
279 __copy_to_user_swizzled(char __user *cpu_vaddr,
280 const char *gpu_vaddr, int gpu_offset,
283 int ret, cpu_offset = 0;
286 int cacheline_end = ALIGN(gpu_offset + 1, 64);
287 int this_length = min(cacheline_end - gpu_offset, length);
288 int swizzled_gpu_offset = gpu_offset ^ 64;
290 ret = __copy_to_user(cpu_vaddr + cpu_offset,
291 gpu_vaddr + swizzled_gpu_offset,
296 cpu_offset += this_length;
297 gpu_offset += this_length;
298 length -= this_length;
305 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
306 const char __user *cpu_vaddr,
309 int ret, cpu_offset = 0;
312 int cacheline_end = ALIGN(gpu_offset + 1, 64);
313 int this_length = min(cacheline_end - gpu_offset, length);
314 int swizzled_gpu_offset = gpu_offset ^ 64;
316 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
317 cpu_vaddr + cpu_offset,
322 cpu_offset += this_length;
323 gpu_offset += this_length;
324 length -= this_length;
331 * Pins the specified object's pages and synchronizes the object with
332 * GPU accesses. Sets needs_clflush to non-zero if the caller should
333 * flush the object from the CPU cache.
335 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
345 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
346 /* If we're not in the cpu read domain, set ourself into the gtt
347 * read domain and manually flush cachelines (if required). This
348 * optimizes for the case when the gpu will dirty the data
349 * anyway again before the next pread happens. */
350 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
352 ret = i915_gem_object_wait_rendering(obj, true);
357 ret = i915_gem_object_get_pages(obj);
361 i915_gem_object_pin_pages(obj);
366 /* Per-page copy function for the shmem pread fastpath.
367 * Flushes invalid cachelines before reading the target if
368 * needs_clflush is set. */
370 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
371 char __user *user_data,
372 bool page_do_bit17_swizzling, bool needs_clflush)
377 if (unlikely(page_do_bit17_swizzling))
380 vaddr = kmap_atomic(page);
382 drm_clflush_virt_range(vaddr + shmem_page_offset,
384 ret = __copy_to_user_inatomic(user_data,
385 vaddr + shmem_page_offset,
387 kunmap_atomic(vaddr);
389 return ret ? -EFAULT : 0;
393 shmem_clflush_swizzled_range(char *addr, unsigned long length,
396 if (unlikely(swizzled)) {
397 unsigned long start = (unsigned long) addr;
398 unsigned long end = (unsigned long) addr + length;
400 /* For swizzling simply ensure that we always flush both
401 * channels. Lame, but simple and it works. Swizzled
402 * pwrite/pread is far from a hotpath - current userspace
403 * doesn't use it at all. */
404 start = round_down(start, 128);
405 end = round_up(end, 128);
407 drm_clflush_virt_range((void *)start, end - start);
409 drm_clflush_virt_range(addr, length);
414 /* Only difference to the fast-path function is that this can handle bit17
415 * and uses non-atomic copy and kmap functions. */
417 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
418 char __user *user_data,
419 bool page_do_bit17_swizzling, bool needs_clflush)
426 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
428 page_do_bit17_swizzling);
430 if (page_do_bit17_swizzling)
431 ret = __copy_to_user_swizzled(user_data,
432 vaddr, shmem_page_offset,
435 ret = __copy_to_user(user_data,
436 vaddr + shmem_page_offset,
440 return ret ? - EFAULT : 0;
444 i915_gem_shmem_pread(struct drm_device *dev,
445 struct drm_i915_gem_object *obj,
446 struct drm_i915_gem_pread *args,
447 struct drm_file *file)
449 char __user *user_data;
452 int shmem_page_offset, page_length, ret = 0;
453 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
455 int needs_clflush = 0;
456 struct sg_page_iter sg_iter;
458 user_data = to_user_ptr(args->data_ptr);
461 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
463 ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
467 offset = args->offset;
469 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
470 offset >> PAGE_SHIFT) {
471 struct page *page = sg_page_iter_page(&sg_iter);
476 /* Operation in this page
478 * shmem_page_offset = offset within page in shmem file
479 * page_length = bytes to copy for this page
481 shmem_page_offset = offset_in_page(offset);
482 page_length = remain;
483 if ((shmem_page_offset + page_length) > PAGE_SIZE)
484 page_length = PAGE_SIZE - shmem_page_offset;
486 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
487 (page_to_phys(page) & (1 << 17)) != 0;
489 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
490 user_data, page_do_bit17_swizzling,
495 mutex_unlock(&dev->struct_mutex);
497 if (likely(!i915.prefault_disable) && !prefaulted) {
498 ret = fault_in_multipages_writeable(user_data, remain);
499 /* Userspace is tricking us, but we've already clobbered
500 * its pages with the prefault and promised to write the
501 * data up to the first fault. Hence ignore any errors
502 * and just continue. */
507 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
508 user_data, page_do_bit17_swizzling,
511 mutex_lock(&dev->struct_mutex);
517 remain -= page_length;
518 user_data += page_length;
519 offset += page_length;
523 i915_gem_object_unpin_pages(obj);
529 * Reads data from the object referenced by handle.
531 * On error, the contents of *data are undefined.
534 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
535 struct drm_file *file)
537 struct drm_i915_gem_pread *args = data;
538 struct drm_i915_gem_object *obj;
544 if (!access_ok(VERIFY_WRITE,
545 to_user_ptr(args->data_ptr),
549 ret = i915_mutex_lock_interruptible(dev);
553 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
554 if (&obj->base == NULL) {
559 /* Bounds check source. */
560 if (args->offset > obj->base.size ||
561 args->size > obj->base.size - args->offset) {
566 /* prime objects have no backing filp to GEM pread/pwrite
569 if (!obj->base.filp) {
574 trace_i915_gem_object_pread(obj, args->offset, args->size);
576 ret = i915_gem_shmem_pread(dev, obj, args, file);
579 drm_gem_object_unreference(&obj->base);
581 mutex_unlock(&dev->struct_mutex);
585 /* This is the fast write path which cannot handle
586 * page faults in the source data
590 fast_user_write(struct io_mapping *mapping,
591 loff_t page_base, int page_offset,
592 char __user *user_data,
595 void __iomem *vaddr_atomic;
597 unsigned long unwritten;
599 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
600 /* We can use the cpu mem copy function because this is X86. */
601 vaddr = (void __force*)vaddr_atomic + page_offset;
602 unwritten = __copy_from_user_inatomic_nocache(vaddr,
604 io_mapping_unmap_atomic(vaddr_atomic);
609 * This is the fast pwrite path, where we copy the data directly from the
610 * user into the GTT, uncached.
613 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
614 struct drm_i915_gem_object *obj,
615 struct drm_i915_gem_pwrite *args,
616 struct drm_file *file)
618 struct drm_i915_private *dev_priv = dev->dev_private;
620 loff_t offset, page_base;
621 char __user *user_data;
622 int page_offset, page_length, ret;
624 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
628 ret = i915_gem_object_set_to_gtt_domain(obj, true);
632 ret = i915_gem_object_put_fence(obj);
636 user_data = to_user_ptr(args->data_ptr);
639 offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
642 /* Operation in this page
644 * page_base = page offset within aperture
645 * page_offset = offset within page
646 * page_length = bytes to copy for this page
648 page_base = offset & PAGE_MASK;
649 page_offset = offset_in_page(offset);
650 page_length = remain;
651 if ((page_offset + remain) > PAGE_SIZE)
652 page_length = PAGE_SIZE - page_offset;
654 /* If we get a fault while copying data, then (presumably) our
655 * source page isn't available. Return the error and we'll
656 * retry in the slow path.
658 if (fast_user_write(dev_priv->gtt.mappable, page_base,
659 page_offset, user_data, page_length)) {
664 remain -= page_length;
665 user_data += page_length;
666 offset += page_length;
670 i915_gem_object_ggtt_unpin(obj);
675 /* Per-page copy function for the shmem pwrite fastpath.
676 * Flushes invalid cachelines before writing to the target if
677 * needs_clflush_before is set and flushes out any written cachelines after
678 * writing if needs_clflush is set. */
680 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
681 char __user *user_data,
682 bool page_do_bit17_swizzling,
683 bool needs_clflush_before,
684 bool needs_clflush_after)
689 if (unlikely(page_do_bit17_swizzling))
692 vaddr = kmap_atomic(page);
693 if (needs_clflush_before)
694 drm_clflush_virt_range(vaddr + shmem_page_offset,
696 ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
697 user_data, page_length);
698 if (needs_clflush_after)
699 drm_clflush_virt_range(vaddr + shmem_page_offset,
701 kunmap_atomic(vaddr);
703 return ret ? -EFAULT : 0;
706 /* Only difference to the fast-path function is that this can handle bit17
707 * and uses non-atomic copy and kmap functions. */
709 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
710 char __user *user_data,
711 bool page_do_bit17_swizzling,
712 bool needs_clflush_before,
713 bool needs_clflush_after)
719 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
720 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
722 page_do_bit17_swizzling);
723 if (page_do_bit17_swizzling)
724 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
728 ret = __copy_from_user(vaddr + shmem_page_offset,
731 if (needs_clflush_after)
732 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
734 page_do_bit17_swizzling);
737 return ret ? -EFAULT : 0;
741 i915_gem_shmem_pwrite(struct drm_device *dev,
742 struct drm_i915_gem_object *obj,
743 struct drm_i915_gem_pwrite *args,
744 struct drm_file *file)
748 char __user *user_data;
749 int shmem_page_offset, page_length, ret = 0;
750 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
751 int hit_slowpath = 0;
752 int needs_clflush_after = 0;
753 int needs_clflush_before = 0;
754 struct sg_page_iter sg_iter;
756 user_data = to_user_ptr(args->data_ptr);
759 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
761 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
762 /* If we're not in the cpu write domain, set ourself into the gtt
763 * write domain and manually flush cachelines (if required). This
764 * optimizes for the case when the gpu will use the data
765 * right away and we therefore have to clflush anyway. */
766 needs_clflush_after = cpu_write_needs_clflush(obj);
767 ret = i915_gem_object_wait_rendering(obj, false);
771 /* Same trick applies to invalidate partially written cachelines read
773 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
774 needs_clflush_before =
775 !cpu_cache_is_coherent(dev, obj->cache_level);
777 ret = i915_gem_object_get_pages(obj);
781 i915_gem_object_pin_pages(obj);
783 offset = args->offset;
786 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
787 offset >> PAGE_SHIFT) {
788 struct page *page = sg_page_iter_page(&sg_iter);
789 int partial_cacheline_write;
794 /* Operation in this page
796 * shmem_page_offset = offset within page in shmem file
797 * page_length = bytes to copy for this page
799 shmem_page_offset = offset_in_page(offset);
801 page_length = remain;
802 if ((shmem_page_offset + page_length) > PAGE_SIZE)
803 page_length = PAGE_SIZE - shmem_page_offset;
805 /* If we don't overwrite a cacheline completely we need to be
806 * careful to have up-to-date data by first clflushing. Don't
807 * overcomplicate things and flush the entire patch. */
808 partial_cacheline_write = needs_clflush_before &&
809 ((shmem_page_offset | page_length)
810 & (boot_cpu_data.x86_clflush_size - 1));
812 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
813 (page_to_phys(page) & (1 << 17)) != 0;
815 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
816 user_data, page_do_bit17_swizzling,
817 partial_cacheline_write,
818 needs_clflush_after);
823 mutex_unlock(&dev->struct_mutex);
824 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
825 user_data, page_do_bit17_swizzling,
826 partial_cacheline_write,
827 needs_clflush_after);
829 mutex_lock(&dev->struct_mutex);
835 remain -= page_length;
836 user_data += page_length;
837 offset += page_length;
841 i915_gem_object_unpin_pages(obj);
845 * Fixup: Flush cpu caches in case we didn't flush the dirty
846 * cachelines in-line while writing and the object moved
847 * out of the cpu write domain while we've dropped the lock.
849 if (!needs_clflush_after &&
850 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
851 if (i915_gem_clflush_object(obj, obj->pin_display))
852 i915_gem_chipset_flush(dev);
856 if (needs_clflush_after)
857 i915_gem_chipset_flush(dev);
863 * Writes data to the object referenced by handle.
865 * On error, the contents of the buffer that were to be modified are undefined.
868 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
869 struct drm_file *file)
871 struct drm_i915_gem_pwrite *args = data;
872 struct drm_i915_gem_object *obj;
878 if (!access_ok(VERIFY_READ,
879 to_user_ptr(args->data_ptr),
883 if (likely(!i915.prefault_disable)) {
884 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
890 ret = i915_mutex_lock_interruptible(dev);
894 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
895 if (&obj->base == NULL) {
900 /* Bounds check destination. */
901 if (args->offset > obj->base.size ||
902 args->size > obj->base.size - args->offset) {
907 /* prime objects have no backing filp to GEM pread/pwrite
910 if (!obj->base.filp) {
915 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
918 /* We can only do the GTT pwrite on untiled buffers, as otherwise
919 * it would end up going through the fenced access, and we'll get
920 * different detiling behavior between reading and writing.
921 * pread/pwrite currently are reading and writing from the CPU
922 * perspective, requiring manual detiling by the client.
925 ret = i915_gem_phys_pwrite(dev, obj, args, file);
929 if (obj->tiling_mode == I915_TILING_NONE &&
930 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
931 cpu_write_needs_clflush(obj)) {
932 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
933 /* Note that the gtt paths might fail with non-page-backed user
934 * pointers (e.g. gtt mappings when moving data between
935 * textures). Fallback to the shmem path in that case. */
938 if (ret == -EFAULT || ret == -ENOSPC)
939 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
942 drm_gem_object_unreference(&obj->base);
944 mutex_unlock(&dev->struct_mutex);
949 i915_gem_check_wedge(struct i915_gpu_error *error,
952 if (i915_reset_in_progress(error)) {
953 /* Non-interruptible callers can't handle -EAGAIN, hence return
954 * -EIO unconditionally for these. */
958 /* Recovery complete, but the reset failed ... */
959 if (i915_terminally_wedged(error))
969 * Compare seqno against outstanding lazy request. Emit a request if they are
973 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
977 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
980 if (seqno == ring->outstanding_lazy_seqno)
981 ret = i915_add_request(ring, NULL);
986 static void fake_irq(unsigned long data)
988 wake_up_process((struct task_struct *)data);
991 static bool missed_irq(struct drm_i915_private *dev_priv,
992 struct intel_ring_buffer *ring)
994 return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
997 static bool can_wait_boost(struct drm_i915_file_private *file_priv)
999 if (file_priv == NULL)
1002 return !atomic_xchg(&file_priv->rps_wait_boost, true);
1006 * __wait_seqno - wait until execution of seqno has finished
1007 * @ring: the ring expected to report seqno
1009 * @reset_counter: reset sequence associated with the given seqno
1010 * @interruptible: do an interruptible wait (normally yes)
1011 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1013 * Note: It is of utmost importance that the passed in seqno and reset_counter
1014 * values have been read by the caller in an smp safe manner. Where read-side
1015 * locks are involved, it is sufficient to read the reset_counter before
1016 * unlocking the lock that protects the seqno. For lockless tricks, the
1017 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1020 * Returns 0 if the seqno was found within the alloted time. Else returns the
1021 * errno with remaining time filled in timeout argument.
1023 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
1024 unsigned reset_counter,
1026 struct timespec *timeout,
1027 struct drm_i915_file_private *file_priv)
1029 struct drm_device *dev = ring->dev;
1030 struct drm_i915_private *dev_priv = dev->dev_private;
1031 const bool irq_test_in_progress =
1032 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
1033 struct timespec before, now;
1035 unsigned long timeout_expire;
1038 WARN(dev_priv->pm.irqs_disabled, "IRQs disabled\n");
1040 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1043 timeout_expire = timeout ? jiffies + timespec_to_jiffies_timeout(timeout) : 0;
1045 if (INTEL_INFO(dev)->gen >= 6 && can_wait_boost(file_priv)) {
1046 gen6_rps_boost(dev_priv);
1048 mod_delayed_work(dev_priv->wq,
1049 &file_priv->mm.idle_work,
1050 msecs_to_jiffies(100));
1053 if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring)))
1056 /* Record current time in case interrupted by signal, or wedged */
1057 trace_i915_gem_request_wait_begin(ring, seqno);
1058 getrawmonotonic(&before);
1060 struct timer_list timer;
1062 prepare_to_wait(&ring->irq_queue, &wait,
1063 interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
1065 /* We need to check whether any gpu reset happened in between
1066 * the caller grabbing the seqno and now ... */
1067 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
1068 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1069 * is truely gone. */
1070 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1076 if (i915_seqno_passed(ring->get_seqno(ring, false), seqno)) {
1081 if (interruptible && signal_pending(current)) {
1086 if (timeout && time_after_eq(jiffies, timeout_expire)) {
1091 timer.function = NULL;
1092 if (timeout || missed_irq(dev_priv, ring)) {
1093 unsigned long expire;
1095 setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
1096 expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire;
1097 mod_timer(&timer, expire);
1102 if (timer.function) {
1103 del_singleshot_timer_sync(&timer);
1104 destroy_timer_on_stack(&timer);
1107 getrawmonotonic(&now);
1108 trace_i915_gem_request_wait_end(ring, seqno);
1110 if (!irq_test_in_progress)
1111 ring->irq_put(ring);
1113 finish_wait(&ring->irq_queue, &wait);
1116 struct timespec sleep_time = timespec_sub(now, before);
1117 *timeout = timespec_sub(*timeout, sleep_time);
1118 if (!timespec_valid(timeout)) /* i.e. negative time remains */
1119 set_normalized_timespec(timeout, 0, 0);
1126 * Waits for a sequence number to be signaled, and cleans up the
1127 * request and object lists appropriately for that event.
1130 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1132 struct drm_device *dev = ring->dev;
1133 struct drm_i915_private *dev_priv = dev->dev_private;
1134 bool interruptible = dev_priv->mm.interruptible;
1137 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1140 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1144 ret = i915_gem_check_olr(ring, seqno);
1148 return __wait_seqno(ring, seqno,
1149 atomic_read(&dev_priv->gpu_error.reset_counter),
1150 interruptible, NULL, NULL);
1154 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj,
1155 struct intel_ring_buffer *ring)
1157 i915_gem_retire_requests_ring(ring);
1159 /* Manually manage the write flush as we may have not yet
1160 * retired the buffer.
1162 * Note that the last_write_seqno is always the earlier of
1163 * the two (read/write) seqno, so if we haved successfully waited,
1164 * we know we have passed the last write.
1166 obj->last_write_seqno = 0;
1167 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1173 * Ensures that all rendering to the object has completed and the object is
1174 * safe to unbind from the GTT or access from the CPU.
1176 static __must_check int
1177 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1180 struct intel_ring_buffer *ring = obj->ring;
1184 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1188 ret = i915_wait_seqno(ring, seqno);
1192 return i915_gem_object_wait_rendering__tail(obj, ring);
1195 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1196 * as the object state may change during this call.
1198 static __must_check int
1199 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1200 struct drm_i915_file_private *file_priv,
1203 struct drm_device *dev = obj->base.dev;
1204 struct drm_i915_private *dev_priv = dev->dev_private;
1205 struct intel_ring_buffer *ring = obj->ring;
1206 unsigned reset_counter;
1210 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1211 BUG_ON(!dev_priv->mm.interruptible);
1213 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1217 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1221 ret = i915_gem_check_olr(ring, seqno);
1225 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1226 mutex_unlock(&dev->struct_mutex);
1227 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, file_priv);
1228 mutex_lock(&dev->struct_mutex);
1232 return i915_gem_object_wait_rendering__tail(obj, ring);
1236 * Called when user space prepares to use an object with the CPU, either
1237 * through the mmap ioctl's mapping or a GTT mapping.
1240 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1241 struct drm_file *file)
1243 struct drm_i915_gem_set_domain *args = data;
1244 struct drm_i915_gem_object *obj;
1245 uint32_t read_domains = args->read_domains;
1246 uint32_t write_domain = args->write_domain;
1249 /* Only handle setting domains to types used by the CPU. */
1250 if (write_domain & I915_GEM_GPU_DOMAINS)
1253 if (read_domains & I915_GEM_GPU_DOMAINS)
1256 /* Having something in the write domain implies it's in the read
1257 * domain, and only that read domain. Enforce that in the request.
1259 if (write_domain != 0 && read_domains != write_domain)
1262 ret = i915_mutex_lock_interruptible(dev);
1266 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1267 if (&obj->base == NULL) {
1272 /* Try to flush the object off the GPU without holding the lock.
1273 * We will repeat the flush holding the lock in the normal manner
1274 * to catch cases where we are gazumped.
1276 ret = i915_gem_object_wait_rendering__nonblocking(obj,
1282 if (read_domains & I915_GEM_DOMAIN_GTT) {
1283 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1285 /* Silently promote "you're not bound, there was nothing to do"
1286 * to success, since the client was just asking us to
1287 * make sure everything was done.
1292 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1296 drm_gem_object_unreference(&obj->base);
1298 mutex_unlock(&dev->struct_mutex);
1303 * Called when user space has done writes to this buffer
1306 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1307 struct drm_file *file)
1309 struct drm_i915_gem_sw_finish *args = data;
1310 struct drm_i915_gem_object *obj;
1313 ret = i915_mutex_lock_interruptible(dev);
1317 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1318 if (&obj->base == NULL) {
1323 /* Pinned buffers may be scanout, so flush the cache */
1324 if (obj->pin_display)
1325 i915_gem_object_flush_cpu_write_domain(obj, true);
1327 drm_gem_object_unreference(&obj->base);
1329 mutex_unlock(&dev->struct_mutex);
1334 * Maps the contents of an object, returning the address it is mapped
1337 * While the mapping holds a reference on the contents of the object, it doesn't
1338 * imply a ref on the object itself.
1341 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1342 struct drm_file *file)
1344 struct drm_i915_gem_mmap *args = data;
1345 struct drm_gem_object *obj;
1348 obj = drm_gem_object_lookup(dev, file, args->handle);
1352 /* prime objects have no backing filp to GEM mmap
1356 drm_gem_object_unreference_unlocked(obj);
1360 addr = vm_mmap(obj->filp, 0, args->size,
1361 PROT_READ | PROT_WRITE, MAP_SHARED,
1363 drm_gem_object_unreference_unlocked(obj);
1364 if (IS_ERR((void *)addr))
1367 args->addr_ptr = (uint64_t) addr;
1373 * i915_gem_fault - fault a page into the GTT
1374 * vma: VMA in question
1377 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1378 * from userspace. The fault handler takes care of binding the object to
1379 * the GTT (if needed), allocating and programming a fence register (again,
1380 * only if needed based on whether the old reg is still valid or the object
1381 * is tiled) and inserting a new PTE into the faulting process.
1383 * Note that the faulting process may involve evicting existing objects
1384 * from the GTT and/or fence registers to make room. So performance may
1385 * suffer if the GTT working set is large or there are few fence registers
1388 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1390 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1391 struct drm_device *dev = obj->base.dev;
1392 struct drm_i915_private *dev_priv = dev->dev_private;
1393 pgoff_t page_offset;
1396 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1398 intel_runtime_pm_get(dev_priv);
1400 /* We don't use vmf->pgoff since that has the fake offset */
1401 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1404 ret = i915_mutex_lock_interruptible(dev);
1408 trace_i915_gem_object_fault(obj, page_offset, true, write);
1410 /* Try to flush the object off the GPU first without holding the lock.
1411 * Upon reacquiring the lock, we will perform our sanity checks and then
1412 * repeat the flush holding the lock in the normal manner to catch cases
1413 * where we are gazumped.
1415 ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
1419 /* Access to snoopable pages through the GTT is incoherent. */
1420 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1425 /* Now bind it into the GTT if needed */
1426 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE);
1430 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1434 ret = i915_gem_object_get_fence(obj);
1438 obj->fault_mappable = true;
1440 pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1444 /* Finally, remap it using the new GTT offset */
1445 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1447 i915_gem_object_ggtt_unpin(obj);
1449 mutex_unlock(&dev->struct_mutex);
1453 /* If this -EIO is due to a gpu hang, give the reset code a
1454 * chance to clean up the mess. Otherwise return the proper
1456 if (i915_terminally_wedged(&dev_priv->gpu_error)) {
1457 ret = VM_FAULT_SIGBUS;
1462 * EAGAIN means the gpu is hung and we'll wait for the error
1463 * handler to reset everything when re-faulting in
1464 * i915_mutex_lock_interruptible.
1471 * EBUSY is ok: this just means that another thread
1472 * already did the job.
1474 ret = VM_FAULT_NOPAGE;
1481 ret = VM_FAULT_SIGBUS;
1484 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1485 ret = VM_FAULT_SIGBUS;
1489 intel_runtime_pm_put(dev_priv);
1493 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1495 struct i915_vma *vma;
1498 * Only the global gtt is relevant for gtt memory mappings, so restrict
1499 * list traversal to objects bound into the global address space. Note
1500 * that the active list should be empty, but better safe than sorry.
1502 WARN_ON(!list_empty(&dev_priv->gtt.base.active_list));
1503 list_for_each_entry(vma, &dev_priv->gtt.base.active_list, mm_list)
1504 i915_gem_release_mmap(vma->obj);
1505 list_for_each_entry(vma, &dev_priv->gtt.base.inactive_list, mm_list)
1506 i915_gem_release_mmap(vma->obj);
1510 * i915_gem_release_mmap - remove physical page mappings
1511 * @obj: obj in question
1513 * Preserve the reservation of the mmapping with the DRM core code, but
1514 * relinquish ownership of the pages back to the system.
1516 * It is vital that we remove the page mapping if we have mapped a tiled
1517 * object through the GTT and then lose the fence register due to
1518 * resource pressure. Similarly if the object has been moved out of the
1519 * aperture, than pages mapped into userspace must be revoked. Removing the
1520 * mapping will then trigger a page fault on the next user access, allowing
1521 * fixup by i915_gem_fault().
1524 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1526 if (!obj->fault_mappable)
1529 drm_vma_node_unmap(&obj->base.vma_node,
1530 obj->base.dev->anon_inode->i_mapping);
1531 obj->fault_mappable = false;
1535 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1539 if (INTEL_INFO(dev)->gen >= 4 ||
1540 tiling_mode == I915_TILING_NONE)
1543 /* Previous chips need a power-of-two fence region when tiling */
1544 if (INTEL_INFO(dev)->gen == 3)
1545 gtt_size = 1024*1024;
1547 gtt_size = 512*1024;
1549 while (gtt_size < size)
1556 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1557 * @obj: object to check
1559 * Return the required GTT alignment for an object, taking into account
1560 * potential fence register mapping.
1563 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1564 int tiling_mode, bool fenced)
1567 * Minimum alignment is 4k (GTT page size), but might be greater
1568 * if a fence register is needed for the object.
1570 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1571 tiling_mode == I915_TILING_NONE)
1575 * Previous chips need to be aligned to the size of the smallest
1576 * fence register that can contain the object.
1578 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1581 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1583 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1586 if (drm_vma_node_has_offset(&obj->base.vma_node))
1589 dev_priv->mm.shrinker_no_lock_stealing = true;
1591 ret = drm_gem_create_mmap_offset(&obj->base);
1595 /* Badly fragmented mmap space? The only way we can recover
1596 * space is by destroying unwanted objects. We can't randomly release
1597 * mmap_offsets as userspace expects them to be persistent for the
1598 * lifetime of the objects. The closest we can is to release the
1599 * offsets on purgeable objects by truncating it and marking it purged,
1600 * which prevents userspace from ever using that object again.
1602 i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1603 ret = drm_gem_create_mmap_offset(&obj->base);
1607 i915_gem_shrink_all(dev_priv);
1608 ret = drm_gem_create_mmap_offset(&obj->base);
1610 dev_priv->mm.shrinker_no_lock_stealing = false;
1615 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1617 drm_gem_free_mmap_offset(&obj->base);
1621 i915_gem_mmap_gtt(struct drm_file *file,
1622 struct drm_device *dev,
1626 struct drm_i915_private *dev_priv = dev->dev_private;
1627 struct drm_i915_gem_object *obj;
1630 ret = i915_mutex_lock_interruptible(dev);
1634 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1635 if (&obj->base == NULL) {
1640 if (obj->base.size > dev_priv->gtt.mappable_end) {
1645 if (obj->madv != I915_MADV_WILLNEED) {
1646 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
1651 ret = i915_gem_object_create_mmap_offset(obj);
1655 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
1658 drm_gem_object_unreference(&obj->base);
1660 mutex_unlock(&dev->struct_mutex);
1665 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1667 * @data: GTT mapping ioctl data
1668 * @file: GEM object info
1670 * Simply returns the fake offset to userspace so it can mmap it.
1671 * The mmap call will end up in drm_gem_mmap(), which will set things
1672 * up so we can get faults in the handler above.
1674 * The fault handler will take care of binding the object into the GTT
1675 * (since it may have been evicted to make room for something), allocating
1676 * a fence register, and mapping the appropriate aperture address into
1680 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1681 struct drm_file *file)
1683 struct drm_i915_gem_mmap_gtt *args = data;
1685 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1688 /* Immediately discard the backing storage */
1690 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1692 struct inode *inode;
1694 i915_gem_object_free_mmap_offset(obj);
1696 if (obj->base.filp == NULL)
1699 /* Our goal here is to return as much of the memory as
1700 * is possible back to the system as we are called from OOM.
1701 * To do this we must instruct the shmfs to drop all of its
1702 * backing pages, *now*.
1704 inode = file_inode(obj->base.filp);
1705 shmem_truncate_range(inode, 0, (loff_t)-1);
1707 obj->madv = __I915_MADV_PURGED;
1711 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1713 return obj->madv == I915_MADV_DONTNEED;
1717 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1719 struct sg_page_iter sg_iter;
1722 BUG_ON(obj->madv == __I915_MADV_PURGED);
1724 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1726 /* In the event of a disaster, abandon all caches and
1727 * hope for the best.
1729 WARN_ON(ret != -EIO);
1730 i915_gem_clflush_object(obj, true);
1731 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1734 if (i915_gem_object_needs_bit17_swizzle(obj))
1735 i915_gem_object_save_bit_17_swizzle(obj);
1737 if (obj->madv == I915_MADV_DONTNEED)
1740 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1741 struct page *page = sg_page_iter_page(&sg_iter);
1744 set_page_dirty(page);
1746 if (obj->madv == I915_MADV_WILLNEED)
1747 mark_page_accessed(page);
1749 page_cache_release(page);
1753 sg_free_table(obj->pages);
1758 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1760 const struct drm_i915_gem_object_ops *ops = obj->ops;
1762 if (obj->pages == NULL)
1765 if (obj->pages_pin_count)
1768 BUG_ON(i915_gem_obj_bound_any(obj));
1770 /* ->put_pages might need to allocate memory for the bit17 swizzle
1771 * array, hence protect them from being reaped by removing them from gtt
1773 list_del(&obj->global_list);
1775 ops->put_pages(obj);
1778 if (i915_gem_object_is_purgeable(obj))
1779 i915_gem_object_truncate(obj);
1784 static unsigned long
1785 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
1786 bool purgeable_only)
1788 struct list_head still_bound_list;
1789 struct drm_i915_gem_object *obj, *next;
1790 unsigned long count = 0;
1792 list_for_each_entry_safe(obj, next,
1793 &dev_priv->mm.unbound_list,
1795 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1796 i915_gem_object_put_pages(obj) == 0) {
1797 count += obj->base.size >> PAGE_SHIFT;
1798 if (count >= target)
1804 * As we may completely rewrite the bound list whilst unbinding
1805 * (due to retiring requests) we have to strictly process only
1806 * one element of the list at the time, and recheck the list
1807 * on every iteration.
1809 INIT_LIST_HEAD(&still_bound_list);
1810 while (count < target && !list_empty(&dev_priv->mm.bound_list)) {
1811 struct i915_vma *vma, *v;
1813 obj = list_first_entry(&dev_priv->mm.bound_list,
1814 typeof(*obj), global_list);
1815 list_move_tail(&obj->global_list, &still_bound_list);
1817 if (!i915_gem_object_is_purgeable(obj) && purgeable_only)
1821 * Hold a reference whilst we unbind this object, as we may
1822 * end up waiting for and retiring requests. This might
1823 * release the final reference (held by the active list)
1824 * and result in the object being freed from under us.
1825 * in this object being freed.
1827 * Note 1: Shrinking the bound list is special since only active
1828 * (and hence bound objects) can contain such limbo objects, so
1829 * we don't need special tricks for shrinking the unbound list.
1830 * The only other place where we have to be careful with active
1831 * objects suddenly disappearing due to retiring requests is the
1834 * Note 2: Even though the bound list doesn't hold a reference
1835 * to the object we can safely grab one here: The final object
1836 * unreferencing and the bound_list are both protected by the
1837 * dev->struct_mutex and so we won't ever be able to observe an
1838 * object on the bound_list with a reference count equals 0.
1840 drm_gem_object_reference(&obj->base);
1842 list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link)
1843 if (i915_vma_unbind(vma))
1846 if (i915_gem_object_put_pages(obj) == 0)
1847 count += obj->base.size >> PAGE_SHIFT;
1849 drm_gem_object_unreference(&obj->base);
1851 list_splice(&still_bound_list, &dev_priv->mm.bound_list);
1856 static unsigned long
1857 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1859 return __i915_gem_shrink(dev_priv, target, true);
1862 static unsigned long
1863 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1865 struct drm_i915_gem_object *obj, *next;
1868 i915_gem_evict_everything(dev_priv->dev);
1870 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
1872 if (i915_gem_object_put_pages(obj) == 0)
1873 freed += obj->base.size >> PAGE_SHIFT;
1879 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1881 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1883 struct address_space *mapping;
1884 struct sg_table *st;
1885 struct scatterlist *sg;
1886 struct sg_page_iter sg_iter;
1888 unsigned long last_pfn = 0; /* suppress gcc warning */
1891 /* Assert that the object is not currently in any GPU domain. As it
1892 * wasn't in the GTT, there shouldn't be any way it could have been in
1895 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
1896 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
1898 st = kmalloc(sizeof(*st), GFP_KERNEL);
1902 page_count = obj->base.size / PAGE_SIZE;
1903 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
1908 /* Get the list of pages out of our struct file. They'll be pinned
1909 * at this point until we release them.
1911 * Fail silently without starting the shrinker
1913 mapping = file_inode(obj->base.filp)->i_mapping;
1914 gfp = mapping_gfp_mask(mapping);
1915 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1916 gfp &= ~(__GFP_IO | __GFP_WAIT);
1919 for (i = 0; i < page_count; i++) {
1920 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1922 i915_gem_purge(dev_priv, page_count);
1923 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1926 /* We've tried hard to allocate the memory by reaping
1927 * our own buffer, now let the real VM do its job and
1928 * go down in flames if truly OOM.
1930 gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD);
1931 gfp |= __GFP_IO | __GFP_WAIT;
1933 i915_gem_shrink_all(dev_priv);
1934 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1938 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1939 gfp &= ~(__GFP_IO | __GFP_WAIT);
1941 #ifdef CONFIG_SWIOTLB
1942 if (swiotlb_nr_tbl()) {
1944 sg_set_page(sg, page, PAGE_SIZE, 0);
1949 if (!i || page_to_pfn(page) != last_pfn + 1) {
1953 sg_set_page(sg, page, PAGE_SIZE, 0);
1955 sg->length += PAGE_SIZE;
1957 last_pfn = page_to_pfn(page);
1959 /* Check that the i965g/gm workaround works. */
1960 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
1962 #ifdef CONFIG_SWIOTLB
1963 if (!swiotlb_nr_tbl())
1968 if (i915_gem_object_needs_bit17_swizzle(obj))
1969 i915_gem_object_do_bit_17_swizzle(obj);
1975 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
1976 page_cache_release(sg_page_iter_page(&sg_iter));
1979 return PTR_ERR(page);
1982 /* Ensure that the associated pages are gathered from the backing storage
1983 * and pinned into our object. i915_gem_object_get_pages() may be called
1984 * multiple times before they are released by a single call to
1985 * i915_gem_object_put_pages() - once the pages are no longer referenced
1986 * either as a result of memory pressure (reaping pages under the shrinker)
1987 * or as the object is itself released.
1990 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1992 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1993 const struct drm_i915_gem_object_ops *ops = obj->ops;
1999 if (obj->madv != I915_MADV_WILLNEED) {
2000 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2004 BUG_ON(obj->pages_pin_count);
2006 ret = ops->get_pages(obj);
2010 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2015 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
2016 struct intel_ring_buffer *ring)
2018 struct drm_device *dev = obj->base.dev;
2019 struct drm_i915_private *dev_priv = dev->dev_private;
2020 u32 seqno = intel_ring_get_seqno(ring);
2022 BUG_ON(ring == NULL);
2023 if (obj->ring != ring && obj->last_write_seqno) {
2024 /* Keep the seqno relative to the current ring */
2025 obj->last_write_seqno = seqno;
2029 /* Add a reference if we're newly entering the active list. */
2031 drm_gem_object_reference(&obj->base);
2035 list_move_tail(&obj->ring_list, &ring->active_list);
2037 obj->last_read_seqno = seqno;
2039 if (obj->fenced_gpu_access) {
2040 obj->last_fenced_seqno = seqno;
2042 /* Bump MRU to take account of the delayed flush */
2043 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2044 struct drm_i915_fence_reg *reg;
2046 reg = &dev_priv->fence_regs[obj->fence_reg];
2047 list_move_tail(®->lru_list,
2048 &dev_priv->mm.fence_list);
2053 void i915_vma_move_to_active(struct i915_vma *vma,
2054 struct intel_ring_buffer *ring)
2056 list_move_tail(&vma->mm_list, &vma->vm->active_list);
2057 return i915_gem_object_move_to_active(vma->obj, ring);
2061 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2063 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2064 struct i915_address_space *vm;
2065 struct i915_vma *vma;
2067 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
2068 BUG_ON(!obj->active);
2070 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2071 vma = i915_gem_obj_to_vma(obj, vm);
2072 if (vma && !list_empty(&vma->mm_list))
2073 list_move_tail(&vma->mm_list, &vm->inactive_list);
2076 list_del_init(&obj->ring_list);
2079 obj->last_read_seqno = 0;
2080 obj->last_write_seqno = 0;
2081 obj->base.write_domain = 0;
2083 obj->last_fenced_seqno = 0;
2084 obj->fenced_gpu_access = false;
2087 drm_gem_object_unreference(&obj->base);
2089 WARN_ON(i915_verify_lists(dev));
2093 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2095 struct drm_i915_private *dev_priv = dev->dev_private;
2096 struct intel_ring_buffer *ring;
2099 /* Carefully retire all requests without writing to the rings */
2100 for_each_ring(ring, dev_priv, i) {
2101 ret = intel_ring_idle(ring);
2105 i915_gem_retire_requests(dev);
2107 /* Finally reset hw state */
2108 for_each_ring(ring, dev_priv, i) {
2109 intel_ring_init_seqno(ring, seqno);
2111 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
2112 ring->sync_seqno[j] = 0;
2118 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2120 struct drm_i915_private *dev_priv = dev->dev_private;
2126 /* HWS page needs to be set less than what we
2127 * will inject to ring
2129 ret = i915_gem_init_seqno(dev, seqno - 1);
2133 /* Carefully set the last_seqno value so that wrap
2134 * detection still works
2136 dev_priv->next_seqno = seqno;
2137 dev_priv->last_seqno = seqno - 1;
2138 if (dev_priv->last_seqno == 0)
2139 dev_priv->last_seqno--;
2145 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2147 struct drm_i915_private *dev_priv = dev->dev_private;
2149 /* reserve 0 for non-seqno */
2150 if (dev_priv->next_seqno == 0) {
2151 int ret = i915_gem_init_seqno(dev, 0);
2155 dev_priv->next_seqno = 1;
2158 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2162 int __i915_add_request(struct intel_ring_buffer *ring,
2163 struct drm_file *file,
2164 struct drm_i915_gem_object *obj,
2167 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2168 struct drm_i915_gem_request *request;
2169 u32 request_ring_position, request_start;
2172 request_start = intel_ring_get_tail(ring);
2174 * Emit any outstanding flushes - execbuf can fail to emit the flush
2175 * after having emitted the batchbuffer command. Hence we need to fix
2176 * things up similar to emitting the lazy request. The difference here
2177 * is that the flush _must_ happen before the next request, no matter
2180 ret = intel_ring_flush_all_caches(ring);
2184 request = ring->preallocated_lazy_request;
2185 if (WARN_ON(request == NULL))
2188 /* Record the position of the start of the request so that
2189 * should we detect the updated seqno part-way through the
2190 * GPU processing the request, we never over-estimate the
2191 * position of the head.
2193 request_ring_position = intel_ring_get_tail(ring);
2195 ret = ring->add_request(ring);
2199 request->seqno = intel_ring_get_seqno(ring);
2200 request->ring = ring;
2201 request->head = request_start;
2202 request->tail = request_ring_position;
2204 /* Whilst this request exists, batch_obj will be on the
2205 * active_list, and so will hold the active reference. Only when this
2206 * request is retired will the the batch_obj be moved onto the
2207 * inactive_list and lose its active reference. Hence we do not need
2208 * to explicitly hold another reference here.
2210 request->batch_obj = obj;
2212 /* Hold a reference to the current context so that we can inspect
2213 * it later in case a hangcheck error event fires.
2215 request->ctx = ring->last_context;
2217 i915_gem_context_reference(request->ctx);
2219 request->emitted_jiffies = jiffies;
2220 list_add_tail(&request->list, &ring->request_list);
2221 request->file_priv = NULL;
2224 struct drm_i915_file_private *file_priv = file->driver_priv;
2226 spin_lock(&file_priv->mm.lock);
2227 request->file_priv = file_priv;
2228 list_add_tail(&request->client_list,
2229 &file_priv->mm.request_list);
2230 spin_unlock(&file_priv->mm.lock);
2233 trace_i915_gem_request_add(ring, request->seqno);
2234 ring->outstanding_lazy_seqno = 0;
2235 ring->preallocated_lazy_request = NULL;
2237 if (!dev_priv->ums.mm_suspended) {
2238 i915_queue_hangcheck(ring->dev);
2240 cancel_delayed_work_sync(&dev_priv->mm.idle_work);
2241 queue_delayed_work(dev_priv->wq,
2242 &dev_priv->mm.retire_work,
2243 round_jiffies_up_relative(HZ));
2244 intel_mark_busy(dev_priv->dev);
2248 *out_seqno = request->seqno;
2253 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2255 struct drm_i915_file_private *file_priv = request->file_priv;
2260 spin_lock(&file_priv->mm.lock);
2261 list_del(&request->client_list);
2262 request->file_priv = NULL;
2263 spin_unlock(&file_priv->mm.lock);
2266 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2267 const struct i915_hw_context *ctx)
2269 unsigned long elapsed;
2271 elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2273 if (ctx->hang_stats.banned)
2276 if (elapsed <= DRM_I915_CTX_BAN_PERIOD) {
2277 if (!i915_gem_context_is_default(ctx)) {
2278 DRM_DEBUG("context hanging too fast, banning!\n");
2280 } else if (dev_priv->gpu_error.stop_rings == 0) {
2281 DRM_ERROR("gpu hanging too fast, banning!\n");
2289 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2290 struct i915_hw_context *ctx,
2293 struct i915_ctx_hang_stats *hs;
2298 hs = &ctx->hang_stats;
2301 hs->banned = i915_context_is_banned(dev_priv, ctx);
2303 hs->guilty_ts = get_seconds();
2305 hs->batch_pending++;
2309 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2311 list_del(&request->list);
2312 i915_gem_request_remove_from_client(request);
2315 i915_gem_context_unreference(request->ctx);
2320 struct drm_i915_gem_request *
2321 i915_gem_find_active_request(struct intel_ring_buffer *ring)
2323 struct drm_i915_gem_request *request;
2324 u32 completed_seqno;
2326 completed_seqno = ring->get_seqno(ring, false);
2328 list_for_each_entry(request, &ring->request_list, list) {
2329 if (i915_seqno_passed(completed_seqno, request->seqno))
2338 static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
2339 struct intel_ring_buffer *ring)
2341 struct drm_i915_gem_request *request;
2344 request = i915_gem_find_active_request(ring);
2346 if (request == NULL)
2349 ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2351 i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2353 list_for_each_entry_continue(request, &ring->request_list, list)
2354 i915_set_reset_status(dev_priv, request->ctx, false);
2357 static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2358 struct intel_ring_buffer *ring)
2360 while (!list_empty(&ring->active_list)) {
2361 struct drm_i915_gem_object *obj;
2363 obj = list_first_entry(&ring->active_list,
2364 struct drm_i915_gem_object,
2367 i915_gem_object_move_to_inactive(obj);
2371 * We must free the requests after all the corresponding objects have
2372 * been moved off active lists. Which is the same order as the normal
2373 * retire_requests function does. This is important if object hold
2374 * implicit references on things like e.g. ppgtt address spaces through
2377 while (!list_empty(&ring->request_list)) {
2378 struct drm_i915_gem_request *request;
2380 request = list_first_entry(&ring->request_list,
2381 struct drm_i915_gem_request,
2384 i915_gem_free_request(request);
2388 void i915_gem_restore_fences(struct drm_device *dev)
2390 struct drm_i915_private *dev_priv = dev->dev_private;
2393 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2394 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2397 * Commit delayed tiling changes if we have an object still
2398 * attached to the fence, otherwise just clear the fence.
2401 i915_gem_object_update_fence(reg->obj, reg,
2402 reg->obj->tiling_mode);
2404 i915_gem_write_fence(dev, i, NULL);
2409 void i915_gem_reset(struct drm_device *dev)
2411 struct drm_i915_private *dev_priv = dev->dev_private;
2412 struct intel_ring_buffer *ring;
2416 * Before we free the objects from the requests, we need to inspect
2417 * them for finding the guilty party. As the requests only borrow
2418 * their reference to the objects, the inspection must be done first.
2420 for_each_ring(ring, dev_priv, i)
2421 i915_gem_reset_ring_status(dev_priv, ring);
2423 for_each_ring(ring, dev_priv, i)
2424 i915_gem_reset_ring_cleanup(dev_priv, ring);
2426 i915_gem_cleanup_ringbuffer(dev);
2428 i915_gem_context_reset(dev);
2430 i915_gem_restore_fences(dev);
2434 * This function clears the request list as sequence numbers are passed.
2437 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2441 if (list_empty(&ring->request_list))
2444 WARN_ON(i915_verify_lists(ring->dev));
2446 seqno = ring->get_seqno(ring, true);
2448 /* Move any buffers on the active list that are no longer referenced
2449 * by the ringbuffer to the flushing/inactive lists as appropriate,
2450 * before we free the context associated with the requests.
2452 while (!list_empty(&ring->active_list)) {
2453 struct drm_i915_gem_object *obj;
2455 obj = list_first_entry(&ring->active_list,
2456 struct drm_i915_gem_object,
2459 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2462 i915_gem_object_move_to_inactive(obj);
2466 while (!list_empty(&ring->request_list)) {
2467 struct drm_i915_gem_request *request;
2469 request = list_first_entry(&ring->request_list,
2470 struct drm_i915_gem_request,
2473 if (!i915_seqno_passed(seqno, request->seqno))
2476 trace_i915_gem_request_retire(ring, request->seqno);
2477 /* We know the GPU must have read the request to have
2478 * sent us the seqno + interrupt, so use the position
2479 * of tail of the request to update the last known position
2482 ring->last_retired_head = request->tail;
2484 i915_gem_free_request(request);
2487 if (unlikely(ring->trace_irq_seqno &&
2488 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2489 ring->irq_put(ring);
2490 ring->trace_irq_seqno = 0;
2493 WARN_ON(i915_verify_lists(ring->dev));
2497 i915_gem_retire_requests(struct drm_device *dev)
2499 struct drm_i915_private *dev_priv = dev->dev_private;
2500 struct intel_ring_buffer *ring;
2504 for_each_ring(ring, dev_priv, i) {
2505 i915_gem_retire_requests_ring(ring);
2506 idle &= list_empty(&ring->request_list);
2510 mod_delayed_work(dev_priv->wq,
2511 &dev_priv->mm.idle_work,
2512 msecs_to_jiffies(100));
2518 i915_gem_retire_work_handler(struct work_struct *work)
2520 struct drm_i915_private *dev_priv =
2521 container_of(work, typeof(*dev_priv), mm.retire_work.work);
2522 struct drm_device *dev = dev_priv->dev;
2525 /* Come back later if the device is busy... */
2527 if (mutex_trylock(&dev->struct_mutex)) {
2528 idle = i915_gem_retire_requests(dev);
2529 mutex_unlock(&dev->struct_mutex);
2532 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2533 round_jiffies_up_relative(HZ));
2537 i915_gem_idle_work_handler(struct work_struct *work)
2539 struct drm_i915_private *dev_priv =
2540 container_of(work, typeof(*dev_priv), mm.idle_work.work);
2542 intel_mark_idle(dev_priv->dev);
2546 * Ensures that an object will eventually get non-busy by flushing any required
2547 * write domains, emitting any outstanding lazy request and retiring and
2548 * completed requests.
2551 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2556 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2560 i915_gem_retire_requests_ring(obj->ring);
2567 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2568 * @DRM_IOCTL_ARGS: standard ioctl arguments
2570 * Returns 0 if successful, else an error is returned with the remaining time in
2571 * the timeout parameter.
2572 * -ETIME: object is still busy after timeout
2573 * -ERESTARTSYS: signal interrupted the wait
2574 * -ENONENT: object doesn't exist
2575 * Also possible, but rare:
2576 * -EAGAIN: GPU wedged
2578 * -ENODEV: Internal IRQ fail
2579 * -E?: The add request failed
2581 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2582 * non-zero timeout parameter the wait ioctl will wait for the given number of
2583 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2584 * without holding struct_mutex the object may become re-busied before this
2585 * function completes. A similar but shorter * race condition exists in the busy
2589 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2591 struct drm_i915_private *dev_priv = dev->dev_private;
2592 struct drm_i915_gem_wait *args = data;
2593 struct drm_i915_gem_object *obj;
2594 struct intel_ring_buffer *ring = NULL;
2595 struct timespec timeout_stack, *timeout = NULL;
2596 unsigned reset_counter;
2600 if (args->timeout_ns >= 0) {
2601 timeout_stack = ns_to_timespec(args->timeout_ns);
2602 timeout = &timeout_stack;
2605 ret = i915_mutex_lock_interruptible(dev);
2609 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2610 if (&obj->base == NULL) {
2611 mutex_unlock(&dev->struct_mutex);
2615 /* Need to make sure the object gets inactive eventually. */
2616 ret = i915_gem_object_flush_active(obj);
2621 seqno = obj->last_read_seqno;
2628 /* Do this after OLR check to make sure we make forward progress polling
2629 * on this IOCTL with a 0 timeout (like busy ioctl)
2631 if (!args->timeout_ns) {
2636 drm_gem_object_unreference(&obj->base);
2637 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2638 mutex_unlock(&dev->struct_mutex);
2640 ret = __wait_seqno(ring, seqno, reset_counter, true, timeout, file->driver_priv);
2642 args->timeout_ns = timespec_to_ns(timeout);
2646 drm_gem_object_unreference(&obj->base);
2647 mutex_unlock(&dev->struct_mutex);
2652 * i915_gem_object_sync - sync an object to a ring.
2654 * @obj: object which may be in use on another ring.
2655 * @to: ring we wish to use the object on. May be NULL.
2657 * This code is meant to abstract object synchronization with the GPU.
2658 * Calling with NULL implies synchronizing the object with the CPU
2659 * rather than a particular GPU ring.
2661 * Returns 0 if successful, else propagates up the lower layer error.
2664 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2665 struct intel_ring_buffer *to)
2667 struct intel_ring_buffer *from = obj->ring;
2671 if (from == NULL || to == from)
2674 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2675 return i915_gem_object_wait_rendering(obj, false);
2677 idx = intel_ring_sync_index(from, to);
2679 seqno = obj->last_read_seqno;
2680 if (seqno <= from->sync_seqno[idx])
2683 ret = i915_gem_check_olr(obj->ring, seqno);
2687 trace_i915_gem_ring_sync_to(from, to, seqno);
2688 ret = to->sync_to(to, from, seqno);
2690 /* We use last_read_seqno because sync_to()
2691 * might have just caused seqno wrap under
2694 from->sync_seqno[idx] = obj->last_read_seqno;
2699 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2701 u32 old_write_domain, old_read_domains;
2703 /* Force a pagefault for domain tracking on next user access */
2704 i915_gem_release_mmap(obj);
2706 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2709 /* Wait for any direct GTT access to complete */
2712 old_read_domains = obj->base.read_domains;
2713 old_write_domain = obj->base.write_domain;
2715 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2716 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2718 trace_i915_gem_object_change_domain(obj,
2723 int i915_vma_unbind(struct i915_vma *vma)
2725 struct drm_i915_gem_object *obj = vma->obj;
2726 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2729 if (list_empty(&vma->vma_link))
2732 if (!drm_mm_node_allocated(&vma->node)) {
2733 i915_gem_vma_destroy(vma);
2740 BUG_ON(obj->pages == NULL);
2742 ret = i915_gem_object_finish_gpu(obj);
2745 /* Continue on if we fail due to EIO, the GPU is hung so we
2746 * should be safe and we need to cleanup or else we might
2747 * cause memory corruption through use-after-free.
2750 i915_gem_object_finish_gtt(obj);
2752 /* release the fence reg _after_ flushing */
2753 ret = i915_gem_object_put_fence(obj);
2757 trace_i915_vma_unbind(vma);
2759 vma->unbind_vma(vma);
2761 i915_gem_gtt_finish_object(obj);
2763 list_del_init(&vma->mm_list);
2764 /* Avoid an unnecessary call to unbind on rebind. */
2765 if (i915_is_ggtt(vma->vm))
2766 obj->map_and_fenceable = true;
2768 drm_mm_remove_node(&vma->node);
2769 i915_gem_vma_destroy(vma);
2771 /* Since the unbound list is global, only move to that list if
2772 * no more VMAs exist. */
2773 if (list_empty(&obj->vma_list))
2774 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2776 /* And finally now the object is completely decoupled from this vma,
2777 * we can drop its hold on the backing storage and allow it to be
2778 * reaped by the shrinker.
2780 i915_gem_object_unpin_pages(obj);
2785 int i915_gpu_idle(struct drm_device *dev)
2787 struct drm_i915_private *dev_priv = dev->dev_private;
2788 struct intel_ring_buffer *ring;
2791 /* Flush everything onto the inactive list. */
2792 for_each_ring(ring, dev_priv, i) {
2793 ret = i915_switch_context(ring, NULL, ring->default_context);
2797 ret = intel_ring_idle(ring);
2805 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2806 struct drm_i915_gem_object *obj)
2808 struct drm_i915_private *dev_priv = dev->dev_private;
2810 int fence_pitch_shift;
2812 if (INTEL_INFO(dev)->gen >= 6) {
2813 fence_reg = FENCE_REG_SANDYBRIDGE_0;
2814 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
2816 fence_reg = FENCE_REG_965_0;
2817 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
2820 fence_reg += reg * 8;
2822 /* To w/a incoherency with non-atomic 64-bit register updates,
2823 * we split the 64-bit update into two 32-bit writes. In order
2824 * for a partial fence not to be evaluated between writes, we
2825 * precede the update with write to turn off the fence register,
2826 * and only enable the fence as the last step.
2828 * For extra levels of paranoia, we make sure each step lands
2829 * before applying the next step.
2831 I915_WRITE(fence_reg, 0);
2832 POSTING_READ(fence_reg);
2835 u32 size = i915_gem_obj_ggtt_size(obj);
2838 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
2840 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
2841 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
2842 if (obj->tiling_mode == I915_TILING_Y)
2843 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2844 val |= I965_FENCE_REG_VALID;
2846 I915_WRITE(fence_reg + 4, val >> 32);
2847 POSTING_READ(fence_reg + 4);
2849 I915_WRITE(fence_reg + 0, val);
2850 POSTING_READ(fence_reg);
2852 I915_WRITE(fence_reg + 4, 0);
2853 POSTING_READ(fence_reg + 4);
2857 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2858 struct drm_i915_gem_object *obj)
2860 struct drm_i915_private *dev_priv = dev->dev_private;
2864 u32 size = i915_gem_obj_ggtt_size(obj);
2868 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
2869 (size & -size) != size ||
2870 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
2871 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2872 i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
2874 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2879 /* Note: pitch better be a power of two tile widths */
2880 pitch_val = obj->stride / tile_width;
2881 pitch_val = ffs(pitch_val) - 1;
2883 val = i915_gem_obj_ggtt_offset(obj);
2884 if (obj->tiling_mode == I915_TILING_Y)
2885 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2886 val |= I915_FENCE_SIZE_BITS(size);
2887 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2888 val |= I830_FENCE_REG_VALID;
2893 reg = FENCE_REG_830_0 + reg * 4;
2895 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2897 I915_WRITE(reg, val);
2901 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2902 struct drm_i915_gem_object *obj)
2904 struct drm_i915_private *dev_priv = dev->dev_private;
2908 u32 size = i915_gem_obj_ggtt_size(obj);
2911 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
2912 (size & -size) != size ||
2913 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
2914 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
2915 i915_gem_obj_ggtt_offset(obj), size);
2917 pitch_val = obj->stride / 128;
2918 pitch_val = ffs(pitch_val) - 1;
2920 val = i915_gem_obj_ggtt_offset(obj);
2921 if (obj->tiling_mode == I915_TILING_Y)
2922 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2923 val |= I830_FENCE_SIZE_BITS(size);
2924 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2925 val |= I830_FENCE_REG_VALID;
2929 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2930 POSTING_READ(FENCE_REG_830_0 + reg * 4);
2933 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
2935 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
2938 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2939 struct drm_i915_gem_object *obj)
2941 struct drm_i915_private *dev_priv = dev->dev_private;
2943 /* Ensure that all CPU reads are completed before installing a fence
2944 * and all writes before removing the fence.
2946 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
2949 WARN(obj && (!obj->stride || !obj->tiling_mode),
2950 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
2951 obj->stride, obj->tiling_mode);
2953 switch (INTEL_INFO(dev)->gen) {
2958 case 4: i965_write_fence_reg(dev, reg, obj); break;
2959 case 3: i915_write_fence_reg(dev, reg, obj); break;
2960 case 2: i830_write_fence_reg(dev, reg, obj); break;
2964 /* And similarly be paranoid that no direct access to this region
2965 * is reordered to before the fence is installed.
2967 if (i915_gem_object_needs_mb(obj))
2971 static inline int fence_number(struct drm_i915_private *dev_priv,
2972 struct drm_i915_fence_reg *fence)
2974 return fence - dev_priv->fence_regs;
2977 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2978 struct drm_i915_fence_reg *fence,
2981 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2982 int reg = fence_number(dev_priv, fence);
2984 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
2987 obj->fence_reg = reg;
2989 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2991 obj->fence_reg = I915_FENCE_REG_NONE;
2993 list_del_init(&fence->lru_list);
2995 obj->fence_dirty = false;
2999 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
3001 if (obj->last_fenced_seqno) {
3002 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
3006 obj->last_fenced_seqno = 0;
3009 obj->fenced_gpu_access = false;
3014 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3016 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3017 struct drm_i915_fence_reg *fence;
3020 ret = i915_gem_object_wait_fence(obj);
3024 if (obj->fence_reg == I915_FENCE_REG_NONE)
3027 fence = &dev_priv->fence_regs[obj->fence_reg];
3029 i915_gem_object_fence_lost(obj);
3030 i915_gem_object_update_fence(obj, fence, false);
3035 static struct drm_i915_fence_reg *
3036 i915_find_fence_reg(struct drm_device *dev)
3038 struct drm_i915_private *dev_priv = dev->dev_private;
3039 struct drm_i915_fence_reg *reg, *avail;
3042 /* First try to find a free reg */
3044 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3045 reg = &dev_priv->fence_regs[i];
3049 if (!reg->pin_count)
3056 /* None available, try to steal one or wait for a user to finish */
3057 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3065 /* Wait for completion of pending flips which consume fences */
3066 if (intel_has_pending_fb_unpin(dev))
3067 return ERR_PTR(-EAGAIN);
3069 return ERR_PTR(-EDEADLK);
3073 * i915_gem_object_get_fence - set up fencing for an object
3074 * @obj: object to map through a fence reg
3076 * When mapping objects through the GTT, userspace wants to be able to write
3077 * to them without having to worry about swizzling if the object is tiled.
3078 * This function walks the fence regs looking for a free one for @obj,
3079 * stealing one if it can't find any.
3081 * It then sets up the reg based on the object's properties: address, pitch
3082 * and tiling format.
3084 * For an untiled surface, this removes any existing fence.
3087 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3089 struct drm_device *dev = obj->base.dev;
3090 struct drm_i915_private *dev_priv = dev->dev_private;
3091 bool enable = obj->tiling_mode != I915_TILING_NONE;
3092 struct drm_i915_fence_reg *reg;
3095 /* Have we updated the tiling parameters upon the object and so
3096 * will need to serialise the write to the associated fence register?
3098 if (obj->fence_dirty) {
3099 ret = i915_gem_object_wait_fence(obj);
3104 /* Just update our place in the LRU if our fence is getting reused. */
3105 if (obj->fence_reg != I915_FENCE_REG_NONE) {
3106 reg = &dev_priv->fence_regs[obj->fence_reg];
3107 if (!obj->fence_dirty) {
3108 list_move_tail(®->lru_list,
3109 &dev_priv->mm.fence_list);
3112 } else if (enable) {
3113 reg = i915_find_fence_reg(dev);
3115 return PTR_ERR(reg);
3118 struct drm_i915_gem_object *old = reg->obj;
3120 ret = i915_gem_object_wait_fence(old);
3124 i915_gem_object_fence_lost(old);
3129 i915_gem_object_update_fence(obj, reg, enable);
3134 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
3135 struct drm_mm_node *gtt_space,
3136 unsigned long cache_level)
3138 struct drm_mm_node *other;
3140 /* On non-LLC machines we have to be careful when putting differing
3141 * types of snoopable memory together to avoid the prefetcher
3142 * crossing memory domains and dying.
3147 if (!drm_mm_node_allocated(gtt_space))
3150 if (list_empty(>t_space->node_list))
3153 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3154 if (other->allocated && !other->hole_follows && other->color != cache_level)
3157 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3158 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3164 static void i915_gem_verify_gtt(struct drm_device *dev)
3167 struct drm_i915_private *dev_priv = dev->dev_private;
3168 struct drm_i915_gem_object *obj;
3171 list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) {
3172 if (obj->gtt_space == NULL) {
3173 printk(KERN_ERR "object found on GTT list with no space reserved\n");
3178 if (obj->cache_level != obj->gtt_space->color) {
3179 printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3180 i915_gem_obj_ggtt_offset(obj),
3181 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3183 obj->gtt_space->color);
3188 if (!i915_gem_valid_gtt_space(dev,
3190 obj->cache_level)) {
3191 printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3192 i915_gem_obj_ggtt_offset(obj),
3193 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3205 * Finds free space in the GTT aperture and binds the object there.
3207 static struct i915_vma *
3208 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3209 struct i915_address_space *vm,
3213 struct drm_device *dev = obj->base.dev;
3214 struct drm_i915_private *dev_priv = dev->dev_private;
3215 u32 size, fence_size, fence_alignment, unfenced_alignment;
3217 flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total;
3218 struct i915_vma *vma;
3221 fence_size = i915_gem_get_gtt_size(dev,
3224 fence_alignment = i915_gem_get_gtt_alignment(dev,
3226 obj->tiling_mode, true);
3227 unfenced_alignment =
3228 i915_gem_get_gtt_alignment(dev,
3230 obj->tiling_mode, false);
3233 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3235 if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3236 DRM_DEBUG("Invalid object alignment requested %u\n", alignment);
3237 return ERR_PTR(-EINVAL);
3240 size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3242 /* If the object is bigger than the entire aperture, reject it early
3243 * before evicting everything in a vain attempt to find space.
3245 if (obj->base.size > gtt_max) {
3246 DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n",
3248 flags & PIN_MAPPABLE ? "mappable" : "total",
3250 return ERR_PTR(-E2BIG);
3253 ret = i915_gem_object_get_pages(obj);
3255 return ERR_PTR(ret);
3257 i915_gem_object_pin_pages(obj);
3259 vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
3264 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3266 obj->cache_level, 0, gtt_max,
3267 DRM_MM_SEARCH_DEFAULT);
3269 ret = i915_gem_evict_something(dev, vm, size, alignment,
3270 obj->cache_level, flags);
3276 if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node,
3277 obj->cache_level))) {
3279 goto err_remove_node;
3282 ret = i915_gem_gtt_prepare_object(obj);
3284 goto err_remove_node;
3286 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3287 list_add_tail(&vma->mm_list, &vm->inactive_list);
3289 if (i915_is_ggtt(vm)) {
3290 bool mappable, fenceable;
3292 fenceable = (vma->node.size == fence_size &&
3293 (vma->node.start & (fence_alignment - 1)) == 0);
3295 mappable = (vma->node.start + obj->base.size <=
3296 dev_priv->gtt.mappable_end);
3298 obj->map_and_fenceable = mappable && fenceable;
3301 WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
3303 trace_i915_vma_bind(vma, flags);
3304 vma->bind_vma(vma, obj->cache_level,
3305 flags & (PIN_MAPPABLE | PIN_GLOBAL) ? GLOBAL_BIND : 0);
3307 i915_gem_verify_gtt(dev);
3311 drm_mm_remove_node(&vma->node);
3313 i915_gem_vma_destroy(vma);
3316 i915_gem_object_unpin_pages(obj);
3321 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3324 /* If we don't have a page list set up, then we're not pinned
3325 * to GPU, and we can ignore the cache flush because it'll happen
3326 * again at bind time.
3328 if (obj->pages == NULL)
3332 * Stolen memory is always coherent with the GPU as it is explicitly
3333 * marked as wc by the system, or the system is cache-coherent.
3338 /* If the GPU is snooping the contents of the CPU cache,
3339 * we do not need to manually clear the CPU cache lines. However,
3340 * the caches are only snooped when the render cache is
3341 * flushed/invalidated. As we always have to emit invalidations
3342 * and flushes when moving into and out of the RENDER domain, correct
3343 * snooping behaviour occurs naturally as the result of our domain
3346 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
3349 trace_i915_gem_object_clflush(obj);
3350 drm_clflush_sg(obj->pages);
3355 /** Flushes the GTT write domain for the object if it's dirty. */
3357 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3359 uint32_t old_write_domain;
3361 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3364 /* No actual flushing is required for the GTT write domain. Writes
3365 * to it immediately go to main memory as far as we know, so there's
3366 * no chipset flush. It also doesn't land in render cache.
3368 * However, we do have to enforce the order so that all writes through
3369 * the GTT land before any writes to the device, such as updates to
3374 old_write_domain = obj->base.write_domain;
3375 obj->base.write_domain = 0;
3377 trace_i915_gem_object_change_domain(obj,
3378 obj->base.read_domains,
3382 /** Flushes the CPU write domain for the object if it's dirty. */
3384 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
3387 uint32_t old_write_domain;
3389 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3392 if (i915_gem_clflush_object(obj, force))
3393 i915_gem_chipset_flush(obj->base.dev);
3395 old_write_domain = obj->base.write_domain;
3396 obj->base.write_domain = 0;
3398 trace_i915_gem_object_change_domain(obj,
3399 obj->base.read_domains,
3404 * Moves a single object to the GTT read, and possibly write domain.
3406 * This function returns when the move is complete, including waiting on
3410 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3412 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3413 uint32_t old_write_domain, old_read_domains;
3416 /* Not valid to be called on unbound objects. */
3417 if (!i915_gem_obj_bound_any(obj))
3420 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3423 ret = i915_gem_object_wait_rendering(obj, !write);
3427 i915_gem_object_flush_cpu_write_domain(obj, false);
3429 /* Serialise direct access to this object with the barriers for
3430 * coherent writes from the GPU, by effectively invalidating the
3431 * GTT domain upon first access.
3433 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3436 old_write_domain = obj->base.write_domain;
3437 old_read_domains = obj->base.read_domains;
3439 /* It should now be out of any other write domains, and we can update
3440 * the domain values for our changes.
3442 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3443 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3445 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3446 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3450 trace_i915_gem_object_change_domain(obj,
3454 /* And bump the LRU for this access */
3455 if (i915_gem_object_is_inactive(obj)) {
3456 struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
3458 list_move_tail(&vma->mm_list,
3459 &dev_priv->gtt.base.inactive_list);
3466 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3467 enum i915_cache_level cache_level)
3469 struct drm_device *dev = obj->base.dev;
3470 struct i915_vma *vma, *next;
3473 if (obj->cache_level == cache_level)
3476 if (i915_gem_obj_is_pinned(obj)) {
3477 DRM_DEBUG("can not change the cache level of pinned objects\n");
3481 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
3482 if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) {
3483 ret = i915_vma_unbind(vma);
3489 if (i915_gem_obj_bound_any(obj)) {
3490 ret = i915_gem_object_finish_gpu(obj);
3494 i915_gem_object_finish_gtt(obj);
3496 /* Before SandyBridge, you could not use tiling or fence
3497 * registers with snooped memory, so relinquish any fences
3498 * currently pointing to our region in the aperture.
3500 if (INTEL_INFO(dev)->gen < 6) {
3501 ret = i915_gem_object_put_fence(obj);
3506 list_for_each_entry(vma, &obj->vma_list, vma_link)
3507 if (drm_mm_node_allocated(&vma->node))
3508 vma->bind_vma(vma, cache_level,
3509 obj->has_global_gtt_mapping ? GLOBAL_BIND : 0);
3512 list_for_each_entry(vma, &obj->vma_list, vma_link)
3513 vma->node.color = cache_level;
3514 obj->cache_level = cache_level;
3516 if (cpu_write_needs_clflush(obj)) {
3517 u32 old_read_domains, old_write_domain;
3519 /* If we're coming from LLC cached, then we haven't
3520 * actually been tracking whether the data is in the
3521 * CPU cache or not, since we only allow one bit set
3522 * in obj->write_domain and have been skipping the clflushes.
3523 * Just set it to the CPU cache for now.
3525 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3527 old_read_domains = obj->base.read_domains;
3528 old_write_domain = obj->base.write_domain;
3530 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3531 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3533 trace_i915_gem_object_change_domain(obj,
3538 i915_gem_verify_gtt(dev);
3542 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3543 struct drm_file *file)
3545 struct drm_i915_gem_caching *args = data;
3546 struct drm_i915_gem_object *obj;
3549 ret = i915_mutex_lock_interruptible(dev);
3553 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3554 if (&obj->base == NULL) {
3559 switch (obj->cache_level) {
3560 case I915_CACHE_LLC:
3561 case I915_CACHE_L3_LLC:
3562 args->caching = I915_CACHING_CACHED;
3566 args->caching = I915_CACHING_DISPLAY;
3570 args->caching = I915_CACHING_NONE;
3574 drm_gem_object_unreference(&obj->base);
3576 mutex_unlock(&dev->struct_mutex);
3580 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3581 struct drm_file *file)
3583 struct drm_i915_gem_caching *args = data;
3584 struct drm_i915_gem_object *obj;
3585 enum i915_cache_level level;
3588 switch (args->caching) {
3589 case I915_CACHING_NONE:
3590 level = I915_CACHE_NONE;
3592 case I915_CACHING_CACHED:
3593 level = I915_CACHE_LLC;
3595 case I915_CACHING_DISPLAY:
3596 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3602 ret = i915_mutex_lock_interruptible(dev);
3606 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3607 if (&obj->base == NULL) {
3612 ret = i915_gem_object_set_cache_level(obj, level);
3614 drm_gem_object_unreference(&obj->base);
3616 mutex_unlock(&dev->struct_mutex);
3620 static bool is_pin_display(struct drm_i915_gem_object *obj)
3622 /* There are 3 sources that pin objects:
3623 * 1. The display engine (scanouts, sprites, cursors);
3624 * 2. Reservations for execbuffer;
3627 * We can ignore reservations as we hold the struct_mutex and
3628 * are only called outside of the reservation path. The user
3629 * can only increment pin_count once, and so if after
3630 * subtracting the potential reference by the user, any pin_count
3631 * remains, it must be due to another use by the display engine.
3633 return i915_gem_obj_to_ggtt(obj)->pin_count - !!obj->user_pin_count;
3637 * Prepare buffer for display plane (scanout, cursors, etc).
3638 * Can be called from an uninterruptible phase (modesetting) and allows
3639 * any flushes to be pipelined (for pageflips).
3642 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3644 struct intel_ring_buffer *pipelined)
3646 u32 old_read_domains, old_write_domain;
3649 if (pipelined != obj->ring) {
3650 ret = i915_gem_object_sync(obj, pipelined);
3655 /* Mark the pin_display early so that we account for the
3656 * display coherency whilst setting up the cache domains.
3658 obj->pin_display = true;
3660 /* The display engine is not coherent with the LLC cache on gen6. As
3661 * a result, we make sure that the pinning that is about to occur is
3662 * done with uncached PTEs. This is lowest common denominator for all
3665 * However for gen6+, we could do better by using the GFDT bit instead
3666 * of uncaching, which would allow us to flush all the LLC-cached data
3667 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3669 ret = i915_gem_object_set_cache_level(obj,
3670 HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
3672 goto err_unpin_display;
3674 /* As the user may map the buffer once pinned in the display plane
3675 * (e.g. libkms for the bootup splash), we have to ensure that we
3676 * always use map_and_fenceable for all scanout buffers.
3678 ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE);
3680 goto err_unpin_display;
3682 i915_gem_object_flush_cpu_write_domain(obj, true);
3684 old_write_domain = obj->base.write_domain;
3685 old_read_domains = obj->base.read_domains;
3687 /* It should now be out of any other write domains, and we can update
3688 * the domain values for our changes.
3690 obj->base.write_domain = 0;
3691 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3693 trace_i915_gem_object_change_domain(obj,
3700 obj->pin_display = is_pin_display(obj);
3705 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
3707 i915_gem_object_ggtt_unpin(obj);
3708 obj->pin_display = is_pin_display(obj);
3712 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3716 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3719 ret = i915_gem_object_wait_rendering(obj, false);
3723 /* Ensure that we invalidate the GPU's caches and TLBs. */
3724 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3729 * Moves a single object to the CPU read, and possibly write domain.
3731 * This function returns when the move is complete, including waiting on
3735 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3737 uint32_t old_write_domain, old_read_domains;
3740 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3743 ret = i915_gem_object_wait_rendering(obj, !write);
3747 i915_gem_object_flush_gtt_write_domain(obj);
3749 old_write_domain = obj->base.write_domain;
3750 old_read_domains = obj->base.read_domains;
3752 /* Flush the CPU cache if it's still invalid. */
3753 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3754 i915_gem_clflush_object(obj, false);
3756 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3759 /* It should now be out of any other write domains, and we can update
3760 * the domain values for our changes.
3762 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3764 /* If we're writing through the CPU, then the GPU read domains will
3765 * need to be invalidated at next use.
3768 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3769 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3772 trace_i915_gem_object_change_domain(obj,
3779 /* Throttle our rendering by waiting until the ring has completed our requests
3780 * emitted over 20 msec ago.
3782 * Note that if we were to use the current jiffies each time around the loop,
3783 * we wouldn't escape the function with any frames outstanding if the time to
3784 * render a frame was over 20ms.
3786 * This should get us reasonable parallelism between CPU and GPU but also
3787 * relatively low latency when blocking on a particular request to finish.
3790 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3792 struct drm_i915_private *dev_priv = dev->dev_private;
3793 struct drm_i915_file_private *file_priv = file->driver_priv;
3794 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3795 struct drm_i915_gem_request *request;
3796 struct intel_ring_buffer *ring = NULL;
3797 unsigned reset_counter;
3801 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
3805 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
3809 spin_lock(&file_priv->mm.lock);
3810 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3811 if (time_after_eq(request->emitted_jiffies, recent_enough))
3814 ring = request->ring;
3815 seqno = request->seqno;
3817 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3818 spin_unlock(&file_priv->mm.lock);
3823 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, NULL);
3825 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3831 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3832 struct i915_address_space *vm,
3836 struct i915_vma *vma;
3839 if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
3842 vma = i915_gem_obj_to_vma(obj, vm);
3844 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3848 vma->node.start & (alignment - 1)) ||
3849 (flags & PIN_MAPPABLE && !obj->map_and_fenceable)) {
3850 WARN(vma->pin_count,
3851 "bo is already pinned with incorrect alignment:"
3852 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
3853 " obj->map_and_fenceable=%d\n",
3854 i915_gem_obj_offset(obj, vm), alignment,
3855 flags & PIN_MAPPABLE,
3856 obj->map_and_fenceable);
3857 ret = i915_vma_unbind(vma);
3865 if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
3866 vma = i915_gem_object_bind_to_vm(obj, vm, alignment, flags);
3868 return PTR_ERR(vma);
3871 if (flags & PIN_GLOBAL && !obj->has_global_gtt_mapping)
3872 vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
3875 if (flags & PIN_MAPPABLE)
3876 obj->pin_mappable |= true;
3882 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
3884 struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
3887 BUG_ON(vma->pin_count == 0);
3888 BUG_ON(!i915_gem_obj_ggtt_bound(obj));
3890 if (--vma->pin_count == 0)
3891 obj->pin_mappable = false;
3895 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3896 struct drm_file *file)
3898 struct drm_i915_gem_pin *args = data;
3899 struct drm_i915_gem_object *obj;
3902 if (INTEL_INFO(dev)->gen >= 6)
3905 ret = i915_mutex_lock_interruptible(dev);
3909 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3910 if (&obj->base == NULL) {
3915 if (obj->madv != I915_MADV_WILLNEED) {
3916 DRM_DEBUG("Attempting to pin a purgeable buffer\n");
3921 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3922 DRM_DEBUG("Already pinned in i915_gem_pin_ioctl(): %d\n",
3928 if (obj->user_pin_count == ULONG_MAX) {
3933 if (obj->user_pin_count == 0) {
3934 ret = i915_gem_obj_ggtt_pin(obj, args->alignment, PIN_MAPPABLE);
3939 obj->user_pin_count++;
3940 obj->pin_filp = file;
3942 args->offset = i915_gem_obj_ggtt_offset(obj);
3944 drm_gem_object_unreference(&obj->base);
3946 mutex_unlock(&dev->struct_mutex);
3951 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3952 struct drm_file *file)
3954 struct drm_i915_gem_pin *args = data;
3955 struct drm_i915_gem_object *obj;
3958 ret = i915_mutex_lock_interruptible(dev);
3962 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3963 if (&obj->base == NULL) {
3968 if (obj->pin_filp != file) {
3969 DRM_DEBUG("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3974 obj->user_pin_count--;
3975 if (obj->user_pin_count == 0) {
3976 obj->pin_filp = NULL;
3977 i915_gem_object_ggtt_unpin(obj);
3981 drm_gem_object_unreference(&obj->base);
3983 mutex_unlock(&dev->struct_mutex);
3988 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3989 struct drm_file *file)
3991 struct drm_i915_gem_busy *args = data;
3992 struct drm_i915_gem_object *obj;
3995 ret = i915_mutex_lock_interruptible(dev);
3999 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4000 if (&obj->base == NULL) {
4005 /* Count all active objects as busy, even if they are currently not used
4006 * by the gpu. Users of this interface expect objects to eventually
4007 * become non-busy without any further actions, therefore emit any
4008 * necessary flushes here.
4010 ret = i915_gem_object_flush_active(obj);
4012 args->busy = obj->active;
4014 BUILD_BUG_ON(I915_NUM_RINGS > 16);
4015 args->busy |= intel_ring_flag(obj->ring) << 16;
4018 drm_gem_object_unreference(&obj->base);
4020 mutex_unlock(&dev->struct_mutex);
4025 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4026 struct drm_file *file_priv)
4028 return i915_gem_ring_throttle(dev, file_priv);
4032 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4033 struct drm_file *file_priv)
4035 struct drm_i915_gem_madvise *args = data;
4036 struct drm_i915_gem_object *obj;
4039 switch (args->madv) {
4040 case I915_MADV_DONTNEED:
4041 case I915_MADV_WILLNEED:
4047 ret = i915_mutex_lock_interruptible(dev);
4051 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4052 if (&obj->base == NULL) {
4057 if (i915_gem_obj_is_pinned(obj)) {
4062 if (obj->madv != __I915_MADV_PURGED)
4063 obj->madv = args->madv;
4065 /* if the object is no longer attached, discard its backing storage */
4066 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
4067 i915_gem_object_truncate(obj);
4069 args->retained = obj->madv != __I915_MADV_PURGED;
4072 drm_gem_object_unreference(&obj->base);
4074 mutex_unlock(&dev->struct_mutex);
4078 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4079 const struct drm_i915_gem_object_ops *ops)
4081 INIT_LIST_HEAD(&obj->global_list);
4082 INIT_LIST_HEAD(&obj->ring_list);
4083 INIT_LIST_HEAD(&obj->obj_exec_link);
4084 INIT_LIST_HEAD(&obj->vma_list);
4088 obj->fence_reg = I915_FENCE_REG_NONE;
4089 obj->madv = I915_MADV_WILLNEED;
4090 /* Avoid an unnecessary call to unbind on the first bind. */
4091 obj->map_and_fenceable = true;
4093 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4096 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4097 .get_pages = i915_gem_object_get_pages_gtt,
4098 .put_pages = i915_gem_object_put_pages_gtt,
4101 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4104 struct drm_i915_gem_object *obj;
4105 struct address_space *mapping;
4108 obj = i915_gem_object_alloc(dev);
4112 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4113 i915_gem_object_free(obj);
4117 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4118 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4119 /* 965gm cannot relocate objects above 4GiB. */
4120 mask &= ~__GFP_HIGHMEM;
4121 mask |= __GFP_DMA32;
4124 mapping = file_inode(obj->base.filp)->i_mapping;
4125 mapping_set_gfp_mask(mapping, mask);
4127 i915_gem_object_init(obj, &i915_gem_object_ops);
4129 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4130 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4133 /* On some devices, we can have the GPU use the LLC (the CPU
4134 * cache) for about a 10% performance improvement
4135 * compared to uncached. Graphics requests other than
4136 * display scanout are coherent with the CPU in
4137 * accessing this cache. This means in this mode we
4138 * don't need to clflush on the CPU side, and on the
4139 * GPU side we only need to flush internal caches to
4140 * get data visible to the CPU.
4142 * However, we maintain the display planes as UC, and so
4143 * need to rebind when first used as such.
4145 obj->cache_level = I915_CACHE_LLC;
4147 obj->cache_level = I915_CACHE_NONE;
4149 trace_i915_gem_object_create(obj);
4154 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4156 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4157 struct drm_device *dev = obj->base.dev;
4158 struct drm_i915_private *dev_priv = dev->dev_private;
4159 struct i915_vma *vma, *next;
4161 intel_runtime_pm_get(dev_priv);
4163 trace_i915_gem_object_destroy(obj);
4166 i915_gem_detach_phys_object(dev, obj);
4168 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4172 ret = i915_vma_unbind(vma);
4173 if (WARN_ON(ret == -ERESTARTSYS)) {
4174 bool was_interruptible;
4176 was_interruptible = dev_priv->mm.interruptible;
4177 dev_priv->mm.interruptible = false;
4179 WARN_ON(i915_vma_unbind(vma));
4181 dev_priv->mm.interruptible = was_interruptible;
4185 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4186 * before progressing. */
4188 i915_gem_object_unpin_pages(obj);
4190 if (WARN_ON(obj->pages_pin_count))
4191 obj->pages_pin_count = 0;
4192 i915_gem_object_put_pages(obj);
4193 i915_gem_object_free_mmap_offset(obj);
4194 i915_gem_object_release_stolen(obj);
4198 if (obj->base.import_attach)
4199 drm_prime_gem_destroy(&obj->base, NULL);
4201 drm_gem_object_release(&obj->base);
4202 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4205 i915_gem_object_free(obj);
4207 intel_runtime_pm_put(dev_priv);
4210 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4211 struct i915_address_space *vm)
4213 struct i915_vma *vma;
4214 list_for_each_entry(vma, &obj->vma_list, vma_link)
4221 void i915_gem_vma_destroy(struct i915_vma *vma)
4223 WARN_ON(vma->node.allocated);
4225 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4226 if (!list_empty(&vma->exec_list))
4229 list_del(&vma->vma_link);
4235 i915_gem_suspend(struct drm_device *dev)
4237 struct drm_i915_private *dev_priv = dev->dev_private;
4240 mutex_lock(&dev->struct_mutex);
4241 if (dev_priv->ums.mm_suspended)
4244 ret = i915_gpu_idle(dev);
4248 i915_gem_retire_requests(dev);
4250 /* Under UMS, be paranoid and evict. */
4251 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4252 i915_gem_evict_everything(dev);
4254 i915_kernel_lost_context(dev);
4255 i915_gem_cleanup_ringbuffer(dev);
4257 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4258 * We need to replace this with a semaphore, or something.
4259 * And not confound ums.mm_suspended!
4261 dev_priv->ums.mm_suspended = !drm_core_check_feature(dev,
4263 mutex_unlock(&dev->struct_mutex);
4265 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4266 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4267 cancel_delayed_work_sync(&dev_priv->mm.idle_work);
4272 mutex_unlock(&dev->struct_mutex);
4276 int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice)
4278 struct drm_device *dev = ring->dev;
4279 struct drm_i915_private *dev_priv = dev->dev_private;
4280 u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4281 u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4284 if (!HAS_L3_DPF(dev) || !remap_info)
4287 ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
4292 * Note: We do not worry about the concurrent register cacheline hang
4293 * here because no other code should access these registers other than
4294 * at initialization time.
4296 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4297 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4298 intel_ring_emit(ring, reg_base + i);
4299 intel_ring_emit(ring, remap_info[i/4]);
4302 intel_ring_advance(ring);
4307 void i915_gem_init_swizzling(struct drm_device *dev)
4309 struct drm_i915_private *dev_priv = dev->dev_private;
4311 if (INTEL_INFO(dev)->gen < 5 ||
4312 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4315 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4316 DISP_TILE_SURFACE_SWIZZLING);
4321 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4323 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4324 else if (IS_GEN7(dev))
4325 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4326 else if (IS_GEN8(dev))
4327 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4333 intel_enable_blt(struct drm_device *dev)
4338 /* The blitter was dysfunctional on early prototypes */
4339 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4340 DRM_INFO("BLT not supported on this pre-production hardware;"
4341 " graphics performance will be degraded.\n");
4348 static int i915_gem_init_rings(struct drm_device *dev)
4350 struct drm_i915_private *dev_priv = dev->dev_private;
4353 ret = intel_init_render_ring_buffer(dev);
4358 ret = intel_init_bsd_ring_buffer(dev);
4360 goto cleanup_render_ring;
4363 if (intel_enable_blt(dev)) {
4364 ret = intel_init_blt_ring_buffer(dev);
4366 goto cleanup_bsd_ring;
4369 if (HAS_VEBOX(dev)) {
4370 ret = intel_init_vebox_ring_buffer(dev);
4372 goto cleanup_blt_ring;
4376 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4378 goto cleanup_vebox_ring;
4383 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4385 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4387 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4388 cleanup_render_ring:
4389 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4395 i915_gem_init_hw(struct drm_device *dev)
4397 struct drm_i915_private *dev_priv = dev->dev_private;
4400 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4403 if (dev_priv->ellc_size)
4404 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4406 if (IS_HASWELL(dev))
4407 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4408 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4410 if (HAS_PCH_NOP(dev)) {
4411 if (IS_IVYBRIDGE(dev)) {
4412 u32 temp = I915_READ(GEN7_MSG_CTL);
4413 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4414 I915_WRITE(GEN7_MSG_CTL, temp);
4415 } else if (INTEL_INFO(dev)->gen >= 7) {
4416 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4417 temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4418 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4422 i915_gem_init_swizzling(dev);
4424 ret = i915_gem_init_rings(dev);
4428 for (i = 0; i < NUM_L3_SLICES(dev); i++)
4429 i915_gem_l3_remap(&dev_priv->ring[RCS], i);
4432 * XXX: Contexts should only be initialized once. Doing a switch to the
4433 * default context switch however is something we'd like to do after
4434 * reset or thaw (the latter may not actually be necessary for HW, but
4435 * goes with our code better). Context switching requires rings (for
4436 * the do_switch), but before enabling PPGTT. So don't move this.
4438 ret = i915_gem_context_enable(dev_priv);
4440 DRM_ERROR("Context enable failed %d\n", ret);
4447 i915_gem_cleanup_ringbuffer(dev);
4451 int i915_gem_init(struct drm_device *dev)
4453 struct drm_i915_private *dev_priv = dev->dev_private;
4456 mutex_lock(&dev->struct_mutex);
4458 if (IS_VALLEYVIEW(dev)) {
4459 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4460 I915_WRITE(VLV_GTLC_WAKE_CTRL, 1);
4461 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10))
4462 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4465 i915_gem_init_global_gtt(dev);
4467 ret = i915_gem_context_init(dev);
4469 mutex_unlock(&dev->struct_mutex);
4473 ret = i915_gem_init_hw(dev);
4474 mutex_unlock(&dev->struct_mutex);
4476 WARN_ON(dev_priv->mm.aliasing_ppgtt);
4477 i915_gem_context_fini(dev);
4478 drm_mm_takedown(&dev_priv->gtt.base.mm);
4482 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4483 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4484 dev_priv->dri1.allow_batchbuffer = 1;
4489 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4491 struct drm_i915_private *dev_priv = dev->dev_private;
4492 struct intel_ring_buffer *ring;
4495 for_each_ring(ring, dev_priv, i)
4496 intel_cleanup_ring_buffer(ring);
4500 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4501 struct drm_file *file_priv)
4503 struct drm_i915_private *dev_priv = dev->dev_private;
4506 if (drm_core_check_feature(dev, DRIVER_MODESET))
4509 if (i915_reset_in_progress(&dev_priv->gpu_error)) {
4510 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4511 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
4514 mutex_lock(&dev->struct_mutex);
4515 dev_priv->ums.mm_suspended = 0;
4517 ret = i915_gem_init_hw(dev);
4519 mutex_unlock(&dev->struct_mutex);
4523 BUG_ON(!list_empty(&dev_priv->gtt.base.active_list));
4524 mutex_unlock(&dev->struct_mutex);
4526 ret = drm_irq_install(dev);
4528 goto cleanup_ringbuffer;
4533 mutex_lock(&dev->struct_mutex);
4534 i915_gem_cleanup_ringbuffer(dev);
4535 dev_priv->ums.mm_suspended = 1;
4536 mutex_unlock(&dev->struct_mutex);
4542 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4543 struct drm_file *file_priv)
4545 if (drm_core_check_feature(dev, DRIVER_MODESET))
4548 drm_irq_uninstall(dev);
4550 return i915_gem_suspend(dev);
4554 i915_gem_lastclose(struct drm_device *dev)
4558 if (drm_core_check_feature(dev, DRIVER_MODESET))
4561 ret = i915_gem_suspend(dev);
4563 DRM_ERROR("failed to idle hardware: %d\n", ret);
4567 init_ring_lists(struct intel_ring_buffer *ring)
4569 INIT_LIST_HEAD(&ring->active_list);
4570 INIT_LIST_HEAD(&ring->request_list);
4573 void i915_init_vm(struct drm_i915_private *dev_priv,
4574 struct i915_address_space *vm)
4576 if (!i915_is_ggtt(vm))
4577 drm_mm_init(&vm->mm, vm->start, vm->total);
4578 vm->dev = dev_priv->dev;
4579 INIT_LIST_HEAD(&vm->active_list);
4580 INIT_LIST_HEAD(&vm->inactive_list);
4581 INIT_LIST_HEAD(&vm->global_link);
4582 list_add_tail(&vm->global_link, &dev_priv->vm_list);
4586 i915_gem_load(struct drm_device *dev)
4588 struct drm_i915_private *dev_priv = dev->dev_private;
4592 kmem_cache_create("i915_gem_object",
4593 sizeof(struct drm_i915_gem_object), 0,
4597 INIT_LIST_HEAD(&dev_priv->vm_list);
4598 i915_init_vm(dev_priv, &dev_priv->gtt.base);
4600 INIT_LIST_HEAD(&dev_priv->context_list);
4601 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4602 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4603 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4604 for (i = 0; i < I915_NUM_RINGS; i++)
4605 init_ring_lists(&dev_priv->ring[i]);
4606 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4607 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4608 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4609 i915_gem_retire_work_handler);
4610 INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
4611 i915_gem_idle_work_handler);
4612 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4614 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4616 I915_WRITE(MI_ARB_STATE,
4617 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4620 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4622 /* Old X drivers will take 0-2 for front, back, depth buffers */
4623 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4624 dev_priv->fence_reg_start = 3;
4626 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4627 dev_priv->num_fence_regs = 32;
4628 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4629 dev_priv->num_fence_regs = 16;
4631 dev_priv->num_fence_regs = 8;
4633 /* Initialize fence registers to zero */
4634 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4635 i915_gem_restore_fences(dev);
4637 i915_gem_detect_bit_6_swizzle(dev);
4638 init_waitqueue_head(&dev_priv->pending_flip_queue);
4640 dev_priv->mm.interruptible = true;
4642 dev_priv->mm.inactive_shrinker.scan_objects = i915_gem_inactive_scan;
4643 dev_priv->mm.inactive_shrinker.count_objects = i915_gem_inactive_count;
4644 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4645 register_shrinker(&dev_priv->mm.inactive_shrinker);
4649 * Create a physically contiguous memory object for this object
4650 * e.g. for cursor + overlay regs
4652 static int i915_gem_init_phys_object(struct drm_device *dev,
4653 int id, int size, int align)
4655 struct drm_i915_private *dev_priv = dev->dev_private;
4656 struct drm_i915_gem_phys_object *phys_obj;
4659 if (dev_priv->mm.phys_objs[id - 1] || !size)
4662 phys_obj = kzalloc(sizeof(*phys_obj), GFP_KERNEL);
4668 phys_obj->handle = drm_pci_alloc(dev, size, align);
4669 if (!phys_obj->handle) {
4674 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4677 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4685 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4687 struct drm_i915_private *dev_priv = dev->dev_private;
4688 struct drm_i915_gem_phys_object *phys_obj;
4690 if (!dev_priv->mm.phys_objs[id - 1])
4693 phys_obj = dev_priv->mm.phys_objs[id - 1];
4694 if (phys_obj->cur_obj) {
4695 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4699 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4701 drm_pci_free(dev, phys_obj->handle);
4703 dev_priv->mm.phys_objs[id - 1] = NULL;
4706 void i915_gem_free_all_phys_object(struct drm_device *dev)
4710 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4711 i915_gem_free_phys_object(dev, i);
4714 void i915_gem_detach_phys_object(struct drm_device *dev,
4715 struct drm_i915_gem_object *obj)
4717 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4724 vaddr = obj->phys_obj->handle->vaddr;
4726 page_count = obj->base.size / PAGE_SIZE;
4727 for (i = 0; i < page_count; i++) {
4728 struct page *page = shmem_read_mapping_page(mapping, i);
4729 if (!IS_ERR(page)) {
4730 char *dst = kmap_atomic(page);
4731 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4734 drm_clflush_pages(&page, 1);
4736 set_page_dirty(page);
4737 mark_page_accessed(page);
4738 page_cache_release(page);
4741 i915_gem_chipset_flush(dev);
4743 obj->phys_obj->cur_obj = NULL;
4744 obj->phys_obj = NULL;
4748 i915_gem_attach_phys_object(struct drm_device *dev,
4749 struct drm_i915_gem_object *obj,
4753 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4754 struct drm_i915_private *dev_priv = dev->dev_private;
4759 if (id > I915_MAX_PHYS_OBJECT)
4762 if (obj->phys_obj) {
4763 if (obj->phys_obj->id == id)
4765 i915_gem_detach_phys_object(dev, obj);
4768 /* create a new object */
4769 if (!dev_priv->mm.phys_objs[id - 1]) {
4770 ret = i915_gem_init_phys_object(dev, id,
4771 obj->base.size, align);
4773 DRM_ERROR("failed to init phys object %d size: %zu\n",
4774 id, obj->base.size);
4779 /* bind to the object */
4780 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4781 obj->phys_obj->cur_obj = obj;
4783 page_count = obj->base.size / PAGE_SIZE;
4785 for (i = 0; i < page_count; i++) {
4789 page = shmem_read_mapping_page(mapping, i);
4791 return PTR_ERR(page);
4793 src = kmap_atomic(page);
4794 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4795 memcpy(dst, src, PAGE_SIZE);
4798 mark_page_accessed(page);
4799 page_cache_release(page);
4806 i915_gem_phys_pwrite(struct drm_device *dev,
4807 struct drm_i915_gem_object *obj,
4808 struct drm_i915_gem_pwrite *args,
4809 struct drm_file *file_priv)
4811 void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4812 char __user *user_data = to_user_ptr(args->data_ptr);
4814 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4815 unsigned long unwritten;
4817 /* The physical object once assigned is fixed for the lifetime
4818 * of the obj, so we can safely drop the lock and continue
4821 mutex_unlock(&dev->struct_mutex);
4822 unwritten = copy_from_user(vaddr, user_data, args->size);
4823 mutex_lock(&dev->struct_mutex);
4828 i915_gem_chipset_flush(dev);
4832 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4834 struct drm_i915_file_private *file_priv = file->driver_priv;
4836 cancel_delayed_work_sync(&file_priv->mm.idle_work);
4838 /* Clean up our request list when the client is going away, so that
4839 * later retire_requests won't dereference our soon-to-be-gone
4842 spin_lock(&file_priv->mm.lock);
4843 while (!list_empty(&file_priv->mm.request_list)) {
4844 struct drm_i915_gem_request *request;
4846 request = list_first_entry(&file_priv->mm.request_list,
4847 struct drm_i915_gem_request,
4849 list_del(&request->client_list);
4850 request->file_priv = NULL;
4852 spin_unlock(&file_priv->mm.lock);
4856 i915_gem_file_idle_work_handler(struct work_struct *work)
4858 struct drm_i915_file_private *file_priv =
4859 container_of(work, typeof(*file_priv), mm.idle_work.work);
4861 atomic_set(&file_priv->rps_wait_boost, false);
4864 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
4866 struct drm_i915_file_private *file_priv;
4869 DRM_DEBUG_DRIVER("\n");
4871 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
4875 file->driver_priv = file_priv;
4876 file_priv->dev_priv = dev->dev_private;
4877 file_priv->file = file;
4879 spin_lock_init(&file_priv->mm.lock);
4880 INIT_LIST_HEAD(&file_priv->mm.request_list);
4881 INIT_DELAYED_WORK(&file_priv->mm.idle_work,
4882 i915_gem_file_idle_work_handler);
4884 ret = i915_gem_context_open(dev, file);
4891 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
4893 if (!mutex_is_locked(mutex))
4896 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4897 return mutex->owner == task;
4899 /* Since UP may be pre-empted, we cannot assume that we own the lock */
4904 static unsigned long
4905 i915_gem_inactive_count(struct shrinker *shrinker, struct shrink_control *sc)
4907 struct drm_i915_private *dev_priv =
4908 container_of(shrinker,
4909 struct drm_i915_private,
4910 mm.inactive_shrinker);
4911 struct drm_device *dev = dev_priv->dev;
4912 struct drm_i915_gem_object *obj;
4914 unsigned long count;
4916 if (!mutex_trylock(&dev->struct_mutex)) {
4917 if (!mutex_is_locked_by(&dev->struct_mutex, current))
4920 if (dev_priv->mm.shrinker_no_lock_stealing)
4927 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
4928 if (obj->pages_pin_count == 0)
4929 count += obj->base.size >> PAGE_SHIFT;
4931 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
4935 if (!i915_gem_obj_is_pinned(obj) && obj->pages_pin_count == 0)
4936 count += obj->base.size >> PAGE_SHIFT;
4940 mutex_unlock(&dev->struct_mutex);
4945 /* All the new VM stuff */
4946 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
4947 struct i915_address_space *vm)
4949 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
4950 struct i915_vma *vma;
4952 if (!dev_priv->mm.aliasing_ppgtt ||
4953 vm == &dev_priv->mm.aliasing_ppgtt->base)
4954 vm = &dev_priv->gtt.base;
4956 BUG_ON(list_empty(&o->vma_list));
4957 list_for_each_entry(vma, &o->vma_list, vma_link) {
4959 return vma->node.start;
4965 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
4966 struct i915_address_space *vm)
4968 struct i915_vma *vma;
4970 list_for_each_entry(vma, &o->vma_list, vma_link)
4971 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
4977 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
4979 struct i915_vma *vma;
4981 list_for_each_entry(vma, &o->vma_list, vma_link)
4982 if (drm_mm_node_allocated(&vma->node))
4988 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
4989 struct i915_address_space *vm)
4991 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
4992 struct i915_vma *vma;
4994 if (!dev_priv->mm.aliasing_ppgtt ||
4995 vm == &dev_priv->mm.aliasing_ppgtt->base)
4996 vm = &dev_priv->gtt.base;
4998 BUG_ON(list_empty(&o->vma_list));
5000 list_for_each_entry(vma, &o->vma_list, vma_link)
5002 return vma->node.size;
5007 static unsigned long
5008 i915_gem_inactive_scan(struct shrinker *shrinker, struct shrink_control *sc)
5010 struct drm_i915_private *dev_priv =
5011 container_of(shrinker,
5012 struct drm_i915_private,
5013 mm.inactive_shrinker);
5014 struct drm_device *dev = dev_priv->dev;
5015 unsigned long freed;
5018 if (!mutex_trylock(&dev->struct_mutex)) {
5019 if (!mutex_is_locked_by(&dev->struct_mutex, current))
5022 if (dev_priv->mm.shrinker_no_lock_stealing)
5028 freed = i915_gem_purge(dev_priv, sc->nr_to_scan);
5029 if (freed < sc->nr_to_scan)
5030 freed += __i915_gem_shrink(dev_priv,
5031 sc->nr_to_scan - freed,
5033 if (freed < sc->nr_to_scan)
5034 freed += i915_gem_shrink_all(dev_priv);
5037 mutex_unlock(&dev->struct_mutex);
5042 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
5044 struct i915_vma *vma;
5046 if (WARN_ON(list_empty(&obj->vma_list)))
5049 vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link);
5050 if (vma->vm != obj_to_ggtt(obj))