2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_gem_clflush.h"
33 #include "i915_vgpu.h"
34 #include "i915_trace.h"
35 #include "intel_drv.h"
36 #include "intel_frontbuffer.h"
37 #include "intel_mocs.h"
38 #include <linux/dma-fence-array.h>
39 #include <linux/kthread.h>
40 #include <linux/reservation.h>
41 #include <linux/shmem_fs.h>
42 #include <linux/slab.h>
43 #include <linux/stop_machine.h>
44 #include <linux/swap.h>
45 #include <linux/pci.h>
46 #include <linux/dma-buf.h>
48 static void i915_gem_flush_free_objects(struct drm_i915_private *i915);
50 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
52 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
55 if (!i915_gem_object_is_coherent(obj))
58 return obj->pin_display;
62 insert_mappable_node(struct i915_ggtt *ggtt,
63 struct drm_mm_node *node, u32 size)
65 memset(node, 0, sizeof(*node));
66 return drm_mm_insert_node_in_range(&ggtt->base.mm, node,
67 size, 0, I915_COLOR_UNEVICTABLE,
68 0, ggtt->mappable_end,
73 remove_mappable_node(struct drm_mm_node *node)
75 drm_mm_remove_node(node);
78 /* some bookkeeping */
79 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
82 spin_lock(&dev_priv->mm.object_stat_lock);
83 dev_priv->mm.object_count++;
84 dev_priv->mm.object_memory += size;
85 spin_unlock(&dev_priv->mm.object_stat_lock);
88 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
91 spin_lock(&dev_priv->mm.object_stat_lock);
92 dev_priv->mm.object_count--;
93 dev_priv->mm.object_memory -= size;
94 spin_unlock(&dev_priv->mm.object_stat_lock);
98 i915_gem_wait_for_error(struct i915_gpu_error *error)
105 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
106 * userspace. If it takes that long something really bad is going on and
107 * we should simply try to bail out and fail as gracefully as possible.
109 ret = wait_event_interruptible_timeout(error->reset_queue,
110 !i915_reset_backoff(error),
113 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
115 } else if (ret < 0) {
122 int i915_mutex_lock_interruptible(struct drm_device *dev)
124 struct drm_i915_private *dev_priv = to_i915(dev);
127 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
131 ret = mutex_lock_interruptible(&dev->struct_mutex);
139 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
140 struct drm_file *file)
142 struct drm_i915_private *dev_priv = to_i915(dev);
143 struct i915_ggtt *ggtt = &dev_priv->ggtt;
144 struct drm_i915_gem_get_aperture *args = data;
145 struct i915_vma *vma;
148 pinned = ggtt->base.reserved;
149 mutex_lock(&dev->struct_mutex);
150 list_for_each_entry(vma, &ggtt->base.active_list, vm_link)
151 if (i915_vma_is_pinned(vma))
152 pinned += vma->node.size;
153 list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link)
154 if (i915_vma_is_pinned(vma))
155 pinned += vma->node.size;
156 mutex_unlock(&dev->struct_mutex);
158 args->aper_size = ggtt->base.total;
159 args->aper_available_size = args->aper_size - pinned;
164 static struct sg_table *
165 i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
167 struct address_space *mapping = obj->base.filp->f_mapping;
168 drm_dma_handle_t *phys;
170 struct scatterlist *sg;
174 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
175 return ERR_PTR(-EINVAL);
177 /* Always aligning to the object size, allows a single allocation
178 * to handle all possible callers, and given typical object sizes,
179 * the alignment of the buddy allocation will naturally match.
181 phys = drm_pci_alloc(obj->base.dev,
183 roundup_pow_of_two(obj->base.size));
185 return ERR_PTR(-ENOMEM);
188 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
192 page = shmem_read_mapping_page(mapping, i);
198 src = kmap_atomic(page);
199 memcpy(vaddr, src, PAGE_SIZE);
200 drm_clflush_virt_range(vaddr, PAGE_SIZE);
207 i915_gem_chipset_flush(to_i915(obj->base.dev));
209 st = kmalloc(sizeof(*st), GFP_KERNEL);
211 st = ERR_PTR(-ENOMEM);
215 if (sg_alloc_table(st, 1, GFP_KERNEL)) {
217 st = ERR_PTR(-ENOMEM);
223 sg->length = obj->base.size;
225 sg_dma_address(sg) = phys->busaddr;
226 sg_dma_len(sg) = obj->base.size;
228 obj->phys_handle = phys;
232 drm_pci_free(obj->base.dev, phys);
237 __i915_gem_object_release_shmem(struct drm_i915_gem_object *obj,
238 struct sg_table *pages,
241 GEM_BUG_ON(obj->mm.madv == __I915_MADV_PURGED);
243 if (obj->mm.madv == I915_MADV_DONTNEED)
244 obj->mm.dirty = false;
247 (obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0 &&
248 !i915_gem_object_is_coherent(obj))
249 drm_clflush_sg(pages);
251 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
252 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
256 i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj,
257 struct sg_table *pages)
259 __i915_gem_object_release_shmem(obj, pages, false);
262 struct address_space *mapping = obj->base.filp->f_mapping;
263 char *vaddr = obj->phys_handle->vaddr;
266 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
270 page = shmem_read_mapping_page(mapping, i);
274 dst = kmap_atomic(page);
275 drm_clflush_virt_range(vaddr, PAGE_SIZE);
276 memcpy(dst, vaddr, PAGE_SIZE);
279 set_page_dirty(page);
280 if (obj->mm.madv == I915_MADV_WILLNEED)
281 mark_page_accessed(page);
285 obj->mm.dirty = false;
288 sg_free_table(pages);
291 drm_pci_free(obj->base.dev, obj->phys_handle);
295 i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
297 i915_gem_object_unpin_pages(obj);
300 static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
301 .get_pages = i915_gem_object_get_pages_phys,
302 .put_pages = i915_gem_object_put_pages_phys,
303 .release = i915_gem_object_release_phys,
306 static const struct drm_i915_gem_object_ops i915_gem_object_ops;
308 int i915_gem_object_unbind(struct drm_i915_gem_object *obj)
310 struct i915_vma *vma;
311 LIST_HEAD(still_in_list);
314 lockdep_assert_held(&obj->base.dev->struct_mutex);
316 /* Closed vma are removed from the obj->vma_list - but they may
317 * still have an active binding on the object. To remove those we
318 * must wait for all rendering to complete to the object (as unbinding
319 * must anyway), and retire the requests.
321 ret = i915_gem_object_wait(obj,
322 I915_WAIT_INTERRUPTIBLE |
325 MAX_SCHEDULE_TIMEOUT,
330 i915_gem_retire_requests(to_i915(obj->base.dev));
332 while ((vma = list_first_entry_or_null(&obj->vma_list,
335 list_move_tail(&vma->obj_link, &still_in_list);
336 ret = i915_vma_unbind(vma);
340 list_splice(&still_in_list, &obj->vma_list);
346 i915_gem_object_wait_fence(struct dma_fence *fence,
349 struct intel_rps_client *rps)
351 struct drm_i915_gem_request *rq;
353 BUILD_BUG_ON(I915_WAIT_INTERRUPTIBLE != 0x1);
355 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
358 if (!dma_fence_is_i915(fence))
359 return dma_fence_wait_timeout(fence,
360 flags & I915_WAIT_INTERRUPTIBLE,
363 rq = to_request(fence);
364 if (i915_gem_request_completed(rq))
367 /* This client is about to stall waiting for the GPU. In many cases
368 * this is undesirable and limits the throughput of the system, as
369 * many clients cannot continue processing user input/output whilst
370 * blocked. RPS autotuning may take tens of milliseconds to respond
371 * to the GPU load and thus incurs additional latency for the client.
372 * We can circumvent that by promoting the GPU frequency to maximum
373 * before we wait. This makes the GPU throttle up much more quickly
374 * (good for benchmarks and user experience, e.g. window animations),
375 * but at a cost of spending more power processing the workload
376 * (bad for battery). Not all clients even want their results
377 * immediately and for them we should just let the GPU select its own
378 * frequency to maximise efficiency. To prevent a single client from
379 * forcing the clocks too high for the whole system, we only allow
380 * each client to waitboost once in a busy period.
383 if (INTEL_GEN(rq->i915) >= 6)
384 gen6_rps_boost(rq->i915, rps, rq->emitted_jiffies);
389 timeout = i915_wait_request(rq, flags, timeout);
392 if (flags & I915_WAIT_LOCKED && i915_gem_request_completed(rq))
393 i915_gem_request_retire_upto(rq);
395 if (rps && i915_gem_request_global_seqno(rq) == intel_engine_last_submit(rq->engine)) {
396 /* The GPU is now idle and this client has stalled.
397 * Since no other client has submitted a request in the
398 * meantime, assume that this client is the only one
399 * supplying work to the GPU but is unable to keep that
400 * work supplied because it is waiting. Since the GPU is
401 * then never kept fully busy, RPS autoclocking will
402 * keep the clocks relatively low, causing further delays.
403 * Compensate by giving the synchronous client credit for
404 * a waitboost next time.
406 spin_lock(&rq->i915->rps.client_lock);
407 list_del_init(&rps->link);
408 spin_unlock(&rq->i915->rps.client_lock);
415 i915_gem_object_wait_reservation(struct reservation_object *resv,
418 struct intel_rps_client *rps)
420 unsigned int seq = __read_seqcount_begin(&resv->seq);
421 struct dma_fence *excl;
422 bool prune_fences = false;
424 if (flags & I915_WAIT_ALL) {
425 struct dma_fence **shared;
426 unsigned int count, i;
429 ret = reservation_object_get_fences_rcu(resv,
430 &excl, &count, &shared);
434 for (i = 0; i < count; i++) {
435 timeout = i915_gem_object_wait_fence(shared[i],
441 dma_fence_put(shared[i]);
444 for (; i < count; i++)
445 dma_fence_put(shared[i]);
448 prune_fences = count && timeout >= 0;
450 excl = reservation_object_get_excl_rcu(resv);
453 if (excl && timeout >= 0) {
454 timeout = i915_gem_object_wait_fence(excl, flags, timeout, rps);
455 prune_fences = timeout >= 0;
460 /* Oportunistically prune the fences iff we know they have *all* been
461 * signaled and that the reservation object has not been changed (i.e.
462 * no new fences have been added).
464 if (prune_fences && !__read_seqcount_retry(&resv->seq, seq)) {
465 if (reservation_object_trylock(resv)) {
466 if (!__read_seqcount_retry(&resv->seq, seq))
467 reservation_object_add_excl_fence(resv, NULL);
468 reservation_object_unlock(resv);
475 static void __fence_set_priority(struct dma_fence *fence, int prio)
477 struct drm_i915_gem_request *rq;
478 struct intel_engine_cs *engine;
480 if (!dma_fence_is_i915(fence))
483 rq = to_request(fence);
485 if (!engine->schedule)
488 engine->schedule(rq, prio);
491 static void fence_set_priority(struct dma_fence *fence, int prio)
493 /* Recurse once into a fence-array */
494 if (dma_fence_is_array(fence)) {
495 struct dma_fence_array *array = to_dma_fence_array(fence);
498 for (i = 0; i < array->num_fences; i++)
499 __fence_set_priority(array->fences[i], prio);
501 __fence_set_priority(fence, prio);
506 i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
510 struct dma_fence *excl;
512 if (flags & I915_WAIT_ALL) {
513 struct dma_fence **shared;
514 unsigned int count, i;
517 ret = reservation_object_get_fences_rcu(obj->resv,
518 &excl, &count, &shared);
522 for (i = 0; i < count; i++) {
523 fence_set_priority(shared[i], prio);
524 dma_fence_put(shared[i]);
529 excl = reservation_object_get_excl_rcu(obj->resv);
533 fence_set_priority(excl, prio);
540 * Waits for rendering to the object to be completed
541 * @obj: i915 gem object
542 * @flags: how to wait (under a lock, for all rendering or just for writes etc)
543 * @timeout: how long to wait
544 * @rps: client (user process) to charge for any waitboosting
547 i915_gem_object_wait(struct drm_i915_gem_object *obj,
550 struct intel_rps_client *rps)
553 #if IS_ENABLED(CONFIG_LOCKDEP)
554 GEM_BUG_ON(debug_locks &&
555 !!lockdep_is_held(&obj->base.dev->struct_mutex) !=
556 !!(flags & I915_WAIT_LOCKED));
558 GEM_BUG_ON(timeout < 0);
560 timeout = i915_gem_object_wait_reservation(obj->resv,
563 return timeout < 0 ? timeout : 0;
566 static struct intel_rps_client *to_rps_client(struct drm_file *file)
568 struct drm_i915_file_private *fpriv = file->driver_priv;
574 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
579 if (align > obj->base.size)
582 if (obj->ops == &i915_gem_phys_ops)
585 if (obj->mm.madv != I915_MADV_WILLNEED)
588 if (obj->base.filp == NULL)
591 ret = i915_gem_object_unbind(obj);
595 __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
599 GEM_BUG_ON(obj->ops != &i915_gem_object_ops);
600 obj->ops = &i915_gem_phys_ops;
602 ret = i915_gem_object_pin_pages(obj);
609 obj->ops = &i915_gem_object_ops;
614 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
615 struct drm_i915_gem_pwrite *args,
616 struct drm_file *file)
618 void *vaddr = obj->phys_handle->vaddr + args->offset;
619 char __user *user_data = u64_to_user_ptr(args->data_ptr);
621 /* We manually control the domain here and pretend that it
622 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
624 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
625 if (copy_from_user(vaddr, user_data, args->size))
628 drm_clflush_virt_range(vaddr, args->size);
629 i915_gem_chipset_flush(to_i915(obj->base.dev));
631 intel_fb_obj_flush(obj, ORIGIN_CPU);
635 void *i915_gem_object_alloc(struct drm_i915_private *dev_priv)
637 return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL);
640 void i915_gem_object_free(struct drm_i915_gem_object *obj)
642 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
643 kmem_cache_free(dev_priv->objects, obj);
647 i915_gem_create(struct drm_file *file,
648 struct drm_i915_private *dev_priv,
652 struct drm_i915_gem_object *obj;
656 size = roundup(size, PAGE_SIZE);
660 /* Allocate the new object */
661 obj = i915_gem_object_create(dev_priv, size);
665 ret = drm_gem_handle_create(file, &obj->base, &handle);
666 /* drop reference from allocate - handle holds it now */
667 i915_gem_object_put(obj);
676 i915_gem_dumb_create(struct drm_file *file,
677 struct drm_device *dev,
678 struct drm_mode_create_dumb *args)
680 /* have to work out size/pitch and return them */
681 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
682 args->size = args->pitch * args->height;
683 return i915_gem_create(file, to_i915(dev),
684 args->size, &args->handle);
688 * Creates a new mm object and returns a handle to it.
689 * @dev: drm device pointer
690 * @data: ioctl data blob
691 * @file: drm file pointer
694 i915_gem_create_ioctl(struct drm_device *dev, void *data,
695 struct drm_file *file)
697 struct drm_i915_private *dev_priv = to_i915(dev);
698 struct drm_i915_gem_create *args = data;
700 i915_gem_flush_free_objects(dev_priv);
702 return i915_gem_create(file, dev_priv,
703 args->size, &args->handle);
706 static inline enum fb_op_origin
707 fb_write_origin(struct drm_i915_gem_object *obj, unsigned int domain)
709 return (domain == I915_GEM_DOMAIN_GTT ?
710 obj->frontbuffer_ggtt_origin : ORIGIN_CPU);
714 flush_write_domain(struct drm_i915_gem_object *obj, unsigned int flush_domains)
716 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
718 if (!(obj->base.write_domain & flush_domains))
721 /* No actual flushing is required for the GTT write domain. Writes
722 * to it "immediately" go to main memory as far as we know, so there's
723 * no chipset flush. It also doesn't land in render cache.
725 * However, we do have to enforce the order so that all writes through
726 * the GTT land before any writes to the device, such as updates to
729 * We also have to wait a bit for the writes to land from the GTT.
730 * An uncached read (i.e. mmio) seems to be ideal for the round-trip
731 * timing. This issue has only been observed when switching quickly
732 * between GTT writes and CPU reads from inside the kernel on recent hw,
733 * and it appears to only affect discrete GTT blocks (i.e. on LLC
734 * system agents we cannot reproduce this behaviour).
738 switch (obj->base.write_domain) {
739 case I915_GEM_DOMAIN_GTT:
740 if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv)) {
741 if (intel_runtime_pm_get_if_in_use(dev_priv)) {
742 spin_lock_irq(&dev_priv->uncore.lock);
743 POSTING_READ_FW(RING_ACTHD(dev_priv->engine[RCS]->mmio_base));
744 spin_unlock_irq(&dev_priv->uncore.lock);
745 intel_runtime_pm_put(dev_priv);
749 intel_fb_obj_flush(obj,
750 fb_write_origin(obj, I915_GEM_DOMAIN_GTT));
753 case I915_GEM_DOMAIN_CPU:
754 i915_gem_clflush_object(obj, I915_CLFLUSH_SYNC);
758 obj->base.write_domain = 0;
762 __copy_to_user_swizzled(char __user *cpu_vaddr,
763 const char *gpu_vaddr, int gpu_offset,
766 int ret, cpu_offset = 0;
769 int cacheline_end = ALIGN(gpu_offset + 1, 64);
770 int this_length = min(cacheline_end - gpu_offset, length);
771 int swizzled_gpu_offset = gpu_offset ^ 64;
773 ret = __copy_to_user(cpu_vaddr + cpu_offset,
774 gpu_vaddr + swizzled_gpu_offset,
779 cpu_offset += this_length;
780 gpu_offset += this_length;
781 length -= this_length;
788 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
789 const char __user *cpu_vaddr,
792 int ret, cpu_offset = 0;
795 int cacheline_end = ALIGN(gpu_offset + 1, 64);
796 int this_length = min(cacheline_end - gpu_offset, length);
797 int swizzled_gpu_offset = gpu_offset ^ 64;
799 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
800 cpu_vaddr + cpu_offset,
805 cpu_offset += this_length;
806 gpu_offset += this_length;
807 length -= this_length;
814 * Pins the specified object's pages and synchronizes the object with
815 * GPU accesses. Sets needs_clflush to non-zero if the caller should
816 * flush the object from the CPU cache.
818 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
819 unsigned int *needs_clflush)
823 lockdep_assert_held(&obj->base.dev->struct_mutex);
826 if (!i915_gem_object_has_struct_page(obj))
829 ret = i915_gem_object_wait(obj,
830 I915_WAIT_INTERRUPTIBLE |
832 MAX_SCHEDULE_TIMEOUT,
837 ret = i915_gem_object_pin_pages(obj);
841 if (i915_gem_object_is_coherent(obj) ||
842 !static_cpu_has(X86_FEATURE_CLFLUSH)) {
843 ret = i915_gem_object_set_to_cpu_domain(obj, false);
850 flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
852 /* If we're not in the cpu read domain, set ourself into the gtt
853 * read domain and manually flush cachelines (if required). This
854 * optimizes for the case when the gpu will dirty the data
855 * anyway again before the next pread happens.
857 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU))
858 *needs_clflush = CLFLUSH_BEFORE;
861 /* return with the pages pinned */
865 i915_gem_object_unpin_pages(obj);
869 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
870 unsigned int *needs_clflush)
874 lockdep_assert_held(&obj->base.dev->struct_mutex);
877 if (!i915_gem_object_has_struct_page(obj))
880 ret = i915_gem_object_wait(obj,
881 I915_WAIT_INTERRUPTIBLE |
884 MAX_SCHEDULE_TIMEOUT,
889 ret = i915_gem_object_pin_pages(obj);
893 if (i915_gem_object_is_coherent(obj) ||
894 !static_cpu_has(X86_FEATURE_CLFLUSH)) {
895 ret = i915_gem_object_set_to_cpu_domain(obj, true);
902 flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
904 /* If we're not in the cpu write domain, set ourself into the
905 * gtt write domain and manually flush cachelines (as required).
906 * This optimizes for the case when the gpu will use the data
907 * right away and we therefore have to clflush anyway.
909 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
910 *needs_clflush |= CLFLUSH_AFTER;
912 /* Same trick applies to invalidate partially written cachelines read
915 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU))
916 *needs_clflush |= CLFLUSH_BEFORE;
919 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
920 obj->mm.dirty = true;
921 /* return with the pages pinned */
925 i915_gem_object_unpin_pages(obj);
930 shmem_clflush_swizzled_range(char *addr, unsigned long length,
933 if (unlikely(swizzled)) {
934 unsigned long start = (unsigned long) addr;
935 unsigned long end = (unsigned long) addr + length;
937 /* For swizzling simply ensure that we always flush both
938 * channels. Lame, but simple and it works. Swizzled
939 * pwrite/pread is far from a hotpath - current userspace
940 * doesn't use it at all. */
941 start = round_down(start, 128);
942 end = round_up(end, 128);
944 drm_clflush_virt_range((void *)start, end - start);
946 drm_clflush_virt_range(addr, length);
951 /* Only difference to the fast-path function is that this can handle bit17
952 * and uses non-atomic copy and kmap functions. */
954 shmem_pread_slow(struct page *page, int offset, int length,
955 char __user *user_data,
956 bool page_do_bit17_swizzling, bool needs_clflush)
963 shmem_clflush_swizzled_range(vaddr + offset, length,
964 page_do_bit17_swizzling);
966 if (page_do_bit17_swizzling)
967 ret = __copy_to_user_swizzled(user_data, vaddr, offset, length);
969 ret = __copy_to_user(user_data, vaddr + offset, length);
972 return ret ? - EFAULT : 0;
976 shmem_pread(struct page *page, int offset, int length, char __user *user_data,
977 bool page_do_bit17_swizzling, bool needs_clflush)
982 if (!page_do_bit17_swizzling) {
983 char *vaddr = kmap_atomic(page);
986 drm_clflush_virt_range(vaddr + offset, length);
987 ret = __copy_to_user_inatomic(user_data, vaddr + offset, length);
988 kunmap_atomic(vaddr);
993 return shmem_pread_slow(page, offset, length, user_data,
994 page_do_bit17_swizzling, needs_clflush);
998 i915_gem_shmem_pread(struct drm_i915_gem_object *obj,
999 struct drm_i915_gem_pread *args)
1001 char __user *user_data;
1003 unsigned int obj_do_bit17_swizzling;
1004 unsigned int needs_clflush;
1005 unsigned int idx, offset;
1008 obj_do_bit17_swizzling = 0;
1009 if (i915_gem_object_needs_bit17_swizzle(obj))
1010 obj_do_bit17_swizzling = BIT(17);
1012 ret = mutex_lock_interruptible(&obj->base.dev->struct_mutex);
1016 ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
1017 mutex_unlock(&obj->base.dev->struct_mutex);
1021 remain = args->size;
1022 user_data = u64_to_user_ptr(args->data_ptr);
1023 offset = offset_in_page(args->offset);
1024 for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {
1025 struct page *page = i915_gem_object_get_page(obj, idx);
1029 if (offset + length > PAGE_SIZE)
1030 length = PAGE_SIZE - offset;
1032 ret = shmem_pread(page, offset, length, user_data,
1033 page_to_phys(page) & obj_do_bit17_swizzling,
1039 user_data += length;
1043 i915_gem_obj_finish_shmem_access(obj);
1048 gtt_user_read(struct io_mapping *mapping,
1049 loff_t base, int offset,
1050 char __user *user_data, int length)
1053 unsigned long unwritten;
1055 /* We can use the cpu mem copy function because this is X86. */
1056 vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base);
1057 unwritten = __copy_to_user_inatomic(user_data, vaddr + offset, length);
1058 io_mapping_unmap_atomic(vaddr);
1060 vaddr = (void __force *)
1061 io_mapping_map_wc(mapping, base, PAGE_SIZE);
1062 unwritten = copy_to_user(user_data, vaddr + offset, length);
1063 io_mapping_unmap(vaddr);
1069 i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
1070 const struct drm_i915_gem_pread *args)
1072 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1073 struct i915_ggtt *ggtt = &i915->ggtt;
1074 struct drm_mm_node node;
1075 struct i915_vma *vma;
1076 void __user *user_data;
1080 ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
1084 intel_runtime_pm_get(i915);
1085 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
1086 PIN_MAPPABLE | PIN_NONBLOCK);
1088 node.start = i915_ggtt_offset(vma);
1089 node.allocated = false;
1090 ret = i915_vma_put_fence(vma);
1092 i915_vma_unpin(vma);
1097 ret = insert_mappable_node(ggtt, &node, PAGE_SIZE);
1100 GEM_BUG_ON(!node.allocated);
1103 ret = i915_gem_object_set_to_gtt_domain(obj, false);
1107 mutex_unlock(&i915->drm.struct_mutex);
1109 user_data = u64_to_user_ptr(args->data_ptr);
1110 remain = args->size;
1111 offset = args->offset;
1113 while (remain > 0) {
1114 /* Operation in this page
1116 * page_base = page offset within aperture
1117 * page_offset = offset within page
1118 * page_length = bytes to copy for this page
1120 u32 page_base = node.start;
1121 unsigned page_offset = offset_in_page(offset);
1122 unsigned page_length = PAGE_SIZE - page_offset;
1123 page_length = remain < page_length ? remain : page_length;
1124 if (node.allocated) {
1126 ggtt->base.insert_page(&ggtt->base,
1127 i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
1128 node.start, I915_CACHE_NONE, 0);
1131 page_base += offset & PAGE_MASK;
1134 if (gtt_user_read(&ggtt->mappable, page_base, page_offset,
1135 user_data, page_length)) {
1140 remain -= page_length;
1141 user_data += page_length;
1142 offset += page_length;
1145 mutex_lock(&i915->drm.struct_mutex);
1147 if (node.allocated) {
1149 ggtt->base.clear_range(&ggtt->base,
1150 node.start, node.size);
1151 remove_mappable_node(&node);
1153 i915_vma_unpin(vma);
1156 intel_runtime_pm_put(i915);
1157 mutex_unlock(&i915->drm.struct_mutex);
1163 * Reads data from the object referenced by handle.
1164 * @dev: drm device pointer
1165 * @data: ioctl data blob
1166 * @file: drm file pointer
1168 * On error, the contents of *data are undefined.
1171 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1172 struct drm_file *file)
1174 struct drm_i915_gem_pread *args = data;
1175 struct drm_i915_gem_object *obj;
1178 if (args->size == 0)
1181 if (!access_ok(VERIFY_WRITE,
1182 u64_to_user_ptr(args->data_ptr),
1186 obj = i915_gem_object_lookup(file, args->handle);
1190 /* Bounds check source. */
1191 if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) {
1196 trace_i915_gem_object_pread(obj, args->offset, args->size);
1198 ret = i915_gem_object_wait(obj,
1199 I915_WAIT_INTERRUPTIBLE,
1200 MAX_SCHEDULE_TIMEOUT,
1201 to_rps_client(file));
1205 ret = i915_gem_object_pin_pages(obj);
1209 ret = i915_gem_shmem_pread(obj, args);
1210 if (ret == -EFAULT || ret == -ENODEV)
1211 ret = i915_gem_gtt_pread(obj, args);
1213 i915_gem_object_unpin_pages(obj);
1215 i915_gem_object_put(obj);
1219 /* This is the fast write path which cannot handle
1220 * page faults in the source data
1224 ggtt_write(struct io_mapping *mapping,
1225 loff_t base, int offset,
1226 char __user *user_data, int length)
1229 unsigned long unwritten;
1231 /* We can use the cpu mem copy function because this is X86. */
1232 vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base);
1233 unwritten = __copy_from_user_inatomic_nocache(vaddr + offset,
1235 io_mapping_unmap_atomic(vaddr);
1237 vaddr = (void __force *)
1238 io_mapping_map_wc(mapping, base, PAGE_SIZE);
1239 unwritten = copy_from_user(vaddr + offset, user_data, length);
1240 io_mapping_unmap(vaddr);
1247 * This is the fast pwrite path, where we copy the data directly from the
1248 * user into the GTT, uncached.
1249 * @obj: i915 GEM object
1250 * @args: pwrite arguments structure
1253 i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
1254 const struct drm_i915_gem_pwrite *args)
1256 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1257 struct i915_ggtt *ggtt = &i915->ggtt;
1258 struct drm_mm_node node;
1259 struct i915_vma *vma;
1261 void __user *user_data;
1264 ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
1268 intel_runtime_pm_get(i915);
1269 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
1270 PIN_MAPPABLE | PIN_NONBLOCK);
1272 node.start = i915_ggtt_offset(vma);
1273 node.allocated = false;
1274 ret = i915_vma_put_fence(vma);
1276 i915_vma_unpin(vma);
1281 ret = insert_mappable_node(ggtt, &node, PAGE_SIZE);
1284 GEM_BUG_ON(!node.allocated);
1287 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1291 mutex_unlock(&i915->drm.struct_mutex);
1293 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
1295 user_data = u64_to_user_ptr(args->data_ptr);
1296 offset = args->offset;
1297 remain = args->size;
1299 /* Operation in this page
1301 * page_base = page offset within aperture
1302 * page_offset = offset within page
1303 * page_length = bytes to copy for this page
1305 u32 page_base = node.start;
1306 unsigned int page_offset = offset_in_page(offset);
1307 unsigned int page_length = PAGE_SIZE - page_offset;
1308 page_length = remain < page_length ? remain : page_length;
1309 if (node.allocated) {
1310 wmb(); /* flush the write before we modify the GGTT */
1311 ggtt->base.insert_page(&ggtt->base,
1312 i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
1313 node.start, I915_CACHE_NONE, 0);
1314 wmb(); /* flush modifications to the GGTT (insert_page) */
1316 page_base += offset & PAGE_MASK;
1318 /* If we get a fault while copying data, then (presumably) our
1319 * source page isn't available. Return the error and we'll
1320 * retry in the slow path.
1321 * If the object is non-shmem backed, we retry again with the
1322 * path that handles page fault.
1324 if (ggtt_write(&ggtt->mappable, page_base, page_offset,
1325 user_data, page_length)) {
1330 remain -= page_length;
1331 user_data += page_length;
1332 offset += page_length;
1334 intel_fb_obj_flush(obj, ORIGIN_CPU);
1336 mutex_lock(&i915->drm.struct_mutex);
1338 if (node.allocated) {
1340 ggtt->base.clear_range(&ggtt->base,
1341 node.start, node.size);
1342 remove_mappable_node(&node);
1344 i915_vma_unpin(vma);
1347 intel_runtime_pm_put(i915);
1348 mutex_unlock(&i915->drm.struct_mutex);
1353 shmem_pwrite_slow(struct page *page, int offset, int length,
1354 char __user *user_data,
1355 bool page_do_bit17_swizzling,
1356 bool needs_clflush_before,
1357 bool needs_clflush_after)
1363 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
1364 shmem_clflush_swizzled_range(vaddr + offset, length,
1365 page_do_bit17_swizzling);
1366 if (page_do_bit17_swizzling)
1367 ret = __copy_from_user_swizzled(vaddr, offset, user_data,
1370 ret = __copy_from_user(vaddr + offset, user_data, length);
1371 if (needs_clflush_after)
1372 shmem_clflush_swizzled_range(vaddr + offset, length,
1373 page_do_bit17_swizzling);
1376 return ret ? -EFAULT : 0;
1379 /* Per-page copy function for the shmem pwrite fastpath.
1380 * Flushes invalid cachelines before writing to the target if
1381 * needs_clflush_before is set and flushes out any written cachelines after
1382 * writing if needs_clflush is set.
1385 shmem_pwrite(struct page *page, int offset, int len, char __user *user_data,
1386 bool page_do_bit17_swizzling,
1387 bool needs_clflush_before,
1388 bool needs_clflush_after)
1393 if (!page_do_bit17_swizzling) {
1394 char *vaddr = kmap_atomic(page);
1396 if (needs_clflush_before)
1397 drm_clflush_virt_range(vaddr + offset, len);
1398 ret = __copy_from_user_inatomic(vaddr + offset, user_data, len);
1399 if (needs_clflush_after)
1400 drm_clflush_virt_range(vaddr + offset, len);
1402 kunmap_atomic(vaddr);
1407 return shmem_pwrite_slow(page, offset, len, user_data,
1408 page_do_bit17_swizzling,
1409 needs_clflush_before,
1410 needs_clflush_after);
1414 i915_gem_shmem_pwrite(struct drm_i915_gem_object *obj,
1415 const struct drm_i915_gem_pwrite *args)
1417 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1418 void __user *user_data;
1420 unsigned int obj_do_bit17_swizzling;
1421 unsigned int partial_cacheline_write;
1422 unsigned int needs_clflush;
1423 unsigned int offset, idx;
1426 ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
1430 ret = i915_gem_obj_prepare_shmem_write(obj, &needs_clflush);
1431 mutex_unlock(&i915->drm.struct_mutex);
1435 obj_do_bit17_swizzling = 0;
1436 if (i915_gem_object_needs_bit17_swizzle(obj))
1437 obj_do_bit17_swizzling = BIT(17);
1439 /* If we don't overwrite a cacheline completely we need to be
1440 * careful to have up-to-date data by first clflushing. Don't
1441 * overcomplicate things and flush the entire patch.
1443 partial_cacheline_write = 0;
1444 if (needs_clflush & CLFLUSH_BEFORE)
1445 partial_cacheline_write = boot_cpu_data.x86_clflush_size - 1;
1447 user_data = u64_to_user_ptr(args->data_ptr);
1448 remain = args->size;
1449 offset = offset_in_page(args->offset);
1450 for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {
1451 struct page *page = i915_gem_object_get_page(obj, idx);
1455 if (offset + length > PAGE_SIZE)
1456 length = PAGE_SIZE - offset;
1458 ret = shmem_pwrite(page, offset, length, user_data,
1459 page_to_phys(page) & obj_do_bit17_swizzling,
1460 (offset | length) & partial_cacheline_write,
1461 needs_clflush & CLFLUSH_AFTER);
1466 user_data += length;
1470 intel_fb_obj_flush(obj, ORIGIN_CPU);
1471 i915_gem_obj_finish_shmem_access(obj);
1476 * Writes data to the object referenced by handle.
1478 * @data: ioctl data blob
1481 * On error, the contents of the buffer that were to be modified are undefined.
1484 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1485 struct drm_file *file)
1487 struct drm_i915_gem_pwrite *args = data;
1488 struct drm_i915_gem_object *obj;
1491 if (args->size == 0)
1494 if (!access_ok(VERIFY_READ,
1495 u64_to_user_ptr(args->data_ptr),
1499 obj = i915_gem_object_lookup(file, args->handle);
1503 /* Bounds check destination. */
1504 if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) {
1509 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1512 if (obj->ops->pwrite)
1513 ret = obj->ops->pwrite(obj, args);
1517 ret = i915_gem_object_wait(obj,
1518 I915_WAIT_INTERRUPTIBLE |
1520 MAX_SCHEDULE_TIMEOUT,
1521 to_rps_client(file));
1525 ret = i915_gem_object_pin_pages(obj);
1530 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1531 * it would end up going through the fenced access, and we'll get
1532 * different detiling behavior between reading and writing.
1533 * pread/pwrite currently are reading and writing from the CPU
1534 * perspective, requiring manual detiling by the client.
1536 if (!i915_gem_object_has_struct_page(obj) ||
1537 cpu_write_needs_clflush(obj))
1538 /* Note that the gtt paths might fail with non-page-backed user
1539 * pointers (e.g. gtt mappings when moving data between
1540 * textures). Fallback to the shmem path in that case.
1542 ret = i915_gem_gtt_pwrite_fast(obj, args);
1544 if (ret == -EFAULT || ret == -ENOSPC) {
1545 if (obj->phys_handle)
1546 ret = i915_gem_phys_pwrite(obj, args, file);
1548 ret = i915_gem_shmem_pwrite(obj, args);
1551 i915_gem_object_unpin_pages(obj);
1553 i915_gem_object_put(obj);
1557 static void i915_gem_object_bump_inactive_ggtt(struct drm_i915_gem_object *obj)
1559 struct drm_i915_private *i915;
1560 struct list_head *list;
1561 struct i915_vma *vma;
1563 list_for_each_entry(vma, &obj->vma_list, obj_link) {
1564 if (!i915_vma_is_ggtt(vma))
1567 if (i915_vma_is_active(vma))
1570 if (!drm_mm_node_allocated(&vma->node))
1573 list_move_tail(&vma->vm_link, &vma->vm->inactive_list);
1576 i915 = to_i915(obj->base.dev);
1577 list = obj->bind_count ? &i915->mm.bound_list : &i915->mm.unbound_list;
1578 list_move_tail(&obj->global_link, list);
1582 * Called when user space prepares to use an object with the CPU, either
1583 * through the mmap ioctl's mapping or a GTT mapping.
1585 * @data: ioctl data blob
1589 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1590 struct drm_file *file)
1592 struct drm_i915_gem_set_domain *args = data;
1593 struct drm_i915_gem_object *obj;
1594 uint32_t read_domains = args->read_domains;
1595 uint32_t write_domain = args->write_domain;
1598 /* Only handle setting domains to types used by the CPU. */
1599 if ((write_domain | read_domains) & I915_GEM_GPU_DOMAINS)
1602 /* Having something in the write domain implies it's in the read
1603 * domain, and only that read domain. Enforce that in the request.
1605 if (write_domain != 0 && read_domains != write_domain)
1608 obj = i915_gem_object_lookup(file, args->handle);
1612 /* Try to flush the object off the GPU without holding the lock.
1613 * We will repeat the flush holding the lock in the normal manner
1614 * to catch cases where we are gazumped.
1616 err = i915_gem_object_wait(obj,
1617 I915_WAIT_INTERRUPTIBLE |
1618 (write_domain ? I915_WAIT_ALL : 0),
1619 MAX_SCHEDULE_TIMEOUT,
1620 to_rps_client(file));
1624 /* Flush and acquire obj->pages so that we are coherent through
1625 * direct access in memory with previous cached writes through
1626 * shmemfs and that our cache domain tracking remains valid.
1627 * For example, if the obj->filp was moved to swap without us
1628 * being notified and releasing the pages, we would mistakenly
1629 * continue to assume that the obj remained out of the CPU cached
1632 err = i915_gem_object_pin_pages(obj);
1636 err = i915_mutex_lock_interruptible(dev);
1640 if (read_domains & I915_GEM_DOMAIN_WC)
1641 err = i915_gem_object_set_to_wc_domain(obj, write_domain);
1642 else if (read_domains & I915_GEM_DOMAIN_GTT)
1643 err = i915_gem_object_set_to_gtt_domain(obj, write_domain);
1645 err = i915_gem_object_set_to_cpu_domain(obj, write_domain);
1647 /* And bump the LRU for this access */
1648 i915_gem_object_bump_inactive_ggtt(obj);
1650 mutex_unlock(&dev->struct_mutex);
1652 if (write_domain != 0)
1653 intel_fb_obj_invalidate(obj,
1654 fb_write_origin(obj, write_domain));
1657 i915_gem_object_unpin_pages(obj);
1659 i915_gem_object_put(obj);
1664 * Called when user space has done writes to this buffer
1666 * @data: ioctl data blob
1670 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1671 struct drm_file *file)
1673 struct drm_i915_gem_sw_finish *args = data;
1674 struct drm_i915_gem_object *obj;
1676 obj = i915_gem_object_lookup(file, args->handle);
1680 /* Pinned buffers may be scanout, so flush the cache */
1681 i915_gem_object_flush_if_display(obj);
1682 i915_gem_object_put(obj);
1688 * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address
1691 * @data: ioctl data blob
1694 * While the mapping holds a reference on the contents of the object, it doesn't
1695 * imply a ref on the object itself.
1699 * DRM driver writers who look a this function as an example for how to do GEM
1700 * mmap support, please don't implement mmap support like here. The modern way
1701 * to implement DRM mmap support is with an mmap offset ioctl (like
1702 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1703 * That way debug tooling like valgrind will understand what's going on, hiding
1704 * the mmap call in a driver private ioctl will break that. The i915 driver only
1705 * does cpu mmaps this way because we didn't know better.
1708 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1709 struct drm_file *file)
1711 struct drm_i915_gem_mmap *args = data;
1712 struct drm_i915_gem_object *obj;
1715 if (args->flags & ~(I915_MMAP_WC))
1718 if (args->flags & I915_MMAP_WC && !boot_cpu_has(X86_FEATURE_PAT))
1721 obj = i915_gem_object_lookup(file, args->handle);
1725 /* prime objects have no backing filp to GEM mmap
1728 if (!obj->base.filp) {
1729 i915_gem_object_put(obj);
1733 addr = vm_mmap(obj->base.filp, 0, args->size,
1734 PROT_READ | PROT_WRITE, MAP_SHARED,
1736 if (args->flags & I915_MMAP_WC) {
1737 struct mm_struct *mm = current->mm;
1738 struct vm_area_struct *vma;
1740 if (down_write_killable(&mm->mmap_sem)) {
1741 i915_gem_object_put(obj);
1744 vma = find_vma(mm, addr);
1747 pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
1750 up_write(&mm->mmap_sem);
1752 /* This may race, but that's ok, it only gets set */
1753 WRITE_ONCE(obj->frontbuffer_ggtt_origin, ORIGIN_CPU);
1755 i915_gem_object_put(obj);
1756 if (IS_ERR((void *)addr))
1759 args->addr_ptr = (uint64_t) addr;
1764 static unsigned int tile_row_pages(struct drm_i915_gem_object *obj)
1766 return i915_gem_object_get_tile_row_size(obj) >> PAGE_SHIFT;
1770 * i915_gem_mmap_gtt_version - report the current feature set for GTT mmaps
1772 * A history of the GTT mmap interface:
1774 * 0 - Everything had to fit into the GTT. Both parties of a memcpy had to
1775 * aligned and suitable for fencing, and still fit into the available
1776 * mappable space left by the pinned display objects. A classic problem
1777 * we called the page-fault-of-doom where we would ping-pong between
1778 * two objects that could not fit inside the GTT and so the memcpy
1779 * would page one object in at the expense of the other between every
1782 * 1 - Objects can be any size, and have any compatible fencing (X Y, or none
1783 * as set via i915_gem_set_tiling() [DRM_I915_GEM_SET_TILING]). If the
1784 * object is too large for the available space (or simply too large
1785 * for the mappable aperture!), a view is created instead and faulted
1786 * into userspace. (This view is aligned and sized appropriately for
1789 * 2 - Recognise WC as a separate cache domain so that we can flush the
1790 * delayed writes via GTT before performing direct access via WC.
1794 * * snoopable objects cannot be accessed via the GTT. It can cause machine
1795 * hangs on some architectures, corruption on others. An attempt to service
1796 * a GTT page fault from a snoopable object will generate a SIGBUS.
1798 * * the object must be able to fit into RAM (physical memory, though no
1799 * limited to the mappable aperture).
1804 * * a new GTT page fault will synchronize rendering from the GPU and flush
1805 * all data to system memory. Subsequent access will not be synchronized.
1807 * * all mappings are revoked on runtime device suspend.
1809 * * there are only 8, 16 or 32 fence registers to share between all users
1810 * (older machines require fence register for display and blitter access
1811 * as well). Contention of the fence registers will cause the previous users
1812 * to be unmapped and any new access will generate new page faults.
1814 * * running out of memory while servicing a fault may generate a SIGBUS,
1815 * rather than the expected SIGSEGV.
1817 int i915_gem_mmap_gtt_version(void)
1822 static inline struct i915_ggtt_view
1823 compute_partial_view(struct drm_i915_gem_object *obj,
1824 pgoff_t page_offset,
1827 struct i915_ggtt_view view;
1829 if (i915_gem_object_is_tiled(obj))
1830 chunk = roundup(chunk, tile_row_pages(obj));
1832 view.type = I915_GGTT_VIEW_PARTIAL;
1833 view.partial.offset = rounddown(page_offset, chunk);
1835 min_t(unsigned int, chunk,
1836 (obj->base.size >> PAGE_SHIFT) - view.partial.offset);
1838 /* If the partial covers the entire object, just create a normal VMA. */
1839 if (chunk >= obj->base.size >> PAGE_SHIFT)
1840 view.type = I915_GGTT_VIEW_NORMAL;
1846 * i915_gem_fault - fault a page into the GTT
1849 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1850 * from userspace. The fault handler takes care of binding the object to
1851 * the GTT (if needed), allocating and programming a fence register (again,
1852 * only if needed based on whether the old reg is still valid or the object
1853 * is tiled) and inserting a new PTE into the faulting process.
1855 * Note that the faulting process may involve evicting existing objects
1856 * from the GTT and/or fence registers to make room. So performance may
1857 * suffer if the GTT working set is large or there are few fence registers
1860 * The current feature set supported by i915_gem_fault() and thus GTT mmaps
1861 * is exposed via I915_PARAM_MMAP_GTT_VERSION (see i915_gem_mmap_gtt_version).
1863 int i915_gem_fault(struct vm_fault *vmf)
1865 #define MIN_CHUNK_PAGES ((1 << 20) >> PAGE_SHIFT) /* 1 MiB */
1866 struct vm_area_struct *area = vmf->vma;
1867 struct drm_i915_gem_object *obj = to_intel_bo(area->vm_private_data);
1868 struct drm_device *dev = obj->base.dev;
1869 struct drm_i915_private *dev_priv = to_i915(dev);
1870 struct i915_ggtt *ggtt = &dev_priv->ggtt;
1871 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1872 struct i915_vma *vma;
1873 pgoff_t page_offset;
1877 /* We don't use vmf->pgoff since that has the fake offset */
1878 page_offset = (vmf->address - area->vm_start) >> PAGE_SHIFT;
1880 trace_i915_gem_object_fault(obj, page_offset, true, write);
1882 /* Try to flush the object off the GPU first without holding the lock.
1883 * Upon acquiring the lock, we will perform our sanity checks and then
1884 * repeat the flush holding the lock in the normal manner to catch cases
1885 * where we are gazumped.
1887 ret = i915_gem_object_wait(obj,
1888 I915_WAIT_INTERRUPTIBLE,
1889 MAX_SCHEDULE_TIMEOUT,
1894 ret = i915_gem_object_pin_pages(obj);
1898 intel_runtime_pm_get(dev_priv);
1900 ret = i915_mutex_lock_interruptible(dev);
1904 /* Access to snoopable pages through the GTT is incoherent. */
1905 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv)) {
1910 /* If the object is smaller than a couple of partial vma, it is
1911 * not worth only creating a single partial vma - we may as well
1912 * clear enough space for the full object.
1914 flags = PIN_MAPPABLE;
1915 if (obj->base.size > 2 * MIN_CHUNK_PAGES << PAGE_SHIFT)
1916 flags |= PIN_NONBLOCK | PIN_NONFAULT;
1918 /* Now pin it into the GTT as needed */
1919 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, flags);
1921 /* Use a partial view if it is bigger than available space */
1922 struct i915_ggtt_view view =
1923 compute_partial_view(obj, page_offset, MIN_CHUNK_PAGES);
1925 /* Userspace is now writing through an untracked VMA, abandon
1926 * all hope that the hardware is able to track future writes.
1928 obj->frontbuffer_ggtt_origin = ORIGIN_CPU;
1930 vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, PIN_MAPPABLE);
1937 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1941 ret = i915_vma_get_fence(vma);
1945 /* Mark as being mmapped into userspace for later revocation */
1946 assert_rpm_wakelock_held(dev_priv);
1947 if (list_empty(&obj->userfault_link))
1948 list_add(&obj->userfault_link, &dev_priv->mm.userfault_list);
1950 /* Finally, remap it using the new GTT offset */
1951 ret = remap_io_mapping(area,
1952 area->vm_start + (vma->ggtt_view.partial.offset << PAGE_SHIFT),
1953 (ggtt->mappable_base + vma->node.start) >> PAGE_SHIFT,
1954 min_t(u64, vma->size, area->vm_end - area->vm_start),
1958 __i915_vma_unpin(vma);
1960 mutex_unlock(&dev->struct_mutex);
1962 intel_runtime_pm_put(dev_priv);
1963 i915_gem_object_unpin_pages(obj);
1968 * We eat errors when the gpu is terminally wedged to avoid
1969 * userspace unduly crashing (gl has no provisions for mmaps to
1970 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1971 * and so needs to be reported.
1973 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1974 ret = VM_FAULT_SIGBUS;
1979 * EAGAIN means the gpu is hung and we'll wait for the error
1980 * handler to reset everything when re-faulting in
1981 * i915_mutex_lock_interruptible.
1988 * EBUSY is ok: this just means that another thread
1989 * already did the job.
1991 ret = VM_FAULT_NOPAGE;
1998 ret = VM_FAULT_SIGBUS;
2001 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
2002 ret = VM_FAULT_SIGBUS;
2009 * i915_gem_release_mmap - remove physical page mappings
2010 * @obj: obj in question
2012 * Preserve the reservation of the mmapping with the DRM core code, but
2013 * relinquish ownership of the pages back to the system.
2015 * It is vital that we remove the page mapping if we have mapped a tiled
2016 * object through the GTT and then lose the fence register due to
2017 * resource pressure. Similarly if the object has been moved out of the
2018 * aperture, than pages mapped into userspace must be revoked. Removing the
2019 * mapping will then trigger a page fault on the next user access, allowing
2020 * fixup by i915_gem_fault().
2023 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
2025 struct drm_i915_private *i915 = to_i915(obj->base.dev);
2027 /* Serialisation between user GTT access and our code depends upon
2028 * revoking the CPU's PTE whilst the mutex is held. The next user
2029 * pagefault then has to wait until we release the mutex.
2031 * Note that RPM complicates somewhat by adding an additional
2032 * requirement that operations to the GGTT be made holding the RPM
2035 lockdep_assert_held(&i915->drm.struct_mutex);
2036 intel_runtime_pm_get(i915);
2038 if (list_empty(&obj->userfault_link))
2041 list_del_init(&obj->userfault_link);
2042 drm_vma_node_unmap(&obj->base.vma_node,
2043 obj->base.dev->anon_inode->i_mapping);
2045 /* Ensure that the CPU's PTE are revoked and there are not outstanding
2046 * memory transactions from userspace before we return. The TLB
2047 * flushing implied above by changing the PTE above *should* be
2048 * sufficient, an extra barrier here just provides us with a bit
2049 * of paranoid documentation about our requirement to serialise
2050 * memory writes before touching registers / GSM.
2055 intel_runtime_pm_put(i915);
2058 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv)
2060 struct drm_i915_gem_object *obj, *on;
2064 * Only called during RPM suspend. All users of the userfault_list
2065 * must be holding an RPM wakeref to ensure that this can not
2066 * run concurrently with themselves (and use the struct_mutex for
2067 * protection between themselves).
2070 list_for_each_entry_safe(obj, on,
2071 &dev_priv->mm.userfault_list, userfault_link) {
2072 list_del_init(&obj->userfault_link);
2073 drm_vma_node_unmap(&obj->base.vma_node,
2074 obj->base.dev->anon_inode->i_mapping);
2077 /* The fence will be lost when the device powers down. If any were
2078 * in use by hardware (i.e. they are pinned), we should not be powering
2079 * down! All other fences will be reacquired by the user upon waking.
2081 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2082 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2084 /* Ideally we want to assert that the fence register is not
2085 * live at this point (i.e. that no piece of code will be
2086 * trying to write through fence + GTT, as that both violates
2087 * our tracking of activity and associated locking/barriers,
2088 * but also is illegal given that the hw is powered down).
2090 * Previously we used reg->pin_count as a "liveness" indicator.
2091 * That is not sufficient, and we need a more fine-grained
2092 * tool if we want to have a sanity check here.
2098 GEM_BUG_ON(!list_empty(®->vma->obj->userfault_link));
2103 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
2105 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
2108 err = drm_gem_create_mmap_offset(&obj->base);
2112 /* Attempt to reap some mmap space from dead objects */
2114 err = i915_gem_wait_for_idle(dev_priv, I915_WAIT_INTERRUPTIBLE);
2118 i915_gem_drain_freed_objects(dev_priv);
2119 err = drm_gem_create_mmap_offset(&obj->base);
2123 } while (flush_delayed_work(&dev_priv->gt.retire_work));
2128 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
2130 drm_gem_free_mmap_offset(&obj->base);
2134 i915_gem_mmap_gtt(struct drm_file *file,
2135 struct drm_device *dev,
2139 struct drm_i915_gem_object *obj;
2142 obj = i915_gem_object_lookup(file, handle);
2146 ret = i915_gem_object_create_mmap_offset(obj);
2148 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
2150 i915_gem_object_put(obj);
2155 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2157 * @data: GTT mapping ioctl data
2158 * @file: GEM object info
2160 * Simply returns the fake offset to userspace so it can mmap it.
2161 * The mmap call will end up in drm_gem_mmap(), which will set things
2162 * up so we can get faults in the handler above.
2164 * The fault handler will take care of binding the object into the GTT
2165 * (since it may have been evicted to make room for something), allocating
2166 * a fence register, and mapping the appropriate aperture address into
2170 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2171 struct drm_file *file)
2173 struct drm_i915_gem_mmap_gtt *args = data;
2175 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
2178 /* Immediately discard the backing storage */
2180 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
2182 i915_gem_object_free_mmap_offset(obj);
2184 if (obj->base.filp == NULL)
2187 /* Our goal here is to return as much of the memory as
2188 * is possible back to the system as we are called from OOM.
2189 * To do this we must instruct the shmfs to drop all of its
2190 * backing pages, *now*.
2192 shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
2193 obj->mm.madv = __I915_MADV_PURGED;
2194 obj->mm.pages = ERR_PTR(-EFAULT);
2197 /* Try to discard unwanted pages */
2198 void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
2200 struct address_space *mapping;
2202 lockdep_assert_held(&obj->mm.lock);
2203 GEM_BUG_ON(obj->mm.pages);
2205 switch (obj->mm.madv) {
2206 case I915_MADV_DONTNEED:
2207 i915_gem_object_truncate(obj);
2208 case __I915_MADV_PURGED:
2212 if (obj->base.filp == NULL)
2215 mapping = obj->base.filp->f_mapping,
2216 invalidate_mapping_pages(mapping, 0, (loff_t)-1);
2220 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj,
2221 struct sg_table *pages)
2223 struct sgt_iter sgt_iter;
2226 __i915_gem_object_release_shmem(obj, pages, true);
2228 i915_gem_gtt_finish_pages(obj, pages);
2230 if (i915_gem_object_needs_bit17_swizzle(obj))
2231 i915_gem_object_save_bit_17_swizzle(obj, pages);
2233 for_each_sgt_page(page, sgt_iter, pages) {
2235 set_page_dirty(page);
2237 if (obj->mm.madv == I915_MADV_WILLNEED)
2238 mark_page_accessed(page);
2242 obj->mm.dirty = false;
2244 sg_free_table(pages);
2248 static void __i915_gem_object_reset_page_iter(struct drm_i915_gem_object *obj)
2250 struct radix_tree_iter iter;
2253 radix_tree_for_each_slot(slot, &obj->mm.get_page.radix, &iter, 0)
2254 radix_tree_delete(&obj->mm.get_page.radix, iter.index);
2257 void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
2258 enum i915_mm_subclass subclass)
2260 struct sg_table *pages;
2262 if (i915_gem_object_has_pinned_pages(obj))
2265 GEM_BUG_ON(obj->bind_count);
2266 if (!READ_ONCE(obj->mm.pages))
2269 /* May be called by shrinker from within get_pages() (on another bo) */
2270 mutex_lock_nested(&obj->mm.lock, subclass);
2271 if (unlikely(atomic_read(&obj->mm.pages_pin_count)))
2274 /* ->put_pages might need to allocate memory for the bit17 swizzle
2275 * array, hence protect them from being reaped by removing them from gtt
2277 pages = fetch_and_zero(&obj->mm.pages);
2280 if (obj->mm.mapping) {
2283 ptr = page_mask_bits(obj->mm.mapping);
2284 if (is_vmalloc_addr(ptr))
2287 kunmap(kmap_to_page(ptr));
2289 obj->mm.mapping = NULL;
2292 __i915_gem_object_reset_page_iter(obj);
2295 obj->ops->put_pages(obj, pages);
2298 mutex_unlock(&obj->mm.lock);
2301 static bool i915_sg_trim(struct sg_table *orig_st)
2303 struct sg_table new_st;
2304 struct scatterlist *sg, *new_sg;
2307 if (orig_st->nents == orig_st->orig_nents)
2310 if (sg_alloc_table(&new_st, orig_st->nents, GFP_KERNEL | __GFP_NOWARN))
2313 new_sg = new_st.sgl;
2314 for_each_sg(orig_st->sgl, sg, orig_st->nents, i) {
2315 sg_set_page(new_sg, sg_page(sg), sg->length, 0);
2316 /* called before being DMA mapped, no need to copy sg->dma_* */
2317 new_sg = sg_next(new_sg);
2319 GEM_BUG_ON(new_sg); /* Should walk exactly nents and hit the end */
2321 sg_free_table(orig_st);
2327 static struct sg_table *
2328 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2330 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
2331 const unsigned long page_count = obj->base.size / PAGE_SIZE;
2333 struct address_space *mapping;
2334 struct sg_table *st;
2335 struct scatterlist *sg;
2336 struct sgt_iter sgt_iter;
2338 unsigned long last_pfn = 0; /* suppress gcc warning */
2339 unsigned int max_segment;
2343 /* Assert that the object is not currently in any GPU domain. As it
2344 * wasn't in the GTT, there shouldn't be any way it could have been in
2347 GEM_BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2348 GEM_BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2350 max_segment = swiotlb_max_segment();
2352 max_segment = rounddown(UINT_MAX, PAGE_SIZE);
2354 st = kmalloc(sizeof(*st), GFP_KERNEL);
2356 return ERR_PTR(-ENOMEM);
2359 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2361 return ERR_PTR(-ENOMEM);
2364 /* Get the list of pages out of our struct file. They'll be pinned
2365 * at this point until we release them.
2367 * Fail silently without starting the shrinker
2369 mapping = obj->base.filp->f_mapping;
2370 gfp = mapping_gfp_constraint(mapping, ~(__GFP_IO | __GFP_RECLAIM));
2371 gfp |= __GFP_NORETRY | __GFP_NOWARN;
2374 for (i = 0; i < page_count; i++) {
2375 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2376 if (unlikely(IS_ERR(page))) {
2377 i915_gem_shrink(dev_priv,
2380 I915_SHRINK_UNBOUND |
2381 I915_SHRINK_PURGEABLE);
2382 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2384 if (unlikely(IS_ERR(page))) {
2387 /* We've tried hard to allocate the memory by reaping
2388 * our own buffer, now let the real VM do its job and
2389 * go down in flames if truly OOM.
2391 * However, since graphics tend to be disposable,
2392 * defer the oom here by reporting the ENOMEM back
2395 reclaim = mapping_gfp_mask(mapping);
2396 reclaim |= __GFP_NORETRY; /* reclaim, but no oom */
2398 page = shmem_read_mapping_page_gfp(mapping, i, reclaim);
2400 ret = PTR_ERR(page);
2405 sg->length >= max_segment ||
2406 page_to_pfn(page) != last_pfn + 1) {
2410 sg_set_page(sg, page, PAGE_SIZE, 0);
2412 sg->length += PAGE_SIZE;
2414 last_pfn = page_to_pfn(page);
2416 /* Check that the i965g/gm workaround works. */
2417 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2419 if (sg) /* loop terminated early; short sg table */
2422 /* Trim unused sg entries to avoid wasting memory. */
2425 ret = i915_gem_gtt_prepare_pages(obj, st);
2427 /* DMA remapping failed? One possible cause is that
2428 * it could not reserve enough large entries, asking
2429 * for PAGE_SIZE chunks instead may be helpful.
2431 if (max_segment > PAGE_SIZE) {
2432 for_each_sgt_page(page, sgt_iter, st)
2436 max_segment = PAGE_SIZE;
2439 dev_warn(&dev_priv->drm.pdev->dev,
2440 "Failed to DMA remap %lu pages\n",
2446 if (i915_gem_object_needs_bit17_swizzle(obj))
2447 i915_gem_object_do_bit_17_swizzle(obj, st);
2454 for_each_sgt_page(page, sgt_iter, st)
2459 /* shmemfs first checks if there is enough memory to allocate the page
2460 * and reports ENOSPC should there be insufficient, along with the usual
2461 * ENOMEM for a genuine allocation failure.
2463 * We use ENOSPC in our driver to mean that we have run out of aperture
2464 * space and so want to translate the error from shmemfs back to our
2465 * usual understanding of ENOMEM.
2470 return ERR_PTR(ret);
2473 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
2474 struct sg_table *pages)
2476 lockdep_assert_held(&obj->mm.lock);
2478 obj->mm.get_page.sg_pos = pages->sgl;
2479 obj->mm.get_page.sg_idx = 0;
2481 obj->mm.pages = pages;
2483 if (i915_gem_object_is_tiled(obj) &&
2484 to_i915(obj->base.dev)->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
2485 GEM_BUG_ON(obj->mm.quirked);
2486 __i915_gem_object_pin_pages(obj);
2487 obj->mm.quirked = true;
2491 static int ____i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2493 struct sg_table *pages;
2495 GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj));
2497 if (unlikely(obj->mm.madv != I915_MADV_WILLNEED)) {
2498 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2502 pages = obj->ops->get_pages(obj);
2503 if (unlikely(IS_ERR(pages)))
2504 return PTR_ERR(pages);
2506 __i915_gem_object_set_pages(obj, pages);
2510 /* Ensure that the associated pages are gathered from the backing storage
2511 * and pinned into our object. i915_gem_object_pin_pages() may be called
2512 * multiple times before they are released by a single call to
2513 * i915_gem_object_unpin_pages() - once the pages are no longer referenced
2514 * either as a result of memory pressure (reaping pages under the shrinker)
2515 * or as the object is itself released.
2517 int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2521 err = mutex_lock_interruptible(&obj->mm.lock);
2525 if (unlikely(IS_ERR_OR_NULL(obj->mm.pages))) {
2526 err = ____i915_gem_object_get_pages(obj);
2530 smp_mb__before_atomic();
2532 atomic_inc(&obj->mm.pages_pin_count);
2535 mutex_unlock(&obj->mm.lock);
2539 /* The 'mapping' part of i915_gem_object_pin_map() below */
2540 static void *i915_gem_object_map(const struct drm_i915_gem_object *obj,
2541 enum i915_map_type type)
2543 unsigned long n_pages = obj->base.size >> PAGE_SHIFT;
2544 struct sg_table *sgt = obj->mm.pages;
2545 struct sgt_iter sgt_iter;
2547 struct page *stack_pages[32];
2548 struct page **pages = stack_pages;
2549 unsigned long i = 0;
2553 /* A single page can always be kmapped */
2554 if (n_pages == 1 && type == I915_MAP_WB)
2555 return kmap(sg_page(sgt->sgl));
2557 if (n_pages > ARRAY_SIZE(stack_pages)) {
2558 /* Too big for stack -- allocate temporary array instead */
2559 pages = kvmalloc_array(n_pages, sizeof(*pages), GFP_TEMPORARY);
2564 for_each_sgt_page(page, sgt_iter, sgt)
2567 /* Check that we have the expected number of pages */
2568 GEM_BUG_ON(i != n_pages);
2572 pgprot = PAGE_KERNEL;
2575 pgprot = pgprot_writecombine(PAGE_KERNEL_IO);
2578 addr = vmap(pages, n_pages, 0, pgprot);
2580 if (pages != stack_pages)
2586 /* get, pin, and map the pages of the object into kernel space */
2587 void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
2588 enum i915_map_type type)
2590 enum i915_map_type has_type;
2595 GEM_BUG_ON(!i915_gem_object_has_struct_page(obj));
2597 ret = mutex_lock_interruptible(&obj->mm.lock);
2599 return ERR_PTR(ret);
2602 if (!atomic_inc_not_zero(&obj->mm.pages_pin_count)) {
2603 if (unlikely(IS_ERR_OR_NULL(obj->mm.pages))) {
2604 ret = ____i915_gem_object_get_pages(obj);
2608 smp_mb__before_atomic();
2610 atomic_inc(&obj->mm.pages_pin_count);
2613 GEM_BUG_ON(!obj->mm.pages);
2615 ptr = page_unpack_bits(obj->mm.mapping, &has_type);
2616 if (ptr && has_type != type) {
2622 if (is_vmalloc_addr(ptr))
2625 kunmap(kmap_to_page(ptr));
2627 ptr = obj->mm.mapping = NULL;
2631 ptr = i915_gem_object_map(obj, type);
2637 obj->mm.mapping = page_pack_bits(ptr, type);
2641 mutex_unlock(&obj->mm.lock);
2645 atomic_dec(&obj->mm.pages_pin_count);
2652 i915_gem_object_pwrite_gtt(struct drm_i915_gem_object *obj,
2653 const struct drm_i915_gem_pwrite *arg)
2655 struct address_space *mapping = obj->base.filp->f_mapping;
2656 char __user *user_data = u64_to_user_ptr(arg->data_ptr);
2660 /* Before we instantiate/pin the backing store for our use, we
2661 * can prepopulate the shmemfs filp efficiently using a write into
2662 * the pagecache. We avoid the penalty of instantiating all the
2663 * pages, important if the user is just writing to a few and never
2664 * uses the object on the GPU, and using a direct write into shmemfs
2665 * allows it to avoid the cost of retrieving a page (either swapin
2666 * or clearing-before-use) before it is overwritten.
2668 if (READ_ONCE(obj->mm.pages))
2671 /* Before the pages are instantiated the object is treated as being
2672 * in the CPU domain. The pages will be clflushed as required before
2673 * use, and we can freely write into the pages directly. If userspace
2674 * races pwrite with any other operation; corruption will ensue -
2675 * that is userspace's prerogative!
2679 offset = arg->offset;
2680 pg = offset_in_page(offset);
2683 unsigned int len, unwritten;
2688 len = PAGE_SIZE - pg;
2692 err = pagecache_write_begin(obj->base.filp, mapping,
2699 unwritten = copy_from_user(vaddr + pg, user_data, len);
2702 err = pagecache_write_end(obj->base.filp, mapping,
2703 offset, len, len - unwritten,
2720 static bool ban_context(const struct i915_gem_context *ctx)
2722 return (i915_gem_context_is_bannable(ctx) &&
2723 ctx->ban_score >= CONTEXT_SCORE_BAN_THRESHOLD);
2726 static void i915_gem_context_mark_guilty(struct i915_gem_context *ctx)
2728 ctx->guilty_count++;
2729 ctx->ban_score += CONTEXT_SCORE_GUILTY;
2730 if (ban_context(ctx))
2731 i915_gem_context_set_banned(ctx);
2733 DRM_DEBUG_DRIVER("context %s marked guilty (score %d) banned? %s\n",
2734 ctx->name, ctx->ban_score,
2735 yesno(i915_gem_context_is_banned(ctx)));
2737 if (!i915_gem_context_is_banned(ctx) || IS_ERR_OR_NULL(ctx->file_priv))
2740 ctx->file_priv->context_bans++;
2741 DRM_DEBUG_DRIVER("client %s has had %d context banned\n",
2742 ctx->name, ctx->file_priv->context_bans);
2745 static void i915_gem_context_mark_innocent(struct i915_gem_context *ctx)
2747 ctx->active_count++;
2750 struct drm_i915_gem_request *
2751 i915_gem_find_active_request(struct intel_engine_cs *engine)
2753 struct drm_i915_gem_request *request, *active = NULL;
2754 unsigned long flags;
2756 /* We are called by the error capture and reset at a random
2757 * point in time. In particular, note that neither is crucially
2758 * ordered with an interrupt. After a hang, the GPU is dead and we
2759 * assume that no more writes can happen (we waited long enough for
2760 * all writes that were in transaction to be flushed) - adding an
2761 * extra delay for a recent interrupt is pointless. Hence, we do
2762 * not need an engine->irq_seqno_barrier() before the seqno reads.
2764 spin_lock_irqsave(&engine->timeline->lock, flags);
2765 list_for_each_entry(request, &engine->timeline->requests, link) {
2766 if (__i915_gem_request_completed(request,
2767 request->global_seqno))
2770 GEM_BUG_ON(request->engine != engine);
2771 GEM_BUG_ON(test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
2772 &request->fence.flags));
2777 spin_unlock_irqrestore(&engine->timeline->lock, flags);
2782 static bool engine_stalled(struct intel_engine_cs *engine)
2784 if (!engine->hangcheck.stalled)
2787 /* Check for possible seqno movement after hang declaration */
2788 if (engine->hangcheck.seqno != intel_engine_get_seqno(engine)) {
2789 DRM_DEBUG_DRIVER("%s pardoned\n", engine->name);
2796 int i915_gem_reset_prepare(struct drm_i915_private *dev_priv)
2798 struct intel_engine_cs *engine;
2799 enum intel_engine_id id;
2802 /* Ensure irq handler finishes, and not run again. */
2803 for_each_engine(engine, dev_priv, id) {
2804 struct drm_i915_gem_request *request;
2806 /* Prevent the signaler thread from updating the request
2807 * state (by calling dma_fence_signal) as we are processing
2808 * the reset. The write from the GPU of the seqno is
2809 * asynchronous and the signaler thread may see a different
2810 * value to us and declare the request complete, even though
2811 * the reset routine have picked that request as the active
2812 * (incomplete) request. This conflict is not handled
2815 kthread_park(engine->breadcrumbs.signaler);
2817 /* Prevent request submission to the hardware until we have
2818 * completed the reset in i915_gem_reset_finish(). If a request
2819 * is completed by one engine, it may then queue a request
2820 * to a second via its engine->irq_tasklet *just* as we are
2821 * calling engine->init_hw() and also writing the ELSP.
2822 * Turning off the engine->irq_tasklet until the reset is over
2823 * prevents the race.
2825 tasklet_kill(&engine->irq_tasklet);
2826 tasklet_disable(&engine->irq_tasklet);
2828 if (engine->irq_seqno_barrier)
2829 engine->irq_seqno_barrier(engine);
2831 if (engine_stalled(engine)) {
2832 request = i915_gem_find_active_request(engine);
2833 if (request && request->fence.error == -EIO)
2834 err = -EIO; /* Previous reset failed! */
2838 i915_gem_revoke_fences(dev_priv);
2843 static void skip_request(struct drm_i915_gem_request *request)
2845 void *vaddr = request->ring->vaddr;
2848 /* As this request likely depends on state from the lost
2849 * context, clear out all the user operations leaving the
2850 * breadcrumb at the end (so we get the fence notifications).
2852 head = request->head;
2853 if (request->postfix < head) {
2854 memset(vaddr + head, 0, request->ring->size - head);
2857 memset(vaddr + head, 0, request->postfix - head);
2859 dma_fence_set_error(&request->fence, -EIO);
2862 static void engine_skip_context(struct drm_i915_gem_request *request)
2864 struct intel_engine_cs *engine = request->engine;
2865 struct i915_gem_context *hung_ctx = request->ctx;
2866 struct intel_timeline *timeline;
2867 unsigned long flags;
2869 timeline = i915_gem_context_lookup_timeline(hung_ctx, engine);
2871 spin_lock_irqsave(&engine->timeline->lock, flags);
2872 spin_lock(&timeline->lock);
2874 list_for_each_entry_continue(request, &engine->timeline->requests, link)
2875 if (request->ctx == hung_ctx)
2876 skip_request(request);
2878 list_for_each_entry(request, &timeline->requests, link)
2879 skip_request(request);
2881 spin_unlock(&timeline->lock);
2882 spin_unlock_irqrestore(&engine->timeline->lock, flags);
2885 /* Returns true if the request was guilty of hang */
2886 static bool i915_gem_reset_request(struct drm_i915_gem_request *request)
2888 /* Read once and return the resolution */
2889 const bool guilty = engine_stalled(request->engine);
2891 /* The guilty request will get skipped on a hung engine.
2893 * Users of client default contexts do not rely on logical
2894 * state preserved between batches so it is safe to execute
2895 * queued requests following the hang. Non default contexts
2896 * rely on preserved state, so skipping a batch loses the
2897 * evolution of the state and it needs to be considered corrupted.
2898 * Executing more queued batches on top of corrupted state is
2899 * risky. But we take the risk by trying to advance through
2900 * the queued requests in order to make the client behaviour
2901 * more predictable around resets, by not throwing away random
2902 * amount of batches it has prepared for execution. Sophisticated
2903 * clients can use gem_reset_stats_ioctl and dma fence status
2904 * (exported via sync_file info ioctl on explicit fences) to observe
2905 * when it loses the context state and should rebuild accordingly.
2907 * The context ban, and ultimately the client ban, mechanism are safety
2908 * valves if client submission ends up resulting in nothing more than
2913 i915_gem_context_mark_guilty(request->ctx);
2914 skip_request(request);
2916 i915_gem_context_mark_innocent(request->ctx);
2917 dma_fence_set_error(&request->fence, -EAGAIN);
2923 static void i915_gem_reset_engine(struct intel_engine_cs *engine)
2925 struct drm_i915_gem_request *request;
2927 request = i915_gem_find_active_request(engine);
2928 if (request && i915_gem_reset_request(request)) {
2929 DRM_DEBUG_DRIVER("resetting %s to restart from tail of request 0x%x\n",
2930 engine->name, request->global_seqno);
2932 /* If this context is now banned, skip all pending requests. */
2933 if (i915_gem_context_is_banned(request->ctx))
2934 engine_skip_context(request);
2937 /* Setup the CS to resume from the breadcrumb of the hung request */
2938 engine->reset_hw(engine, request);
2941 void i915_gem_reset(struct drm_i915_private *dev_priv)
2943 struct intel_engine_cs *engine;
2944 enum intel_engine_id id;
2946 lockdep_assert_held(&dev_priv->drm.struct_mutex);
2948 i915_gem_retire_requests(dev_priv);
2950 for_each_engine(engine, dev_priv, id) {
2951 struct i915_gem_context *ctx;
2953 i915_gem_reset_engine(engine);
2954 ctx = fetch_and_zero(&engine->last_retired_context);
2956 engine->context_unpin(engine, ctx);
2959 i915_gem_restore_fences(dev_priv);
2961 if (dev_priv->gt.awake) {
2962 intel_sanitize_gt_powersave(dev_priv);
2963 intel_enable_gt_powersave(dev_priv);
2964 if (INTEL_GEN(dev_priv) >= 6)
2965 gen6_rps_busy(dev_priv);
2969 void i915_gem_reset_finish(struct drm_i915_private *dev_priv)
2971 struct intel_engine_cs *engine;
2972 enum intel_engine_id id;
2974 lockdep_assert_held(&dev_priv->drm.struct_mutex);
2976 for_each_engine(engine, dev_priv, id) {
2977 tasklet_enable(&engine->irq_tasklet);
2978 kthread_unpark(engine->breadcrumbs.signaler);
2982 static void nop_submit_request(struct drm_i915_gem_request *request)
2984 dma_fence_set_error(&request->fence, -EIO);
2985 i915_gem_request_submit(request);
2986 intel_engine_init_global_seqno(request->engine, request->global_seqno);
2989 static void engine_set_wedged(struct intel_engine_cs *engine)
2991 struct drm_i915_gem_request *request;
2992 unsigned long flags;
2994 /* We need to be sure that no thread is running the old callback as
2995 * we install the nop handler (otherwise we would submit a request
2996 * to hardware that will never complete). In order to prevent this
2997 * race, we wait until the machine is idle before making the swap
2998 * (using stop_machine()).
3000 engine->submit_request = nop_submit_request;
3002 /* Mark all executing requests as skipped */
3003 spin_lock_irqsave(&engine->timeline->lock, flags);
3004 list_for_each_entry(request, &engine->timeline->requests, link)
3005 dma_fence_set_error(&request->fence, -EIO);
3006 spin_unlock_irqrestore(&engine->timeline->lock, flags);
3008 /* Mark all pending requests as complete so that any concurrent
3009 * (lockless) lookup doesn't try and wait upon the request as we
3012 intel_engine_init_global_seqno(engine,
3013 intel_engine_last_submit(engine));
3016 * Clear the execlists queue up before freeing the requests, as those
3017 * are the ones that keep the context and ringbuffer backing objects
3021 if (i915.enable_execlists) {
3022 struct execlist_port *port = engine->execlist_port;
3023 unsigned long flags;
3026 spin_lock_irqsave(&engine->timeline->lock, flags);
3028 for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++)
3029 i915_gem_request_put(port_request(&port[n]));
3030 memset(engine->execlist_port, 0, sizeof(engine->execlist_port));
3031 engine->execlist_queue = RB_ROOT;
3032 engine->execlist_first = NULL;
3034 spin_unlock_irqrestore(&engine->timeline->lock, flags);
3038 static int __i915_gem_set_wedged_BKL(void *data)
3040 struct drm_i915_private *i915 = data;
3041 struct intel_engine_cs *engine;
3042 enum intel_engine_id id;
3044 for_each_engine(engine, i915, id)
3045 engine_set_wedged(engine);
3050 void i915_gem_set_wedged(struct drm_i915_private *dev_priv)
3052 lockdep_assert_held(&dev_priv->drm.struct_mutex);
3053 set_bit(I915_WEDGED, &dev_priv->gpu_error.flags);
3055 /* Retire completed requests first so the list of inflight/incomplete
3056 * requests is accurate and we don't try and mark successful requests
3057 * as in error during __i915_gem_set_wedged_BKL().
3059 i915_gem_retire_requests(dev_priv);
3061 stop_machine(__i915_gem_set_wedged_BKL, dev_priv, NULL);
3063 i915_gem_context_lost(dev_priv);
3065 mod_delayed_work(dev_priv->wq, &dev_priv->gt.idle_work, 0);
3068 bool i915_gem_unset_wedged(struct drm_i915_private *i915)
3070 struct i915_gem_timeline *tl;
3073 lockdep_assert_held(&i915->drm.struct_mutex);
3074 if (!test_bit(I915_WEDGED, &i915->gpu_error.flags))
3077 /* Before unwedging, make sure that all pending operations
3078 * are flushed and errored out - we may have requests waiting upon
3079 * third party fences. We marked all inflight requests as EIO, and
3080 * every execbuf since returned EIO, for consistency we want all
3081 * the currently pending requests to also be marked as EIO, which
3082 * is done inside our nop_submit_request - and so we must wait.
3084 * No more can be submitted until we reset the wedged bit.
3086 list_for_each_entry(tl, &i915->gt.timelines, link) {
3087 for (i = 0; i < ARRAY_SIZE(tl->engine); i++) {
3088 struct drm_i915_gem_request *rq;
3090 rq = i915_gem_active_peek(&tl->engine[i].last_request,
3091 &i915->drm.struct_mutex);
3095 /* We can't use our normal waiter as we want to
3096 * avoid recursively trying to handle the current
3097 * reset. The basic dma_fence_default_wait() installs
3098 * a callback for dma_fence_signal(), which is
3099 * triggered by our nop handler (indirectly, the
3100 * callback enables the signaler thread which is
3101 * woken by the nop_submit_request() advancing the seqno
3102 * and when the seqno passes the fence, the signaler
3103 * then signals the fence waking us up).
3105 if (dma_fence_default_wait(&rq->fence, true,
3106 MAX_SCHEDULE_TIMEOUT) < 0)
3111 /* Undo nop_submit_request. We prevent all new i915 requests from
3112 * being queued (by disallowing execbuf whilst wedged) so having
3113 * waited for all active requests above, we know the system is idle
3114 * and do not have to worry about a thread being inside
3115 * engine->submit_request() as we swap over. So unlike installing
3116 * the nop_submit_request on reset, we can do this from normal
3117 * context and do not require stop_machine().
3119 intel_engines_reset_default_submission(i915);
3121 smp_mb__before_atomic(); /* complete takeover before enabling execbuf */
3122 clear_bit(I915_WEDGED, &i915->gpu_error.flags);
3128 i915_gem_retire_work_handler(struct work_struct *work)
3130 struct drm_i915_private *dev_priv =
3131 container_of(work, typeof(*dev_priv), gt.retire_work.work);
3132 struct drm_device *dev = &dev_priv->drm;
3134 /* Come back later if the device is busy... */
3135 if (mutex_trylock(&dev->struct_mutex)) {
3136 i915_gem_retire_requests(dev_priv);
3137 mutex_unlock(&dev->struct_mutex);
3140 /* Keep the retire handler running until we are finally idle.
3141 * We do not need to do this test under locking as in the worst-case
3142 * we queue the retire worker once too often.
3144 if (READ_ONCE(dev_priv->gt.awake)) {
3145 i915_queue_hangcheck(dev_priv);
3146 queue_delayed_work(dev_priv->wq,
3147 &dev_priv->gt.retire_work,
3148 round_jiffies_up_relative(HZ));
3153 i915_gem_idle_work_handler(struct work_struct *work)
3155 struct drm_i915_private *dev_priv =
3156 container_of(work, typeof(*dev_priv), gt.idle_work.work);
3157 struct drm_device *dev = &dev_priv->drm;
3158 bool rearm_hangcheck;
3160 if (!READ_ONCE(dev_priv->gt.awake))
3164 * Wait for last execlists context complete, but bail out in case a
3165 * new request is submitted.
3167 wait_for(intel_engines_are_idle(dev_priv), 10);
3168 if (READ_ONCE(dev_priv->gt.active_requests))
3172 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
3174 if (!mutex_trylock(&dev->struct_mutex)) {
3175 /* Currently busy, come back later */
3176 mod_delayed_work(dev_priv->wq,
3177 &dev_priv->gt.idle_work,
3178 msecs_to_jiffies(50));
3183 * New request retired after this work handler started, extend active
3184 * period until next instance of the work.
3186 if (work_pending(work))
3189 if (dev_priv->gt.active_requests)
3192 if (wait_for(intel_engines_are_idle(dev_priv), 10))
3193 DRM_ERROR("Timeout waiting for engines to idle\n");
3195 intel_engines_mark_idle(dev_priv);
3196 i915_gem_timelines_mark_idle(dev_priv);
3198 GEM_BUG_ON(!dev_priv->gt.awake);
3199 dev_priv->gt.awake = false;
3200 rearm_hangcheck = false;
3202 if (INTEL_GEN(dev_priv) >= 6)
3203 gen6_rps_idle(dev_priv);
3204 intel_runtime_pm_put(dev_priv);
3206 mutex_unlock(&dev->struct_mutex);
3209 if (rearm_hangcheck) {
3210 GEM_BUG_ON(!dev_priv->gt.awake);
3211 i915_queue_hangcheck(dev_priv);
3215 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file)
3217 struct drm_i915_gem_object *obj = to_intel_bo(gem);
3218 struct drm_i915_file_private *fpriv = file->driver_priv;
3219 struct i915_vma *vma, *vn;
3221 mutex_lock(&obj->base.dev->struct_mutex);
3222 list_for_each_entry_safe(vma, vn, &obj->vma_list, obj_link)
3223 if (vma->vm->file == fpriv)
3224 i915_vma_close(vma);
3226 if (i915_gem_object_is_active(obj) &&
3227 !i915_gem_object_has_active_reference(obj)) {
3228 i915_gem_object_set_active_reference(obj);
3229 i915_gem_object_get(obj);
3231 mutex_unlock(&obj->base.dev->struct_mutex);
3234 static unsigned long to_wait_timeout(s64 timeout_ns)
3237 return MAX_SCHEDULE_TIMEOUT;
3239 if (timeout_ns == 0)
3242 return nsecs_to_jiffies_timeout(timeout_ns);
3246 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
3247 * @dev: drm device pointer
3248 * @data: ioctl data blob
3249 * @file: drm file pointer
3251 * Returns 0 if successful, else an error is returned with the remaining time in
3252 * the timeout parameter.
3253 * -ETIME: object is still busy after timeout
3254 * -ERESTARTSYS: signal interrupted the wait
3255 * -ENONENT: object doesn't exist
3256 * Also possible, but rare:
3257 * -EAGAIN: GPU wedged
3259 * -ENODEV: Internal IRQ fail
3260 * -E?: The add request failed
3262 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
3263 * non-zero timeout parameter the wait ioctl will wait for the given number of
3264 * nanoseconds on an object becoming unbusy. Since the wait itself does so
3265 * without holding struct_mutex the object may become re-busied before this
3266 * function completes. A similar but shorter * race condition exists in the busy
3270 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
3272 struct drm_i915_gem_wait *args = data;
3273 struct drm_i915_gem_object *obj;
3277 if (args->flags != 0)
3280 obj = i915_gem_object_lookup(file, args->bo_handle);
3284 start = ktime_get();
3286 ret = i915_gem_object_wait(obj,
3287 I915_WAIT_INTERRUPTIBLE | I915_WAIT_ALL,
3288 to_wait_timeout(args->timeout_ns),
3289 to_rps_client(file));
3291 if (args->timeout_ns > 0) {
3292 args->timeout_ns -= ktime_to_ns(ktime_sub(ktime_get(), start));
3293 if (args->timeout_ns < 0)
3294 args->timeout_ns = 0;
3297 * Apparently ktime isn't accurate enough and occasionally has a
3298 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
3299 * things up to make the test happy. We allow up to 1 jiffy.
3301 * This is a regression from the timespec->ktime conversion.
3303 if (ret == -ETIME && !nsecs_to_jiffies(args->timeout_ns))
3304 args->timeout_ns = 0;
3307 i915_gem_object_put(obj);
3311 static int wait_for_timeline(struct i915_gem_timeline *tl, unsigned int flags)
3315 for (i = 0; i < ARRAY_SIZE(tl->engine); i++) {
3316 ret = i915_gem_active_wait(&tl->engine[i].last_request, flags);
3324 static int wait_for_engine(struct intel_engine_cs *engine, int timeout_ms)
3326 return wait_for(intel_engine_is_idle(engine), timeout_ms);
3329 static int wait_for_engines(struct drm_i915_private *i915)
3331 struct intel_engine_cs *engine;
3332 enum intel_engine_id id;
3334 for_each_engine(engine, i915, id) {
3335 if (GEM_WARN_ON(wait_for_engine(engine, 50))) {
3336 i915_gem_set_wedged(i915);
3340 GEM_BUG_ON(intel_engine_get_seqno(engine) !=
3341 intel_engine_last_submit(engine));
3347 int i915_gem_wait_for_idle(struct drm_i915_private *i915, unsigned int flags)
3351 /* If the device is asleep, we have no requests outstanding */
3352 if (!READ_ONCE(i915->gt.awake))
3355 if (flags & I915_WAIT_LOCKED) {
3356 struct i915_gem_timeline *tl;
3358 lockdep_assert_held(&i915->drm.struct_mutex);
3360 list_for_each_entry(tl, &i915->gt.timelines, link) {
3361 ret = wait_for_timeline(tl, flags);
3366 i915_gem_retire_requests(i915);
3367 GEM_BUG_ON(i915->gt.active_requests);
3369 ret = wait_for_engines(i915);
3371 ret = wait_for_timeline(&i915->gt.global_timeline, flags);
3377 static void __i915_gem_object_flush_for_display(struct drm_i915_gem_object *obj)
3379 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU && !obj->cache_dirty)
3382 i915_gem_clflush_object(obj, I915_CLFLUSH_FORCE);
3383 obj->base.write_domain = 0;
3386 void i915_gem_object_flush_if_display(struct drm_i915_gem_object *obj)
3388 if (!READ_ONCE(obj->pin_display))
3391 mutex_lock(&obj->base.dev->struct_mutex);
3392 __i915_gem_object_flush_for_display(obj);
3393 mutex_unlock(&obj->base.dev->struct_mutex);
3397 * Moves a single object to the WC read, and possibly write domain.
3398 * @obj: object to act on
3399 * @write: ask for write access or read only
3401 * This function returns when the move is complete, including waiting on
3405 i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write)
3409 lockdep_assert_held(&obj->base.dev->struct_mutex);
3411 ret = i915_gem_object_wait(obj,
3412 I915_WAIT_INTERRUPTIBLE |
3414 (write ? I915_WAIT_ALL : 0),
3415 MAX_SCHEDULE_TIMEOUT,
3420 if (obj->base.write_domain == I915_GEM_DOMAIN_WC)
3423 /* Flush and acquire obj->pages so that we are coherent through
3424 * direct access in memory with previous cached writes through
3425 * shmemfs and that our cache domain tracking remains valid.
3426 * For example, if the obj->filp was moved to swap without us
3427 * being notified and releasing the pages, we would mistakenly
3428 * continue to assume that the obj remained out of the CPU cached
3431 ret = i915_gem_object_pin_pages(obj);
3435 flush_write_domain(obj, ~I915_GEM_DOMAIN_WC);
3437 /* Serialise direct access to this object with the barriers for
3438 * coherent writes from the GPU, by effectively invalidating the
3439 * WC domain upon first access.
3441 if ((obj->base.read_domains & I915_GEM_DOMAIN_WC) == 0)
3444 /* It should now be out of any other write domains, and we can update
3445 * the domain values for our changes.
3447 GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_WC) != 0);
3448 obj->base.read_domains |= I915_GEM_DOMAIN_WC;
3450 obj->base.read_domains = I915_GEM_DOMAIN_WC;
3451 obj->base.write_domain = I915_GEM_DOMAIN_WC;
3452 obj->mm.dirty = true;
3455 i915_gem_object_unpin_pages(obj);
3460 * Moves a single object to the GTT read, and possibly write domain.
3461 * @obj: object to act on
3462 * @write: ask for write access or read only
3464 * This function returns when the move is complete, including waiting on
3468 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3472 lockdep_assert_held(&obj->base.dev->struct_mutex);
3474 ret = i915_gem_object_wait(obj,
3475 I915_WAIT_INTERRUPTIBLE |
3477 (write ? I915_WAIT_ALL : 0),
3478 MAX_SCHEDULE_TIMEOUT,
3483 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3486 /* Flush and acquire obj->pages so that we are coherent through
3487 * direct access in memory with previous cached writes through
3488 * shmemfs and that our cache domain tracking remains valid.
3489 * For example, if the obj->filp was moved to swap without us
3490 * being notified and releasing the pages, we would mistakenly
3491 * continue to assume that the obj remained out of the CPU cached
3494 ret = i915_gem_object_pin_pages(obj);
3498 flush_write_domain(obj, ~I915_GEM_DOMAIN_GTT);
3500 /* Serialise direct access to this object with the barriers for
3501 * coherent writes from the GPU, by effectively invalidating the
3502 * GTT domain upon first access.
3504 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3507 /* It should now be out of any other write domains, and we can update
3508 * the domain values for our changes.
3510 GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3511 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3513 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3514 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3515 obj->mm.dirty = true;
3518 i915_gem_object_unpin_pages(obj);
3523 * Changes the cache-level of an object across all VMA.
3524 * @obj: object to act on
3525 * @cache_level: new cache level to set for the object
3527 * After this function returns, the object will be in the new cache-level
3528 * across all GTT and the contents of the backing storage will be coherent,
3529 * with respect to the new cache-level. In order to keep the backing storage
3530 * coherent for all users, we only allow a single cache level to be set
3531 * globally on the object and prevent it from being changed whilst the
3532 * hardware is reading from the object. That is if the object is currently
3533 * on the scanout it will be set to uncached (or equivalent display
3534 * cache coherency) and all non-MOCS GPU access will also be uncached so
3535 * that all direct access to the scanout remains coherent.
3537 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3538 enum i915_cache_level cache_level)
3540 struct i915_vma *vma;
3543 lockdep_assert_held(&obj->base.dev->struct_mutex);
3545 if (obj->cache_level == cache_level)
3548 /* Inspect the list of currently bound VMA and unbind any that would
3549 * be invalid given the new cache-level. This is principally to
3550 * catch the issue of the CS prefetch crossing page boundaries and
3551 * reading an invalid PTE on older architectures.
3554 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3555 if (!drm_mm_node_allocated(&vma->node))
3558 if (i915_vma_is_pinned(vma)) {
3559 DRM_DEBUG("can not change the cache level of pinned objects\n");
3563 if (i915_gem_valid_gtt_space(vma, cache_level))
3566 ret = i915_vma_unbind(vma);
3570 /* As unbinding may affect other elements in the
3571 * obj->vma_list (due to side-effects from retiring
3572 * an active vma), play safe and restart the iterator.
3577 /* We can reuse the existing drm_mm nodes but need to change the
3578 * cache-level on the PTE. We could simply unbind them all and
3579 * rebind with the correct cache-level on next use. However since
3580 * we already have a valid slot, dma mapping, pages etc, we may as
3581 * rewrite the PTE in the belief that doing so tramples upon less
3582 * state and so involves less work.
3584 if (obj->bind_count) {
3585 /* Before we change the PTE, the GPU must not be accessing it.
3586 * If we wait upon the object, we know that all the bound
3587 * VMA are no longer active.
3589 ret = i915_gem_object_wait(obj,
3590 I915_WAIT_INTERRUPTIBLE |
3593 MAX_SCHEDULE_TIMEOUT,
3598 if (!HAS_LLC(to_i915(obj->base.dev)) &&
3599 cache_level != I915_CACHE_NONE) {
3600 /* Access to snoopable pages through the GTT is
3601 * incoherent and on some machines causes a hard
3602 * lockup. Relinquish the CPU mmaping to force
3603 * userspace to refault in the pages and we can
3604 * then double check if the GTT mapping is still
3605 * valid for that pointer access.
3607 i915_gem_release_mmap(obj);
3609 /* As we no longer need a fence for GTT access,
3610 * we can relinquish it now (and so prevent having
3611 * to steal a fence from someone else on the next
3612 * fence request). Note GPU activity would have
3613 * dropped the fence as all snoopable access is
3614 * supposed to be linear.
3616 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3617 ret = i915_vma_put_fence(vma);
3622 /* We either have incoherent backing store and
3623 * so no GTT access or the architecture is fully
3624 * coherent. In such cases, existing GTT mmaps
3625 * ignore the cache bit in the PTE and we can
3626 * rewrite it without confusing the GPU or having
3627 * to force userspace to fault back in its mmaps.
3631 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3632 if (!drm_mm_node_allocated(&vma->node))
3635 ret = i915_vma_bind(vma, cache_level, PIN_UPDATE);
3641 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU &&
3642 i915_gem_object_is_coherent(obj))
3643 obj->cache_dirty = true;
3645 list_for_each_entry(vma, &obj->vma_list, obj_link)
3646 vma->node.color = cache_level;
3647 obj->cache_level = cache_level;
3652 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3653 struct drm_file *file)
3655 struct drm_i915_gem_caching *args = data;
3656 struct drm_i915_gem_object *obj;
3660 obj = i915_gem_object_lookup_rcu(file, args->handle);
3666 switch (obj->cache_level) {
3667 case I915_CACHE_LLC:
3668 case I915_CACHE_L3_LLC:
3669 args->caching = I915_CACHING_CACHED;
3673 args->caching = I915_CACHING_DISPLAY;
3677 args->caching = I915_CACHING_NONE;
3685 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3686 struct drm_file *file)
3688 struct drm_i915_private *i915 = to_i915(dev);
3689 struct drm_i915_gem_caching *args = data;
3690 struct drm_i915_gem_object *obj;
3691 enum i915_cache_level level;
3694 switch (args->caching) {
3695 case I915_CACHING_NONE:
3696 level = I915_CACHE_NONE;
3698 case I915_CACHING_CACHED:
3700 * Due to a HW issue on BXT A stepping, GPU stores via a
3701 * snooped mapping may leave stale data in a corresponding CPU
3702 * cacheline, whereas normally such cachelines would get
3705 if (!HAS_LLC(i915) && !HAS_SNOOP(i915))
3708 level = I915_CACHE_LLC;
3710 case I915_CACHING_DISPLAY:
3711 level = HAS_WT(i915) ? I915_CACHE_WT : I915_CACHE_NONE;
3717 obj = i915_gem_object_lookup(file, args->handle);
3721 if (obj->cache_level == level)
3724 ret = i915_gem_object_wait(obj,
3725 I915_WAIT_INTERRUPTIBLE,
3726 MAX_SCHEDULE_TIMEOUT,
3727 to_rps_client(file));
3731 ret = i915_mutex_lock_interruptible(dev);
3735 ret = i915_gem_object_set_cache_level(obj, level);
3736 mutex_unlock(&dev->struct_mutex);
3739 i915_gem_object_put(obj);
3744 * Prepare buffer for display plane (scanout, cursors, etc).
3745 * Can be called from an uninterruptible phase (modesetting) and allows
3746 * any flushes to be pipelined (for pageflips).
3749 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3751 const struct i915_ggtt_view *view)
3753 struct i915_vma *vma;
3756 lockdep_assert_held(&obj->base.dev->struct_mutex);
3758 /* Mark the pin_display early so that we account for the
3759 * display coherency whilst setting up the cache domains.
3763 /* The display engine is not coherent with the LLC cache on gen6. As
3764 * a result, we make sure that the pinning that is about to occur is
3765 * done with uncached PTEs. This is lowest common denominator for all
3768 * However for gen6+, we could do better by using the GFDT bit instead
3769 * of uncaching, which would allow us to flush all the LLC-cached data
3770 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3772 ret = i915_gem_object_set_cache_level(obj,
3773 HAS_WT(to_i915(obj->base.dev)) ?
3774 I915_CACHE_WT : I915_CACHE_NONE);
3777 goto err_unpin_display;
3780 /* As the user may map the buffer once pinned in the display plane
3781 * (e.g. libkms for the bootup splash), we have to ensure that we
3782 * always use map_and_fenceable for all scanout buffers. However,
3783 * it may simply be too big to fit into mappable, in which case
3784 * put it anyway and hope that userspace can cope (but always first
3785 * try to preserve the existing ABI).
3787 vma = ERR_PTR(-ENOSPC);
3788 if (!view || view->type == I915_GGTT_VIEW_NORMAL)
3789 vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment,
3790 PIN_MAPPABLE | PIN_NONBLOCK);
3792 struct drm_i915_private *i915 = to_i915(obj->base.dev);
3795 /* Valleyview is definitely limited to scanning out the first
3796 * 512MiB. Lets presume this behaviour was inherited from the
3797 * g4x display engine and that all earlier gen are similarly
3798 * limited. Testing suggests that it is a little more
3799 * complicated than this. For example, Cherryview appears quite
3800 * happy to scanout from anywhere within its global aperture.
3803 if (HAS_GMCH_DISPLAY(i915))
3804 flags = PIN_MAPPABLE;
3805 vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, flags);
3808 goto err_unpin_display;
3810 vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
3812 /* Treat this as an end-of-frame, like intel_user_framebuffer_dirty() */
3813 __i915_gem_object_flush_for_display(obj);
3814 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
3816 /* It should now be out of any other write domains, and we can update
3817 * the domain values for our changes.
3819 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3829 i915_gem_object_unpin_from_display_plane(struct i915_vma *vma)
3831 lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
3833 if (WARN_ON(vma->obj->pin_display == 0))
3836 if (--vma->obj->pin_display == 0)
3837 vma->display_alignment = I915_GTT_MIN_ALIGNMENT;
3839 /* Bump the LRU to try and avoid premature eviction whilst flipping */
3840 i915_gem_object_bump_inactive_ggtt(vma->obj);
3842 i915_vma_unpin(vma);
3846 * Moves a single object to the CPU read, and possibly write domain.
3847 * @obj: object to act on
3848 * @write: requesting write or read-only access
3850 * This function returns when the move is complete, including waiting on
3854 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3858 lockdep_assert_held(&obj->base.dev->struct_mutex);
3860 ret = i915_gem_object_wait(obj,
3861 I915_WAIT_INTERRUPTIBLE |
3863 (write ? I915_WAIT_ALL : 0),
3864 MAX_SCHEDULE_TIMEOUT,
3869 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3872 flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
3874 /* Flush the CPU cache if it's still invalid. */
3875 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3876 i915_gem_clflush_object(obj, I915_CLFLUSH_SYNC);
3877 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3880 /* It should now be out of any other write domains, and we can update
3881 * the domain values for our changes.
3883 GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3885 /* If we're writing through the CPU, then the GPU read domains will
3886 * need to be invalidated at next use.
3889 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3890 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3896 /* Throttle our rendering by waiting until the ring has completed our requests
3897 * emitted over 20 msec ago.
3899 * Note that if we were to use the current jiffies each time around the loop,
3900 * we wouldn't escape the function with any frames outstanding if the time to
3901 * render a frame was over 20ms.
3903 * This should get us reasonable parallelism between CPU and GPU but also
3904 * relatively low latency when blocking on a particular request to finish.
3907 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3909 struct drm_i915_private *dev_priv = to_i915(dev);
3910 struct drm_i915_file_private *file_priv = file->driver_priv;
3911 unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES;
3912 struct drm_i915_gem_request *request, *target = NULL;
3915 /* ABI: return -EIO if already wedged */
3916 if (i915_terminally_wedged(&dev_priv->gpu_error))
3919 spin_lock(&file_priv->mm.lock);
3920 list_for_each_entry(request, &file_priv->mm.request_list, client_link) {
3921 if (time_after_eq(request->emitted_jiffies, recent_enough))
3925 list_del(&target->client_link);
3926 target->file_priv = NULL;
3932 i915_gem_request_get(target);
3933 spin_unlock(&file_priv->mm.lock);
3938 ret = i915_wait_request(target,
3939 I915_WAIT_INTERRUPTIBLE,
3940 MAX_SCHEDULE_TIMEOUT);
3941 i915_gem_request_put(target);
3943 return ret < 0 ? ret : 0;
3947 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
3948 const struct i915_ggtt_view *view,
3953 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3954 struct i915_address_space *vm = &dev_priv->ggtt.base;
3955 struct i915_vma *vma;
3958 lockdep_assert_held(&obj->base.dev->struct_mutex);
3960 vma = i915_vma_instance(obj, vm, view);
3961 if (unlikely(IS_ERR(vma)))
3964 if (i915_vma_misplaced(vma, size, alignment, flags)) {
3965 if (flags & PIN_NONBLOCK &&
3966 (i915_vma_is_pinned(vma) || i915_vma_is_active(vma)))
3967 return ERR_PTR(-ENOSPC);
3969 if (flags & PIN_MAPPABLE) {
3970 /* If the required space is larger than the available
3971 * aperture, we will not able to find a slot for the
3972 * object and unbinding the object now will be in
3973 * vain. Worse, doing so may cause us to ping-pong
3974 * the object in and out of the Global GTT and
3975 * waste a lot of cycles under the mutex.
3977 if (vma->fence_size > dev_priv->ggtt.mappable_end)
3978 return ERR_PTR(-E2BIG);
3980 /* If NONBLOCK is set the caller is optimistically
3981 * trying to cache the full object within the mappable
3982 * aperture, and *must* have a fallback in place for
3983 * situations where we cannot bind the object. We
3984 * can be a little more lax here and use the fallback
3985 * more often to avoid costly migrations of ourselves
3986 * and other objects within the aperture.
3988 * Half-the-aperture is used as a simple heuristic.
3989 * More interesting would to do search for a free
3990 * block prior to making the commitment to unbind.
3991 * That caters for the self-harm case, and with a
3992 * little more heuristics (e.g. NOFAULT, NOEVICT)
3993 * we could try to minimise harm to others.
3995 if (flags & PIN_NONBLOCK &&
3996 vma->fence_size > dev_priv->ggtt.mappable_end / 2)
3997 return ERR_PTR(-ENOSPC);
4000 WARN(i915_vma_is_pinned(vma),
4001 "bo is already pinned in ggtt with incorrect alignment:"
4002 " offset=%08x, req.alignment=%llx,"
4003 " req.map_and_fenceable=%d, vma->map_and_fenceable=%d\n",
4004 i915_ggtt_offset(vma), alignment,
4005 !!(flags & PIN_MAPPABLE),
4006 i915_vma_is_map_and_fenceable(vma));
4007 ret = i915_vma_unbind(vma);
4009 return ERR_PTR(ret);
4012 ret = i915_vma_pin(vma, size, alignment, flags | PIN_GLOBAL);
4014 return ERR_PTR(ret);
4019 static __always_inline unsigned int __busy_read_flag(unsigned int id)
4021 /* Note that we could alias engines in the execbuf API, but
4022 * that would be very unwise as it prevents userspace from
4023 * fine control over engine selection. Ahem.
4025 * This should be something like EXEC_MAX_ENGINE instead of
4028 BUILD_BUG_ON(I915_NUM_ENGINES > 16);
4029 return 0x10000 << id;
4032 static __always_inline unsigned int __busy_write_id(unsigned int id)
4034 /* The uABI guarantees an active writer is also amongst the read
4035 * engines. This would be true if we accessed the activity tracking
4036 * under the lock, but as we perform the lookup of the object and
4037 * its activity locklessly we can not guarantee that the last_write
4038 * being active implies that we have set the same engine flag from
4039 * last_read - hence we always set both read and write busy for
4042 return id | __busy_read_flag(id);
4045 static __always_inline unsigned int
4046 __busy_set_if_active(const struct dma_fence *fence,
4047 unsigned int (*flag)(unsigned int id))
4049 struct drm_i915_gem_request *rq;
4051 /* We have to check the current hw status of the fence as the uABI
4052 * guarantees forward progress. We could rely on the idle worker
4053 * to eventually flush us, but to minimise latency just ask the
4056 * Note we only report on the status of native fences.
4058 if (!dma_fence_is_i915(fence))
4061 /* opencode to_request() in order to avoid const warnings */
4062 rq = container_of(fence, struct drm_i915_gem_request, fence);
4063 if (i915_gem_request_completed(rq))
4066 return flag(rq->engine->uabi_id);
4069 static __always_inline unsigned int
4070 busy_check_reader(const struct dma_fence *fence)
4072 return __busy_set_if_active(fence, __busy_read_flag);
4075 static __always_inline unsigned int
4076 busy_check_writer(const struct dma_fence *fence)
4081 return __busy_set_if_active(fence, __busy_write_id);
4085 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4086 struct drm_file *file)
4088 struct drm_i915_gem_busy *args = data;
4089 struct drm_i915_gem_object *obj;
4090 struct reservation_object_list *list;
4096 obj = i915_gem_object_lookup_rcu(file, args->handle);
4100 /* A discrepancy here is that we do not report the status of
4101 * non-i915 fences, i.e. even though we may report the object as idle,
4102 * a call to set-domain may still stall waiting for foreign rendering.
4103 * This also means that wait-ioctl may report an object as busy,
4104 * where busy-ioctl considers it idle.
4106 * We trade the ability to warn of foreign fences to report on which
4107 * i915 engines are active for the object.
4109 * Alternatively, we can trade that extra information on read/write
4112 * !reservation_object_test_signaled_rcu(obj->resv, true);
4113 * to report the overall busyness. This is what the wait-ioctl does.
4117 seq = raw_read_seqcount(&obj->resv->seq);
4119 /* Translate the exclusive fence to the READ *and* WRITE engine */
4120 args->busy = busy_check_writer(rcu_dereference(obj->resv->fence_excl));
4122 /* Translate shared fences to READ set of engines */
4123 list = rcu_dereference(obj->resv->fence);
4125 unsigned int shared_count = list->shared_count, i;
4127 for (i = 0; i < shared_count; ++i) {
4128 struct dma_fence *fence =
4129 rcu_dereference(list->shared[i]);
4131 args->busy |= busy_check_reader(fence);
4135 if (args->busy && read_seqcount_retry(&obj->resv->seq, seq))
4145 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4146 struct drm_file *file_priv)
4148 return i915_gem_ring_throttle(dev, file_priv);
4152 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4153 struct drm_file *file_priv)
4155 struct drm_i915_private *dev_priv = to_i915(dev);
4156 struct drm_i915_gem_madvise *args = data;
4157 struct drm_i915_gem_object *obj;
4160 switch (args->madv) {
4161 case I915_MADV_DONTNEED:
4162 case I915_MADV_WILLNEED:
4168 obj = i915_gem_object_lookup(file_priv, args->handle);
4172 err = mutex_lock_interruptible(&obj->mm.lock);
4176 if (obj->mm.pages &&
4177 i915_gem_object_is_tiled(obj) &&
4178 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
4179 if (obj->mm.madv == I915_MADV_WILLNEED) {
4180 GEM_BUG_ON(!obj->mm.quirked);
4181 __i915_gem_object_unpin_pages(obj);
4182 obj->mm.quirked = false;
4184 if (args->madv == I915_MADV_WILLNEED) {
4185 GEM_BUG_ON(obj->mm.quirked);
4186 __i915_gem_object_pin_pages(obj);
4187 obj->mm.quirked = true;
4191 if (obj->mm.madv != __I915_MADV_PURGED)
4192 obj->mm.madv = args->madv;
4194 /* if the object is no longer attached, discard its backing storage */
4195 if (obj->mm.madv == I915_MADV_DONTNEED && !obj->mm.pages)
4196 i915_gem_object_truncate(obj);
4198 args->retained = obj->mm.madv != __I915_MADV_PURGED;
4199 mutex_unlock(&obj->mm.lock);
4202 i915_gem_object_put(obj);
4207 frontbuffer_retire(struct i915_gem_active *active,
4208 struct drm_i915_gem_request *request)
4210 struct drm_i915_gem_object *obj =
4211 container_of(active, typeof(*obj), frontbuffer_write);
4213 intel_fb_obj_flush(obj, ORIGIN_CS);
4216 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4217 const struct drm_i915_gem_object_ops *ops)
4219 mutex_init(&obj->mm.lock);
4221 INIT_LIST_HEAD(&obj->global_link);
4222 INIT_LIST_HEAD(&obj->userfault_link);
4223 INIT_LIST_HEAD(&obj->obj_exec_link);
4224 INIT_LIST_HEAD(&obj->vma_list);
4225 INIT_LIST_HEAD(&obj->batch_pool_link);
4229 reservation_object_init(&obj->__builtin_resv);
4230 obj->resv = &obj->__builtin_resv;
4232 obj->frontbuffer_ggtt_origin = ORIGIN_GTT;
4233 init_request_active(&obj->frontbuffer_write, frontbuffer_retire);
4235 obj->mm.madv = I915_MADV_WILLNEED;
4236 INIT_RADIX_TREE(&obj->mm.get_page.radix, GFP_KERNEL | __GFP_NOWARN);
4237 mutex_init(&obj->mm.get_page.lock);
4239 i915_gem_info_add_obj(to_i915(obj->base.dev), obj->base.size);
4242 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4243 .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE |
4244 I915_GEM_OBJECT_IS_SHRINKABLE,
4246 .get_pages = i915_gem_object_get_pages_gtt,
4247 .put_pages = i915_gem_object_put_pages_gtt,
4249 .pwrite = i915_gem_object_pwrite_gtt,
4252 struct drm_i915_gem_object *
4253 i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size)
4255 struct drm_i915_gem_object *obj;
4256 struct address_space *mapping;
4260 /* There is a prevalence of the assumption that we fit the object's
4261 * page count inside a 32bit _signed_ variable. Let's document this and
4262 * catch if we ever need to fix it. In the meantime, if you do spot
4263 * such a local variable, please consider fixing!
4265 if (size >> PAGE_SHIFT > INT_MAX)
4266 return ERR_PTR(-E2BIG);
4268 if (overflows_type(size, obj->base.size))
4269 return ERR_PTR(-E2BIG);
4271 obj = i915_gem_object_alloc(dev_priv);
4273 return ERR_PTR(-ENOMEM);
4275 ret = drm_gem_object_init(&dev_priv->drm, &obj->base, size);
4279 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4280 if (IS_I965GM(dev_priv) || IS_I965G(dev_priv)) {
4281 /* 965gm cannot relocate objects above 4GiB. */
4282 mask &= ~__GFP_HIGHMEM;
4283 mask |= __GFP_DMA32;
4286 mapping = obj->base.filp->f_mapping;
4287 mapping_set_gfp_mask(mapping, mask);
4289 i915_gem_object_init(obj, &i915_gem_object_ops);
4291 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4292 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4294 if (HAS_LLC(dev_priv)) {
4295 /* On some devices, we can have the GPU use the LLC (the CPU
4296 * cache) for about a 10% performance improvement
4297 * compared to uncached. Graphics requests other than
4298 * display scanout are coherent with the CPU in
4299 * accessing this cache. This means in this mode we
4300 * don't need to clflush on the CPU side, and on the
4301 * GPU side we only need to flush internal caches to
4302 * get data visible to the CPU.
4304 * However, we maintain the display planes as UC, and so
4305 * need to rebind when first used as such.
4307 obj->cache_level = I915_CACHE_LLC;
4309 obj->cache_level = I915_CACHE_NONE;
4311 trace_i915_gem_object_create(obj);
4316 i915_gem_object_free(obj);
4317 return ERR_PTR(ret);
4320 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4322 /* If we are the last user of the backing storage (be it shmemfs
4323 * pages or stolen etc), we know that the pages are going to be
4324 * immediately released. In this case, we can then skip copying
4325 * back the contents from the GPU.
4328 if (obj->mm.madv != I915_MADV_WILLNEED)
4331 if (obj->base.filp == NULL)
4334 /* At first glance, this looks racy, but then again so would be
4335 * userspace racing mmap against close. However, the first external
4336 * reference to the filp can only be obtained through the
4337 * i915_gem_mmap_ioctl() which safeguards us against the user
4338 * acquiring such a reference whilst we are in the middle of
4339 * freeing the object.
4341 return atomic_long_read(&obj->base.filp->f_count) == 1;
4344 static void __i915_gem_free_objects(struct drm_i915_private *i915,
4345 struct llist_node *freed)
4347 struct drm_i915_gem_object *obj, *on;
4349 mutex_lock(&i915->drm.struct_mutex);
4350 intel_runtime_pm_get(i915);
4351 llist_for_each_entry(obj, freed, freed) {
4352 struct i915_vma *vma, *vn;
4354 trace_i915_gem_object_destroy(obj);
4356 GEM_BUG_ON(i915_gem_object_is_active(obj));
4357 list_for_each_entry_safe(vma, vn,
4358 &obj->vma_list, obj_link) {
4359 GEM_BUG_ON(!i915_vma_is_ggtt(vma));
4360 GEM_BUG_ON(i915_vma_is_active(vma));
4361 vma->flags &= ~I915_VMA_PIN_MASK;
4362 i915_vma_close(vma);
4364 GEM_BUG_ON(!list_empty(&obj->vma_list));
4365 GEM_BUG_ON(!RB_EMPTY_ROOT(&obj->vma_tree));
4367 list_del(&obj->global_link);
4369 intel_runtime_pm_put(i915);
4370 mutex_unlock(&i915->drm.struct_mutex);
4374 llist_for_each_entry_safe(obj, on, freed, freed) {
4375 GEM_BUG_ON(obj->bind_count);
4376 GEM_BUG_ON(atomic_read(&obj->frontbuffer_bits));
4378 if (obj->ops->release)
4379 obj->ops->release(obj);
4381 if (WARN_ON(i915_gem_object_has_pinned_pages(obj)))
4382 atomic_set(&obj->mm.pages_pin_count, 0);
4383 __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
4384 GEM_BUG_ON(obj->mm.pages);
4386 if (obj->base.import_attach)
4387 drm_prime_gem_destroy(&obj->base, NULL);
4389 reservation_object_fini(&obj->__builtin_resv);
4390 drm_gem_object_release(&obj->base);
4391 i915_gem_info_remove_obj(i915, obj->base.size);
4394 i915_gem_object_free(obj);
4398 static void i915_gem_flush_free_objects(struct drm_i915_private *i915)
4400 struct llist_node *freed;
4402 freed = llist_del_all(&i915->mm.free_list);
4403 if (unlikely(freed))
4404 __i915_gem_free_objects(i915, freed);
4407 static void __i915_gem_free_work(struct work_struct *work)
4409 struct drm_i915_private *i915 =
4410 container_of(work, struct drm_i915_private, mm.free_work);
4411 struct llist_node *freed;
4413 /* All file-owned VMA should have been released by this point through
4414 * i915_gem_close_object(), or earlier by i915_gem_context_close().
4415 * However, the object may also be bound into the global GTT (e.g.
4416 * older GPUs without per-process support, or for direct access through
4417 * the GTT either for the user or for scanout). Those VMA still need to
4421 while ((freed = llist_del_all(&i915->mm.free_list))) {
4422 __i915_gem_free_objects(i915, freed);
4428 static void __i915_gem_free_object_rcu(struct rcu_head *head)
4430 struct drm_i915_gem_object *obj =
4431 container_of(head, typeof(*obj), rcu);
4432 struct drm_i915_private *i915 = to_i915(obj->base.dev);
4434 /* We can't simply use call_rcu() from i915_gem_free_object()
4435 * as we need to block whilst unbinding, and the call_rcu
4436 * task may be called from softirq context. So we take a
4437 * detour through a worker.
4439 if (llist_add(&obj->freed, &i915->mm.free_list))
4440 schedule_work(&i915->mm.free_work);
4443 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4445 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4447 if (obj->mm.quirked)
4448 __i915_gem_object_unpin_pages(obj);
4450 if (discard_backing_storage(obj))
4451 obj->mm.madv = I915_MADV_DONTNEED;
4453 /* Before we free the object, make sure any pure RCU-only
4454 * read-side critical sections are complete, e.g.
4455 * i915_gem_busy_ioctl(). For the corresponding synchronized
4456 * lookup see i915_gem_object_lookup_rcu().
4458 call_rcu(&obj->rcu, __i915_gem_free_object_rcu);
4461 void __i915_gem_object_release_unless_active(struct drm_i915_gem_object *obj)
4463 lockdep_assert_held(&obj->base.dev->struct_mutex);
4465 GEM_BUG_ON(i915_gem_object_has_active_reference(obj));
4466 if (i915_gem_object_is_active(obj))
4467 i915_gem_object_set_active_reference(obj);
4469 i915_gem_object_put(obj);
4472 static void assert_kernel_context_is_current(struct drm_i915_private *dev_priv)
4474 struct intel_engine_cs *engine;
4475 enum intel_engine_id id;
4477 for_each_engine(engine, dev_priv, id)
4478 GEM_BUG_ON(engine->last_retired_context &&
4479 !i915_gem_context_is_kernel(engine->last_retired_context));
4482 void i915_gem_sanitize(struct drm_i915_private *i915)
4485 * If we inherit context state from the BIOS or earlier occupants
4486 * of the GPU, the GPU may be in an inconsistent state when we
4487 * try to take over. The only way to remove the earlier state
4488 * is by resetting. However, resetting on earlier gen is tricky as
4489 * it may impact the display and we are uncertain about the stability
4490 * of the reset, so this could be applied to even earlier gen.
4492 if (INTEL_GEN(i915) >= 5) {
4493 int reset = intel_gpu_reset(i915, ALL_ENGINES);
4494 WARN_ON(reset && reset != -ENODEV);
4498 int i915_gem_suspend(struct drm_i915_private *dev_priv)
4500 struct drm_device *dev = &dev_priv->drm;
4503 intel_runtime_pm_get(dev_priv);
4504 intel_suspend_gt_powersave(dev_priv);
4506 mutex_lock(&dev->struct_mutex);
4508 /* We have to flush all the executing contexts to main memory so
4509 * that they can saved in the hibernation image. To ensure the last
4510 * context image is coherent, we have to switch away from it. That
4511 * leaves the dev_priv->kernel_context still active when
4512 * we actually suspend, and its image in memory may not match the GPU
4513 * state. Fortunately, the kernel_context is disposable and we do
4514 * not rely on its state.
4516 ret = i915_gem_switch_to_kernel_context(dev_priv);
4520 ret = i915_gem_wait_for_idle(dev_priv,
4521 I915_WAIT_INTERRUPTIBLE |
4526 assert_kernel_context_is_current(dev_priv);
4527 i915_gem_context_lost(dev_priv);
4528 mutex_unlock(&dev->struct_mutex);
4530 intel_guc_suspend(dev_priv);
4532 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
4533 cancel_delayed_work_sync(&dev_priv->gt.retire_work);
4535 /* As the idle_work is rearming if it detects a race, play safe and
4536 * repeat the flush until it is definitely idle.
4538 while (flush_delayed_work(&dev_priv->gt.idle_work))
4541 i915_gem_drain_freed_objects(dev_priv);
4543 /* Assert that we sucessfully flushed all the work and
4544 * reset the GPU back to its idle, low power state.
4546 WARN_ON(dev_priv->gt.awake);
4547 WARN_ON(!intel_engines_are_idle(dev_priv));
4550 * Neither the BIOS, ourselves or any other kernel
4551 * expects the system to be in execlists mode on startup,
4552 * so we need to reset the GPU back to legacy mode. And the only
4553 * known way to disable logical contexts is through a GPU reset.
4555 * So in order to leave the system in a known default configuration,
4556 * always reset the GPU upon unload and suspend. Afterwards we then
4557 * clean up the GEM state tracking, flushing off the requests and
4558 * leaving the system in a known idle state.
4560 * Note that is of the upmost importance that the GPU is idle and
4561 * all stray writes are flushed *before* we dismantle the backing
4562 * storage for the pinned objects.
4564 * However, since we are uncertain that resetting the GPU on older
4565 * machines is a good idea, we don't - just in case it leaves the
4566 * machine in an unusable condition.
4568 i915_gem_sanitize(dev_priv);
4572 mutex_unlock(&dev->struct_mutex);
4574 intel_runtime_pm_put(dev_priv);
4578 void i915_gem_resume(struct drm_i915_private *dev_priv)
4580 struct drm_device *dev = &dev_priv->drm;
4582 WARN_ON(dev_priv->gt.awake);
4584 mutex_lock(&dev->struct_mutex);
4585 i915_gem_restore_gtt_mappings(dev_priv);
4587 /* As we didn't flush the kernel context before suspend, we cannot
4588 * guarantee that the context image is complete. So let's just reset
4589 * it and start again.
4591 dev_priv->gt.resume(dev_priv);
4593 mutex_unlock(&dev->struct_mutex);
4596 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv)
4598 if (INTEL_GEN(dev_priv) < 5 ||
4599 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4602 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4603 DISP_TILE_SURFACE_SWIZZLING);
4605 if (IS_GEN5(dev_priv))
4608 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4609 if (IS_GEN6(dev_priv))
4610 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4611 else if (IS_GEN7(dev_priv))
4612 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4613 else if (IS_GEN8(dev_priv))
4614 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4619 static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base)
4621 I915_WRITE(RING_CTL(base), 0);
4622 I915_WRITE(RING_HEAD(base), 0);
4623 I915_WRITE(RING_TAIL(base), 0);
4624 I915_WRITE(RING_START(base), 0);
4627 static void init_unused_rings(struct drm_i915_private *dev_priv)
4629 if (IS_I830(dev_priv)) {
4630 init_unused_ring(dev_priv, PRB1_BASE);
4631 init_unused_ring(dev_priv, SRB0_BASE);
4632 init_unused_ring(dev_priv, SRB1_BASE);
4633 init_unused_ring(dev_priv, SRB2_BASE);
4634 init_unused_ring(dev_priv, SRB3_BASE);
4635 } else if (IS_GEN2(dev_priv)) {
4636 init_unused_ring(dev_priv, SRB0_BASE);
4637 init_unused_ring(dev_priv, SRB1_BASE);
4638 } else if (IS_GEN3(dev_priv)) {
4639 init_unused_ring(dev_priv, PRB1_BASE);
4640 init_unused_ring(dev_priv, PRB2_BASE);
4644 static int __i915_gem_restart_engines(void *data)
4646 struct drm_i915_private *i915 = data;
4647 struct intel_engine_cs *engine;
4648 enum intel_engine_id id;
4651 for_each_engine(engine, i915, id) {
4652 err = engine->init_hw(engine);
4660 int i915_gem_init_hw(struct drm_i915_private *dev_priv)
4664 dev_priv->gt.last_init_time = ktime_get();
4666 /* Double layer security blanket, see i915_gem_init() */
4667 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4669 if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9)
4670 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4672 if (IS_HASWELL(dev_priv))
4673 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
4674 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4676 if (HAS_PCH_NOP(dev_priv)) {
4677 if (IS_IVYBRIDGE(dev_priv)) {
4678 u32 temp = I915_READ(GEN7_MSG_CTL);
4679 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4680 I915_WRITE(GEN7_MSG_CTL, temp);
4681 } else if (INTEL_GEN(dev_priv) >= 7) {
4682 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4683 temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4684 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4688 i915_gem_init_swizzling(dev_priv);
4691 * At least 830 can leave some of the unused rings
4692 * "active" (ie. head != tail) after resume which
4693 * will prevent c3 entry. Makes sure all unused rings
4696 init_unused_rings(dev_priv);
4698 BUG_ON(!dev_priv->kernel_context);
4700 ret = i915_ppgtt_init_hw(dev_priv);
4702 DRM_ERROR("PPGTT enable HW failed %d\n", ret);
4706 /* Need to do basic initialisation of all rings first: */
4707 ret = __i915_gem_restart_engines(dev_priv);
4711 intel_mocs_init_l3cc_table(dev_priv);
4713 /* We can't enable contexts until all firmware is loaded */
4714 ret = intel_uc_init_hw(dev_priv);
4719 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4723 bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value)
4725 if (INTEL_INFO(dev_priv)->gen < 6)
4728 /* TODO: make semaphores and Execlists play nicely together */
4729 if (i915.enable_execlists)
4735 /* Enable semaphores on SNB when IO remapping is off */
4736 if (IS_GEN6(dev_priv) && intel_vtd_active())
4742 int i915_gem_init(struct drm_i915_private *dev_priv)
4746 mutex_lock(&dev_priv->drm.struct_mutex);
4748 dev_priv->mm.unordered_timeline = dma_fence_context_alloc(1);
4750 if (!i915.enable_execlists) {
4751 dev_priv->gt.resume = intel_legacy_submission_resume;
4752 dev_priv->gt.cleanup_engine = intel_engine_cleanup;
4754 dev_priv->gt.resume = intel_lr_context_resume;
4755 dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup;
4758 /* This is just a security blanket to placate dragons.
4759 * On some systems, we very sporadically observe that the first TLBs
4760 * used by the CS may be stale, despite us poking the TLB reset. If
4761 * we hold the forcewake during initialisation these problems
4762 * just magically go away.
4764 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4766 i915_gem_init_userptr(dev_priv);
4768 ret = i915_gem_init_ggtt(dev_priv);
4772 ret = i915_gem_context_init(dev_priv);
4776 ret = intel_engines_init(dev_priv);
4780 ret = i915_gem_init_hw(dev_priv);
4782 /* Allow engine initialisation to fail by marking the GPU as
4783 * wedged. But we only want to do this where the GPU is angry,
4784 * for all other failure, such as an allocation failure, bail.
4786 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4787 i915_gem_set_wedged(dev_priv);
4792 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4793 mutex_unlock(&dev_priv->drm.struct_mutex);
4798 void i915_gem_init_mmio(struct drm_i915_private *i915)
4800 i915_gem_sanitize(i915);
4804 i915_gem_cleanup_engines(struct drm_i915_private *dev_priv)
4806 struct intel_engine_cs *engine;
4807 enum intel_engine_id id;
4809 for_each_engine(engine, dev_priv, id)
4810 dev_priv->gt.cleanup_engine(engine);
4814 i915_gem_load_init_fences(struct drm_i915_private *dev_priv)
4818 if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) &&
4819 !IS_CHERRYVIEW(dev_priv))
4820 dev_priv->num_fence_regs = 32;
4821 else if (INTEL_INFO(dev_priv)->gen >= 4 ||
4822 IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
4823 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv))
4824 dev_priv->num_fence_regs = 16;
4826 dev_priv->num_fence_regs = 8;
4828 if (intel_vgpu_active(dev_priv))
4829 dev_priv->num_fence_regs =
4830 I915_READ(vgtif_reg(avail_rs.fence_num));
4832 /* Initialize fence registers to zero */
4833 for (i = 0; i < dev_priv->num_fence_regs; i++) {
4834 struct drm_i915_fence_reg *fence = &dev_priv->fence_regs[i];
4836 fence->i915 = dev_priv;
4838 list_add_tail(&fence->link, &dev_priv->mm.fence_list);
4840 i915_gem_restore_fences(dev_priv);
4842 i915_gem_detect_bit_6_swizzle(dev_priv);
4846 i915_gem_load_init(struct drm_i915_private *dev_priv)
4850 dev_priv->objects = KMEM_CACHE(drm_i915_gem_object, SLAB_HWCACHE_ALIGN);
4851 if (!dev_priv->objects)
4854 dev_priv->vmas = KMEM_CACHE(i915_vma, SLAB_HWCACHE_ALIGN);
4855 if (!dev_priv->vmas)
4858 dev_priv->requests = KMEM_CACHE(drm_i915_gem_request,
4859 SLAB_HWCACHE_ALIGN |
4860 SLAB_RECLAIM_ACCOUNT |
4861 SLAB_TYPESAFE_BY_RCU);
4862 if (!dev_priv->requests)
4865 dev_priv->dependencies = KMEM_CACHE(i915_dependency,
4866 SLAB_HWCACHE_ALIGN |
4867 SLAB_RECLAIM_ACCOUNT);
4868 if (!dev_priv->dependencies)
4871 dev_priv->priorities = KMEM_CACHE(i915_priolist, SLAB_HWCACHE_ALIGN);
4872 if (!dev_priv->priorities)
4873 goto err_dependencies;
4875 mutex_lock(&dev_priv->drm.struct_mutex);
4876 INIT_LIST_HEAD(&dev_priv->gt.timelines);
4877 err = i915_gem_timeline_init__global(dev_priv);
4878 mutex_unlock(&dev_priv->drm.struct_mutex);
4880 goto err_priorities;
4882 INIT_LIST_HEAD(&dev_priv->context_list);
4883 INIT_WORK(&dev_priv->mm.free_work, __i915_gem_free_work);
4884 init_llist_head(&dev_priv->mm.free_list);
4885 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4886 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4887 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4888 INIT_LIST_HEAD(&dev_priv->mm.userfault_list);
4889 INIT_DELAYED_WORK(&dev_priv->gt.retire_work,
4890 i915_gem_retire_work_handler);
4891 INIT_DELAYED_WORK(&dev_priv->gt.idle_work,
4892 i915_gem_idle_work_handler);
4893 init_waitqueue_head(&dev_priv->gpu_error.wait_queue);
4894 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4896 init_waitqueue_head(&dev_priv->pending_flip_queue);
4898 atomic_set(&dev_priv->mm.bsd_engine_dispatch_index, 0);
4900 spin_lock_init(&dev_priv->fb_tracking.lock);
4905 kmem_cache_destroy(dev_priv->priorities);
4907 kmem_cache_destroy(dev_priv->dependencies);
4909 kmem_cache_destroy(dev_priv->requests);
4911 kmem_cache_destroy(dev_priv->vmas);
4913 kmem_cache_destroy(dev_priv->objects);
4918 void i915_gem_load_cleanup(struct drm_i915_private *dev_priv)
4920 i915_gem_drain_freed_objects(dev_priv);
4921 WARN_ON(!llist_empty(&dev_priv->mm.free_list));
4922 WARN_ON(dev_priv->mm.object_count);
4924 mutex_lock(&dev_priv->drm.struct_mutex);
4925 i915_gem_timeline_fini(&dev_priv->gt.global_timeline);
4926 WARN_ON(!list_empty(&dev_priv->gt.timelines));
4927 mutex_unlock(&dev_priv->drm.struct_mutex);
4929 kmem_cache_destroy(dev_priv->priorities);
4930 kmem_cache_destroy(dev_priv->dependencies);
4931 kmem_cache_destroy(dev_priv->requests);
4932 kmem_cache_destroy(dev_priv->vmas);
4933 kmem_cache_destroy(dev_priv->objects);
4935 /* And ensure that our DESTROY_BY_RCU slabs are truly destroyed */
4939 int i915_gem_freeze(struct drm_i915_private *dev_priv)
4941 /* Discard all purgeable objects, let userspace recover those as
4942 * required after resuming.
4944 i915_gem_shrink_all(dev_priv);
4949 int i915_gem_freeze_late(struct drm_i915_private *dev_priv)
4951 struct drm_i915_gem_object *obj;
4952 struct list_head *phases[] = {
4953 &dev_priv->mm.unbound_list,
4954 &dev_priv->mm.bound_list,
4958 /* Called just before we write the hibernation image.
4960 * We need to update the domain tracking to reflect that the CPU
4961 * will be accessing all the pages to create and restore from the
4962 * hibernation, and so upon restoration those pages will be in the
4965 * To make sure the hibernation image contains the latest state,
4966 * we update that state just before writing out the image.
4968 * To try and reduce the hibernation image, we manually shrink
4969 * the objects as well, see i915_gem_freeze()
4972 i915_gem_shrink(dev_priv, -1UL, I915_SHRINK_UNBOUND);
4973 i915_gem_drain_freed_objects(dev_priv);
4975 mutex_lock(&dev_priv->drm.struct_mutex);
4976 for (p = phases; *p; p++) {
4977 list_for_each_entry(obj, *p, global_link) {
4978 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4979 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4982 mutex_unlock(&dev_priv->drm.struct_mutex);
4987 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4989 struct drm_i915_file_private *file_priv = file->driver_priv;
4990 struct drm_i915_gem_request *request;
4992 /* Clean up our request list when the client is going away, so that
4993 * later retire_requests won't dereference our soon-to-be-gone
4996 spin_lock(&file_priv->mm.lock);
4997 list_for_each_entry(request, &file_priv->mm.request_list, client_link)
4998 request->file_priv = NULL;
4999 spin_unlock(&file_priv->mm.lock);
5001 if (!list_empty(&file_priv->rps.link)) {
5002 spin_lock(&to_i915(dev)->rps.client_lock);
5003 list_del(&file_priv->rps.link);
5004 spin_unlock(&to_i915(dev)->rps.client_lock);
5008 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
5010 struct drm_i915_file_private *file_priv;
5015 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
5019 file->driver_priv = file_priv;
5020 file_priv->dev_priv = to_i915(dev);
5021 file_priv->file = file;
5022 INIT_LIST_HEAD(&file_priv->rps.link);
5024 spin_lock_init(&file_priv->mm.lock);
5025 INIT_LIST_HEAD(&file_priv->mm.request_list);
5027 file_priv->bsd_engine = -1;
5029 ret = i915_gem_context_open(dev, file);
5037 * i915_gem_track_fb - update frontbuffer tracking
5038 * @old: current GEM buffer for the frontbuffer slots
5039 * @new: new GEM buffer for the frontbuffer slots
5040 * @frontbuffer_bits: bitmask of frontbuffer slots
5042 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5043 * from @old and setting them in @new. Both @old and @new can be NULL.
5045 void i915_gem_track_fb(struct drm_i915_gem_object *old,
5046 struct drm_i915_gem_object *new,
5047 unsigned frontbuffer_bits)
5049 /* Control of individual bits within the mask are guarded by
5050 * the owning plane->mutex, i.e. we can never see concurrent
5051 * manipulation of individual bits. But since the bitfield as a whole
5052 * is updated using RMW, we need to use atomics in order to update
5055 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES >
5056 sizeof(atomic_t) * BITS_PER_BYTE);
5059 WARN_ON(!(atomic_read(&old->frontbuffer_bits) & frontbuffer_bits));
5060 atomic_andnot(frontbuffer_bits, &old->frontbuffer_bits);
5064 WARN_ON(atomic_read(&new->frontbuffer_bits) & frontbuffer_bits);
5065 atomic_or(frontbuffer_bits, &new->frontbuffer_bits);
5069 /* Allocate a new GEM object and fill it with the supplied data */
5070 struct drm_i915_gem_object *
5071 i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
5072 const void *data, size_t size)
5074 struct drm_i915_gem_object *obj;
5079 obj = i915_gem_object_create(dev_priv, round_up(size, PAGE_SIZE));
5083 GEM_BUG_ON(obj->base.write_domain != I915_GEM_DOMAIN_CPU);
5085 file = obj->base.filp;
5088 unsigned int len = min_t(typeof(size), size, PAGE_SIZE);
5090 void *pgdata, *vaddr;
5092 err = pagecache_write_begin(file, file->f_mapping,
5099 memcpy(vaddr, data, len);
5102 err = pagecache_write_end(file, file->f_mapping,
5116 i915_gem_object_put(obj);
5117 return ERR_PTR(err);
5120 struct scatterlist *
5121 i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
5123 unsigned int *offset)
5125 struct i915_gem_object_page_iter *iter = &obj->mm.get_page;
5126 struct scatterlist *sg;
5127 unsigned int idx, count;
5130 GEM_BUG_ON(n >= obj->base.size >> PAGE_SHIFT);
5131 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
5133 /* As we iterate forward through the sg, we record each entry in a
5134 * radixtree for quick repeated (backwards) lookups. If we have seen
5135 * this index previously, we will have an entry for it.
5137 * Initial lookup is O(N), but this is amortized to O(1) for
5138 * sequential page access (where each new request is consecutive
5139 * to the previous one). Repeated lookups are O(lg(obj->base.size)),
5140 * i.e. O(1) with a large constant!
5142 if (n < READ_ONCE(iter->sg_idx))
5145 mutex_lock(&iter->lock);
5147 /* We prefer to reuse the last sg so that repeated lookup of this
5148 * (or the subsequent) sg are fast - comparing against the last
5149 * sg is faster than going through the radixtree.
5154 count = __sg_page_count(sg);
5156 while (idx + count <= n) {
5157 unsigned long exception, i;
5160 /* If we cannot allocate and insert this entry, or the
5161 * individual pages from this range, cancel updating the
5162 * sg_idx so that on this lookup we are forced to linearly
5163 * scan onwards, but on future lookups we will try the
5164 * insertion again (in which case we need to be careful of
5165 * the error return reporting that we have already inserted
5168 ret = radix_tree_insert(&iter->radix, idx, sg);
5169 if (ret && ret != -EEXIST)
5173 RADIX_TREE_EXCEPTIONAL_ENTRY |
5174 idx << RADIX_TREE_EXCEPTIONAL_SHIFT;
5175 for (i = 1; i < count; i++) {
5176 ret = radix_tree_insert(&iter->radix, idx + i,
5178 if (ret && ret != -EEXIST)
5183 sg = ____sg_next(sg);
5184 count = __sg_page_count(sg);
5191 mutex_unlock(&iter->lock);
5193 if (unlikely(n < idx)) /* insertion completed by another thread */
5196 /* In case we failed to insert the entry into the radixtree, we need
5197 * to look beyond the current sg.
5199 while (idx + count <= n) {
5201 sg = ____sg_next(sg);
5202 count = __sg_page_count(sg);
5211 sg = radix_tree_lookup(&iter->radix, n);
5214 /* If this index is in the middle of multi-page sg entry,
5215 * the radixtree will contain an exceptional entry that points
5216 * to the start of that range. We will return the pointer to
5217 * the base page and the offset of this page within the
5221 if (unlikely(radix_tree_exception(sg))) {
5222 unsigned long base =
5223 (unsigned long)sg >> RADIX_TREE_EXCEPTIONAL_SHIFT;
5225 sg = radix_tree_lookup(&iter->radix, base);
5237 i915_gem_object_get_page(struct drm_i915_gem_object *obj, unsigned int n)
5239 struct scatterlist *sg;
5240 unsigned int offset;
5242 GEM_BUG_ON(!i915_gem_object_has_struct_page(obj));
5244 sg = i915_gem_object_get_sg(obj, n, &offset);
5245 return nth_page(sg_page(sg), offset);
5248 /* Like i915_gem_object_get_page(), but mark the returned page dirty */
5250 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
5255 page = i915_gem_object_get_page(obj, n);
5257 set_page_dirty(page);
5263 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
5266 struct scatterlist *sg;
5267 unsigned int offset;
5269 sg = i915_gem_object_get_sg(obj, n, &offset);
5270 return sg_dma_address(sg) + (offset << PAGE_SHIFT);
5273 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
5274 #include "selftests/scatterlist.c"
5275 #include "selftests/mock_gem_device.c"
5276 #include "selftests/huge_gem_object.c"
5277 #include "selftests/i915_gem_object.c"
5278 #include "selftests/i915_gem_coherency.c"