2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
28 #include <linux/dma-fence-array.h>
29 #include <linux/kthread.h>
30 #include <linux/dma-resv.h>
31 #include <linux/shmem_fs.h>
32 #include <linux/slab.h>
33 #include <linux/stop_machine.h>
34 #include <linux/swap.h>
35 #include <linux/pci.h>
36 #include <linux/dma-buf.h>
37 #include <linux/mman.h>
39 #include <drm/drm_cache.h>
40 #include <drm/drm_vma_manager.h>
42 #include "display/intel_display.h"
43 #include "display/intel_frontbuffer.h"
45 #include "gem/i915_gem_clflush.h"
46 #include "gem/i915_gem_context.h"
47 #include "gem/i915_gem_ioctls.h"
48 #include "gem/i915_gem_mman.h"
49 #include "gem/i915_gem_pm.h"
50 #include "gem/i915_gem_region.h"
51 #include "gem/i915_gem_userptr.h"
52 #include "gt/intel_engine_user.h"
53 #include "gt/intel_gt.h"
54 #include "gt/intel_gt_pm.h"
55 #include "gt/intel_workarounds.h"
58 #include "i915_file_private.h"
59 #include "i915_trace.h"
60 #include "i915_vgpu.h"
64 insert_mappable_node(struct i915_ggtt *ggtt, struct drm_mm_node *node, u32 size)
68 err = mutex_lock_interruptible(&ggtt->vm.mutex);
72 memset(node, 0, sizeof(*node));
73 err = drm_mm_insert_node_in_range(&ggtt->vm.mm, node,
74 size, 0, I915_COLOR_UNEVICTABLE,
75 0, ggtt->mappable_end,
78 mutex_unlock(&ggtt->vm.mutex);
84 remove_mappable_node(struct i915_ggtt *ggtt, struct drm_mm_node *node)
86 mutex_lock(&ggtt->vm.mutex);
87 drm_mm_remove_node(node);
88 mutex_unlock(&ggtt->vm.mutex);
92 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
93 struct drm_file *file)
95 struct drm_i915_private *i915 = to_i915(dev);
96 struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
97 struct drm_i915_gem_get_aperture *args = data;
101 if (mutex_lock_interruptible(&ggtt->vm.mutex))
104 pinned = ggtt->vm.reserved;
105 list_for_each_entry(vma, &ggtt->vm.bound_list, vm_link)
106 if (i915_vma_is_pinned(vma))
107 pinned += vma->node.size;
109 mutex_unlock(&ggtt->vm.mutex);
111 args->aper_size = ggtt->vm.total;
112 args->aper_available_size = args->aper_size - pinned;
117 int i915_gem_object_unbind(struct drm_i915_gem_object *obj,
120 struct intel_runtime_pm *rpm = &to_i915(obj->base.dev)->runtime_pm;
121 LIST_HEAD(still_in_list);
122 intel_wakeref_t wakeref;
123 struct i915_vma *vma;
126 assert_object_held(obj);
128 if (list_empty(&obj->vma.list))
132 * As some machines use ACPI to handle runtime-resume callbacks, and
133 * ACPI is quite kmalloc happy, we cannot resume beneath the vm->mutex
134 * as they are required by the shrinker. Ergo, we wake the device up
135 * first just in case.
137 wakeref = intel_runtime_pm_get(rpm);
141 spin_lock(&obj->vma.lock);
142 while (!ret && (vma = list_first_entry_or_null(&obj->vma.list,
145 struct i915_address_space *vm = vma->vm;
147 list_move_tail(&vma->obj_link, &still_in_list);
148 if (!i915_vma_is_bound(vma, I915_VMA_BIND_MASK))
151 if (flags & I915_GEM_OBJECT_UNBIND_TEST) {
157 if (!i915_vm_tryopen(vm))
160 /* Prevent vma being freed by i915_vma_parked as we unbind */
161 vma = __i915_vma_get(vma);
162 spin_unlock(&obj->vma.lock);
165 bool vm_trylock = !!(flags & I915_GEM_OBJECT_UNBIND_VM_TRYLOCK);
167 if (flags & I915_GEM_OBJECT_UNBIND_ASYNC) {
168 assert_object_held(vma->obj);
169 ret = i915_vma_unbind_async(vma, vm_trylock);
172 if (ret == -EBUSY && (flags & I915_GEM_OBJECT_UNBIND_ACTIVE ||
173 !i915_vma_is_active(vma))) {
175 if (mutex_trylock(&vma->vm->mutex)) {
176 ret = __i915_vma_unbind(vma);
177 mutex_unlock(&vma->vm->mutex);
182 ret = i915_vma_unbind(vma);
190 spin_lock(&obj->vma.lock);
192 list_splice_init(&still_in_list, &obj->vma.list);
193 spin_unlock(&obj->vma.lock);
195 if (ret == -EAGAIN && flags & I915_GEM_OBJECT_UNBIND_BARRIER) {
196 rcu_barrier(); /* flush the i915_vm_release() */
200 intel_runtime_pm_put(rpm, wakeref);
206 shmem_pread(struct page *page, int offset, int len, char __user *user_data,
215 drm_clflush_virt_range(vaddr + offset, len);
217 ret = __copy_to_user(user_data, vaddr + offset, len);
221 return ret ? -EFAULT : 0;
225 i915_gem_shmem_pread(struct drm_i915_gem_object *obj,
226 struct drm_i915_gem_pread *args)
228 unsigned int needs_clflush;
229 unsigned int idx, offset;
230 char __user *user_data;
234 ret = i915_gem_object_lock_interruptible(obj, NULL);
238 ret = i915_gem_object_pin_pages(obj);
242 ret = i915_gem_object_prepare_read(obj, &needs_clflush);
246 i915_gem_object_finish_access(obj);
247 i915_gem_object_unlock(obj);
250 user_data = u64_to_user_ptr(args->data_ptr);
251 offset = offset_in_page(args->offset);
252 for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {
253 struct page *page = i915_gem_object_get_page(obj, idx);
254 unsigned int length = min_t(u64, remain, PAGE_SIZE - offset);
256 ret = shmem_pread(page, offset, length, user_data,
266 i915_gem_object_unpin_pages(obj);
270 i915_gem_object_unpin_pages(obj);
272 i915_gem_object_unlock(obj);
277 gtt_user_read(struct io_mapping *mapping,
278 loff_t base, int offset,
279 char __user *user_data, int length)
282 unsigned long unwritten;
284 /* We can use the cpu mem copy function because this is X86. */
285 vaddr = io_mapping_map_atomic_wc(mapping, base);
286 unwritten = __copy_to_user_inatomic(user_data,
287 (void __force *)vaddr + offset,
289 io_mapping_unmap_atomic(vaddr);
291 vaddr = io_mapping_map_wc(mapping, base, PAGE_SIZE);
292 unwritten = copy_to_user(user_data,
293 (void __force *)vaddr + offset,
295 io_mapping_unmap(vaddr);
300 static struct i915_vma *i915_gem_gtt_prepare(struct drm_i915_gem_object *obj,
301 struct drm_mm_node *node,
304 struct drm_i915_private *i915 = to_i915(obj->base.dev);
305 struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
306 struct i915_vma *vma;
307 struct i915_gem_ww_ctx ww;
310 i915_gem_ww_ctx_init(&ww, true);
312 vma = ERR_PTR(-ENODEV);
313 ret = i915_gem_object_lock(obj, &ww);
317 ret = i915_gem_object_set_to_gtt_domain(obj, write);
321 if (!i915_gem_object_is_tiled(obj))
322 vma = i915_gem_object_ggtt_pin_ww(obj, &ww, NULL, 0, 0,
324 PIN_NONBLOCK /* NOWARN */ |
326 if (vma == ERR_PTR(-EDEADLK)) {
329 } else if (!IS_ERR(vma)) {
330 node->start = i915_ggtt_offset(vma);
333 ret = insert_mappable_node(ggtt, node, PAGE_SIZE);
336 GEM_BUG_ON(!drm_mm_node_allocated(node));
340 ret = i915_gem_object_pin_pages(obj);
342 if (drm_mm_node_allocated(node)) {
343 ggtt->vm.clear_range(&ggtt->vm, node->start, node->size);
344 remove_mappable_node(ggtt, node);
351 if (ret == -EDEADLK) {
352 ret = i915_gem_ww_ctx_backoff(&ww);
356 i915_gem_ww_ctx_fini(&ww);
358 return ret ? ERR_PTR(ret) : vma;
361 static void i915_gem_gtt_cleanup(struct drm_i915_gem_object *obj,
362 struct drm_mm_node *node,
363 struct i915_vma *vma)
365 struct drm_i915_private *i915 = to_i915(obj->base.dev);
366 struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
368 i915_gem_object_unpin_pages(obj);
369 if (drm_mm_node_allocated(node)) {
370 ggtt->vm.clear_range(&ggtt->vm, node->start, node->size);
371 remove_mappable_node(ggtt, node);
378 i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
379 const struct drm_i915_gem_pread *args)
381 struct drm_i915_private *i915 = to_i915(obj->base.dev);
382 struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
383 intel_wakeref_t wakeref;
384 struct drm_mm_node node;
385 void __user *user_data;
386 struct i915_vma *vma;
390 wakeref = intel_runtime_pm_get(&i915->runtime_pm);
392 vma = i915_gem_gtt_prepare(obj, &node, false);
398 user_data = u64_to_user_ptr(args->data_ptr);
400 offset = args->offset;
403 /* Operation in this page
405 * page_base = page offset within aperture
406 * page_offset = offset within page
407 * page_length = bytes to copy for this page
409 u32 page_base = node.start;
410 unsigned page_offset = offset_in_page(offset);
411 unsigned page_length = PAGE_SIZE - page_offset;
412 page_length = remain < page_length ? remain : page_length;
413 if (drm_mm_node_allocated(&node)) {
414 ggtt->vm.insert_page(&ggtt->vm,
415 i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
416 node.start, I915_CACHE_NONE, 0);
418 page_base += offset & PAGE_MASK;
421 if (gtt_user_read(&ggtt->iomap, page_base, page_offset,
422 user_data, page_length)) {
427 remain -= page_length;
428 user_data += page_length;
429 offset += page_length;
432 i915_gem_gtt_cleanup(obj, &node, vma);
434 intel_runtime_pm_put(&i915->runtime_pm, wakeref);
439 * Reads data from the object referenced by handle.
440 * @dev: drm device pointer
441 * @data: ioctl data blob
442 * @file: drm file pointer
444 * On error, the contents of *data are undefined.
447 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
448 struct drm_file *file)
450 struct drm_i915_private *i915 = to_i915(dev);
451 struct drm_i915_gem_pread *args = data;
452 struct drm_i915_gem_object *obj;
455 /* PREAD is disallowed for all platforms after TGL-LP. This also
456 * covers all platforms with local memory.
458 if (GRAPHICS_VER(i915) >= 12 && !IS_TIGERLAKE(i915))
464 if (!access_ok(u64_to_user_ptr(args->data_ptr),
468 obj = i915_gem_object_lookup(file, args->handle);
472 /* Bounds check source. */
473 if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) {
478 trace_i915_gem_object_pread(obj, args->offset, args->size);
481 ret = obj->ops->pread(obj, args);
485 ret = i915_gem_object_wait(obj,
486 I915_WAIT_INTERRUPTIBLE,
487 MAX_SCHEDULE_TIMEOUT);
491 ret = i915_gem_shmem_pread(obj, args);
492 if (ret == -EFAULT || ret == -ENODEV)
493 ret = i915_gem_gtt_pread(obj, args);
496 i915_gem_object_put(obj);
500 /* This is the fast write path which cannot handle
501 * page faults in the source data
505 ggtt_write(struct io_mapping *mapping,
506 loff_t base, int offset,
507 char __user *user_data, int length)
510 unsigned long unwritten;
512 /* We can use the cpu mem copy function because this is X86. */
513 vaddr = io_mapping_map_atomic_wc(mapping, base);
514 unwritten = __copy_from_user_inatomic_nocache((void __force *)vaddr + offset,
516 io_mapping_unmap_atomic(vaddr);
518 vaddr = io_mapping_map_wc(mapping, base, PAGE_SIZE);
519 unwritten = copy_from_user((void __force *)vaddr + offset,
521 io_mapping_unmap(vaddr);
528 * This is the fast pwrite path, where we copy the data directly from the
529 * user into the GTT, uncached.
530 * @obj: i915 GEM object
531 * @args: pwrite arguments structure
534 i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
535 const struct drm_i915_gem_pwrite *args)
537 struct drm_i915_private *i915 = to_i915(obj->base.dev);
538 struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
539 struct intel_runtime_pm *rpm = &i915->runtime_pm;
540 intel_wakeref_t wakeref;
541 struct drm_mm_node node;
542 struct i915_vma *vma;
544 void __user *user_data;
547 if (i915_gem_object_has_struct_page(obj)) {
549 * Avoid waking the device up if we can fallback, as
550 * waking/resuming is very slow (worst-case 10-100 ms
551 * depending on PCI sleeps and our own resume time).
552 * This easily dwarfs any performance advantage from
553 * using the cache bypass of indirect GGTT access.
555 wakeref = intel_runtime_pm_get_if_in_use(rpm);
559 /* No backing pages, no fallback, we must force GGTT access */
560 wakeref = intel_runtime_pm_get(rpm);
563 vma = i915_gem_gtt_prepare(obj, &node, true);
569 i915_gem_object_invalidate_frontbuffer(obj, ORIGIN_CPU);
571 user_data = u64_to_user_ptr(args->data_ptr);
572 offset = args->offset;
575 /* Operation in this page
577 * page_base = page offset within aperture
578 * page_offset = offset within page
579 * page_length = bytes to copy for this page
581 u32 page_base = node.start;
582 unsigned int page_offset = offset_in_page(offset);
583 unsigned int page_length = PAGE_SIZE - page_offset;
584 page_length = remain < page_length ? remain : page_length;
585 if (drm_mm_node_allocated(&node)) {
586 /* flush the write before we modify the GGTT */
587 intel_gt_flush_ggtt_writes(ggtt->vm.gt);
588 ggtt->vm.insert_page(&ggtt->vm,
589 i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
590 node.start, I915_CACHE_NONE, 0);
591 wmb(); /* flush modifications to the GGTT (insert_page) */
593 page_base += offset & PAGE_MASK;
595 /* If we get a fault while copying data, then (presumably) our
596 * source page isn't available. Return the error and we'll
597 * retry in the slow path.
598 * If the object is non-shmem backed, we retry again with the
599 * path that handles page fault.
601 if (ggtt_write(&ggtt->iomap, page_base, page_offset,
602 user_data, page_length)) {
607 remain -= page_length;
608 user_data += page_length;
609 offset += page_length;
612 intel_gt_flush_ggtt_writes(ggtt->vm.gt);
613 i915_gem_object_flush_frontbuffer(obj, ORIGIN_CPU);
615 i915_gem_gtt_cleanup(obj, &node, vma);
617 intel_runtime_pm_put(rpm, wakeref);
621 /* Per-page copy function for the shmem pwrite fastpath.
622 * Flushes invalid cachelines before writing to the target if
623 * needs_clflush_before is set and flushes out any written cachelines after
624 * writing if needs_clflush is set.
627 shmem_pwrite(struct page *page, int offset, int len, char __user *user_data,
628 bool needs_clflush_before,
629 bool needs_clflush_after)
636 if (needs_clflush_before)
637 drm_clflush_virt_range(vaddr + offset, len);
639 ret = __copy_from_user(vaddr + offset, user_data, len);
640 if (!ret && needs_clflush_after)
641 drm_clflush_virt_range(vaddr + offset, len);
645 return ret ? -EFAULT : 0;
649 i915_gem_shmem_pwrite(struct drm_i915_gem_object *obj,
650 const struct drm_i915_gem_pwrite *args)
652 unsigned int partial_cacheline_write;
653 unsigned int needs_clflush;
654 unsigned int offset, idx;
655 void __user *user_data;
659 ret = i915_gem_object_lock_interruptible(obj, NULL);
663 ret = i915_gem_object_pin_pages(obj);
667 ret = i915_gem_object_prepare_write(obj, &needs_clflush);
671 i915_gem_object_finish_access(obj);
672 i915_gem_object_unlock(obj);
674 /* If we don't overwrite a cacheline completely we need to be
675 * careful to have up-to-date data by first clflushing. Don't
676 * overcomplicate things and flush the entire patch.
678 partial_cacheline_write = 0;
679 if (needs_clflush & CLFLUSH_BEFORE)
680 partial_cacheline_write = boot_cpu_data.x86_clflush_size - 1;
682 user_data = u64_to_user_ptr(args->data_ptr);
684 offset = offset_in_page(args->offset);
685 for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {
686 struct page *page = i915_gem_object_get_page(obj, idx);
687 unsigned int length = min_t(u64, remain, PAGE_SIZE - offset);
689 ret = shmem_pwrite(page, offset, length, user_data,
690 (offset | length) & partial_cacheline_write,
691 needs_clflush & CLFLUSH_AFTER);
700 i915_gem_object_flush_frontbuffer(obj, ORIGIN_CPU);
702 i915_gem_object_unpin_pages(obj);
706 i915_gem_object_unpin_pages(obj);
708 i915_gem_object_unlock(obj);
713 * Writes data to the object referenced by handle.
715 * @data: ioctl data blob
718 * On error, the contents of the buffer that were to be modified are undefined.
721 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
722 struct drm_file *file)
724 struct drm_i915_private *i915 = to_i915(dev);
725 struct drm_i915_gem_pwrite *args = data;
726 struct drm_i915_gem_object *obj;
729 /* PWRITE is disallowed for all platforms after TGL-LP. This also
730 * covers all platforms with local memory.
732 if (GRAPHICS_VER(i915) >= 12 && !IS_TIGERLAKE(i915))
738 if (!access_ok(u64_to_user_ptr(args->data_ptr), args->size))
741 obj = i915_gem_object_lookup(file, args->handle);
745 /* Bounds check destination. */
746 if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) {
751 /* Writes not allowed into this read-only object */
752 if (i915_gem_object_is_readonly(obj)) {
757 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
760 if (obj->ops->pwrite)
761 ret = obj->ops->pwrite(obj, args);
765 ret = i915_gem_object_wait(obj,
766 I915_WAIT_INTERRUPTIBLE |
768 MAX_SCHEDULE_TIMEOUT);
773 /* We can only do the GTT pwrite on untiled buffers, as otherwise
774 * it would end up going through the fenced access, and we'll get
775 * different detiling behavior between reading and writing.
776 * pread/pwrite currently are reading and writing from the CPU
777 * perspective, requiring manual detiling by the client.
779 if (!i915_gem_object_has_struct_page(obj) ||
780 i915_gem_cpu_write_needs_clflush(obj))
781 /* Note that the gtt paths might fail with non-page-backed user
782 * pointers (e.g. gtt mappings when moving data between
783 * textures). Fallback to the shmem path in that case.
785 ret = i915_gem_gtt_pwrite_fast(obj, args);
787 if (ret == -EFAULT || ret == -ENOSPC) {
788 if (i915_gem_object_has_struct_page(obj))
789 ret = i915_gem_shmem_pwrite(obj, args);
793 i915_gem_object_put(obj);
798 * Called when user space has done writes to this buffer
800 * @data: ioctl data blob
804 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
805 struct drm_file *file)
807 struct drm_i915_gem_sw_finish *args = data;
808 struct drm_i915_gem_object *obj;
810 obj = i915_gem_object_lookup(file, args->handle);
815 * Proxy objects are barred from CPU access, so there is no
816 * need to ban sw_finish as it is a nop.
819 /* Pinned buffers may be scanout, so flush the cache */
820 i915_gem_object_flush_if_display(obj);
821 i915_gem_object_put(obj);
826 void i915_gem_runtime_suspend(struct drm_i915_private *i915)
828 struct drm_i915_gem_object *obj, *on;
832 * Only called during RPM suspend. All users of the userfault_list
833 * must be holding an RPM wakeref to ensure that this can not
834 * run concurrently with themselves (and use the struct_mutex for
835 * protection between themselves).
838 list_for_each_entry_safe(obj, on,
839 &to_gt(i915)->ggtt->userfault_list, userfault_link)
840 __i915_gem_object_release_mmap_gtt(obj);
843 * The fence will be lost when the device powers down. If any were
844 * in use by hardware (i.e. they are pinned), we should not be powering
845 * down! All other fences will be reacquired by the user upon waking.
847 for (i = 0; i < to_gt(i915)->ggtt->num_fences; i++) {
848 struct i915_fence_reg *reg = &to_gt(i915)->ggtt->fence_regs[i];
851 * Ideally we want to assert that the fence register is not
852 * live at this point (i.e. that no piece of code will be
853 * trying to write through fence + GTT, as that both violates
854 * our tracking of activity and associated locking/barriers,
855 * but also is illegal given that the hw is powered down).
857 * Previously we used reg->pin_count as a "liveness" indicator.
858 * That is not sufficient, and we need a more fine-grained
859 * tool if we want to have a sanity check here.
865 GEM_BUG_ON(i915_vma_has_userfault(reg->vma));
870 static void discard_ggtt_vma(struct i915_vma *vma)
872 struct drm_i915_gem_object *obj = vma->obj;
874 spin_lock(&obj->vma.lock);
875 if (!RB_EMPTY_NODE(&vma->obj_node)) {
876 rb_erase(&vma->obj_node, &obj->vma.tree);
877 RB_CLEAR_NODE(&vma->obj_node);
879 spin_unlock(&obj->vma.lock);
883 i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object *obj,
884 struct i915_gem_ww_ctx *ww,
885 const struct i915_ggtt_view *view,
886 u64 size, u64 alignment, u64 flags)
888 struct drm_i915_private *i915 = to_i915(obj->base.dev);
889 struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
890 struct i915_vma *vma;
895 if (flags & PIN_MAPPABLE &&
896 (!view || view->type == I915_GGTT_VIEW_NORMAL)) {
898 * If the required space is larger than the available
899 * aperture, we will not able to find a slot for the
900 * object and unbinding the object now will be in
901 * vain. Worse, doing so may cause us to ping-pong
902 * the object in and out of the Global GTT and
903 * waste a lot of cycles under the mutex.
905 if (obj->base.size > ggtt->mappable_end)
906 return ERR_PTR(-E2BIG);
909 * If NONBLOCK is set the caller is optimistically
910 * trying to cache the full object within the mappable
911 * aperture, and *must* have a fallback in place for
912 * situations where we cannot bind the object. We
913 * can be a little more lax here and use the fallback
914 * more often to avoid costly migrations of ourselves
915 * and other objects within the aperture.
917 * Half-the-aperture is used as a simple heuristic.
918 * More interesting would to do search for a free
919 * block prior to making the commitment to unbind.
920 * That caters for the self-harm case, and with a
921 * little more heuristics (e.g. NOFAULT, NOEVICT)
922 * we could try to minimise harm to others.
924 if (flags & PIN_NONBLOCK &&
925 obj->base.size > ggtt->mappable_end / 2)
926 return ERR_PTR(-ENOSPC);
930 vma = i915_vma_instance(obj, &ggtt->vm, view);
934 if (i915_vma_misplaced(vma, size, alignment, flags)) {
935 if (flags & PIN_NONBLOCK) {
936 if (i915_vma_is_pinned(vma) || i915_vma_is_active(vma))
937 return ERR_PTR(-ENOSPC);
939 if (flags & PIN_MAPPABLE &&
940 vma->fence_size > ggtt->mappable_end / 2)
941 return ERR_PTR(-ENOSPC);
944 if (i915_vma_is_pinned(vma) || i915_vma_is_active(vma)) {
945 discard_ggtt_vma(vma);
949 ret = i915_vma_unbind(vma);
954 ret = i915_vma_pin_ww(vma, ww, size, alignment, flags | PIN_GLOBAL);
959 if (vma->fence && !i915_gem_object_is_tiled(obj)) {
960 mutex_lock(&ggtt->vm.mutex);
961 i915_vma_revoke_fence(vma);
962 mutex_unlock(&ggtt->vm.mutex);
965 ret = i915_vma_wait_for_bind(vma);
974 struct i915_vma * __must_check
975 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
976 const struct i915_ggtt_view *view,
977 u64 size, u64 alignment, u64 flags)
979 struct i915_gem_ww_ctx ww;
980 struct i915_vma *ret;
983 for_i915_gem_ww(&ww, err, true) {
984 err = i915_gem_object_lock(obj, &ww);
988 ret = i915_gem_object_ggtt_pin_ww(obj, &ww, view, size,
994 return err ? ERR_PTR(err) : ret;
998 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
999 struct drm_file *file_priv)
1001 struct drm_i915_private *i915 = to_i915(dev);
1002 struct drm_i915_gem_madvise *args = data;
1003 struct drm_i915_gem_object *obj;
1006 switch (args->madv) {
1007 case I915_MADV_DONTNEED:
1008 case I915_MADV_WILLNEED:
1014 obj = i915_gem_object_lookup(file_priv, args->handle);
1018 err = i915_gem_object_lock_interruptible(obj, NULL);
1022 if (i915_gem_object_has_pages(obj) &&
1023 i915_gem_object_is_tiled(obj) &&
1024 i915->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
1025 if (obj->mm.madv == I915_MADV_WILLNEED) {
1026 GEM_BUG_ON(!i915_gem_object_has_tiling_quirk(obj));
1027 i915_gem_object_clear_tiling_quirk(obj);
1028 i915_gem_object_make_shrinkable(obj);
1030 if (args->madv == I915_MADV_WILLNEED) {
1031 GEM_BUG_ON(i915_gem_object_has_tiling_quirk(obj));
1032 i915_gem_object_make_unshrinkable(obj);
1033 i915_gem_object_set_tiling_quirk(obj);
1037 if (obj->mm.madv != __I915_MADV_PURGED) {
1038 obj->mm.madv = args->madv;
1039 if (obj->ops->adjust_lru)
1040 obj->ops->adjust_lru(obj);
1043 if (i915_gem_object_has_pages(obj) ||
1044 i915_gem_object_has_self_managed_shrink_list(obj)) {
1045 unsigned long flags;
1047 spin_lock_irqsave(&i915->mm.obj_lock, flags);
1048 if (!list_empty(&obj->mm.link)) {
1049 struct list_head *list;
1051 if (obj->mm.madv != I915_MADV_WILLNEED)
1052 list = &i915->mm.purge_list;
1054 list = &i915->mm.shrink_list;
1055 list_move_tail(&obj->mm.link, list);
1058 spin_unlock_irqrestore(&i915->mm.obj_lock, flags);
1061 /* if the object is no longer attached, discard its backing storage */
1062 if (obj->mm.madv == I915_MADV_DONTNEED &&
1063 !i915_gem_object_has_pages(obj))
1064 i915_gem_object_truncate(obj);
1066 args->retained = obj->mm.madv != __I915_MADV_PURGED;
1068 i915_gem_object_unlock(obj);
1070 i915_gem_object_put(obj);
1074 int i915_gem_init(struct drm_i915_private *dev_priv)
1078 /* We need to fallback to 4K pages if host doesn't support huge gtt. */
1079 if (intel_vgpu_active(dev_priv) && !intel_vgpu_has_huge_gtt(dev_priv))
1080 mkwrite_device_info(dev_priv)->page_sizes =
1081 I915_GTT_PAGE_SIZE_4K;
1083 ret = i915_gem_init_userptr(dev_priv);
1087 intel_uc_fetch_firmwares(&to_gt(dev_priv)->uc);
1088 intel_wopcm_init(&dev_priv->wopcm);
1090 ret = i915_init_ggtt(dev_priv);
1092 GEM_BUG_ON(ret == -EIO);
1097 * Despite its name intel_init_clock_gating applies both display
1098 * clock gating workarounds; GT mmio workarounds and the occasional
1099 * GT power context workaround. Worse, sometimes it includes a context
1100 * register workaround which we need to apply before we record the
1101 * default HW state for all contexts.
1103 * FIXME: break up the workarounds and apply them at the right time!
1105 intel_init_clock_gating(dev_priv);
1107 ret = intel_gt_init(to_gt(dev_priv));
1114 * Unwinding is complicated by that we want to handle -EIO to mean
1115 * disable GPU submission but keep KMS alive. We want to mark the
1116 * HW as irrevisibly wedged, but keep enough state around that the
1117 * driver doesn't explode during runtime.
1120 i915_gem_drain_workqueue(dev_priv);
1123 intel_uc_cleanup_firmwares(&to_gt(dev_priv)->uc);
1127 * Allow engines or uC initialisation to fail by marking the GPU
1128 * as wedged. But we only want to do this when the GPU is angry,
1129 * for all other failure, such as an allocation failure, bail.
1131 if (!intel_gt_is_wedged(to_gt(dev_priv))) {
1132 i915_probe_error(dev_priv,
1133 "Failed to initialize GPU, declaring it wedged!\n");
1134 intel_gt_set_wedged(to_gt(dev_priv));
1137 /* Minimal basic recovery for KMS */
1138 ret = i915_ggtt_enable_hw(dev_priv);
1139 i915_ggtt_resume(to_gt(dev_priv)->ggtt);
1140 intel_init_clock_gating(dev_priv);
1143 i915_gem_drain_freed_objects(dev_priv);
1148 void i915_gem_driver_register(struct drm_i915_private *i915)
1150 i915_gem_driver_register__shrinker(i915);
1152 intel_engines_driver_register(i915);
1155 void i915_gem_driver_unregister(struct drm_i915_private *i915)
1157 i915_gem_driver_unregister__shrinker(i915);
1160 void i915_gem_driver_remove(struct drm_i915_private *dev_priv)
1162 intel_wakeref_auto_fini(&to_gt(dev_priv)->ggtt->userfault_wakeref);
1164 i915_gem_suspend_late(dev_priv);
1165 intel_gt_driver_remove(to_gt(dev_priv));
1166 dev_priv->uabi_engines = RB_ROOT;
1168 /* Flush any outstanding unpin_work. */
1169 i915_gem_drain_workqueue(dev_priv);
1171 i915_gem_drain_freed_objects(dev_priv);
1174 void i915_gem_driver_release(struct drm_i915_private *dev_priv)
1176 intel_gt_driver_release(to_gt(dev_priv));
1178 intel_uc_cleanup_firmwares(&to_gt(dev_priv)->uc);
1180 i915_gem_drain_freed_objects(dev_priv);
1182 drm_WARN_ON(&dev_priv->drm, !list_empty(&dev_priv->gem.contexts.list));
1185 static void i915_gem_init__mm(struct drm_i915_private *i915)
1187 spin_lock_init(&i915->mm.obj_lock);
1189 init_llist_head(&i915->mm.free_list);
1191 INIT_LIST_HEAD(&i915->mm.purge_list);
1192 INIT_LIST_HEAD(&i915->mm.shrink_list);
1194 i915_gem_init__objects(i915);
1197 void i915_gem_init_early(struct drm_i915_private *dev_priv)
1199 i915_gem_init__mm(dev_priv);
1200 i915_gem_init__contexts(dev_priv);
1202 spin_lock_init(&dev_priv->fb_tracking.lock);
1205 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv)
1207 i915_gem_drain_freed_objects(dev_priv);
1208 GEM_BUG_ON(!llist_empty(&dev_priv->mm.free_list));
1209 GEM_BUG_ON(atomic_read(&dev_priv->mm.free_count));
1210 drm_WARN_ON(&dev_priv->drm, dev_priv->mm.shrink_count);
1213 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file)
1215 struct drm_i915_file_private *file_priv;
1220 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
1224 file->driver_priv = file_priv;
1225 file_priv->dev_priv = i915;
1226 file_priv->file = file;
1228 file_priv->bsd_engine = -1;
1229 file_priv->hang_timestamp = jiffies;
1231 ret = i915_gem_context_open(i915, file);
1238 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1239 #include "selftests/mock_gem_device.c"
1240 #include "selftests/i915_gem.c"