drivers/gpu/drm/i915/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 #include <uapi/drm/i915_drm.h>
  34 #include <uapi/drm/drm_fourcc.h>
  35
  36 #include <asm/hypervisor.h>
  37
  38 #include <linux/io-mapping.h>
  39 #include <linux/i2c.h>
  40 #include <linux/i2c-algo-bit.h>
  41 #include <linux/backlight.h>
  42 #include <linux/hash.h>
  43 #include <linux/intel-iommu.h>
  44 #include <linux/kref.h>
  45 #include <linux/mm_types.h>
  46 #include <linux/perf_event.h>
  47 #include <linux/pm_qos.h>
  48 #include <linux/dma-resv.h>
  49 #include <linux/shmem_fs.h>
  50 #include <linux/stackdepot.h>
  51 #include <linux/xarray.h>
  52
  53 #include <drm/intel-gtt.h>
  54 #include <drm/drm_gem.h>
  55 #include <drm/drm_auth.h>
  56 #include <drm/drm_cache.h>
  57 #include <drm/drm_util.h>
  58 #include <drm/drm_dsc.h>
  59 #include <drm/drm_atomic.h>
  60 #include <drm/drm_connector.h>
  61 #include <drm/i915_mei_hdcp_interface.h>
  62
  63 #include "i915_params.h"
  64 #include "i915_reg.h"
  65 #include "i915_utils.h"
  66
  67 #include "display/intel_bios.h"
  68 #include "display/intel_display.h"
  69 #include "display/intel_display_power.h"
  70 #include "display/intel_dpll_mgr.h"
  71 #include "display/intel_dsb.h"
  72 #include "display/intel_frontbuffer.h"
  73 #include "display/intel_global_state.h"
  74 #include "display/intel_gmbus.h"
  75 #include "display/intel_opregion.h"
  76
  77 #include "gem/i915_gem_context_types.h"
  78 #include "gem/i915_gem_shrinker.h"
  79 #include "gem/i915_gem_stolen.h"
  80
  81 #include "gt/intel_engine.h"
  82 #include "gt/intel_gt_types.h"
  83 #include "gt/intel_region_lmem.h"
  84 #include "gt/intel_workarounds.h"
  85 #include "gt/uc/intel_uc.h"
  86
  87 #include "intel_device_info.h"
  88 #include "intel_memory_region.h"
  89 #include "intel_pch.h"
  90 #include "intel_runtime_pm.h"
  91 #include "intel_step.h"
  92 #include "intel_uncore.h"
  93 #include "intel_wakeref.h"
  94 #include "intel_wopcm.h"
  95
  96 #include "i915_gem.h"
  97 #include "i915_gem_gtt.h"
  98 #include "i915_gpu_error.h"
  99 #include "i915_perf_types.h"
 100 #include "i915_request.h"
 101 #include "i915_scheduler.h"
 102 #include "gt/intel_timeline.h"
 103 #include "i915_vma.h"
 104 #include "i915_irq.h"
 105
 106
 107 /* General customization:
 108  */
 109
 110 #define DRIVER_NAME             "i915"
 111 #define DRIVER_DESC             "Intel Graphics"
 112 #define DRIVER_DATE             "20201103"
 113 #define DRIVER_TIMESTAMP        1604406085
 114
 115 struct drm_i915_gem_object;
 116
 117 enum hpd_pin {
 118         HPD_NONE = 0,
 119         HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
 120         HPD_CRT,
 121         HPD_SDVO_B,
 122         HPD_SDVO_C,
 123         HPD_PORT_A,
 124         HPD_PORT_B,
 125         HPD_PORT_C,
 126         HPD_PORT_D,
 127         HPD_PORT_E,
 128         HPD_PORT_TC1,
 129         HPD_PORT_TC2,
 130         HPD_PORT_TC3,
 131         HPD_PORT_TC4,
 132         HPD_PORT_TC5,
 133         HPD_PORT_TC6,
 134
 135         HPD_NUM_PINS
 136 };
 137
 138 #define for_each_hpd_pin(__pin) \
 139         for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
 140
 141 /* Threshold == 5 for long IRQs, 50 for short */
 142 #define HPD_STORM_DEFAULT_THRESHOLD 50
 143
 144 struct i915_hotplug {
 145         struct delayed_work hotplug_work;
 146
 147         const u32 *hpd, *pch_hpd;
 148
 149         struct {
 150                 unsigned long last_jiffies;
 151                 int count;
 152                 enum {
 153                         HPD_ENABLED = 0,
 154                         HPD_DISABLED = 1,
 155                         HPD_MARK_DISABLED = 2
 156                 } state;
 157         } stats[HPD_NUM_PINS];
 158         u32 event_bits;
 159         u32 retry_bits;
 160         struct delayed_work reenable_work;
 161
 162         u32 long_port_mask;
 163         u32 short_port_mask;
 164         struct work_struct dig_port_work;
 165
 166         struct work_struct poll_init_work;
 167         bool poll_enabled;
 168
 169         unsigned int hpd_storm_threshold;
 170         /* Whether or not to count short HPD IRQs in HPD storms */
 171         u8 hpd_short_storm_enabled;
 172
 173         /*
 174          * if we get a HPD irq from DP and a HPD irq from non-DP
 175          * the non-DP HPD could block the workqueue on a mode config
 176          * mutex getting, that userspace may have taken. However
 177          * userspace is waiting on the DP workqueue to run which is
 178          * blocked behind the non-DP one.
 179          */
 180         struct workqueue_struct *dp_wq;
 181 };
 182
 183 #define I915_GEM_GPU_DOMAINS \
 184         (I915_GEM_DOMAIN_RENDER | \
 185          I915_GEM_DOMAIN_SAMPLER | \
 186          I915_GEM_DOMAIN_COMMAND | \
 187          I915_GEM_DOMAIN_INSTRUCTION | \
 188          I915_GEM_DOMAIN_VERTEX)
 189
 190 struct drm_i915_private;
 191 struct i915_mm_struct;
 192 struct i915_mmu_object;
 193
 194 struct drm_i915_file_private {
 195         struct drm_i915_private *dev_priv;
 196
 197         union {
 198                 struct drm_file *file;
 199                 struct rcu_head rcu;
 200         };
 201
 202         struct xarray context_xa;
 203         struct xarray vm_xa;
 204
 205         unsigned int bsd_engine;
 206
 207 /*
 208  * Every context ban increments per client ban score. Also
 209  * hangs in short succession increments ban score. If ban threshold
 210  * is reached, client is considered banned and submitting more work
 211  * will fail. This is a stop gap measure to limit the badly behaving
 212  * clients access to gpu. Note that unbannable contexts never increment
 213  * the client ban score.
 214  */
 215 #define I915_CLIENT_SCORE_HANG_FAST     1
 216 #define   I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
 217 #define I915_CLIENT_SCORE_CONTEXT_BAN   3
 218 #define I915_CLIENT_SCORE_BANNED        9
 219         /** ban_score: Accumulated score of all ctx bans and fast hangs. */
 220         atomic_t ban_score;
 221         unsigned long hang_timestamp;
 222 };
 223
 224 /* Interface history:
 225  *
 226  * 1.1: Original.
 227  * 1.2: Add Power Management
 228  * 1.3: Add vblank support
 229  * 1.4: Fix cmdbuffer path, add heap destroy
 230  * 1.5: Add vblank pipe configuration
 231  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 232  *      - Support vertical blank on secondary display pipe
 233  */
 234 #define DRIVER_MAJOR            1
 235 #define DRIVER_MINOR            6
 236 #define DRIVER_PATCHLEVEL       0
 237
 238 struct intel_overlay;
 239 struct intel_overlay_error_state;
 240
 241 struct sdvo_device_mapping {
 242         u8 initialized;
 243         u8 dvo_port;
 244         u8 slave_addr;
 245         u8 dvo_wiring;
 246         u8 i2c_pin;
 247         u8 ddc_pin;
 248 };
 249
 250 struct intel_connector;
 251 struct intel_encoder;
 252 struct intel_atomic_state;
 253 struct intel_cdclk_config;
 254 struct intel_cdclk_state;
 255 struct intel_cdclk_vals;
 256 struct intel_initial_plane_config;
 257 struct intel_crtc;
 258 struct intel_limit;
 259 struct dpll;
 260
 261 struct drm_i915_display_funcs {
 262         void (*get_cdclk)(struct drm_i915_private *dev_priv,
 263                           struct intel_cdclk_config *cdclk_config);
 264         void (*set_cdclk)(struct drm_i915_private *dev_priv,
 265                           const struct intel_cdclk_config *cdclk_config,
 266                           enum pipe pipe);
 267         int (*bw_calc_min_cdclk)(struct intel_atomic_state *state);
 268         int (*get_fifo_size)(struct drm_i915_private *dev_priv,
 269                              enum i9xx_plane_id i9xx_plane);
 270         int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state);
 271         int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state);
 272         void (*initial_watermarks)(struct intel_atomic_state *state,
 273                                    struct intel_crtc *crtc);
 274         void (*atomic_update_watermarks)(struct intel_atomic_state *state,
 275                                          struct intel_crtc *crtc);
 276         void (*optimize_watermarks)(struct intel_atomic_state *state,
 277                                     struct intel_crtc *crtc);
 278         int (*compute_global_watermarks)(struct intel_atomic_state *state);
 279         void (*update_wm)(struct intel_crtc *crtc);
 280         int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
 281         u8 (*calc_voltage_level)(int cdclk);
 282         /* Returns the active state of the crtc, and if the crtc is active,
 283          * fills out the pipe-config with the hw state. */
 284         bool (*get_pipe_config)(struct intel_crtc *,
 285                                 struct intel_crtc_state *);
 286         void (*get_initial_plane_config)(struct intel_crtc *,
 287                                          struct intel_initial_plane_config *);
 288         int (*crtc_compute_clock)(struct intel_crtc *crtc,
 289                                   struct intel_crtc_state *crtc_state);
 290         void (*crtc_enable)(struct intel_atomic_state *state,
 291                             struct intel_crtc *crtc);
 292         void (*crtc_disable)(struct intel_atomic_state *state,
 293                              struct intel_crtc *crtc);
 294         void (*commit_modeset_enables)(struct intel_atomic_state *state);
 295         void (*commit_modeset_disables)(struct intel_atomic_state *state);
 296         void (*audio_codec_enable)(struct intel_encoder *encoder,
 297                                    const struct intel_crtc_state *crtc_state,
 298                                    const struct drm_connector_state *conn_state);
 299         void (*audio_codec_disable)(struct intel_encoder *encoder,
 300                                     const struct intel_crtc_state *old_crtc_state,
 301                                     const struct drm_connector_state *old_conn_state);
 302         void (*fdi_link_train)(struct intel_crtc *crtc,
 303                                const struct intel_crtc_state *crtc_state);
 304         void (*init_clock_gating)(struct drm_i915_private *dev_priv);
 305         void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
 306         /* clock updates for mode set */
 307         /* cursor updates */
 308         /* render clock increase/decrease */
 309         /* display clock increase/decrease */
 310         /* pll clock increase/decrease */
 311
 312         int (*color_check)(struct intel_crtc_state *crtc_state);
 313         /*
 314          * Program double buffered color management registers during
 315          * vblank evasion. The registers should then latch during the
 316          * next vblank start, alongside any other double buffered registers
 317          * involved with the same commit.
 318          */
 319         void (*color_commit)(const struct intel_crtc_state *crtc_state);
 320         /*
 321          * Load LUTs (and other single buffered color management
 322          * registers). Will (hopefully) be called during the vblank
 323          * following the latching of any double buffered registers
 324          * involved with the same commit.
 325          */
 326         void (*load_luts)(const struct intel_crtc_state *crtc_state);
 327         void (*read_luts)(struct intel_crtc_state *crtc_state);
 328 };
 329
 330 struct intel_csr {
 331         struct work_struct work;
 332         const char *fw_path;
 333         u32 required_version;
 334         u32 max_fw_size; /* bytes */
 335         u32 *dmc_payload;
 336         u32 dmc_fw_size; /* dwords */
 337         u32 version;
 338         u32 mmio_count;
 339         i915_reg_t mmioaddr[20];
 340         u32 mmiodata[20];
 341         u32 dc_state;
 342         u32 target_dc_state;
 343         u32 allowed_dc_mask;
 344         intel_wakeref_t wakeref;
 345 };
 346
 347 enum i915_cache_level {
 348         I915_CACHE_NONE = 0,
 349         I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
 350         I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
 351                               caches, eg sampler/render caches, and the
 352                               large Last-Level-Cache. LLC is coherent with
 353                               the CPU, but L3 is only visible to the GPU. */
 354         I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
 355 };
 356
 357 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
 358
 359 struct intel_fbc {
 360         /* This is always the inner lock when overlapping with struct_mutex and
 361          * it's the outer lock when overlapping with stolen_lock. */
 362         struct mutex lock;
 363         unsigned threshold;
 364         unsigned int possible_framebuffer_bits;
 365         unsigned int busy_bits;
 366         struct intel_crtc *crtc;
 367
 368         struct drm_mm_node compressed_fb;
 369         struct drm_mm_node *compressed_llb;
 370
 371         bool false_color;
 372
 373         bool active;
 374         bool activated;
 375         bool flip_pending;
 376
 377         bool underrun_detected;
 378         struct work_struct underrun_work;
 379
 380         /*
 381          * Due to the atomic rules we can't access some structures without the
 382          * appropriate locking, so we cache information here in order to avoid
 383          * these problems.
 384          */
 385         struct intel_fbc_state_cache {
 386                 struct {
 387                         unsigned int mode_flags;
 388                         u32 hsw_bdw_pixel_rate;
 389                 } crtc;
 390
 391                 struct {
 392                         unsigned int rotation;
 393                         int src_w;
 394                         int src_h;
 395                         bool visible;
 396                         /*
 397                          * Display surface base address adjustement for
 398                          * pageflips. Note that on gen4+ this only adjusts up
 399                          * to a tile, offsets within a tile are handled in
 400                          * the hw itself (with the TILEOFF register).
 401                          */
 402                         int adjusted_x;
 403                         int adjusted_y;
 404
 405                         u16 pixel_blend_mode;
 406                 } plane;
 407
 408                 struct {
 409                         const struct drm_format_info *format;
 410                         unsigned int stride;
 411                         u64 modifier;
 412                 } fb;
 413
 414                 unsigned int fence_y_offset;
 415                 u16 gen9_wa_cfb_stride;
 416                 u16 interval;
 417                 s8 fence_id;
 418                 bool psr2_active;
 419         } state_cache;
 420
 421         /*
 422          * This structure contains everything that's relevant to program the
 423          * hardware registers. When we want to figure out if we need to disable
 424          * and re-enable FBC for a new configuration we just check if there's
 425          * something different in the struct. The genx_fbc_activate functions
 426          * are supposed to read from it in order to program the registers.
 427          */
 428         struct intel_fbc_reg_params {
 429                 struct {
 430                         enum pipe pipe;
 431                         enum i9xx_plane_id i9xx_plane;
 432                 } crtc;
 433
 434                 struct {
 435                         const struct drm_format_info *format;
 436                         unsigned int stride;
 437                         u64 modifier;
 438                 } fb;
 439
 440                 int cfb_size;
 441                 unsigned int fence_y_offset;
 442                 u16 gen9_wa_cfb_stride;
 443                 u16 interval;
 444                 s8 fence_id;
 445                 bool plane_visible;
 446         } params;
 447
 448         const char *no_fbc_reason;
 449 };
 450
 451 /*
 452  * HIGH_RR is the highest eDP panel refresh rate read from EDID
 453  * LOW_RR is the lowest eDP panel refresh rate found from EDID
 454  * parsing for same resolution.
 455  */
 456 enum drrs_refresh_rate_type {
 457         DRRS_HIGH_RR,
 458         DRRS_LOW_RR,
 459         DRRS_MAX_RR, /* RR count */
 460 };
 461
 462 enum drrs_support_type {
 463         DRRS_NOT_SUPPORTED = 0,
 464         STATIC_DRRS_SUPPORT = 1,
 465         SEAMLESS_DRRS_SUPPORT = 2
 466 };
 467
 468 struct intel_dp;
 469 struct i915_drrs {
 470         struct mutex mutex;
 471         struct delayed_work work;
 472         struct intel_dp *dp;
 473         unsigned busy_frontbuffer_bits;
 474         enum drrs_refresh_rate_type refresh_rate_type;
 475         enum drrs_support_type type;
 476 };
 477
 478 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
 479 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
 480 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
 481 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
 482 #define QUIRK_INCREASE_T12_DELAY (1<<6)
 483 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
 484
 485 struct intel_fbdev;
 486 struct intel_fbc_work;
 487
 488 struct intel_gmbus {
 489         struct i2c_adapter adapter;
 490 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
 491         u32 force_bit;
 492         u32 reg0;
 493         i915_reg_t gpio_reg;
 494         struct i2c_algo_bit_data bit_algo;
 495         struct drm_i915_private *dev_priv;
 496 };
 497
 498 struct i915_suspend_saved_registers {
 499         u32 saveDSPARB;
 500         u32 saveSWF0[16];
 501         u32 saveSWF1[16];
 502         u32 saveSWF3[3];
 503         u16 saveGCDGMBUS;
 504 };
 505
 506 struct vlv_s0ix_state;
 507
 508 #define MAX_L3_SLICES 2
 509 struct intel_l3_parity {
 510         u32 *remap_info[MAX_L3_SLICES];
 511         struct work_struct error_work;
 512         int which_slice;
 513 };
 514
 515 struct i915_gem_mm {
 516         /** Memory allocator for GTT stolen memory */
 517         struct drm_mm stolen;
 518         /** Protects the usage of the GTT stolen memory allocator. This is
 519          * always the inner lock when overlapping with struct_mutex. */
 520         struct mutex stolen_lock;
 521
 522         /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
 523         spinlock_t obj_lock;
 524
 525         /**
 526          * List of objects which are purgeable.
 527          */
 528         struct list_head purge_list;
 529
 530         /**
 531          * List of objects which have allocated pages and are shrinkable.
 532          */
 533         struct list_head shrink_list;
 534
 535         /**
 536          * List of objects which are pending destruction.
 537          */
 538         struct llist_head free_list;
 539         struct work_struct free_work;
 540         /**
 541          * Count of objects pending destructions. Used to skip needlessly
 542          * waiting on an RCU barrier if no objects are waiting to be freed.
 543          */
 544         atomic_t free_count;
 545
 546         /**
 547          * tmpfs instance used for shmem backed objects
 548          */
 549         struct vfsmount *gemfs;
 550
 551         struct intel_memory_region *regions[INTEL_REGION_UNKNOWN];
 552
 553         struct notifier_block oom_notifier;
 554         struct notifier_block vmap_notifier;
 555         struct shrinker shrinker;
 556
 557 #ifdef CONFIG_MMU_NOTIFIER
 558         /**
 559          * notifier_lock for mmu notifiers, memory may not be allocated
 560          * while holding this lock.
 561          */
 562         spinlock_t notifier_lock;
 563 #endif
 564
 565         /* shrinker accounting, also useful for userland debugging */
 566         u64 shrink_memory;
 567         u32 shrink_count;
 568 };
 569
 570 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
 571
 572 unsigned long i915_fence_context_timeout(const struct drm_i915_private *i915,
 573                                          u64 context);
 574
 575 static inline unsigned long
 576 i915_fence_timeout(const struct drm_i915_private *i915)
 577 {
 578         return i915_fence_context_timeout(i915, U64_MAX);
 579 }
 580
 581 /* Amount of SAGV/QGV points, BSpec precisely defines this */
 582 #define I915_NUM_QGV_POINTS 8
 583
 584 struct ddi_vbt_port_info {
 585         /* Non-NULL if port present. */
 586         struct intel_bios_encoder_data *devdata;
 587
 588         int max_tmds_clock;
 589
 590         /* This is an index in the HDMI/DVI DDI buffer translation table. */
 591         u8 hdmi_level_shift;
 592         u8 hdmi_level_shift_set:1;
 593
 594         u8 alternate_aux_channel;
 595         u8 alternate_ddc_pin;
 596
 597         int dp_max_link_rate;           /* 0 for not limited by VBT */
 598 };
 599
 600 enum psr_lines_to_wait {
 601         PSR_0_LINES_TO_WAIT = 0,
 602         PSR_1_LINE_TO_WAIT,
 603         PSR_4_LINES_TO_WAIT,
 604         PSR_8_LINES_TO_WAIT
 605 };
 606
 607 struct intel_vbt_data {
 608         /* bdb version */
 609         u16 version;
 610
 611         struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
 612         struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
 613
 614         /* Feature bits */
 615         unsigned int int_tv_support:1;
 616         unsigned int lvds_dither:1;
 617         unsigned int int_crt_support:1;
 618         unsigned int lvds_use_ssc:1;
 619         unsigned int int_lvds_support:1;
 620         unsigned int display_clock_mode:1;
 621         unsigned int fdi_rx_polarity_inverted:1;
 622         unsigned int panel_type:4;
 623         int lvds_ssc_freq;
 624         unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
 625         enum drm_panel_orientation orientation;
 626
 627         enum drrs_support_type drrs_type;
 628
 629         struct {
 630                 int rate;
 631                 int lanes;
 632                 int preemphasis;
 633                 int vswing;
 634                 bool low_vswing;
 635                 bool initialized;
 636                 int bpp;
 637                 struct edp_power_seq pps;
 638                 bool hobl;
 639         } edp;
 640
 641         struct {
 642                 bool enable;
 643                 bool full_link;
 644                 bool require_aux_wakeup;
 645                 int idle_frames;
 646                 enum psr_lines_to_wait lines_to_wait;
 647                 int tp1_wakeup_time_us;
 648                 int tp2_tp3_wakeup_time_us;
 649                 int psr2_tp2_tp3_wakeup_time_us;
 650         } psr;
 651
 652         struct {
 653                 u16 pwm_freq_hz;
 654                 bool present;
 655                 bool active_low_pwm;
 656                 u8 min_brightness;      /* min_brightness/255 of max */
 657                 u8 controller;          /* brightness controller number */
 658                 enum intel_backlight_type type;
 659         } backlight;
 660
 661         /* MIPI DSI */
 662         struct {
 663                 u16 panel_id;
 664                 struct mipi_config *config;
 665                 struct mipi_pps_data *pps;
 666                 u16 bl_ports;
 667                 u16 cabc_ports;
 668                 u8 seq_version;
 669                 u32 size;
 670                 u8 *data;
 671                 const u8 *sequence[MIPI_SEQ_MAX];
 672                 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
 673                 enum drm_panel_orientation orientation;
 674         } dsi;
 675
 676         int crt_ddc_pin;
 677
 678         struct list_head display_devices;
 679
 680         struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
 681         struct sdvo_device_mapping sdvo_mappings[2];
 682 };
 683
 684 enum intel_ddb_partitioning {
 685         INTEL_DDB_PART_1_2,
 686         INTEL_DDB_PART_5_6, /* IVB+ */
 687 };
 688
 689 struct ilk_wm_values {
 690         u32 wm_pipe[3];
 691         u32 wm_lp[3];
 692         u32 wm_lp_spr[3];
 693         bool enable_fbc_wm;
 694         enum intel_ddb_partitioning partitioning;
 695 };
 696
 697 struct g4x_pipe_wm {
 698         u16 plane[I915_MAX_PLANES];
 699         u16 fbc;
 700 };
 701
 702 struct g4x_sr_wm {
 703         u16 plane;
 704         u16 cursor;
 705         u16 fbc;
 706 };
 707
 708 struct vlv_wm_ddl_values {
 709         u8 plane[I915_MAX_PLANES];
 710 };
 711
 712 struct vlv_wm_values {
 713         struct g4x_pipe_wm pipe[3];
 714         struct g4x_sr_wm sr;
 715         struct vlv_wm_ddl_values ddl[3];
 716         u8 level;
 717         bool cxsr;
 718 };
 719
 720 struct g4x_wm_values {
 721         struct g4x_pipe_wm pipe[2];
 722         struct g4x_sr_wm sr;
 723         struct g4x_sr_wm hpll;
 724         bool cxsr;
 725         bool hpll_en;
 726         bool fbc_en;
 727 };
 728
 729 struct skl_ddb_entry {
 730         u16 start, end; /* in number of blocks, 'end' is exclusive */
 731 };
 732
 733 static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)
 734 {
 735         return entry->end - entry->start;
 736 }
 737
 738 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
 739                                        const struct skl_ddb_entry *e2)
 740 {
 741         if (e1->start == e2->start && e1->end == e2->end)
 742                 return true;
 743
 744         return false;
 745 }
 746
 747 struct i915_frontbuffer_tracking {
 748         spinlock_t lock;
 749
 750         /*
 751          * Tracking bits for delayed frontbuffer flushing du to gpu activity or
 752          * scheduled flips.
 753          */
 754         unsigned busy_bits;
 755         unsigned flip_bits;
 756 };
 757
 758 struct i915_virtual_gpu {
 759         struct mutex lock; /* serialises sending of g2v_notify command pkts */
 760         bool active;
 761         u32 caps;
 762 };
 763
 764 struct intel_cdclk_config {
 765         unsigned int cdclk, vco, ref, bypass;
 766         u8 voltage_level;
 767 };
 768
 769 struct i915_selftest_stash {
 770         atomic_t counter;
 771 };
 772
 773 struct drm_i915_private {
 774         struct drm_device drm;
 775
 776         /* FIXME: Device release actions should all be moved to drmm_ */
 777         bool do_release;
 778
 779         /* i915 device parameters */
 780         struct i915_params params;
 781
 782         const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
 783         struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
 784         struct intel_driver_caps caps;
 785
 786         /**
 787          * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
 788          * end of stolen which we can optionally use to create GEM objects
 789          * backed by stolen memory. Note that stolen_usable_size tells us
 790          * exactly how much of this we are actually allowed to use, given that
 791          * some portion of it is in fact reserved for use by hardware functions.
 792          */
 793         struct resource dsm;
 794         /**
 795          * Reseved portion of Data Stolen Memory
 796          */
 797         struct resource dsm_reserved;
 798
 799         /*
 800          * Stolen memory is segmented in hardware with different portions
 801          * offlimits to certain functions.
 802          *
 803          * The drm_mm is initialised to the total accessible range, as found
 804          * from the PCI config. On Broadwell+, this is further restricted to
 805          * avoid the first page! The upper end of stolen memory is reserved for
 806          * hardware functions and similarly removed from the accessible range.
 807          */
 808         resource_size_t stolen_usable_size;     /* Total size minus reserved ranges */
 809
 810         struct intel_uncore uncore;
 811         struct intel_uncore_mmio_debug mmio_debug;
 812
 813         struct i915_virtual_gpu vgpu;
 814
 815         struct intel_gvt *gvt;
 816
 817         struct intel_wopcm wopcm;
 818
 819         struct intel_csr csr;
 820
 821         struct intel_gmbus gmbus[GMBUS_NUM_PINS];
 822
 823         /** gmbus_mutex protects against concurrent usage of the single hw gmbus
 824          * controller on different i2c buses. */
 825         struct mutex gmbus_mutex;
 826
 827         /**
 828          * Base address of where the gmbus and gpio blocks are located (either
 829          * on PCH or on SoC for platforms without PCH).
 830          */
 831         u32 gpio_mmio_base;
 832
 833         u32 hsw_psr_mmio_adjust;
 834
 835         /* MMIO base address for MIPI regs */
 836         u32 mipi_mmio_base;
 837
 838         u32 pps_mmio_base;
 839
 840         wait_queue_head_t gmbus_wait_queue;
 841
 842         struct pci_dev *bridge_dev;
 843
 844         struct rb_root uabi_engines;
 845
 846         struct resource mch_res;
 847
 848         /* protects the irq masks */
 849         spinlock_t irq_lock;
 850
 851         bool display_irqs_enabled;
 852
 853         /* Sideband mailbox protection */
 854         struct mutex sb_lock;
 855         struct pm_qos_request sb_qos;
 856
 857         /** Cached value of IMR to avoid reads in updating the bitfield */
 858         union {
 859                 u32 irq_mask;
 860                 u32 de_irq_mask[I915_MAX_PIPES];
 861         };
 862         u32 pipestat_irq_mask[I915_MAX_PIPES];
 863
 864         struct i915_hotplug hotplug;
 865         struct intel_fbc fbc;
 866         struct i915_drrs drrs;
 867         struct intel_opregion opregion;
 868         struct intel_vbt_data vbt;
 869
 870         bool preserve_bios_swizzle;
 871
 872         /* overlay */
 873         struct intel_overlay *overlay;
 874
 875         /* backlight registers and fields in struct intel_panel */
 876         struct mutex backlight_lock;
 877
 878         /* protects panel power sequencer state */
 879         struct mutex pps_mutex;
 880
 881         unsigned int fsb_freq, mem_freq, is_ddr3;
 882         unsigned int skl_preferred_vco_freq;
 883         unsigned int max_cdclk_freq;
 884
 885         unsigned int max_dotclk_freq;
 886         unsigned int hpll_freq;
 887         unsigned int fdi_pll_freq;
 888         unsigned int czclk_freq;
 889
 890         struct {
 891                 /* The current hardware cdclk configuration */
 892                 struct intel_cdclk_config hw;
 893
 894                 /* cdclk, divider, and ratio table from bspec */
 895                 const struct intel_cdclk_vals *table;
 896
 897                 struct intel_global_obj obj;
 898         } cdclk;
 899
 900         struct {
 901                 /* The current hardware dbuf configuration */
 902                 u8 enabled_slices;
 903
 904                 struct intel_global_obj obj;
 905         } dbuf;
 906
 907         /**
 908          * wq - Driver workqueue for GEM.
 909          *
 910          * NOTE: Work items scheduled here are not allowed to grab any modeset
 911          * locks, for otherwise the flushing done in the pageflip code will
 912          * result in deadlocks.
 913          */
 914         struct workqueue_struct *wq;
 915
 916         /* ordered wq for modesets */
 917         struct workqueue_struct *modeset_wq;
 918         /* unbound hipri wq for page flips/plane updates */
 919         struct workqueue_struct *flip_wq;
 920
 921         /* Display functions */
 922         struct drm_i915_display_funcs display;
 923
 924         /* PCH chipset type */
 925         enum intel_pch pch_type;
 926         unsigned short pch_id;
 927
 928         unsigned long quirks;
 929
 930         struct drm_atomic_state *modeset_restore_state;
 931         struct drm_modeset_acquire_ctx reset_ctx;
 932
 933         struct i915_ggtt ggtt; /* VM representing the global address space */
 934
 935         struct i915_gem_mm mm;
 936
 937         /* Kernel Modesetting */
 938
 939         struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
 940         struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
 941
 942         /**
 943          * dpll and cdclk state is protected by connection_mutex
 944          * dpll.lock serializes intel_{prepare,enable,disable}_shared_dpll.
 945          * Must be global rather than per dpll, because on some platforms plls
 946          * share registers.
 947          */
 948         struct {
 949                 struct mutex lock;
 950
 951                 int num_shared_dpll;
 952                 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
 953                 const struct intel_dpll_mgr *mgr;
 954
 955                 struct {
 956                         int nssc;
 957                         int ssc;
 958                 } ref_clks;
 959         } dpll;
 960
 961         struct list_head global_obj_list;
 962
 963         /*
 964          * For reading active_pipes holding any crtc lock is
 965          * sufficient, for writing must hold all of them.
 966          */
 967         u8 active_pipes;
 968
 969         struct i915_wa_list gt_wa_list;
 970
 971         struct i915_frontbuffer_tracking fb_tracking;
 972
 973         struct intel_atomic_helper {
 974                 struct llist_head free_list;
 975                 struct work_struct free_work;
 976         } atomic_helper;
 977
 978         bool mchbar_need_disable;
 979
 980         struct intel_l3_parity l3_parity;
 981
 982         /*
 983          * HTI (aka HDPORT) state read during initial hw readout.  Most
 984          * platforms don't have HTI, so this will just stay 0.  Those that do
 985          * will use this later to figure out which PLLs and PHYs are unavailable
 986          * for driver usage.
 987          */
 988         u32 hti_state;
 989
 990         /*
 991          * edram size in MB.
 992          * Cannot be determined by PCIID. You must always read a register.
 993          */
 994         u32 edram_size_mb;
 995
 996         struct i915_power_domains power_domains;
 997
 998         struct i915_gpu_error gpu_error;
 999
1000         struct drm_i915_gem_object *vlv_pctx;
1001
1002         /* list of fbdev register on this device */
1003         struct intel_fbdev *fbdev;
1004         struct work_struct fbdev_suspend_work;
1005
1006         struct drm_property *broadcast_rgb_property;
1007         struct drm_property *force_audio_property;
1008
1009         /* hda/i915 audio component */
1010         struct i915_audio_component *audio_component;
1011         bool audio_component_registered;
1012         /**
1013          * av_mutex - mutex for audio/video sync
1014          *
1015          */
1016         struct mutex av_mutex;
1017         int audio_power_refcount;
1018         u32 audio_freq_cntrl;
1019
1020         u32 fdi_rx_config;
1021
1022         /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1023         u32 chv_phy_control;
1024         /*
1025          * Shadows for CHV DPLL_MD regs to keep the state
1026          * checker somewhat working in the presence hardware
1027          * crappiness (can't read out DPLL_MD for pipes B & C).
1028          */
1029         u32 chv_dpll_md[I915_MAX_PIPES];
1030         u32 bxt_phy_grc;
1031
1032         u32 suspend_count;
1033         bool power_domains_suspended;
1034         struct i915_suspend_saved_registers regfile;
1035         struct vlv_s0ix_state *vlv_s0ix_state;
1036
1037         enum {
1038                 I915_SAGV_UNKNOWN = 0,
1039                 I915_SAGV_DISABLED,
1040                 I915_SAGV_ENABLED,
1041                 I915_SAGV_NOT_CONTROLLED
1042         } sagv_status;
1043
1044         u32 sagv_block_time_us;
1045
1046         struct {
1047                 /*
1048                  * Raw watermark latency values:
1049                  * in 0.1us units for WM0,
1050                  * in 0.5us units for WM1+.
1051                  */
1052                 /* primary */
1053                 u16 pri_latency[5];
1054                 /* sprite */
1055                 u16 spr_latency[5];
1056                 /* cursor */
1057                 u16 cur_latency[5];
1058                 /*
1059                  * Raw watermark memory latency values
1060                  * for SKL for all 8 levels
1061                  * in 1us units.
1062                  */
1063                 u16 skl_latency[8];
1064
1065                 /* current hardware state */
1066                 union {
1067                         struct ilk_wm_values hw;
1068                         struct vlv_wm_values vlv;
1069                         struct g4x_wm_values g4x;
1070                 };
1071
1072                 u8 max_level;
1073
1074                 /*
1075                  * Should be held around atomic WM register writing; also
1076                  * protects * intel_crtc->wm.active and
1077                  * crtc_state->wm.need_postvbl_update.
1078                  */
1079                 struct mutex wm_mutex;
1080         } wm;
1081
1082         struct dram_info {
1083                 bool wm_lv_0_adjust_needed;
1084                 u8 num_channels;
1085                 bool symmetric_memory;
1086                 enum intel_dram_type {
1087                         INTEL_DRAM_UNKNOWN,
1088                         INTEL_DRAM_DDR3,
1089                         INTEL_DRAM_DDR4,
1090                         INTEL_DRAM_LPDDR3,
1091                         INTEL_DRAM_LPDDR4,
1092                         INTEL_DRAM_DDR5,
1093                         INTEL_DRAM_LPDDR5,
1094                 } type;
1095                 u8 num_qgv_points;
1096         } dram_info;
1097
1098         struct intel_bw_info {
1099                 /* for each QGV point */
1100                 unsigned int deratedbw[I915_NUM_QGV_POINTS];
1101                 u8 num_qgv_points;
1102                 u8 num_planes;
1103         } max_bw[6];
1104
1105         struct intel_global_obj bw_obj;
1106
1107         struct intel_runtime_pm runtime_pm;
1108
1109         struct i915_perf perf;
1110
1111         /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1112         struct intel_gt gt;
1113
1114         struct {
1115                 struct i915_gem_contexts {
1116                         spinlock_t lock; /* locks list */
1117                         struct list_head list;
1118                 } contexts;
1119
1120                 /*
1121                  * We replace the local file with a global mappings as the
1122                  * backing storage for the mmap is on the device and not
1123                  * on the struct file, and we do not want to prolong the
1124                  * lifetime of the local fd. To minimise the number of
1125                  * anonymous inodes we create, we use a global singleton to
1126                  * share the global mapping.
1127                  */
1128                 struct file *mmap_singleton;
1129         } gem;
1130
1131         u8 framestart_delay;
1132
1133         u8 pch_ssc_use;
1134
1135         /* For i915gm/i945gm vblank irq workaround */
1136         u8 vblank_enabled;
1137
1138         /* perform PHY state sanity checks? */
1139         bool chv_phy_assert[2];
1140
1141         bool ipc_enabled;
1142
1143         /* Used to save the pipe-to-encoder mapping for audio */
1144         struct intel_encoder *av_enc_map[I915_MAX_PIPES];
1145
1146         /* necessary resource sharing with HDMI LPE audio driver. */
1147         struct {
1148                 struct platform_device *platdev;
1149                 int     irq;
1150         } lpe_audio;
1151
1152         struct i915_pmu pmu;
1153
1154         struct i915_hdcp_comp_master *hdcp_master;
1155         bool hdcp_comp_added;
1156
1157         /* Mutex to protect the above hdcp component related values. */
1158         struct mutex hdcp_comp_mutex;
1159
1160         I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
1161
1162         /*
1163          * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1164          * will be rejected. Instead look for a better place.
1165          */
1166 };
1167
1168 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1169 {
1170         return container_of(dev, struct drm_i915_private, drm);
1171 }
1172
1173 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
1174 {
1175         return dev_get_drvdata(kdev);
1176 }
1177
1178 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
1179 {
1180         return pci_get_drvdata(pdev);
1181 }
1182
1183 /* Simple iterator over all initialised engines */
1184 #define for_each_engine(engine__, dev_priv__, id__) \
1185         for ((id__) = 0; \
1186              (id__) < I915_NUM_ENGINES; \
1187              (id__)++) \
1188                 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
1189
1190 /* Iterator over subset of engines selected by mask */
1191 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
1192         for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \
1193              (tmp__) ? \
1194              ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \
1195              0;)
1196
1197 #define rb_to_uabi_engine(rb) \
1198         rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
1199
1200 #define for_each_uabi_engine(engine__, i915__) \
1201         for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
1202              (engine__); \
1203              (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
1204
1205 #define for_each_uabi_class_engine(engine__, class__, i915__) \
1206         for ((engine__) = intel_engine_lookup_user((i915__), (class__), 0); \
1207              (engine__) && (engine__)->uabi_class == (class__); \
1208              (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
1209
1210 #define I915_GTT_OFFSET_NONE ((u32)-1)
1211
1212 /*
1213  * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1214  * considered to be the frontbuffer for the given plane interface-wise. This
1215  * doesn't mean that the hw necessarily already scans it out, but that any
1216  * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1217  *
1218  * We have one bit per pipe and per scanout plane type.
1219  */
1220 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
1221 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
1222         BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
1223         BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
1224         BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
1225 })
1226 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1227         BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1228 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1229         GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
1230                 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1231
1232 #define INTEL_INFO(dev_priv)    (&(dev_priv)->__info)
1233 #define RUNTIME_INFO(dev_priv)  (&(dev_priv)->__runtime)
1234 #define DRIVER_CAPS(dev_priv)   (&(dev_priv)->caps)
1235
1236 #define INTEL_DEVID(dev_priv)   (RUNTIME_INFO(dev_priv)->device_id)
1237
1238 /*
1239  * Deprecated: this will be replaced by individual IP checks:
1240  * GRAPHICS_VER(), MEDIA_VER() and DISPLAY_VER()
1241  */
1242 #define INTEL_GEN(dev_priv)             GRAPHICS_VER(dev_priv)
1243 /*
1244  * Deprecated: use IS_GRAPHICS_VER(), IS_MEDIA_VER() and IS_DISPLAY_VER() as
1245  * appropriate.
1246  */
1247 #define IS_GEN_RANGE(dev_priv, s, e)    IS_GRAPHICS_VER(dev_priv, (s), (e))
1248 /*
1249  * Deprecated: use GRAPHICS_VER(), MEDIA_VER() and DISPLAY_VER() as appropriate.
1250  */
1251 #define IS_GEN(dev_priv, n)             (GRAPHICS_VER(dev_priv) == (n))
1252
1253 #define GRAPHICS_VER(i915)              (INTEL_INFO(i915)->graphics_ver)
1254 #define IS_GRAPHICS_VER(i915, from, until) \
1255         (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
1256
1257 #define MEDIA_VER(i915)                 (INTEL_INFO(i915)->media_ver)
1258 #define IS_MEDIA_VER(i915, from, until) \
1259         (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))
1260
1261 #define DISPLAY_VER(i915)       (INTEL_INFO(i915)->display.ver)
1262 #define IS_DISPLAY_VER(i915, from, until) \
1263         (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
1264
1265 #define REVID_FOREVER           0xff
1266 #define INTEL_REVID(dev_priv)   (to_pci_dev((dev_priv)->drm.dev)->revision)
1267
1268 #define HAS_DSB(dev_priv)       (INTEL_INFO(dev_priv)->display.has_dsb)
1269
1270 /*
1271  * Return true if revision is in range [since,until] inclusive.
1272  *
1273  * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
1274  */
1275 #define IS_REVID(p, since, until) \
1276         (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
1277
1278 #define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step)
1279 #define INTEL_GT_STEP(__i915) (RUNTIME_INFO(__i915)->step.gt_step)
1280
1281 #define IS_DISPLAY_STEP(__i915, since, until) \
1282         (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \
1283          INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) <= (until))
1284
1285 #define IS_GT_STEP(__i915, since, until) \
1286         (drm_WARN_ON(&(__i915)->drm, INTEL_GT_STEP(__i915) == STEP_NONE), \
1287          INTEL_GT_STEP(__i915) >= (since) && INTEL_GT_STEP(__i915) <= (until))
1288
1289 static __always_inline unsigned int
1290 __platform_mask_index(const struct intel_runtime_info *info,
1291                       enum intel_platform p)
1292 {
1293         const unsigned int pbits =
1294                 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
1295
1296         /* Expand the platform_mask array if this fails. */
1297         BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
1298                      pbits * ARRAY_SIZE(info->platform_mask));
1299
1300         return p / pbits;
1301 }
1302
1303 static __always_inline unsigned int
1304 __platform_mask_bit(const struct intel_runtime_info *info,
1305                     enum intel_platform p)
1306 {
1307         const unsigned int pbits =
1308                 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
1309
1310         return p % pbits + INTEL_SUBPLATFORM_BITS;
1311 }
1312
1313 static inline u32
1314 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
1315 {
1316         const unsigned int pi = __platform_mask_index(info, p);
1317
1318         return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK;
1319 }
1320
1321 static __always_inline bool
1322 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
1323 {
1324         const struct intel_runtime_info *info = RUNTIME_INFO(i915);
1325         const unsigned int pi = __platform_mask_index(info, p);
1326         const unsigned int pb = __platform_mask_bit(info, p);
1327
1328         BUILD_BUG_ON(!__builtin_constant_p(p));
1329
1330         return info->platform_mask[pi] & BIT(pb);
1331 }
1332
1333 static __always_inline bool
1334 IS_SUBPLATFORM(const struct drm_i915_private *i915,
1335                enum intel_platform p, unsigned int s)
1336 {
1337         const struct intel_runtime_info *info = RUNTIME_INFO(i915);
1338         const unsigned int pi = __platform_mask_index(info, p);
1339         const unsigned int pb = __platform_mask_bit(info, p);
1340         const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
1341         const u32 mask = info->platform_mask[pi];
1342
1343         BUILD_BUG_ON(!__builtin_constant_p(p));
1344         BUILD_BUG_ON(!__builtin_constant_p(s));
1345         BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
1346
1347         /* Shift and test on the MSB position so sign flag can be used. */
1348         return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
1349 }
1350
1351 #define IS_MOBILE(dev_priv)     (INTEL_INFO(dev_priv)->is_mobile)
1352 #define IS_DGFX(dev_priv)   (INTEL_INFO(dev_priv)->is_dgfx)
1353
1354 #define IS_I830(dev_priv)       IS_PLATFORM(dev_priv, INTEL_I830)
1355 #define IS_I845G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I845G)
1356 #define IS_I85X(dev_priv)       IS_PLATFORM(dev_priv, INTEL_I85X)
1357 #define IS_I865G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I865G)
1358 #define IS_I915G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I915G)
1359 #define IS_I915GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I915GM)
1360 #define IS_I945G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I945G)
1361 #define IS_I945GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I945GM)
1362 #define IS_I965G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I965G)
1363 #define IS_I965GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I965GM)
1364 #define IS_G45(dev_priv)        IS_PLATFORM(dev_priv, INTEL_G45)
1365 #define IS_GM45(dev_priv)       IS_PLATFORM(dev_priv, INTEL_GM45)
1366 #define IS_G4X(dev_priv)        (IS_G45(dev_priv) || IS_GM45(dev_priv))
1367 #define IS_PINEVIEW(dev_priv)   IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
1368 #define IS_G33(dev_priv)        IS_PLATFORM(dev_priv, INTEL_G33)
1369 #define IS_IRONLAKE(dev_priv)   IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
1370 #define IS_IRONLAKE_M(dev_priv) \
1371         (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
1372 #define IS_SANDYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SANDYBRIDGE)
1373 #define IS_IVYBRIDGE(dev_priv)  IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
1374 #define IS_IVB_GT1(dev_priv)    (IS_IVYBRIDGE(dev_priv) && \
1375                                  INTEL_INFO(dev_priv)->gt == 1)
1376 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
1377 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
1378 #define IS_HASWELL(dev_priv)    IS_PLATFORM(dev_priv, INTEL_HASWELL)
1379 #define IS_BROADWELL(dev_priv)  IS_PLATFORM(dev_priv, INTEL_BROADWELL)
1380 #define IS_SKYLAKE(dev_priv)    IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
1381 #define IS_BROXTON(dev_priv)    IS_PLATFORM(dev_priv, INTEL_BROXTON)
1382 #define IS_KABYLAKE(dev_priv)   IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
1383 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
1384 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
1385 #define IS_COMETLAKE(dev_priv)  IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
1386 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
1387 #define IS_ICELAKE(dev_priv)    IS_PLATFORM(dev_priv, INTEL_ICELAKE)
1388 #define IS_JSL_EHL(dev_priv)    (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \
1389                                 IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
1390 #define IS_TIGERLAKE(dev_priv)  IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
1391 #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
1392 #define IS_DG1(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG1)
1393 #define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
1394 #define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P)
1395 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
1396                                     (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
1397 #define IS_BDW_ULT(dev_priv) \
1398         IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
1399 #define IS_BDW_ULX(dev_priv) \
1400         IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
1401 #define IS_BDW_GT3(dev_priv)    (IS_BROADWELL(dev_priv) && \
1402                                  INTEL_INFO(dev_priv)->gt == 3)
1403 #define IS_HSW_ULT(dev_priv) \
1404         IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
1405 #define IS_HSW_GT3(dev_priv)    (IS_HASWELL(dev_priv) && \
1406                                  INTEL_INFO(dev_priv)->gt == 3)
1407 #define IS_HSW_GT1(dev_priv)    (IS_HASWELL(dev_priv) && \
1408                                  INTEL_INFO(dev_priv)->gt == 1)
1409 /* ULX machines are also considered ULT. */
1410 #define IS_HSW_ULX(dev_priv) \
1411         IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
1412 #define IS_SKL_ULT(dev_priv) \
1413         IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
1414 #define IS_SKL_ULX(dev_priv) \
1415         IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
1416 #define IS_KBL_ULT(dev_priv) \
1417         IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
1418 #define IS_KBL_ULX(dev_priv) \
1419         IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
1420 #define IS_SKL_GT2(dev_priv)    (IS_SKYLAKE(dev_priv) && \
1421                                  INTEL_INFO(dev_priv)->gt == 2)
1422 #define IS_SKL_GT3(dev_priv)    (IS_SKYLAKE(dev_priv) && \
1423                                  INTEL_INFO(dev_priv)->gt == 3)
1424 #define IS_SKL_GT4(dev_priv)    (IS_SKYLAKE(dev_priv) && \
1425                                  INTEL_INFO(dev_priv)->gt == 4)
1426 #define IS_KBL_GT2(dev_priv)    (IS_KABYLAKE(dev_priv) && \
1427                                  INTEL_INFO(dev_priv)->gt == 2)
1428 #define IS_KBL_GT3(dev_priv)    (IS_KABYLAKE(dev_priv) && \
1429                                  INTEL_INFO(dev_priv)->gt == 3)
1430 #define IS_CFL_ULT(dev_priv) \
1431         IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
1432 #define IS_CFL_ULX(dev_priv) \
1433         IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
1434 #define IS_CFL_GT2(dev_priv)    (IS_COFFEELAKE(dev_priv) && \
1435                                  INTEL_INFO(dev_priv)->gt == 2)
1436 #define IS_CFL_GT3(dev_priv)    (IS_COFFEELAKE(dev_priv) && \
1437                                  INTEL_INFO(dev_priv)->gt == 3)
1438
1439 #define IS_CML_ULT(dev_priv) \
1440         IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
1441 #define IS_CML_ULX(dev_priv) \
1442         IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
1443 #define IS_CML_GT2(dev_priv)    (IS_COMETLAKE(dev_priv) && \
1444                                  INTEL_INFO(dev_priv)->gt == 2)
1445
1446 #define IS_CNL_WITH_PORT_F(dev_priv) \
1447         IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
1448 #define IS_ICL_WITH_PORT_F(dev_priv) \
1449         IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
1450
1451 #define IS_TGL_U(dev_priv) \
1452         IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULT)
1453
1454 #define IS_TGL_Y(dev_priv) \
1455         IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULX)
1456
1457 #define SKL_REVID_A0            0x0
1458 #define SKL_REVID_B0            0x1
1459 #define SKL_REVID_C0            0x2
1460 #define SKL_REVID_D0            0x3
1461 #define SKL_REVID_E0            0x4
1462 #define SKL_REVID_F0            0x5
1463 #define SKL_REVID_G0            0x6
1464 #define SKL_REVID_H0            0x7
1465
1466 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
1467
1468 #define BXT_REVID_A0            0x0
1469 #define BXT_REVID_A1            0x1
1470 #define BXT_REVID_B0            0x3
1471 #define BXT_REVID_B_LAST        0x8
1472 #define BXT_REVID_C0            0x9
1473
1474 #define IS_BXT_REVID(dev_priv, since, until) \
1475         (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
1476
1477 #define IS_KBL_GT_STEP(dev_priv, since, until) \
1478         (IS_KABYLAKE(dev_priv) && IS_GT_STEP(dev_priv, since, until))
1479 #define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \
1480         (IS_KABYLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, since, until))
1481
1482 #define GLK_REVID_A0            0x0
1483 #define GLK_REVID_A1            0x1
1484 #define GLK_REVID_A2            0x2
1485 #define GLK_REVID_B0            0x3
1486
1487 #define IS_GLK_REVID(dev_priv, since, until) \
1488         (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
1489
1490 #define CNL_REVID_A0            0x0
1491 #define CNL_REVID_B0            0x1
1492 #define CNL_REVID_C0            0x2
1493
1494 #define IS_CNL_REVID(p, since, until) \
1495         (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
1496
1497 #define ICL_REVID_A0            0x0
1498 #define ICL_REVID_A2            0x1
1499 #define ICL_REVID_B0            0x3
1500 #define ICL_REVID_B2            0x4
1501 #define ICL_REVID_C0            0x5
1502
1503 #define IS_ICL_REVID(p, since, until) \
1504         (IS_ICELAKE(p) && IS_REVID(p, since, until))
1505
1506 #define EHL_REVID_A0            0x0
1507 #define EHL_REVID_B0            0x1
1508
1509 #define IS_JSL_EHL_REVID(p, since, until) \
1510         (IS_JSL_EHL(p) && IS_REVID(p, since, until))
1511
1512 #define IS_TGL_DISPLAY_STEP(__i915, since, until) \
1513         (IS_TIGERLAKE(__i915) && \
1514          IS_DISPLAY_STEP(__i915, since, until))
1515
1516 #define IS_TGL_UY_GT_STEP(__i915, since, until) \
1517         ((IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \
1518          IS_GT_STEP(__i915, since, until))
1519
1520 #define IS_TGL_GT_STEP(__i915, since, until) \
1521         (IS_TIGERLAKE(__i915) && !(IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \
1522          IS_GT_STEP(__i915, since, until))
1523
1524 #define RKL_REVID_A0            0x0
1525 #define RKL_REVID_B0            0x1
1526 #define RKL_REVID_C0            0x4
1527
1528 #define IS_RKL_REVID(p, since, until) \
1529         (IS_ROCKETLAKE(p) && IS_REVID(p, since, until))
1530
1531 #define DG1_REVID_A0            0x0
1532 #define DG1_REVID_B0            0x1
1533
1534 #define IS_DG1_REVID(p, since, until) \
1535         (IS_DG1(p) && IS_REVID(p, since, until))
1536
1537 #define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
1538         (IS_ALDERLAKE_S(__i915) && \
1539          IS_DISPLAY_STEP(__i915, since, until))
1540
1541 #define IS_ADLS_GT_STEP(__i915, since, until) \
1542         (IS_ALDERLAKE_S(__i915) && \
1543          IS_GT_STEP(__i915, since, until))
1544
1545 #define IS_ADLP_DISPLAY_STEP(__i915, since, until) \
1546         (IS_ALDERLAKE_P(__i915) && \
1547          IS_DISPLAY_STEP(__i915, since, until))
1548
1549 #define IS_ADLP_GT_STEP(__i915, since, until) \
1550         (IS_ALDERLAKE_P(__i915) && \
1551          IS_GT_STEP(__i915, since, until))
1552
1553 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
1554 #define IS_GEN9_LP(dev_priv)    (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
1555 #define IS_GEN9_BC(dev_priv)    (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
1556
1557 #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
1558 #define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
1559
1560 #define ENGINE_INSTANCES_MASK(gt, first, count) ({              \
1561         unsigned int first__ = (first);                                 \
1562         unsigned int count__ = (count);                                 \
1563         ((gt)->info.engine_mask &                                               \
1564          GENMASK(first__ + count__ - 1, first__)) >> first__;           \
1565 })
1566 #define VDBOX_MASK(gt) \
1567         ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
1568 #define VEBOX_MASK(gt) \
1569         ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
1570
1571 /*
1572  * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
1573  * All later gens can run the final buffer from the ppgtt
1574  */
1575 #define CMDPARSER_USES_GGTT(dev_priv) IS_GEN(dev_priv, 7)
1576
1577 #define HAS_LLC(dev_priv)       (INTEL_INFO(dev_priv)->has_llc)
1578 #define HAS_SNOOP(dev_priv)     (INTEL_INFO(dev_priv)->has_snoop)
1579 #define HAS_EDRAM(dev_priv)     ((dev_priv)->edram_size_mb)
1580 #define HAS_SECURE_BATCHES(dev_priv) (INTEL_GEN(dev_priv) < 6)
1581 #define HAS_WT(dev_priv)        HAS_EDRAM(dev_priv)
1582
1583 #define HWS_NEEDS_PHYSICAL(dev_priv)    (INTEL_INFO(dev_priv)->hws_needs_physical)
1584
1585 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
1586                 (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
1587 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
1588                 (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
1589
1590 #define HAS_MASTER_UNIT_IRQ(dev_priv) (INTEL_INFO(dev_priv)->has_master_unit_irq)
1591
1592 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
1593
1594 #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)
1595 #define HAS_PPGTT(dev_priv) \
1596         (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
1597 #define HAS_FULL_PPGTT(dev_priv) \
1598         (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
1599
1600 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
1601         GEM_BUG_ON((sizes) == 0); \
1602         ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \
1603 })
1604
1605 #define HAS_OVERLAY(dev_priv)            (INTEL_INFO(dev_priv)->display.has_overlay)
1606 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
1607                 (INTEL_INFO(dev_priv)->display.overlay_needs_physical)
1608
1609 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1610 #define HAS_BROKEN_CS_TLB(dev_priv)     (IS_I830(dev_priv) || IS_I845G(dev_priv))
1611
1612 #define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv)   \
1613         (IS_BROADWELL(dev_priv) || IS_GEN(dev_priv, 9))
1614
1615 /* WaRsDisableCoarsePowerGating:skl,cnl */
1616 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv)                    \
1617         (IS_CANNONLAKE(dev_priv) ||                                     \
1618          IS_SKL_GT3(dev_priv) ||                                        \
1619          IS_SKL_GT4(dev_priv))
1620
1621 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
1622 #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
1623                                         IS_GEMINILAKE(dev_priv) || \
1624                                         IS_KABYLAKE(dev_priv))
1625
1626 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1627  * rows, which changed the alignment requirements and fence programming.
1628  */
1629 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \
1630                                          !(IS_I915G(dev_priv) || \
1631                                          IS_I915GM(dev_priv)))
1632 #define SUPPORTS_TV(dev_priv)           (INTEL_INFO(dev_priv)->display.supports_tv)
1633 #define I915_HAS_HOTPLUG(dev_priv)      (INTEL_INFO(dev_priv)->display.has_hotplug)
1634
1635 #define HAS_FW_BLC(dev_priv)    (INTEL_GEN(dev_priv) > 2)
1636 #define HAS_FBC(dev_priv)       (INTEL_INFO(dev_priv)->display.has_fbc)
1637 #define HAS_CUR_FBC(dev_priv)   (!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7)
1638
1639 #define HAS_IPS(dev_priv)       (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
1640
1641 #define HAS_DP_MST(dev_priv)    (INTEL_INFO(dev_priv)->display.has_dp_mst)
1642
1643 #define HAS_DDI(dev_priv)                (INTEL_INFO(dev_priv)->display.has_ddi)
1644 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
1645 #define HAS_PSR(dev_priv)                (INTEL_INFO(dev_priv)->display.has_psr)
1646 #define HAS_PSR_HW_TRACKING(dev_priv) \
1647         (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
1648 #define HAS_PSR2_SEL_FETCH(dev_priv)     (INTEL_GEN(dev_priv) >= 12)
1649 #define HAS_TRANSCODER(dev_priv, trans)  ((INTEL_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0)
1650
1651 #define HAS_RC6(dev_priv)                (INTEL_INFO(dev_priv)->has_rc6)
1652 #define HAS_RC6p(dev_priv)               (INTEL_INFO(dev_priv)->has_rc6p)
1653 #define HAS_RC6pp(dev_priv)              (false) /* HW was never validated */
1654
1655 #define HAS_RPS(dev_priv)       (INTEL_INFO(dev_priv)->has_rps)
1656
1657 #define HAS_CSR(dev_priv)       (INTEL_INFO(dev_priv)->display.has_csr)
1658
1659 #define HAS_MSO(i915)           (INTEL_GEN(i915) >= 12)
1660
1661 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
1662 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
1663
1664 #define HAS_IPC(dev_priv)                (INTEL_INFO(dev_priv)->display.has_ipc)
1665
1666 #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
1667 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
1668
1669 #define HAS_GT_UC(dev_priv)     (INTEL_INFO(dev_priv)->has_gt_uc)
1670
1671 #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
1672
1673 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv)     (INTEL_INFO(dev_priv)->has_global_mocs)
1674
1675
1676 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
1677
1678 #define HAS_LSPCON(dev_priv) (IS_GEN_RANGE(dev_priv, 9, 10))
1679
1680 /* DPF == dynamic parity feature */
1681 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
1682 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
1683                                  2 : HAS_L3_DPF(dev_priv))
1684
1685 #define GT_FREQUENCY_MULTIPLIER 50
1686 #define GEN9_FREQ_SCALER 3
1687
1688 #define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask))
1689
1690 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0)
1691
1692 #define HAS_VRR(i915)   (INTEL_GEN(i915) >= 12)
1693
1694 /* Only valid when HAS_DISPLAY() is true */
1695 #define INTEL_DISPLAY_ENABLED(dev_priv) \
1696         (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !(dev_priv)->params.disable_display)
1697
1698 static inline bool run_as_guest(void)
1699 {
1700         return !hypervisor_is_type(X86_HYPER_NATIVE);
1701 }
1702
1703 #define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \
1704                                               IS_ALDERLAKE_S(dev_priv))
1705
1706 static inline bool intel_vtd_active(void)
1707 {
1708 #ifdef CONFIG_INTEL_IOMMU
1709         if (intel_iommu_gfx_mapped)
1710                 return true;
1711 #endif
1712
1713         /* Running as a guest, we assume the host is enforcing VT'd */
1714         return run_as_guest();
1715 }
1716
1717 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
1718 {
1719         return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
1720 }
1721
1722 static inline bool
1723 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
1724 {
1725         return IS_BROXTON(dev_priv) && intel_vtd_active();
1726 }
1727
1728 /* i915_drv.c */
1729 extern const struct dev_pm_ops i915_pm_ops;
1730
1731 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
1732 void i915_driver_remove(struct drm_i915_private *i915);
1733 void i915_driver_shutdown(struct drm_i915_private *i915);
1734
1735 int i915_resume_switcheroo(struct drm_i915_private *i915);
1736 int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state);
1737
1738 int i915_getparam_ioctl(struct drm_device *dev, void *data,
1739                         struct drm_file *file_priv);
1740
1741 /* i915_gem.c */
1742 int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
1743 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
1744 void i915_gem_init_early(struct drm_i915_private *dev_priv);
1745 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
1746
1747 struct intel_memory_region *i915_gem_shmem_setup(struct drm_i915_private *i915);
1748
1749 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
1750 {
1751         /*
1752          * A single pass should suffice to release all the freed objects (along
1753          * most call paths) , but be a little more paranoid in that freeing
1754          * the objects does take a little amount of time, during which the rcu
1755          * callbacks could have added new objects into the freed list, and
1756          * armed the work again.
1757          */
1758         while (atomic_read(&i915->mm.free_count)) {
1759                 flush_work(&i915->mm.free_work);
1760                 rcu_barrier();
1761         }
1762 }
1763
1764 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
1765 {
1766         /*
1767          * Similar to objects above (see i915_gem_drain_freed-objects), in
1768          * general we have workers that are armed by RCU and then rearm
1769          * themselves in their callbacks. To be paranoid, we need to
1770          * drain the workqueue a second time after waiting for the RCU
1771          * grace period so that we catch work queued via RCU from the first
1772          * pass. As neither drain_workqueue() nor flush_workqueue() report
1773          * a result, we make an assumption that we only don't require more
1774          * than 3 passes to catch all _recursive_ RCU delayed work.
1775          *
1776          */
1777         int pass = 3;
1778         do {
1779                 flush_workqueue(i915->wq);
1780                 rcu_barrier();
1781                 i915_gem_drain_freed_objects(i915);
1782         } while (--pass);
1783         drain_workqueue(i915->wq);
1784 }
1785
1786 struct i915_vma * __must_check
1787 i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object *obj,
1788                             struct i915_gem_ww_ctx *ww,
1789                             const struct i915_ggtt_view *view,
1790                             u64 size, u64 alignment, u64 flags);
1791
1792 static inline struct i915_vma * __must_check
1793 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
1794                          const struct i915_ggtt_view *view,
1795                          u64 size, u64 alignment, u64 flags)
1796 {
1797         return i915_gem_object_ggtt_pin_ww(obj, NULL, view, size, alignment, flags);
1798 }
1799
1800 int i915_gem_object_unbind(struct drm_i915_gem_object *obj,
1801                            unsigned long flags);
1802 #define I915_GEM_OBJECT_UNBIND_ACTIVE BIT(0)
1803 #define I915_GEM_OBJECT_UNBIND_BARRIER BIT(1)
1804 #define I915_GEM_OBJECT_UNBIND_TEST BIT(2)
1805
1806 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
1807
1808 int i915_gem_dumb_create(struct drm_file *file_priv,
1809                          struct drm_device *dev,
1810                          struct drm_mode_create_dumb *args);
1811
1812 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
1813
1814 static inline u32 i915_reset_count(struct i915_gpu_error *error)
1815 {
1816         return atomic_read(&error->reset_count);
1817 }
1818
1819 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
1820                                           const struct intel_engine_cs *engine)
1821 {
1822         return atomic_read(&error->reset_engine_count[engine->uabi_class]);
1823 }
1824
1825 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
1826 void i915_gem_driver_register(struct drm_i915_private *i915);
1827 void i915_gem_driver_unregister(struct drm_i915_private *i915);
1828 void i915_gem_driver_remove(struct drm_i915_private *dev_priv);
1829 void i915_gem_driver_release(struct drm_i915_private *dev_priv);
1830 void i915_gem_suspend(struct drm_i915_private *dev_priv);
1831 void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
1832 void i915_gem_resume(struct drm_i915_private *dev_priv);
1833
1834 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
1835
1836 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1837                                     enum i915_cache_level cache_level);
1838
1839 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1840                                 struct dma_buf *dma_buf);
1841
1842 struct dma_buf *i915_gem_prime_export(struct drm_gem_object *gem_obj, int flags);
1843
1844 static inline struct i915_gem_context *
1845 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
1846 {
1847         return xa_load(&file_priv->context_xa, id);
1848 }
1849
1850 static inline struct i915_gem_context *
1851 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
1852 {
1853         struct i915_gem_context *ctx;
1854
1855         rcu_read_lock();
1856         ctx = __i915_gem_context_lookup_rcu(file_priv, id);
1857         if (ctx && !kref_get_unless_zero(&ctx->ref))
1858                 ctx = NULL;
1859         rcu_read_unlock();
1860
1861         return ctx;
1862 }
1863
1864 /* i915_gem_evict.c */
1865 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
1866                                           u64 min_size, u64 alignment,
1867                                           unsigned long color,
1868                                           u64 start, u64 end,
1869                                           unsigned flags);
1870 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
1871                                          struct drm_mm_node *node,
1872                                          unsigned int flags);
1873 int i915_gem_evict_vm(struct i915_address_space *vm);
1874
1875 /* i915_gem_internal.c */
1876 struct drm_i915_gem_object *
1877 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
1878                                 phys_addr_t size);
1879
1880 /* i915_gem_tiling.c */
1881 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
1882 {
1883         struct drm_i915_private *i915 = to_i915(obj->base.dev);
1884
1885         return i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
1886                 i915_gem_object_is_tiled(obj);
1887 }
1888
1889 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
1890                         unsigned int tiling, unsigned int stride);
1891 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
1892                              unsigned int tiling, unsigned int stride);
1893
1894 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
1895
1896 /* i915_cmd_parser.c */
1897 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
1898 int intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
1899 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
1900 unsigned long *intel_engine_cmd_parser_alloc_jump_whitelist(u32 batch_length,
1901                                                             bool trampoline);
1902
1903 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
1904                             struct i915_vma *batch,
1905                             unsigned long batch_offset,
1906                             unsigned long batch_length,
1907                             struct i915_vma *shadow,
1908                             unsigned long *jump_whitelist,
1909                             void *shadow_map,
1910                             const void *batch_map);
1911 #define I915_CMD_PARSER_TRAMPOLINE_SIZE 8
1912
1913 /* intel_device_info.c */
1914 static inline struct intel_device_info *
1915 mkwrite_device_info(struct drm_i915_private *dev_priv)
1916 {
1917         return (struct intel_device_info *)INTEL_INFO(dev_priv);
1918 }
1919
1920 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
1921                         struct drm_file *file);
1922
1923 /* i915_mm.c */
1924 int remap_io_sg(struct vm_area_struct *vma,
1925                 unsigned long addr, unsigned long size,
1926                 struct scatterlist *sgl, resource_size_t iobase);
1927
1928 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
1929 {
1930         if (INTEL_GEN(i915) >= 10)
1931                 return CNL_HWS_CSB_WRITE_INDEX;
1932         else
1933                 return I915_HWS_CSB_WRITE_INDEX;
1934 }
1935
1936 static inline enum i915_map_type
1937 i915_coherent_map_type(struct drm_i915_private *i915)
1938 {
1939         return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
1940 }
1941
1942 #endif