1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <asm/hypervisor.h>
38 #include <linux/io-mapping.h>
39 #include <linux/i2c.h>
40 #include <linux/i2c-algo-bit.h>
41 #include <linux/backlight.h>
42 #include <linux/hash.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/kref.h>
45 #include <linux/mm_types.h>
46 #include <linux/perf_event.h>
47 #include <linux/pm_qos.h>
48 #include <linux/dma-resv.h>
49 #include <linux/shmem_fs.h>
50 #include <linux/stackdepot.h>
51 #include <linux/xarray.h>
53 #include <drm/intel-gtt.h>
54 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
55 #include <drm/drm_gem.h>
56 #include <drm/drm_auth.h>
57 #include <drm/drm_cache.h>
58 #include <drm/drm_util.h>
59 #include <drm/drm_dsc.h>
60 #include <drm/drm_atomic.h>
61 #include <drm/drm_connector.h>
62 #include <drm/i915_mei_hdcp_interface.h>
64 #include "i915_params.h"
66 #include "i915_utils.h"
68 #include "display/intel_bios.h"
69 #include "display/intel_display.h"
70 #include "display/intel_display_power.h"
71 #include "display/intel_dpll_mgr.h"
72 #include "display/intel_dsb.h"
73 #include "display/intel_frontbuffer.h"
74 #include "display/intel_global_state.h"
75 #include "display/intel_gmbus.h"
76 #include "display/intel_opregion.h"
78 #include "gem/i915_gem_context_types.h"
79 #include "gem/i915_gem_shrinker.h"
80 #include "gem/i915_gem_stolen.h"
82 #include "gt/intel_engine.h"
83 #include "gt/intel_gt_types.h"
84 #include "gt/intel_region_lmem.h"
85 #include "gt/intel_workarounds.h"
86 #include "gt/uc/intel_uc.h"
88 #include "intel_device_info.h"
89 #include "intel_pch.h"
90 #include "intel_runtime_pm.h"
91 #include "intel_memory_region.h"
92 #include "intel_uncore.h"
93 #include "intel_wakeref.h"
94 #include "intel_wopcm.h"
97 #include "i915_gem_gtt.h"
98 #include "i915_gpu_error.h"
99 #include "i915_perf_types.h"
100 #include "i915_request.h"
101 #include "i915_scheduler.h"
102 #include "gt/intel_timeline.h"
103 #include "i915_vma.h"
104 #include "i915_irq.h"
107 /* General customization:
110 #define DRIVER_NAME "i915"
111 #define DRIVER_DESC "Intel Graphics"
112 #define DRIVER_DATE "20201103"
113 #define DRIVER_TIMESTAMP 1604406085
115 struct drm_i915_gem_object;
119 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
138 #define for_each_hpd_pin(__pin) \
139 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
141 /* Threshold == 5 for long IRQs, 50 for short */
142 #define HPD_STORM_DEFAULT_THRESHOLD 50
144 struct i915_hotplug {
145 struct delayed_work hotplug_work;
147 const u32 *hpd, *pch_hpd;
150 unsigned long last_jiffies;
155 HPD_MARK_DISABLED = 2
157 } stats[HPD_NUM_PINS];
160 struct delayed_work reenable_work;
164 struct work_struct dig_port_work;
166 struct work_struct poll_init_work;
169 unsigned int hpd_storm_threshold;
170 /* Whether or not to count short HPD IRQs in HPD storms */
171 u8 hpd_short_storm_enabled;
174 * if we get a HPD irq from DP and a HPD irq from non-DP
175 * the non-DP HPD could block the workqueue on a mode config
176 * mutex getting, that userspace may have taken. However
177 * userspace is waiting on the DP workqueue to run which is
178 * blocked behind the non-DP one.
180 struct workqueue_struct *dp_wq;
183 #define I915_GEM_GPU_DOMAINS \
184 (I915_GEM_DOMAIN_RENDER | \
185 I915_GEM_DOMAIN_SAMPLER | \
186 I915_GEM_DOMAIN_COMMAND | \
187 I915_GEM_DOMAIN_INSTRUCTION | \
188 I915_GEM_DOMAIN_VERTEX)
190 struct drm_i915_private;
191 struct i915_mm_struct;
192 struct i915_mmu_object;
194 struct drm_i915_file_private {
195 struct drm_i915_private *dev_priv;
198 struct drm_file *file;
202 struct xarray context_xa;
205 unsigned int bsd_engine;
208 * Every context ban increments per client ban score. Also
209 * hangs in short succession increments ban score. If ban threshold
210 * is reached, client is considered banned and submitting more work
211 * will fail. This is a stop gap measure to limit the badly behaving
212 * clients access to gpu. Note that unbannable contexts never increment
213 * the client ban score.
215 #define I915_CLIENT_SCORE_HANG_FAST 1
216 #define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
217 #define I915_CLIENT_SCORE_CONTEXT_BAN 3
218 #define I915_CLIENT_SCORE_BANNED 9
219 /** ban_score: Accumulated score of all ctx bans and fast hangs. */
221 unsigned long hang_timestamp;
224 /* Interface history:
227 * 1.2: Add Power Management
228 * 1.3: Add vblank support
229 * 1.4: Fix cmdbuffer path, add heap destroy
230 * 1.5: Add vblank pipe configuration
231 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
232 * - Support vertical blank on secondary display pipe
234 #define DRIVER_MAJOR 1
235 #define DRIVER_MINOR 6
236 #define DRIVER_PATCHLEVEL 0
238 struct intel_overlay;
239 struct intel_overlay_error_state;
241 struct sdvo_device_mapping {
250 struct intel_connector;
251 struct intel_encoder;
252 struct intel_atomic_state;
253 struct intel_cdclk_config;
254 struct intel_cdclk_state;
255 struct intel_cdclk_vals;
256 struct intel_initial_plane_config;
261 struct drm_i915_display_funcs {
262 void (*get_cdclk)(struct drm_i915_private *dev_priv,
263 struct intel_cdclk_config *cdclk_config);
264 void (*set_cdclk)(struct drm_i915_private *dev_priv,
265 const struct intel_cdclk_config *cdclk_config,
267 int (*bw_calc_min_cdclk)(struct intel_atomic_state *state);
268 int (*get_fifo_size)(struct drm_i915_private *dev_priv,
269 enum i9xx_plane_id i9xx_plane);
270 int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state);
271 int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state);
272 void (*initial_watermarks)(struct intel_atomic_state *state,
273 struct intel_crtc *crtc);
274 void (*atomic_update_watermarks)(struct intel_atomic_state *state,
275 struct intel_crtc *crtc);
276 void (*optimize_watermarks)(struct intel_atomic_state *state,
277 struct intel_crtc *crtc);
278 int (*compute_global_watermarks)(struct intel_atomic_state *state);
279 void (*update_wm)(struct intel_crtc *crtc);
280 int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
281 u8 (*calc_voltage_level)(int cdclk);
282 /* Returns the active state of the crtc, and if the crtc is active,
283 * fills out the pipe-config with the hw state. */
284 bool (*get_pipe_config)(struct intel_crtc *,
285 struct intel_crtc_state *);
286 void (*get_initial_plane_config)(struct intel_crtc *,
287 struct intel_initial_plane_config *);
288 int (*crtc_compute_clock)(struct intel_crtc *crtc,
289 struct intel_crtc_state *crtc_state);
290 void (*crtc_enable)(struct intel_atomic_state *state,
291 struct intel_crtc *crtc);
292 void (*crtc_disable)(struct intel_atomic_state *state,
293 struct intel_crtc *crtc);
294 void (*commit_modeset_enables)(struct intel_atomic_state *state);
295 void (*commit_modeset_disables)(struct intel_atomic_state *state);
296 void (*audio_codec_enable)(struct intel_encoder *encoder,
297 const struct intel_crtc_state *crtc_state,
298 const struct drm_connector_state *conn_state);
299 void (*audio_codec_disable)(struct intel_encoder *encoder,
300 const struct intel_crtc_state *old_crtc_state,
301 const struct drm_connector_state *old_conn_state);
302 void (*fdi_link_train)(struct intel_crtc *crtc,
303 const struct intel_crtc_state *crtc_state);
304 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
305 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
306 /* clock updates for mode set */
308 /* render clock increase/decrease */
309 /* display clock increase/decrease */
310 /* pll clock increase/decrease */
312 int (*color_check)(struct intel_crtc_state *crtc_state);
314 * Program double buffered color management registers during
315 * vblank evasion. The registers should then latch during the
316 * next vblank start, alongside any other double buffered registers
317 * involved with the same commit.
319 void (*color_commit)(const struct intel_crtc_state *crtc_state);
321 * Load LUTs (and other single buffered color management
322 * registers). Will (hopefully) be called during the vblank
323 * following the latching of any double buffered registers
324 * involved with the same commit.
326 void (*load_luts)(const struct intel_crtc_state *crtc_state);
327 void (*read_luts)(struct intel_crtc_state *crtc_state);
331 struct work_struct work;
333 u32 required_version;
334 u32 max_fw_size; /* bytes */
336 u32 dmc_fw_size; /* dwords */
339 i915_reg_t mmioaddr[20];
344 intel_wakeref_t wakeref;
347 enum i915_cache_level {
349 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
350 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
351 caches, eg sampler/render caches, and the
352 large Last-Level-Cache. LLC is coherent with
353 the CPU, but L3 is only visible to the GPU. */
354 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
357 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
360 /* This is always the inner lock when overlapping with struct_mutex and
361 * it's the outer lock when overlapping with stolen_lock. */
364 unsigned int possible_framebuffer_bits;
365 unsigned int busy_bits;
366 struct intel_crtc *crtc;
368 struct drm_mm_node compressed_fb;
369 struct drm_mm_node *compressed_llb;
377 bool underrun_detected;
378 struct work_struct underrun_work;
381 * Due to the atomic rules we can't access some structures without the
382 * appropriate locking, so we cache information here in order to avoid
385 struct intel_fbc_state_cache {
387 unsigned int mode_flags;
388 u32 hsw_bdw_pixel_rate;
392 unsigned int rotation;
397 * Display surface base address adjustement for
398 * pageflips. Note that on gen4+ this only adjusts up
399 * to a tile, offsets within a tile are handled in
400 * the hw itself (with the TILEOFF register).
405 u16 pixel_blend_mode;
409 const struct drm_format_info *format;
414 unsigned int fence_y_offset;
415 u16 gen9_wa_cfb_stride;
422 * This structure contains everything that's relevant to program the
423 * hardware registers. When we want to figure out if we need to disable
424 * and re-enable FBC for a new configuration we just check if there's
425 * something different in the struct. The genx_fbc_activate functions
426 * are supposed to read from it in order to program the registers.
428 struct intel_fbc_reg_params {
431 enum i9xx_plane_id i9xx_plane;
435 const struct drm_format_info *format;
441 unsigned int fence_y_offset;
442 u16 gen9_wa_cfb_stride;
448 const char *no_fbc_reason;
452 * HIGH_RR is the highest eDP panel refresh rate read from EDID
453 * LOW_RR is the lowest eDP panel refresh rate found from EDID
454 * parsing for same resolution.
456 enum drrs_refresh_rate_type {
459 DRRS_MAX_RR, /* RR count */
462 enum drrs_support_type {
463 DRRS_NOT_SUPPORTED = 0,
464 STATIC_DRRS_SUPPORT = 1,
465 SEAMLESS_DRRS_SUPPORT = 2
471 struct delayed_work work;
473 unsigned busy_frontbuffer_bits;
474 enum drrs_refresh_rate_type refresh_rate_type;
475 enum drrs_support_type type;
481 #define I915_PSR_DEBUG_MODE_MASK 0x0f
482 #define I915_PSR_DEBUG_DEFAULT 0x00
483 #define I915_PSR_DEBUG_DISABLE 0x01
484 #define I915_PSR_DEBUG_ENABLE 0x02
485 #define I915_PSR_DEBUG_FORCE_PSR1 0x03
486 #define I915_PSR_DEBUG_IRQ 0x10
493 enum transcoder transcoder;
495 struct work_struct work;
496 unsigned busy_frontbuffer_bits;
497 bool sink_psr2_support;
499 bool colorimetry_support;
501 bool psr2_sel_fetch_enabled;
502 u8 sink_sync_latency;
503 ktime_t last_entry_attempt;
505 bool sink_not_reliable;
507 u16 su_x_granularity;
509 u32 dc3co_exit_delay;
510 struct delayed_work dc3co_work;
511 struct drm_dp_vsc_sdp vsc;
514 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
515 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
516 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
517 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
518 #define QUIRK_INCREASE_T12_DELAY (1<<6)
519 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
522 struct intel_fbc_work;
525 struct i2c_adapter adapter;
526 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
530 struct i2c_algo_bit_data bit_algo;
531 struct drm_i915_private *dev_priv;
534 struct i915_suspend_saved_registers {
542 struct vlv_s0ix_state;
544 #define MAX_L3_SLICES 2
545 struct intel_l3_parity {
546 u32 *remap_info[MAX_L3_SLICES];
547 struct work_struct error_work;
552 /** Memory allocator for GTT stolen memory */
553 struct drm_mm stolen;
554 /** Protects the usage of the GTT stolen memory allocator. This is
555 * always the inner lock when overlapping with struct_mutex. */
556 struct mutex stolen_lock;
558 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
562 * List of objects which are purgeable.
564 struct list_head purge_list;
567 * List of objects which have allocated pages and are shrinkable.
569 struct list_head shrink_list;
572 * List of objects which are pending destruction.
574 struct llist_head free_list;
575 struct work_struct free_work;
577 * Count of objects pending destructions. Used to skip needlessly
578 * waiting on an RCU barrier if no objects are waiting to be freed.
583 * tmpfs instance used for shmem backed objects
585 struct vfsmount *gemfs;
587 struct intel_memory_region *regions[INTEL_REGION_UNKNOWN];
589 struct notifier_block oom_notifier;
590 struct notifier_block vmap_notifier;
591 struct shrinker shrinker;
594 * Workqueue to fault in userptr pages, flushed by the execbuf
595 * when required but otherwise left to userspace to try again
598 struct workqueue_struct *userptr_wq;
600 /* shrinker accounting, also useful for userland debugging */
605 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
607 unsigned long i915_fence_context_timeout(const struct drm_i915_private *i915,
610 static inline unsigned long
611 i915_fence_timeout(const struct drm_i915_private *i915)
613 return i915_fence_context_timeout(i915, U64_MAX);
616 /* Amount of SAGV/QGV points, BSpec precisely defines this */
617 #define I915_NUM_QGV_POINTS 8
619 struct ddi_vbt_port_info {
620 /* Non-NULL if port present. */
621 const struct child_device_config *child;
625 /* This is an index in the HDMI/DVI DDI buffer translation table. */
627 u8 hdmi_level_shift_set:1;
633 u8 supports_typec_usb:1;
636 u8 alternate_aux_channel;
637 u8 alternate_ddc_pin;
641 int dp_max_link_rate; /* 0 for not limited by VBT */
644 enum psr_lines_to_wait {
645 PSR_0_LINES_TO_WAIT = 0,
651 struct intel_vbt_data {
652 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
653 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
656 unsigned int int_tv_support:1;
657 unsigned int lvds_dither:1;
658 unsigned int int_crt_support:1;
659 unsigned int lvds_use_ssc:1;
660 unsigned int int_lvds_support:1;
661 unsigned int display_clock_mode:1;
662 unsigned int fdi_rx_polarity_inverted:1;
663 unsigned int panel_type:4;
665 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
666 enum drm_panel_orientation orientation;
668 enum drrs_support_type drrs_type;
678 struct edp_power_seq pps;
685 bool require_aux_wakeup;
687 enum psr_lines_to_wait lines_to_wait;
688 int tp1_wakeup_time_us;
689 int tp2_tp3_wakeup_time_us;
690 int psr2_tp2_tp3_wakeup_time_us;
697 u8 min_brightness; /* min_brightness/255 of max */
698 u8 controller; /* brightness controller number */
699 enum intel_backlight_type type;
705 struct mipi_config *config;
706 struct mipi_pps_data *pps;
712 const u8 *sequence[MIPI_SEQ_MAX];
713 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
714 enum drm_panel_orientation orientation;
719 struct list_head display_devices;
721 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
722 struct sdvo_device_mapping sdvo_mappings[2];
725 enum intel_ddb_partitioning {
727 INTEL_DDB_PART_5_6, /* IVB+ */
730 struct ilk_wm_values {
735 enum intel_ddb_partitioning partitioning;
739 u16 plane[I915_MAX_PLANES];
749 struct vlv_wm_ddl_values {
750 u8 plane[I915_MAX_PLANES];
753 struct vlv_wm_values {
754 struct g4x_pipe_wm pipe[3];
756 struct vlv_wm_ddl_values ddl[3];
761 struct g4x_wm_values {
762 struct g4x_pipe_wm pipe[2];
764 struct g4x_sr_wm hpll;
770 struct skl_ddb_entry {
771 u16 start, end; /* in number of blocks, 'end' is exclusive */
774 static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)
776 return entry->end - entry->start;
779 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
780 const struct skl_ddb_entry *e2)
782 if (e1->start == e2->start && e1->end == e2->end)
788 struct i915_frontbuffer_tracking {
792 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
799 struct i915_virtual_gpu {
800 struct mutex lock; /* serialises sending of g2v_notify command pkts */
805 struct intel_cdclk_config {
806 unsigned int cdclk, vco, ref, bypass;
810 struct i915_selftest_stash {
814 struct drm_i915_private {
815 struct drm_device drm;
817 /* FIXME: Device release actions should all be moved to drmm_ */
820 /* i915 device parameters */
821 struct i915_params params;
823 const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
824 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
825 struct intel_driver_caps caps;
828 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
829 * end of stolen which we can optionally use to create GEM objects
830 * backed by stolen memory. Note that stolen_usable_size tells us
831 * exactly how much of this we are actually allowed to use, given that
832 * some portion of it is in fact reserved for use by hardware functions.
836 * Reseved portion of Data Stolen Memory
838 struct resource dsm_reserved;
841 * Stolen memory is segmented in hardware with different portions
842 * offlimits to certain functions.
844 * The drm_mm is initialised to the total accessible range, as found
845 * from the PCI config. On Broadwell+, this is further restricted to
846 * avoid the first page! The upper end of stolen memory is reserved for
847 * hardware functions and similarly removed from the accessible range.
849 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */
851 struct intel_uncore uncore;
852 struct intel_uncore_mmio_debug mmio_debug;
854 struct i915_virtual_gpu vgpu;
856 struct intel_gvt *gvt;
858 struct intel_wopcm wopcm;
860 struct intel_csr csr;
862 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
864 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
865 * controller on different i2c buses. */
866 struct mutex gmbus_mutex;
869 * Base address of where the gmbus and gpio blocks are located (either
870 * on PCH or on SoC for platforms without PCH).
874 u32 hsw_psr_mmio_adjust;
876 /* MMIO base address for MIPI regs */
881 wait_queue_head_t gmbus_wait_queue;
883 struct pci_dev *bridge_dev;
885 struct rb_root uabi_engines;
887 struct resource mch_res;
889 /* protects the irq masks */
892 bool display_irqs_enabled;
894 /* Sideband mailbox protection */
895 struct mutex sb_lock;
896 struct pm_qos_request sb_qos;
898 /** Cached value of IMR to avoid reads in updating the bitfield */
901 u32 de_irq_mask[I915_MAX_PIPES];
903 u32 pipestat_irq_mask[I915_MAX_PIPES];
905 struct i915_hotplug hotplug;
906 struct intel_fbc fbc;
907 struct i915_drrs drrs;
908 struct intel_opregion opregion;
909 struct intel_vbt_data vbt;
911 bool preserve_bios_swizzle;
914 struct intel_overlay *overlay;
916 /* backlight registers and fields in struct intel_panel */
917 struct mutex backlight_lock;
919 /* protects panel power sequencer state */
920 struct mutex pps_mutex;
922 unsigned int fsb_freq, mem_freq, is_ddr3;
923 unsigned int skl_preferred_vco_freq;
924 unsigned int max_cdclk_freq;
926 unsigned int max_dotclk_freq;
927 unsigned int hpll_freq;
928 unsigned int fdi_pll_freq;
929 unsigned int czclk_freq;
932 /* The current hardware cdclk configuration */
933 struct intel_cdclk_config hw;
935 /* cdclk, divider, and ratio table from bspec */
936 const struct intel_cdclk_vals *table;
938 struct intel_global_obj obj;
942 /* The current hardware dbuf configuration */
945 struct intel_global_obj obj;
949 * wq - Driver workqueue for GEM.
951 * NOTE: Work items scheduled here are not allowed to grab any modeset
952 * locks, for otherwise the flushing done in the pageflip code will
953 * result in deadlocks.
955 struct workqueue_struct *wq;
957 /* ordered wq for modesets */
958 struct workqueue_struct *modeset_wq;
959 /* unbound hipri wq for page flips/plane updates */
960 struct workqueue_struct *flip_wq;
962 /* Display functions */
963 struct drm_i915_display_funcs display;
965 /* PCH chipset type */
966 enum intel_pch pch_type;
967 unsigned short pch_id;
969 unsigned long quirks;
971 struct drm_atomic_state *modeset_restore_state;
972 struct drm_modeset_acquire_ctx reset_ctx;
974 struct i915_ggtt ggtt; /* VM representing the global address space */
976 struct i915_gem_mm mm;
977 DECLARE_HASHTABLE(mm_structs, 7);
980 /* Kernel Modesetting */
982 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
983 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
986 * dpll and cdclk state is protected by connection_mutex
987 * dpll.lock serializes intel_{prepare,enable,disable}_shared_dpll.
988 * Must be global rather than per dpll, because on some platforms plls
995 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
996 const struct intel_dpll_mgr *mgr;
1004 struct list_head global_obj_list;
1007 * For reading active_pipes holding any crtc lock is
1008 * sufficient, for writing must hold all of them.
1012 struct i915_wa_list gt_wa_list;
1014 struct i915_frontbuffer_tracking fb_tracking;
1016 struct intel_atomic_helper {
1017 struct llist_head free_list;
1018 struct work_struct free_work;
1021 bool mchbar_need_disable;
1023 struct intel_l3_parity l3_parity;
1026 * HTI (aka HDPORT) state read during initial hw readout. Most
1027 * platforms don't have HTI, so this will just stay 0. Those that do
1028 * will use this later to figure out which PLLs and PHYs are unavailable
1035 * Cannot be determined by PCIID. You must always read a register.
1039 struct i915_power_domains power_domains;
1041 struct i915_psr psr;
1043 struct i915_gpu_error gpu_error;
1045 struct drm_i915_gem_object *vlv_pctx;
1047 /* list of fbdev register on this device */
1048 struct intel_fbdev *fbdev;
1049 struct work_struct fbdev_suspend_work;
1051 struct drm_property *broadcast_rgb_property;
1052 struct drm_property *force_audio_property;
1054 /* hda/i915 audio component */
1055 struct i915_audio_component *audio_component;
1056 bool audio_component_registered;
1058 * av_mutex - mutex for audio/video sync
1061 struct mutex av_mutex;
1062 int audio_power_refcount;
1063 u32 audio_freq_cntrl;
1067 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1068 u32 chv_phy_control;
1070 * Shadows for CHV DPLL_MD regs to keep the state
1071 * checker somewhat working in the presence hardware
1072 * crappiness (can't read out DPLL_MD for pipes B & C).
1074 u32 chv_dpll_md[I915_MAX_PIPES];
1078 bool power_domains_suspended;
1079 struct i915_suspend_saved_registers regfile;
1080 struct vlv_s0ix_state *vlv_s0ix_state;
1083 I915_SAGV_UNKNOWN = 0,
1086 I915_SAGV_NOT_CONTROLLED
1089 u32 sagv_block_time_us;
1093 * Raw watermark latency values:
1094 * in 0.1us units for WM0,
1095 * in 0.5us units for WM1+.
1104 * Raw watermark memory latency values
1105 * for SKL for all 8 levels
1110 /* current hardware state */
1112 struct ilk_wm_values hw;
1113 struct vlv_wm_values vlv;
1114 struct g4x_wm_values g4x;
1120 * Should be held around atomic WM register writing; also
1121 * protects * intel_crtc->wm.active and
1122 * crtc_state->wm.need_postvbl_update.
1124 struct mutex wm_mutex;
1128 bool wm_lv_0_adjust_needed;
1130 bool symmetric_memory;
1131 enum intel_dram_type {
1141 struct intel_bw_info {
1142 /* for each QGV point */
1143 unsigned int deratedbw[I915_NUM_QGV_POINTS];
1148 struct intel_global_obj bw_obj;
1150 struct intel_runtime_pm runtime_pm;
1152 struct i915_perf perf;
1154 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1158 struct i915_gem_contexts {
1159 spinlock_t lock; /* locks list */
1160 struct list_head list;
1164 * We replace the local file with a global mappings as the
1165 * backing storage for the mmap is on the device and not
1166 * on the struct file, and we do not want to prolong the
1167 * lifetime of the local fd. To minimise the number of
1168 * anonymous inodes we create, we use a global singleton to
1169 * share the global mapping.
1171 struct file *mmap_singleton;
1174 u8 framestart_delay;
1178 /* For i915gm/i945gm vblank irq workaround */
1181 /* perform PHY state sanity checks? */
1182 bool chv_phy_assert[2];
1186 /* Used to save the pipe-to-encoder mapping for audio */
1187 struct intel_encoder *av_enc_map[I915_MAX_PIPES];
1189 /* necessary resource sharing with HDMI LPE audio driver. */
1191 struct platform_device *platdev;
1195 struct i915_pmu pmu;
1197 struct i915_hdcp_comp_master *hdcp_master;
1198 bool hdcp_comp_added;
1200 /* Mutex to protect the above hdcp component related values. */
1201 struct mutex hdcp_comp_mutex;
1203 I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
1206 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1207 * will be rejected. Instead look for a better place.
1211 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1213 return container_of(dev, struct drm_i915_private, drm);
1216 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
1218 return dev_get_drvdata(kdev);
1221 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
1223 return pci_get_drvdata(pdev);
1226 /* Simple iterator over all initialised engines */
1227 #define for_each_engine(engine__, dev_priv__, id__) \
1229 (id__) < I915_NUM_ENGINES; \
1231 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
1233 /* Iterator over subset of engines selected by mask */
1234 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
1235 for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \
1237 ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \
1240 #define rb_to_uabi_engine(rb) \
1241 rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
1243 #define for_each_uabi_engine(engine__, i915__) \
1244 for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
1246 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
1248 #define for_each_uabi_class_engine(engine__, class__, i915__) \
1249 for ((engine__) = intel_engine_lookup_user((i915__), (class__), 0); \
1250 (engine__) && (engine__)->uabi_class == (class__); \
1251 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
1253 #define I915_GTT_OFFSET_NONE ((u32)-1)
1256 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1257 * considered to be the frontbuffer for the given plane interface-wise. This
1258 * doesn't mean that the hw necessarily already scans it out, but that any
1259 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1261 * We have one bit per pipe and per scanout plane type.
1263 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
1264 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
1265 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
1266 BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
1267 BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
1269 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1270 BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1271 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1272 GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
1273 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1275 #define INTEL_INFO(dev_priv) (&(dev_priv)->__info)
1276 #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime)
1277 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
1279 #define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen)
1280 #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id)
1282 #define REVID_FOREVER 0xff
1283 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
1285 #define INTEL_GEN_MASK(s, e) ( \
1286 BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
1287 BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
1288 GENMASK((e) - 1, (s) - 1))
1290 /* Returns true if Gen is in inclusive range [Start, End] */
1291 #define IS_GEN_RANGE(dev_priv, s, e) \
1292 (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e))))
1294 #define IS_GEN(dev_priv, n) \
1295 (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \
1296 INTEL_INFO(dev_priv)->gen == (n))
1298 #define HAS_DSB(dev_priv) (INTEL_INFO(dev_priv)->display.has_dsb)
1301 * Return true if revision is in range [since,until] inclusive.
1303 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
1305 #define IS_REVID(p, since, until) \
1306 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
1308 static __always_inline unsigned int
1309 __platform_mask_index(const struct intel_runtime_info *info,
1310 enum intel_platform p)
1312 const unsigned int pbits =
1313 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
1315 /* Expand the platform_mask array if this fails. */
1316 BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
1317 pbits * ARRAY_SIZE(info->platform_mask));
1322 static __always_inline unsigned int
1323 __platform_mask_bit(const struct intel_runtime_info *info,
1324 enum intel_platform p)
1326 const unsigned int pbits =
1327 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
1329 return p % pbits + INTEL_SUBPLATFORM_BITS;
1333 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
1335 const unsigned int pi = __platform_mask_index(info, p);
1337 return info->platform_mask[pi] & ((1 << INTEL_SUBPLATFORM_BITS) - 1);
1340 static __always_inline bool
1341 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
1343 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
1344 const unsigned int pi = __platform_mask_index(info, p);
1345 const unsigned int pb = __platform_mask_bit(info, p);
1347 BUILD_BUG_ON(!__builtin_constant_p(p));
1349 return info->platform_mask[pi] & BIT(pb);
1352 static __always_inline bool
1353 IS_SUBPLATFORM(const struct drm_i915_private *i915,
1354 enum intel_platform p, unsigned int s)
1356 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
1357 const unsigned int pi = __platform_mask_index(info, p);
1358 const unsigned int pb = __platform_mask_bit(info, p);
1359 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
1360 const u32 mask = info->platform_mask[pi];
1362 BUILD_BUG_ON(!__builtin_constant_p(p));
1363 BUILD_BUG_ON(!__builtin_constant_p(s));
1364 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
1366 /* Shift and test on the MSB position so sign flag can be used. */
1367 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
1370 #define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile)
1371 #define IS_DGFX(dev_priv) (INTEL_INFO(dev_priv)->is_dgfx)
1373 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
1374 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
1375 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X)
1376 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G)
1377 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G)
1378 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM)
1379 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G)
1380 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM)
1381 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G)
1382 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM)
1383 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
1384 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
1385 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
1386 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
1387 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
1388 #define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
1389 #define IS_IRONLAKE_M(dev_priv) \
1390 (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
1391 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
1392 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
1393 INTEL_INFO(dev_priv)->gt == 1)
1394 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
1395 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
1396 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
1397 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL)
1398 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
1399 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON)
1400 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
1401 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
1402 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
1403 #define IS_COMETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
1404 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
1405 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
1406 #define IS_JSL_EHL(dev_priv) (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \
1407 IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
1408 #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
1409 #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
1410 #define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1)
1411 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
1412 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
1413 #define IS_BDW_ULT(dev_priv) \
1414 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
1415 #define IS_BDW_ULX(dev_priv) \
1416 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
1417 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
1418 INTEL_INFO(dev_priv)->gt == 3)
1419 #define IS_HSW_ULT(dev_priv) \
1420 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
1421 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
1422 INTEL_INFO(dev_priv)->gt == 3)
1423 #define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \
1424 INTEL_INFO(dev_priv)->gt == 1)
1425 /* ULX machines are also considered ULT. */
1426 #define IS_HSW_ULX(dev_priv) \
1427 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
1428 #define IS_SKL_ULT(dev_priv) \
1429 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
1430 #define IS_SKL_ULX(dev_priv) \
1431 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
1432 #define IS_KBL_ULT(dev_priv) \
1433 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
1434 #define IS_KBL_ULX(dev_priv) \
1435 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
1436 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
1437 INTEL_INFO(dev_priv)->gt == 2)
1438 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
1439 INTEL_INFO(dev_priv)->gt == 3)
1440 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
1441 INTEL_INFO(dev_priv)->gt == 4)
1442 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
1443 INTEL_INFO(dev_priv)->gt == 2)
1444 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
1445 INTEL_INFO(dev_priv)->gt == 3)
1446 #define IS_CFL_ULT(dev_priv) \
1447 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
1448 #define IS_CFL_ULX(dev_priv) \
1449 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
1450 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
1451 INTEL_INFO(dev_priv)->gt == 2)
1452 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
1453 INTEL_INFO(dev_priv)->gt == 3)
1455 #define IS_CML_ULT(dev_priv) \
1456 IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
1457 #define IS_CML_ULX(dev_priv) \
1458 IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
1459 #define IS_CML_GT2(dev_priv) (IS_COMETLAKE(dev_priv) && \
1460 INTEL_INFO(dev_priv)->gt == 2)
1462 #define IS_CNL_WITH_PORT_F(dev_priv) \
1463 IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
1464 #define IS_ICL_WITH_PORT_F(dev_priv) \
1465 IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
1467 #define IS_TGL_U(dev_priv) \
1468 IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULT)
1470 #define IS_TGL_Y(dev_priv) \
1471 IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULX)
1473 #define SKL_REVID_A0 0x0
1474 #define SKL_REVID_B0 0x1
1475 #define SKL_REVID_C0 0x2
1476 #define SKL_REVID_D0 0x3
1477 #define SKL_REVID_E0 0x4
1478 #define SKL_REVID_F0 0x5
1479 #define SKL_REVID_G0 0x6
1480 #define SKL_REVID_H0 0x7
1482 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
1484 #define BXT_REVID_A0 0x0
1485 #define BXT_REVID_A1 0x1
1486 #define BXT_REVID_B0 0x3
1487 #define BXT_REVID_B_LAST 0x8
1488 #define BXT_REVID_C0 0x9
1490 #define IS_BXT_REVID(dev_priv, since, until) \
1491 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
1505 struct i915_rev_steppings {
1510 /* Defined in intel_workarounds.c */
1511 extern const struct i915_rev_steppings kbl_revids[];
1513 #define IS_KBL_GT_REVID(dev_priv, since, until) \
1514 (IS_KABYLAKE(dev_priv) && \
1515 kbl_revids[INTEL_REVID(dev_priv)].gt_stepping >= since && \
1516 kbl_revids[INTEL_REVID(dev_priv)].gt_stepping <= until)
1517 #define IS_KBL_DISP_REVID(dev_priv, since, until) \
1518 (IS_KABYLAKE(dev_priv) && \
1519 kbl_revids[INTEL_REVID(dev_priv)].disp_stepping >= since && \
1520 kbl_revids[INTEL_REVID(dev_priv)].disp_stepping <= until)
1522 #define GLK_REVID_A0 0x0
1523 #define GLK_REVID_A1 0x1
1524 #define GLK_REVID_A2 0x2
1525 #define GLK_REVID_B0 0x3
1527 #define IS_GLK_REVID(dev_priv, since, until) \
1528 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
1530 #define CNL_REVID_A0 0x0
1531 #define CNL_REVID_B0 0x1
1532 #define CNL_REVID_C0 0x2
1534 #define IS_CNL_REVID(p, since, until) \
1535 (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
1537 #define ICL_REVID_A0 0x0
1538 #define ICL_REVID_A2 0x1
1539 #define ICL_REVID_B0 0x3
1540 #define ICL_REVID_B2 0x4
1541 #define ICL_REVID_C0 0x5
1543 #define IS_ICL_REVID(p, since, until) \
1544 (IS_ICELAKE(p) && IS_REVID(p, since, until))
1546 #define EHL_REVID_A0 0x0
1547 #define EHL_REVID_B0 0x1
1549 #define IS_JSL_EHL_REVID(p, since, until) \
1550 (IS_JSL_EHL(p) && IS_REVID(p, since, until))
1560 #define TGL_UY_REVIDS_SIZE 4
1561 #define TGL_REVIDS_SIZE 2
1563 extern const struct i915_rev_steppings tgl_uy_revids[TGL_UY_REVIDS_SIZE];
1564 extern const struct i915_rev_steppings tgl_revids[TGL_REVIDS_SIZE];
1566 static inline const struct i915_rev_steppings *
1567 tgl_revids_get(struct drm_i915_private *dev_priv)
1569 u8 revid = INTEL_REVID(dev_priv);
1571 const struct i915_rev_steppings *tgl_revid_tbl;
1573 if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
1574 tgl_revid_tbl = tgl_uy_revids;
1575 size = ARRAY_SIZE(tgl_uy_revids);
1577 tgl_revid_tbl = tgl_revids;
1578 size = ARRAY_SIZE(tgl_revids);
1581 revid = min_t(u8, revid, size - 1);
1583 return &tgl_revid_tbl[revid];
1586 #define IS_TGL_DISP_REVID(p, since, until) \
1587 (IS_TIGERLAKE(p) && \
1588 tgl_revids_get(p)->disp_stepping >= (since) && \
1589 tgl_revids_get(p)->disp_stepping <= (until))
1591 #define IS_TGL_UY_GT_REVID(p, since, until) \
1592 ((IS_TGL_U(p) || IS_TGL_Y(p)) && \
1593 tgl_revids_get(p)->gt_stepping >= (since) && \
1594 tgl_revids_get(p)->gt_stepping <= (until))
1596 #define IS_TGL_GT_REVID(p, since, until) \
1597 (IS_TIGERLAKE(p) && \
1598 !(IS_TGL_U(p) || IS_TGL_Y(p)) && \
1599 tgl_revids_get(p)->gt_stepping >= (since) && \
1600 tgl_revids_get(p)->gt_stepping <= (until))
1602 #define RKL_REVID_A0 0x0
1603 #define RKL_REVID_B0 0x1
1604 #define RKL_REVID_C0 0x4
1606 #define IS_RKL_REVID(p, since, until) \
1607 (IS_ROCKETLAKE(p) && IS_REVID(p, since, until))
1609 #define DG1_REVID_A0 0x0
1610 #define DG1_REVID_B0 0x1
1612 #define IS_DG1_REVID(p, since, until) \
1613 (IS_DG1(p) && IS_REVID(p, since, until))
1615 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
1616 #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
1617 #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
1619 #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
1620 #define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
1622 #define ENGINE_INSTANCES_MASK(gt, first, count) ({ \
1623 unsigned int first__ = (first); \
1624 unsigned int count__ = (count); \
1625 ((gt)->info.engine_mask & \
1626 GENMASK(first__ + count__ - 1, first__)) >> first__; \
1628 #define VDBOX_MASK(gt) \
1629 ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
1630 #define VEBOX_MASK(gt) \
1631 ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
1634 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
1635 * All later gens can run the final buffer from the ppgtt
1637 #define CMDPARSER_USES_GGTT(dev_priv) IS_GEN(dev_priv, 7)
1639 #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
1640 #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
1641 #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
1642 #define HAS_SECURE_BATCHES(dev_priv) (INTEL_GEN(dev_priv) < 6)
1643 #define HAS_WT(dev_priv) HAS_EDRAM(dev_priv)
1645 #define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical)
1647 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
1648 (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
1649 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
1650 (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
1652 #define HAS_MASTER_UNIT_IRQ(dev_priv) (INTEL_INFO(dev_priv)->has_master_unit_irq)
1654 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
1656 #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)
1657 #define HAS_PPGTT(dev_priv) \
1658 (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
1659 #define HAS_FULL_PPGTT(dev_priv) \
1660 (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
1662 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
1663 GEM_BUG_ON((sizes) == 0); \
1664 ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \
1667 #define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay)
1668 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
1669 (INTEL_INFO(dev_priv)->display.overlay_needs_physical)
1671 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1672 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
1674 #define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv) \
1675 (IS_BROADWELL(dev_priv) || IS_GEN(dev_priv, 9))
1677 /* WaRsDisableCoarsePowerGating:skl,cnl */
1678 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
1679 (IS_CANNONLAKE(dev_priv) || \
1680 IS_SKL_GT3(dev_priv) || \
1681 IS_SKL_GT4(dev_priv))
1683 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
1684 #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
1685 IS_GEMINILAKE(dev_priv) || \
1686 IS_KABYLAKE(dev_priv))
1688 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1689 * rows, which changed the alignment requirements and fence programming.
1691 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \
1692 !(IS_I915G(dev_priv) || \
1693 IS_I915GM(dev_priv)))
1694 #define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv)
1695 #define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug)
1697 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
1698 #define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc)
1699 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7)
1701 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
1703 #define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst)
1705 #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
1706 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg)
1707 #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
1708 #define HAS_PSR_HW_TRACKING(dev_priv) \
1709 (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
1710 #define HAS_PSR2_SEL_FETCH(dev_priv) (INTEL_GEN(dev_priv) >= 12)
1711 #define HAS_TRANSCODER(dev_priv, trans) ((INTEL_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0)
1713 #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6)
1714 #define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p)
1715 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
1717 #define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps)
1719 #define HAS_CSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_csr)
1721 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
1722 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
1724 #define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
1726 #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
1727 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
1729 #define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc)
1731 #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
1733 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs)
1736 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
1738 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
1740 /* DPF == dynamic parity feature */
1741 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
1742 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
1743 2 : HAS_L3_DPF(dev_priv))
1745 #define GT_FREQUENCY_MULTIPLIER 50
1746 #define GEN9_FREQ_SCALER 3
1748 #define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask))
1750 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0)
1752 #define HAS_VRR(i915) (INTEL_GEN(i915) >= 12)
1754 /* Only valid when HAS_DISPLAY() is true */
1755 #define INTEL_DISPLAY_ENABLED(dev_priv) \
1756 (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !(dev_priv)->params.disable_display)
1758 static inline bool run_as_guest(void)
1760 return !hypervisor_is_type(X86_HYPER_NATIVE);
1763 static inline bool intel_vtd_active(void)
1765 #ifdef CONFIG_INTEL_IOMMU
1766 if (intel_iommu_gfx_mapped)
1770 /* Running as a guest, we assume the host is enforcing VT'd */
1771 return run_as_guest();
1774 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
1776 return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
1780 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
1782 return IS_BROXTON(dev_priv) && intel_vtd_active();
1786 extern const struct dev_pm_ops i915_pm_ops;
1788 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
1789 void i915_driver_remove(struct drm_i915_private *i915);
1790 void i915_driver_shutdown(struct drm_i915_private *i915);
1792 int i915_resume_switcheroo(struct drm_i915_private *i915);
1793 int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state);
1795 int i915_getparam_ioctl(struct drm_device *dev, void *data,
1796 struct drm_file *file_priv);
1799 int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
1800 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
1801 void i915_gem_init_early(struct drm_i915_private *dev_priv);
1802 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
1804 struct intel_memory_region *i915_gem_shmem_setup(struct drm_i915_private *i915);
1806 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
1809 * A single pass should suffice to release all the freed objects (along
1810 * most call paths) , but be a little more paranoid in that freeing
1811 * the objects does take a little amount of time, during which the rcu
1812 * callbacks could have added new objects into the freed list, and
1813 * armed the work again.
1815 while (atomic_read(&i915->mm.free_count)) {
1816 flush_work(&i915->mm.free_work);
1821 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
1824 * Similar to objects above (see i915_gem_drain_freed-objects), in
1825 * general we have workers that are armed by RCU and then rearm
1826 * themselves in their callbacks. To be paranoid, we need to
1827 * drain the workqueue a second time after waiting for the RCU
1828 * grace period so that we catch work queued via RCU from the first
1829 * pass. As neither drain_workqueue() nor flush_workqueue() report
1830 * a result, we make an assumption that we only don't require more
1831 * than 3 passes to catch all _recursive_ RCU delayed work.
1836 flush_workqueue(i915->wq);
1838 i915_gem_drain_freed_objects(i915);
1840 drain_workqueue(i915->wq);
1843 struct i915_vma * __must_check
1844 i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object *obj,
1845 struct i915_gem_ww_ctx *ww,
1846 const struct i915_ggtt_view *view,
1847 u64 size, u64 alignment, u64 flags);
1849 static inline struct i915_vma * __must_check
1850 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
1851 const struct i915_ggtt_view *view,
1852 u64 size, u64 alignment, u64 flags)
1854 return i915_gem_object_ggtt_pin_ww(obj, NULL, view, size, alignment, flags);
1857 int i915_gem_object_unbind(struct drm_i915_gem_object *obj,
1858 unsigned long flags);
1859 #define I915_GEM_OBJECT_UNBIND_ACTIVE BIT(0)
1860 #define I915_GEM_OBJECT_UNBIND_BARRIER BIT(1)
1861 #define I915_GEM_OBJECT_UNBIND_TEST BIT(2)
1863 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
1865 int i915_gem_dumb_create(struct drm_file *file_priv,
1866 struct drm_device *dev,
1867 struct drm_mode_create_dumb *args);
1869 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
1871 static inline u32 i915_reset_count(struct i915_gpu_error *error)
1873 return atomic_read(&error->reset_count);
1876 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
1877 const struct intel_engine_cs *engine)
1879 return atomic_read(&error->reset_engine_count[engine->uabi_class]);
1882 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
1883 void i915_gem_driver_register(struct drm_i915_private *i915);
1884 void i915_gem_driver_unregister(struct drm_i915_private *i915);
1885 void i915_gem_driver_remove(struct drm_i915_private *dev_priv);
1886 void i915_gem_driver_release(struct drm_i915_private *dev_priv);
1887 void i915_gem_suspend(struct drm_i915_private *dev_priv);
1888 void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
1889 void i915_gem_resume(struct drm_i915_private *dev_priv);
1891 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
1893 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1894 enum i915_cache_level cache_level);
1896 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1897 struct dma_buf *dma_buf);
1899 struct dma_buf *i915_gem_prime_export(struct drm_gem_object *gem_obj, int flags);
1901 static inline struct i915_gem_context *
1902 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
1904 return xa_load(&file_priv->context_xa, id);
1907 static inline struct i915_gem_context *
1908 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
1910 struct i915_gem_context *ctx;
1913 ctx = __i915_gem_context_lookup_rcu(file_priv, id);
1914 if (ctx && !kref_get_unless_zero(&ctx->ref))
1921 /* i915_gem_evict.c */
1922 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
1923 u64 min_size, u64 alignment,
1924 unsigned long color,
1927 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
1928 struct drm_mm_node *node,
1929 unsigned int flags);
1930 int i915_gem_evict_vm(struct i915_address_space *vm);
1932 /* i915_gem_internal.c */
1933 struct drm_i915_gem_object *
1934 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
1937 /* i915_gem_tiling.c */
1938 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
1940 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1942 return i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
1943 i915_gem_object_is_tiled(obj);
1946 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
1947 unsigned int tiling, unsigned int stride);
1948 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
1949 unsigned int tiling, unsigned int stride);
1951 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
1953 /* i915_cmd_parser.c */
1954 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
1955 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
1956 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
1957 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
1958 struct i915_vma *batch,
1959 unsigned long batch_offset,
1960 unsigned long batch_length,
1961 struct i915_vma *shadow,
1963 #define I915_CMD_PARSER_TRAMPOLINE_SIZE 8
1965 /* intel_device_info.c */
1966 static inline struct intel_device_info *
1967 mkwrite_device_info(struct drm_i915_private *dev_priv)
1969 return (struct intel_device_info *)INTEL_INFO(dev_priv);
1972 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
1973 struct drm_file *file);
1976 int remap_io_mapping(struct vm_area_struct *vma,
1977 unsigned long addr, unsigned long pfn, unsigned long size,
1978 struct io_mapping *iomap);
1979 int remap_io_sg(struct vm_area_struct *vma,
1980 unsigned long addr, unsigned long size,
1981 struct scatterlist *sgl, resource_size_t iobase);
1983 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
1985 if (INTEL_GEN(i915) >= 10)
1986 return CNL_HWS_CSB_WRITE_INDEX;
1988 return I915_HWS_CSB_WRITE_INDEX;
1991 static inline enum i915_map_type
1992 i915_coherent_map_type(struct drm_i915_private *i915)
1994 return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;