drivers/gpu/drm/i915/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 #include <uapi/drm/i915_drm.h>
  34
  35 #include <linux/pm_qos.h>
  36
  37 #include <drm/ttm/ttm_device.h>
  38
  39 #include "display/intel_display.h"
  40 #include "display/intel_display_core.h"
  41
  42 #include "gem/i915_gem_context_types.h"
  43 #include "gem/i915_gem_shrinker.h"
  44 #include "gem/i915_gem_stolen.h"
  45
  46 #include "gt/intel_engine.h"
  47 #include "gt/intel_gt_types.h"
  48 #include "gt/intel_region_lmem.h"
  49 #include "gt/intel_workarounds.h"
  50 #include "gt/uc/intel_uc.h"
  51
  52 #include "i915_drm_client.h"
  53 #include "i915_gem.h"
  54 #include "i915_gpu_error.h"
  55 #include "i915_params.h"
  56 #include "i915_perf_types.h"
  57 #include "i915_scheduler.h"
  58 #include "i915_utils.h"
  59 #include "intel_device_info.h"
  60 #include "intel_memory_region.h"
  61 #include "intel_pch.h"
  62 #include "intel_runtime_pm.h"
  63 #include "intel_step.h"
  64 #include "intel_uncore.h"
  65 #include "intel_wopcm.h"
  66
  67 struct drm_i915_clock_gating_funcs;
  68 struct drm_i915_gem_object;
  69 struct drm_i915_private;
  70 struct intel_connector;
  71 struct intel_dp;
  72 struct intel_encoder;
  73 struct intel_limit;
  74 struct intel_overlay_error_state;
  75 struct vlv_s0ix_state;
  76
  77 #define I915_GEM_GPU_DOMAINS \
  78         (I915_GEM_DOMAIN_RENDER | \
  79          I915_GEM_DOMAIN_SAMPLER | \
  80          I915_GEM_DOMAIN_COMMAND | \
  81          I915_GEM_DOMAIN_INSTRUCTION | \
  82          I915_GEM_DOMAIN_VERTEX)
  83
  84 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
  85
  86 #define GEM_QUIRK_PIN_SWIZZLED_PAGES    BIT(0)
  87
  88 struct i915_suspend_saved_registers {
  89         u32 saveDSPARB;
  90         u32 saveSWF0[16];
  91         u32 saveSWF1[16];
  92         u32 saveSWF3[3];
  93         u16 saveGCDGMBUS;
  94 };
  95
  96 #define MAX_L3_SLICES 2
  97 struct intel_l3_parity {
  98         u32 *remap_info[MAX_L3_SLICES];
  99         struct work_struct error_work;
 100         int which_slice;
 101 };
 102
 103 struct i915_gem_mm {
 104         /*
 105          * Shortcut for the stolen region. This points to either
 106          * INTEL_REGION_STOLEN_SMEM for integrated platforms, or
 107          * INTEL_REGION_STOLEN_LMEM for discrete, or NULL if the device doesn't
 108          * support stolen.
 109          */
 110         struct intel_memory_region *stolen_region;
 111         /** Memory allocator for GTT stolen memory */
 112         struct drm_mm stolen;
 113         /** Protects the usage of the GTT stolen memory allocator. This is
 114          * always the inner lock when overlapping with struct_mutex. */
 115         struct mutex stolen_lock;
 116
 117         /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
 118         spinlock_t obj_lock;
 119
 120         /**
 121          * List of objects which are purgeable.
 122          */
 123         struct list_head purge_list;
 124
 125         /**
 126          * List of objects which have allocated pages and are shrinkable.
 127          */
 128         struct list_head shrink_list;
 129
 130         /**
 131          * List of objects which are pending destruction.
 132          */
 133         struct llist_head free_list;
 134         struct work_struct free_work;
 135         /**
 136          * Count of objects pending destructions. Used to skip needlessly
 137          * waiting on an RCU barrier if no objects are waiting to be freed.
 138          */
 139         atomic_t free_count;
 140
 141         /**
 142          * tmpfs instance used for shmem backed objects
 143          */
 144         struct vfsmount *gemfs;
 145
 146         struct intel_memory_region *regions[INTEL_REGION_UNKNOWN];
 147
 148         struct notifier_block oom_notifier;
 149         struct notifier_block vmap_notifier;
 150         struct shrinker shrinker;
 151
 152 #ifdef CONFIG_MMU_NOTIFIER
 153         /**
 154          * notifier_lock for mmu notifiers, memory may not be allocated
 155          * while holding this lock.
 156          */
 157         rwlock_t notifier_lock;
 158 #endif
 159
 160         /* shrinker accounting, also useful for userland debugging */
 161         u64 shrink_memory;
 162         u32 shrink_count;
 163 };
 164
 165 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
 166
 167 unsigned long i915_fence_context_timeout(const struct drm_i915_private *i915,
 168                                          u64 context);
 169
 170 static inline unsigned long
 171 i915_fence_timeout(const struct drm_i915_private *i915)
 172 {
 173         return i915_fence_context_timeout(i915, U64_MAX);
 174 }
 175
 176 #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
 177
 178 struct i915_virtual_gpu {
 179         struct mutex lock; /* serialises sending of g2v_notify command pkts */
 180         bool active;
 181         u32 caps;
 182         u32 *initial_mmio;
 183         u8 *initial_cfg_space;
 184         struct list_head entry;
 185 };
 186
 187 struct i915_selftest_stash {
 188         atomic_t counter;
 189         struct ida mock_region_instances;
 190 };
 191
 192 struct drm_i915_private {
 193         struct drm_device drm;
 194
 195         struct intel_display display;
 196
 197         /* FIXME: Device release actions should all be moved to drmm_ */
 198         bool do_release;
 199
 200         /* i915 device parameters */
 201         struct i915_params params;
 202
 203         const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
 204         struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
 205         struct intel_driver_caps caps;
 206
 207         /**
 208          * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
 209          * end of stolen which we can optionally use to create GEM objects
 210          * backed by stolen memory. Note that stolen_usable_size tells us
 211          * exactly how much of this we are actually allowed to use, given that
 212          * some portion of it is in fact reserved for use by hardware functions.
 213          */
 214         struct resource dsm;
 215         /**
 216          * Reseved portion of Data Stolen Memory
 217          */
 218         struct resource dsm_reserved;
 219
 220         /*
 221          * Stolen memory is segmented in hardware with different portions
 222          * offlimits to certain functions.
 223          *
 224          * The drm_mm is initialised to the total accessible range, as found
 225          * from the PCI config. On Broadwell+, this is further restricted to
 226          * avoid the first page! The upper end of stolen memory is reserved for
 227          * hardware functions and similarly removed from the accessible range.
 228          */
 229         resource_size_t stolen_usable_size;     /* Total size minus reserved ranges */
 230
 231         struct intel_uncore uncore;
 232         struct intel_uncore_mmio_debug mmio_debug;
 233
 234         struct i915_virtual_gpu vgpu;
 235
 236         struct intel_gvt *gvt;
 237
 238         struct intel_wopcm wopcm;
 239
 240         struct pci_dev *bridge_dev;
 241
 242         struct rb_root uabi_engines;
 243         unsigned int engine_uabi_class_count[I915_LAST_UABI_ENGINE_CLASS + 1];
 244
 245         struct resource mch_res;
 246
 247         /* protects the irq masks */
 248         spinlock_t irq_lock;
 249
 250         bool display_irqs_enabled;
 251
 252         /* Sideband mailbox protection */
 253         struct mutex sb_lock;
 254         struct pm_qos_request sb_qos;
 255
 256         /** Cached value of IMR to avoid reads in updating the bitfield */
 257         union {
 258                 u32 irq_mask;
 259                 u32 de_irq_mask[I915_MAX_PIPES];
 260         };
 261         u32 pipestat_irq_mask[I915_MAX_PIPES];
 262
 263         bool preserve_bios_swizzle;
 264
 265         unsigned int fsb_freq, mem_freq, is_ddr3;
 266         unsigned int skl_preferred_vco_freq;
 267
 268         unsigned int max_dotclk_freq;
 269         unsigned int hpll_freq;
 270         unsigned int czclk_freq;
 271
 272         /**
 273          * wq - Driver workqueue for GEM.
 274          *
 275          * NOTE: Work items scheduled here are not allowed to grab any modeset
 276          * locks, for otherwise the flushing done in the pageflip code will
 277          * result in deadlocks.
 278          */
 279         struct workqueue_struct *wq;
 280
 281         /* pm private clock gating functions */
 282         const struct drm_i915_clock_gating_funcs *clock_gating_funcs;
 283
 284         /* PCH chipset type */
 285         enum intel_pch pch_type;
 286         unsigned short pch_id;
 287
 288         unsigned long gem_quirks;
 289
 290         struct drm_atomic_state *modeset_restore_state;
 291         struct drm_modeset_acquire_ctx reset_ctx;
 292
 293         struct i915_gem_mm mm;
 294
 295         bool mchbar_need_disable;
 296
 297         struct intel_l3_parity l3_parity;
 298
 299         /*
 300          * edram size in MB.
 301          * Cannot be determined by PCIID. You must always read a register.
 302          */
 303         u32 edram_size_mb;
 304
 305         struct i915_gpu_error gpu_error;
 306
 307         /*
 308          * Shadows for CHV DPLL_MD regs to keep the state
 309          * checker somewhat working in the presence hardware
 310          * crappiness (can't read out DPLL_MD for pipes B & C).
 311          */
 312         u32 chv_dpll_md[I915_MAX_PIPES];
 313         u32 bxt_phy_grc;
 314
 315         u32 suspend_count;
 316         struct i915_suspend_saved_registers regfile;
 317         struct vlv_s0ix_state *vlv_s0ix_state;
 318
 319         struct dram_info {
 320                 bool wm_lv_0_adjust_needed;
 321                 u8 num_channels;
 322                 bool symmetric_memory;
 323                 enum intel_dram_type {
 324                         INTEL_DRAM_UNKNOWN,
 325                         INTEL_DRAM_DDR3,
 326                         INTEL_DRAM_DDR4,
 327                         INTEL_DRAM_LPDDR3,
 328                         INTEL_DRAM_LPDDR4,
 329                         INTEL_DRAM_DDR5,
 330                         INTEL_DRAM_LPDDR5,
 331                 } type;
 332                 u8 num_qgv_points;
 333                 u8 num_psf_gv_points;
 334         } dram_info;
 335
 336         struct intel_runtime_pm runtime_pm;
 337
 338         struct i915_perf perf;
 339
 340         struct i915_hwmon *hwmon;
 341
 342         /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
 343         struct intel_gt gt0;
 344
 345         /*
 346          * i915->gt[0] == &i915->gt0
 347          */
 348 #define I915_MAX_GT 4
 349         struct intel_gt *gt[I915_MAX_GT];
 350
 351         struct kobject *sysfs_gt;
 352
 353         /* Quick lookup of media GT (current platforms only have one) */
 354         struct intel_gt *media_gt;
 355
 356         struct {
 357                 struct i915_gem_contexts {
 358                         spinlock_t lock; /* locks list */
 359                         struct list_head list;
 360                 } contexts;
 361
 362                 /*
 363                  * We replace the local file with a global mappings as the
 364                  * backing storage for the mmap is on the device and not
 365                  * on the struct file, and we do not want to prolong the
 366                  * lifetime of the local fd. To minimise the number of
 367                  * anonymous inodes we create, we use a global singleton to
 368                  * share the global mapping.
 369                  */
 370                 struct file *mmap_singleton;
 371         } gem;
 372
 373         u8 pch_ssc_use;
 374
 375         /* For i915gm/i945gm vblank irq workaround */
 376         u8 vblank_enabled;
 377
 378         bool irq_enabled;
 379
 380         /*
 381          * DG2: Mask of PHYs that were not calibrated by the firmware
 382          * and should not be used.
 383          */
 384         u8 snps_phy_failed_calibration;
 385
 386         struct i915_pmu pmu;
 387
 388         struct i915_drm_clients clients;
 389
 390         /* The TTM device structure. */
 391         struct ttm_device bdev;
 392
 393         I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
 394
 395         /*
 396          * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
 397          * will be rejected. Instead look for a better place.
 398          */
 399 };
 400
 401 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
 402 {
 403         return container_of(dev, struct drm_i915_private, drm);
 404 }
 405
 406 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
 407 {
 408         return dev_get_drvdata(kdev);
 409 }
 410
 411 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
 412 {
 413         return pci_get_drvdata(pdev);
 414 }
 415
 416 static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
 417 {
 418         return &i915->gt0;
 419 }
 420
 421 /* Simple iterator over all initialised engines */
 422 #define for_each_engine(engine__, dev_priv__, id__) \
 423         for ((id__) = 0; \
 424              (id__) < I915_NUM_ENGINES; \
 425              (id__)++) \
 426                 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
 427
 428 /* Iterator over subset of engines selected by mask */
 429 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
 430         for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \
 431              (tmp__) ? \
 432              ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \
 433              0;)
 434
 435 #define rb_to_uabi_engine(rb) \
 436         rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
 437
 438 #define for_each_uabi_engine(engine__, i915__) \
 439         for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
 440              (engine__); \
 441              (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
 442
 443 #define for_each_uabi_class_engine(engine__, class__, i915__) \
 444         for ((engine__) = intel_engine_lookup_user((i915__), (class__), 0); \
 445              (engine__) && (engine__)->uabi_class == (class__); \
 446              (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
 447
 448 #define INTEL_INFO(dev_priv)    (&(dev_priv)->__info)
 449 #define RUNTIME_INFO(dev_priv)  (&(dev_priv)->__runtime)
 450 #define DRIVER_CAPS(dev_priv)   (&(dev_priv)->caps)
 451
 452 #define INTEL_DEVID(dev_priv)   (RUNTIME_INFO(dev_priv)->device_id)
 453
 454 #define IP_VER(ver, rel)                ((ver) << 8 | (rel))
 455
 456 #define GRAPHICS_VER(i915)              (RUNTIME_INFO(i915)->graphics.ip.ver)
 457 #define GRAPHICS_VER_FULL(i915)         IP_VER(RUNTIME_INFO(i915)->graphics.ip.ver, \
 458                                                RUNTIME_INFO(i915)->graphics.ip.rel)
 459 #define IS_GRAPHICS_VER(i915, from, until) \
 460         (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
 461
 462 #define MEDIA_VER(i915)                 (RUNTIME_INFO(i915)->media.ip.ver)
 463 #define MEDIA_VER_FULL(i915)            IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \
 464                                                RUNTIME_INFO(i915)->media.ip.rel)
 465 #define IS_MEDIA_VER(i915, from, until) \
 466         (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))
 467
 468 #define DISPLAY_VER(i915)       (RUNTIME_INFO(i915)->display.ip.ver)
 469 #define IS_DISPLAY_VER(i915, from, until) \
 470         (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
 471
 472 #define INTEL_REVID(dev_priv)   (to_pci_dev((dev_priv)->drm.dev)->revision)
 473
 474 #define HAS_DSB(dev_priv)       (INTEL_INFO(dev_priv)->display.has_dsb)
 475
 476 #define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step)
 477 #define INTEL_GRAPHICS_STEP(__i915) (RUNTIME_INFO(__i915)->step.graphics_step)
 478 #define INTEL_MEDIA_STEP(__i915) (RUNTIME_INFO(__i915)->step.media_step)
 479 #define INTEL_BASEDIE_STEP(__i915) (RUNTIME_INFO(__i915)->step.basedie_step)
 480
 481 #define IS_DISPLAY_STEP(__i915, since, until) \
 482         (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \
 483          INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) < (until))
 484
 485 #define IS_GRAPHICS_STEP(__i915, since, until) \
 486         (drm_WARN_ON(&(__i915)->drm, INTEL_GRAPHICS_STEP(__i915) == STEP_NONE), \
 487          INTEL_GRAPHICS_STEP(__i915) >= (since) && INTEL_GRAPHICS_STEP(__i915) < (until))
 488
 489 #define IS_MEDIA_STEP(__i915, since, until) \
 490         (drm_WARN_ON(&(__i915)->drm, INTEL_MEDIA_STEP(__i915) == STEP_NONE), \
 491          INTEL_MEDIA_STEP(__i915) >= (since) && INTEL_MEDIA_STEP(__i915) < (until))
 492
 493 #define IS_BASEDIE_STEP(__i915, since, until) \
 494         (drm_WARN_ON(&(__i915)->drm, INTEL_BASEDIE_STEP(__i915) == STEP_NONE), \
 495          INTEL_BASEDIE_STEP(__i915) >= (since) && INTEL_BASEDIE_STEP(__i915) < (until))
 496
 497 static __always_inline unsigned int
 498 __platform_mask_index(const struct intel_runtime_info *info,
 499                       enum intel_platform p)
 500 {
 501         const unsigned int pbits =
 502                 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
 503
 504         /* Expand the platform_mask array if this fails. */
 505         BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
 506                      pbits * ARRAY_SIZE(info->platform_mask));
 507
 508         return p / pbits;
 509 }
 510
 511 static __always_inline unsigned int
 512 __platform_mask_bit(const struct intel_runtime_info *info,
 513                     enum intel_platform p)
 514 {
 515         const unsigned int pbits =
 516                 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
 517
 518         return p % pbits + INTEL_SUBPLATFORM_BITS;
 519 }
 520
 521 static inline u32
 522 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
 523 {
 524         const unsigned int pi = __platform_mask_index(info, p);
 525
 526         return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK;
 527 }
 528
 529 static __always_inline bool
 530 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
 531 {
 532         const struct intel_runtime_info *info = RUNTIME_INFO(i915);
 533         const unsigned int pi = __platform_mask_index(info, p);
 534         const unsigned int pb = __platform_mask_bit(info, p);
 535
 536         BUILD_BUG_ON(!__builtin_constant_p(p));
 537
 538         return info->platform_mask[pi] & BIT(pb);
 539 }
 540
 541 static __always_inline bool
 542 IS_SUBPLATFORM(const struct drm_i915_private *i915,
 543                enum intel_platform p, unsigned int s)
 544 {
 545         const struct intel_runtime_info *info = RUNTIME_INFO(i915);
 546         const unsigned int pi = __platform_mask_index(info, p);
 547         const unsigned int pb = __platform_mask_bit(info, p);
 548         const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
 549         const u32 mask = info->platform_mask[pi];
 550
 551         BUILD_BUG_ON(!__builtin_constant_p(p));
 552         BUILD_BUG_ON(!__builtin_constant_p(s));
 553         BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
 554
 555         /* Shift and test on the MSB position so sign flag can be used. */
 556         return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
 557 }
 558
 559 #define IS_MOBILE(dev_priv)     (INTEL_INFO(dev_priv)->is_mobile)
 560 #define IS_DGFX(dev_priv)   (INTEL_INFO(dev_priv)->is_dgfx)
 561
 562 #define IS_I830(dev_priv)       IS_PLATFORM(dev_priv, INTEL_I830)
 563 #define IS_I845G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I845G)
 564 #define IS_I85X(dev_priv)       IS_PLATFORM(dev_priv, INTEL_I85X)
 565 #define IS_I865G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I865G)
 566 #define IS_I915G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I915G)
 567 #define IS_I915GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I915GM)
 568 #define IS_I945G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I945G)
 569 #define IS_I945GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I945GM)
 570 #define IS_I965G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I965G)
 571 #define IS_I965GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I965GM)
 572 #define IS_G45(dev_priv)        IS_PLATFORM(dev_priv, INTEL_G45)
 573 #define IS_GM45(dev_priv)       IS_PLATFORM(dev_priv, INTEL_GM45)
 574 #define IS_G4X(dev_priv)        (IS_G45(dev_priv) || IS_GM45(dev_priv))
 575 #define IS_PINEVIEW(dev_priv)   IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
 576 #define IS_G33(dev_priv)        IS_PLATFORM(dev_priv, INTEL_G33)
 577 #define IS_IRONLAKE(dev_priv)   IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
 578 #define IS_IRONLAKE_M(dev_priv) \
 579         (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
 580 #define IS_SANDYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SANDYBRIDGE)
 581 #define IS_IVYBRIDGE(dev_priv)  IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
 582 #define IS_IVB_GT1(dev_priv)    (IS_IVYBRIDGE(dev_priv) && \
 583                                  INTEL_INFO(dev_priv)->gt == 1)
 584 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
 585 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
 586 #define IS_HASWELL(dev_priv)    IS_PLATFORM(dev_priv, INTEL_HASWELL)
 587 #define IS_BROADWELL(dev_priv)  IS_PLATFORM(dev_priv, INTEL_BROADWELL)
 588 #define IS_SKYLAKE(dev_priv)    IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
 589 #define IS_BROXTON(dev_priv)    IS_PLATFORM(dev_priv, INTEL_BROXTON)
 590 #define IS_KABYLAKE(dev_priv)   IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
 591 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
 592 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
 593 #define IS_COMETLAKE(dev_priv)  IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
 594 #define IS_ICELAKE(dev_priv)    IS_PLATFORM(dev_priv, INTEL_ICELAKE)
 595 #define IS_JSL_EHL(dev_priv)    (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \
 596                                 IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
 597 #define IS_TIGERLAKE(dev_priv)  IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
 598 #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
 599 #define IS_DG1(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG1)
 600 #define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
 601 #define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P)
 602 #define IS_XEHPSDV(dev_priv) IS_PLATFORM(dev_priv, INTEL_XEHPSDV)
 603 #define IS_DG2(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG2)
 604 #define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, INTEL_PONTEVECCHIO)
 605 #define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_METEORLAKE)
 606
 607 #define IS_METEORLAKE_M(dev_priv) \
 608         IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
 609 #define IS_METEORLAKE_P(dev_priv) \
 610         IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P)
 611 #define IS_DG2_G10(dev_priv) \
 612         IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
 613 #define IS_DG2_G11(dev_priv) \
 614         IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
 615 #define IS_DG2_G12(dev_priv) \
 616         IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12)
 617 #define IS_ADLS_RPLS(dev_priv) \
 618         IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
 619 #define IS_ADLP_N(dev_priv) \
 620         IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
 621 #define IS_ADLP_RPLP(dev_priv) \
 622         IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
 623 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
 624                                     (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
 625 #define IS_BDW_ULT(dev_priv) \
 626         IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
 627 #define IS_BDW_ULX(dev_priv) \
 628         IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
 629 #define IS_BDW_GT3(dev_priv)    (IS_BROADWELL(dev_priv) && \
 630                                  INTEL_INFO(dev_priv)->gt == 3)
 631 #define IS_HSW_ULT(dev_priv) \
 632         IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
 633 #define IS_HSW_GT3(dev_priv)    (IS_HASWELL(dev_priv) && \
 634                                  INTEL_INFO(dev_priv)->gt == 3)
 635 #define IS_HSW_GT1(dev_priv)    (IS_HASWELL(dev_priv) && \
 636                                  INTEL_INFO(dev_priv)->gt == 1)
 637 /* ULX machines are also considered ULT. */
 638 #define IS_HSW_ULX(dev_priv) \
 639         IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
 640 #define IS_SKL_ULT(dev_priv) \
 641         IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
 642 #define IS_SKL_ULX(dev_priv) \
 643         IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
 644 #define IS_KBL_ULT(dev_priv) \
 645         IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
 646 #define IS_KBL_ULX(dev_priv) \
 647         IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
 648 #define IS_SKL_GT2(dev_priv)    (IS_SKYLAKE(dev_priv) && \
 649                                  INTEL_INFO(dev_priv)->gt == 2)
 650 #define IS_SKL_GT3(dev_priv)    (IS_SKYLAKE(dev_priv) && \
 651                                  INTEL_INFO(dev_priv)->gt == 3)
 652 #define IS_SKL_GT4(dev_priv)    (IS_SKYLAKE(dev_priv) && \
 653                                  INTEL_INFO(dev_priv)->gt == 4)
 654 #define IS_KBL_GT2(dev_priv)    (IS_KABYLAKE(dev_priv) && \
 655                                  INTEL_INFO(dev_priv)->gt == 2)
 656 #define IS_KBL_GT3(dev_priv)    (IS_KABYLAKE(dev_priv) && \
 657                                  INTEL_INFO(dev_priv)->gt == 3)
 658 #define IS_CFL_ULT(dev_priv) \
 659         IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
 660 #define IS_CFL_ULX(dev_priv) \
 661         IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
 662 #define IS_CFL_GT2(dev_priv)    (IS_COFFEELAKE(dev_priv) && \
 663                                  INTEL_INFO(dev_priv)->gt == 2)
 664 #define IS_CFL_GT3(dev_priv)    (IS_COFFEELAKE(dev_priv) && \
 665                                  INTEL_INFO(dev_priv)->gt == 3)
 666
 667 #define IS_CML_ULT(dev_priv) \
 668         IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
 669 #define IS_CML_ULX(dev_priv) \
 670         IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
 671 #define IS_CML_GT2(dev_priv)    (IS_COMETLAKE(dev_priv) && \
 672                                  INTEL_INFO(dev_priv)->gt == 2)
 673
 674 #define IS_ICL_WITH_PORT_F(dev_priv) \
 675         IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
 676
 677 #define IS_TGL_UY(dev_priv) \
 678         IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
 679
 680 #define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until))
 681
 682 #define IS_KBL_GRAPHICS_STEP(dev_priv, since, until) \
 683         (IS_KABYLAKE(dev_priv) && IS_GRAPHICS_STEP(dev_priv, since, until))
 684 #define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \
 685         (IS_KABYLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, since, until))
 686
 687 #define IS_JSL_EHL_GRAPHICS_STEP(p, since, until) \
 688         (IS_JSL_EHL(p) && IS_GRAPHICS_STEP(p, since, until))
 689 #define IS_JSL_EHL_DISPLAY_STEP(p, since, until) \
 690         (IS_JSL_EHL(p) && IS_DISPLAY_STEP(p, since, until))
 691
 692 #define IS_TGL_DISPLAY_STEP(__i915, since, until) \
 693         (IS_TIGERLAKE(__i915) && \
 694          IS_DISPLAY_STEP(__i915, since, until))
 695
 696 #define IS_TGL_UY_GRAPHICS_STEP(__i915, since, until) \
 697         (IS_TGL_UY(__i915) && \
 698          IS_GRAPHICS_STEP(__i915, since, until))
 699
 700 #define IS_TGL_GRAPHICS_STEP(__i915, since, until) \
 701         (IS_TIGERLAKE(__i915) && !IS_TGL_UY(__i915)) && \
 702          IS_GRAPHICS_STEP(__i915, since, until))
 703
 704 #define IS_RKL_DISPLAY_STEP(p, since, until) \
 705         (IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
 706
 707 #define IS_DG1_GRAPHICS_STEP(p, since, until) \
 708         (IS_DG1(p) && IS_GRAPHICS_STEP(p, since, until))
 709 #define IS_DG1_DISPLAY_STEP(p, since, until) \
 710         (IS_DG1(p) && IS_DISPLAY_STEP(p, since, until))
 711
 712 #define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
 713         (IS_ALDERLAKE_S(__i915) && \
 714          IS_DISPLAY_STEP(__i915, since, until))
 715
 716 #define IS_ADLS_GRAPHICS_STEP(__i915, since, until) \
 717         (IS_ALDERLAKE_S(__i915) && \
 718          IS_GRAPHICS_STEP(__i915, since, until))
 719
 720 #define IS_ADLP_DISPLAY_STEP(__i915, since, until) \
 721         (IS_ALDERLAKE_P(__i915) && \
 722          IS_DISPLAY_STEP(__i915, since, until))
 723
 724 #define IS_ADLP_GRAPHICS_STEP(__i915, since, until) \
 725         (IS_ALDERLAKE_P(__i915) && \
 726          IS_GRAPHICS_STEP(__i915, since, until))
 727
 728 #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
 729         (IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
 730
 731 /*
 732  * DG2 hardware steppings are a bit unusual.  The hardware design was forked to
 733  * create three variants (G10, G11, and G12) which each have distinct
 734  * workaround sets.  The G11 and G12 forks of the DG2 design reset the GT
 735  * stepping back to "A0" for their first iterations, even though they're more
 736  * similar to a G10 B0 stepping and G10 C0 stepping respectively in terms of
 737  * functionality and workarounds.  However the display stepping does not reset
 738  * in the same manner --- a specific stepping like "B0" has a consistent
 739  * meaning regardless of whether it belongs to a G10, G11, or G12 DG2.
 740  *
 741  * TLDR:  All GT workarounds and stepping-specific logic must be applied in
 742  * relation to a specific subplatform (G10/G11/G12), whereas display workarounds
 743  * and stepping-specific logic will be applied with a general DG2-wide stepping
 744  * number.
 745  */
 746 #define IS_DG2_GRAPHICS_STEP(__i915, variant, since, until) \
 747         (IS_SUBPLATFORM(__i915, INTEL_DG2, INTEL_SUBPLATFORM_##variant) && \
 748          IS_GRAPHICS_STEP(__i915, since, until))
 749
 750 #define IS_DG2_DISPLAY_STEP(__i915, since, until) \
 751         (IS_DG2(__i915) && \
 752          IS_DISPLAY_STEP(__i915, since, until))
 753
 754 #define IS_PVC_BD_STEP(__i915, since, until) \
 755         (IS_PONTEVECCHIO(__i915) && \
 756          IS_BASEDIE_STEP(__i915, since, until))
 757
 758 #define IS_PVC_CT_STEP(__i915, since, until) \
 759         (IS_PONTEVECCHIO(__i915) && \
 760          IS_GRAPHICS_STEP(__i915, since, until))
 761
 762 #define IS_LP(dev_priv)         (INTEL_INFO(dev_priv)->is_lp)
 763 #define IS_GEN9_LP(dev_priv)    (GRAPHICS_VER(dev_priv) == 9 && IS_LP(dev_priv))
 764 #define IS_GEN9_BC(dev_priv)    (GRAPHICS_VER(dev_priv) == 9 && !IS_LP(dev_priv))
 765
 766 #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
 767 #define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
 768
 769 #define ENGINE_INSTANCES_MASK(gt, first, count) ({              \
 770         unsigned int first__ = (first);                                 \
 771         unsigned int count__ = (count);                                 \
 772         ((gt)->info.engine_mask &                                               \
 773          GENMASK(first__ + count__ - 1, first__)) >> first__;           \
 774 })
 775 #define RCS_MASK(gt) \
 776         ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS)
 777 #define BCS_MASK(gt) \
 778         ENGINE_INSTANCES_MASK(gt, BCS0, I915_MAX_BCS)
 779 #define VDBOX_MASK(gt) \
 780         ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
 781 #define VEBOX_MASK(gt) \
 782         ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
 783 #define CCS_MASK(gt) \
 784         ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS)
 785
 786 #define HAS_MEDIA_RATIO_MODE(dev_priv) (INTEL_INFO(dev_priv)->has_media_ratio_mode)
 787
 788 /*
 789  * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
 790  * All later gens can run the final buffer from the ppgtt
 791  */
 792 #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
 793
 794 #define HAS_LLC(dev_priv)       (INTEL_INFO(dev_priv)->has_llc)
 795 #define HAS_4TILE(dev_priv)     (INTEL_INFO(dev_priv)->has_4tile)
 796 #define HAS_SNOOP(dev_priv)     (INTEL_INFO(dev_priv)->has_snoop)
 797 #define HAS_EDRAM(dev_priv)     ((dev_priv)->edram_size_mb)
 798 #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
 799 #define HAS_WT(dev_priv)        HAS_EDRAM(dev_priv)
 800
 801 #define HWS_NEEDS_PHYSICAL(dev_priv)    (INTEL_INFO(dev_priv)->hws_needs_physical)
 802
 803 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
 804                 (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
 805 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
 806                 (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
 807
 808 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
 809
 810 #define INTEL_PPGTT(dev_priv) (RUNTIME_INFO(dev_priv)->ppgtt_type)
 811 #define HAS_PPGTT(dev_priv) \
 812         (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
 813 #define HAS_FULL_PPGTT(dev_priv) \
 814         (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
 815
 816 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
 817         GEM_BUG_ON((sizes) == 0); \
 818         ((sizes) & ~RUNTIME_INFO(dev_priv)->page_sizes) == 0; \
 819 })
 820
 821 #define HAS_OVERLAY(dev_priv)            (INTEL_INFO(dev_priv)->display.has_overlay)
 822 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
 823                 (INTEL_INFO(dev_priv)->display.overlay_needs_physical)
 824
 825 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
 826 #define HAS_BROKEN_CS_TLB(dev_priv)     (IS_I830(dev_priv) || IS_I845G(dev_priv))
 827
 828 #define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv)   \
 829         (IS_BROADWELL(dev_priv) || GRAPHICS_VER(dev_priv) == 9)
 830
 831 /* WaRsDisableCoarsePowerGating:skl,cnl */
 832 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv)                    \
 833         (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
 834
 835 #define HAS_GMBUS_IRQ(dev_priv) (DISPLAY_VER(dev_priv) >= 4)
 836 #define HAS_GMBUS_BURST_READ(dev_priv) (DISPLAY_VER(dev_priv) >= 11 || \
 837                                         IS_GEMINILAKE(dev_priv) || \
 838                                         IS_KABYLAKE(dev_priv))
 839
 840 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
 841  * rows, which changed the alignment requirements and fence programming.
 842  */
 843 #define HAS_128_BYTE_Y_TILING(dev_priv) (GRAPHICS_VER(dev_priv) != 2 && \
 844                                          !(IS_I915G(dev_priv) || IS_I915GM(dev_priv)))
 845 #define SUPPORTS_TV(dev_priv)           (INTEL_INFO(dev_priv)->display.supports_tv)
 846 #define I915_HAS_HOTPLUG(dev_priv)      (INTEL_INFO(dev_priv)->display.has_hotplug)
 847
 848 #define HAS_FW_BLC(dev_priv)    (DISPLAY_VER(dev_priv) > 2)
 849 #define HAS_FBC(dev_priv)       (RUNTIME_INFO(dev_priv)->fbc_mask != 0)
 850 #define HAS_CUR_FBC(dev_priv)   (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) >= 7)
 851
 852 #define HAS_IPS(dev_priv)       (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
 853
 854 #define HAS_DP_MST(dev_priv)    (INTEL_INFO(dev_priv)->display.has_dp_mst)
 855 #define HAS_DP20(dev_priv)      (IS_DG2(dev_priv) || DISPLAY_VER(dev_priv) >= 14)
 856
 857 #define HAS_DOUBLE_BUFFERED_M_N(dev_priv)       (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
 858
 859 #define HAS_CDCLK_CRAWL(dev_priv)        (INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
 860 #define HAS_CDCLK_SQUASH(dev_priv)       (INTEL_INFO(dev_priv)->display.has_cdclk_squash)
 861 #define HAS_DDI(dev_priv)                (INTEL_INFO(dev_priv)->display.has_ddi)
 862 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
 863 #define HAS_PSR(dev_priv)                (INTEL_INFO(dev_priv)->display.has_psr)
 864 #define HAS_PSR_HW_TRACKING(dev_priv) \
 865         (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
 866 #define HAS_PSR2_SEL_FETCH(dev_priv)     (DISPLAY_VER(dev_priv) >= 12)
 867 #define HAS_TRANSCODER(dev_priv, trans)  ((RUNTIME_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0)
 868
 869 #define HAS_RC6(dev_priv)                (INTEL_INFO(dev_priv)->has_rc6)
 870 #define HAS_RC6p(dev_priv)               (INTEL_INFO(dev_priv)->has_rc6p)
 871 #define HAS_RC6pp(dev_priv)              (false) /* HW was never validated */
 872
 873 #define HAS_RPS(dev_priv)       (INTEL_INFO(dev_priv)->has_rps)
 874
 875 #define HAS_DMC(dev_priv)       (RUNTIME_INFO(dev_priv)->has_dmc)
 876
 877 #define HAS_HECI_PXP(dev_priv) \
 878         (INTEL_INFO(dev_priv)->has_heci_pxp)
 879
 880 #define HAS_HECI_GSCFI(dev_priv) \
 881         (INTEL_INFO(dev_priv)->has_heci_gscfi)
 882
 883 #define HAS_HECI_GSC(dev_priv) (HAS_HECI_PXP(dev_priv) || HAS_HECI_GSCFI(dev_priv))
 884
 885 #define HAS_MSO(i915)           (DISPLAY_VER(i915) >= 12)
 886
 887 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
 888 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
 889
 890 #define HAS_OA_BPC_REPORTING(dev_priv) \
 891         (INTEL_INFO(dev_priv)->has_oa_bpc_reporting)
 892 #define HAS_OA_SLICE_CONTRIB_LIMITS(dev_priv) \
 893         (INTEL_INFO(dev_priv)->has_oa_slice_contrib_limits)
 894
 895 /*
 896  * Set this flag, when platform requires 64K GTT page sizes or larger for
 897  * device local memory access.
 898  */
 899 #define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)
 900
 901 #define HAS_IPC(dev_priv)                (INTEL_INFO(dev_priv)->display.has_ipc)
 902
 903 #define HAS_REGION(i915, i) (RUNTIME_INFO(i915)->memory_regions & (i))
 904 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
 905
 906 #define HAS_EXTRA_GT_LIST(dev_priv)   (INTEL_INFO(dev_priv)->extra_gt_list)
 907
 908 /*
 909  * Platform has the dedicated compression control state for each lmem surfaces
 910  * stored in lmem to support the 3D and media compression formats.
 911  */
 912 #define HAS_FLAT_CCS(dev_priv)   (INTEL_INFO(dev_priv)->has_flat_ccs)
 913
 914 #define HAS_GT_UC(dev_priv)     (INTEL_INFO(dev_priv)->has_gt_uc)
 915
 916 #define HAS_POOLED_EU(dev_priv) (RUNTIME_INFO(dev_priv)->has_pooled_eu)
 917
 918 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv)     (INTEL_INFO(dev_priv)->has_global_mocs)
 919
 920 #define HAS_PXP(dev_priv)  ((IS_ENABLED(CONFIG_DRM_I915_PXP) && \
 921                             INTEL_INFO(dev_priv)->has_pxp) && \
 922                             VDBOX_MASK(to_gt(dev_priv)))
 923
 924 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
 925
 926 #define HAS_GMD_ID(i915)        (INTEL_INFO(i915)->has_gmd_id)
 927
 928 #define HAS_LSPCON(dev_priv) (IS_DISPLAY_VER(dev_priv, 9, 10))
 929
 930 #define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
 931
 932 /* DPF == dynamic parity feature */
 933 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
 934 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
 935                                  2 : HAS_L3_DPF(dev_priv))
 936
 937 #define GT_FREQUENCY_MULTIPLIER 50
 938 #define GEN9_FREQ_SCALER 3
 939
 940 #define INTEL_NUM_PIPES(dev_priv) (hweight8(RUNTIME_INFO(dev_priv)->pipe_mask))
 941
 942 #define HAS_DISPLAY(dev_priv) (RUNTIME_INFO(dev_priv)->pipe_mask != 0)
 943
 944 #define HAS_VRR(i915)   (DISPLAY_VER(i915) >= 11)
 945
 946 #define HAS_ASYNC_FLIPS(i915)           (DISPLAY_VER(i915) >= 5)
 947
 948 /* Only valid when HAS_DISPLAY() is true */
 949 #define INTEL_DISPLAY_ENABLED(dev_priv) \
 950         (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)),         \
 951          !(dev_priv)->params.disable_display &&                         \
 952          !intel_opregion_headless_sku(dev_priv))
 953
 954 #define HAS_GUC_DEPRIVILEGE(dev_priv) \
 955         (INTEL_INFO(dev_priv)->has_guc_deprivilege)
 956
 957 #define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \
 958                                               IS_ALDERLAKE_S(dev_priv))
 959
 960 #define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
 961
 962 #define HAS_3D_PIPELINE(i915)   (INTEL_INFO(i915)->has_3d_pipeline)
 963
 964 #define HAS_ONE_EU_PER_FUSE_BIT(i915)   (INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
 965
 966 #define HAS_LMEMBAR_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \
 967                                        GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
 968
 969 /* intel_device_info.c */
 970 static inline struct intel_device_info *
 971 mkwrite_device_info(struct drm_i915_private *dev_priv)
 972 {
 973         return (struct intel_device_info *)INTEL_INFO(dev_priv);
 974 }
 975
 976 #endif