drivers/gpu/drm/i915/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 #include <uapi/drm/i915_drm.h>
  34 #include <uapi/drm/drm_fourcc.h>
  35
  36 #include <linux/io-mapping.h>
  37 #include <linux/i2c.h>
  38 #include <linux/i2c-algo-bit.h>
  39 #include <linux/backlight.h>
  40 #include <linux/hash.h>
  41 #include <linux/intel-iommu.h>
  42 #include <linux/kref.h>
  43 #include <linux/mm_types.h>
  44 #include <linux/perf_event.h>
  45 #include <linux/pm_qos.h>
  46 #include <linux/dma-resv.h>
  47 #include <linux/shmem_fs.h>
  48 #include <linux/stackdepot.h>
  49
  50 #include <drm/intel-gtt.h>
  51 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
  52 #include <drm/drm_gem.h>
  53 #include <drm/drm_auth.h>
  54 #include <drm/drm_cache.h>
  55 #include <drm/drm_util.h>
  56 #include <drm/drm_dsc.h>
  57 #include <drm/drm_atomic.h>
  58 #include <drm/drm_connector.h>
  59 #include <drm/i915_mei_hdcp_interface.h>
  60
  61 #include "i915_fixed.h"
  62 #include "i915_params.h"
  63 #include "i915_reg.h"
  64 #include "i915_utils.h"
  65
  66 #include "display/intel_bios.h"
  67 #include "display/intel_display.h"
  68 #include "display/intel_display_power.h"
  69 #include "display/intel_dpll_mgr.h"
  70 #include "display/intel_dsb.h"
  71 #include "display/intel_frontbuffer.h"
  72 #include "display/intel_gmbus.h"
  73 #include "display/intel_opregion.h"
  74
  75 #include "gem/i915_gem_context_types.h"
  76 #include "gem/i915_gem_shrinker.h"
  77 #include "gem/i915_gem_stolen.h"
  78
  79 #include "gt/intel_lrc.h"
  80 #include "gt/intel_engine.h"
  81 #include "gt/intel_gt_types.h"
  82 #include "gt/intel_workarounds.h"
  83 #include "gt/uc/intel_uc.h"
  84
  85 #include "intel_device_info.h"
  86 #include "intel_pch.h"
  87 #include "intel_runtime_pm.h"
  88 #include "intel_memory_region.h"
  89 #include "intel_uncore.h"
  90 #include "intel_wakeref.h"
  91 #include "intel_wopcm.h"
  92
  93 #include "i915_gem.h"
  94 #include "i915_gem_fence_reg.h"
  95 #include "i915_gem_gtt.h"
  96 #include "i915_gpu_error.h"
  97 #include "i915_perf_types.h"
  98 #include "i915_request.h"
  99 #include "i915_scheduler.h"
 100 #include "gt/intel_timeline.h"
 101 #include "i915_vma.h"
 102 #include "i915_irq.h"
 103
 104 #include "intel_gvt.h"
 105
 106 /* General customization:
 107  */
 108
 109 #define DRIVER_NAME             "i915"
 110 #define DRIVER_DESC             "Intel Graphics"
 111 #define DRIVER_DATE             "20191021"
 112 #define DRIVER_TIMESTAMP        1571651766
 113
 114 struct drm_i915_gem_object;
 115
 116 enum hpd_pin {
 117         HPD_NONE = 0,
 118         HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
 119         HPD_CRT,
 120         HPD_SDVO_B,
 121         HPD_SDVO_C,
 122         HPD_PORT_A,
 123         HPD_PORT_B,
 124         HPD_PORT_C,
 125         HPD_PORT_D,
 126         HPD_PORT_E,
 127         HPD_PORT_F,
 128         HPD_PORT_G,
 129         HPD_PORT_H,
 130         HPD_PORT_I,
 131
 132         HPD_NUM_PINS
 133 };
 134
 135 #define for_each_hpd_pin(__pin) \
 136         for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
 137
 138 /* Threshold == 5 for long IRQs, 50 for short */
 139 #define HPD_STORM_DEFAULT_THRESHOLD 50
 140
 141 struct i915_hotplug {
 142         struct delayed_work hotplug_work;
 143
 144         struct {
 145                 unsigned long last_jiffies;
 146                 int count;
 147                 enum {
 148                         HPD_ENABLED = 0,
 149                         HPD_DISABLED = 1,
 150                         HPD_MARK_DISABLED = 2
 151                 } state;
 152         } stats[HPD_NUM_PINS];
 153         u32 event_bits;
 154         u32 retry_bits;
 155         struct delayed_work reenable_work;
 156
 157         u32 long_port_mask;
 158         u32 short_port_mask;
 159         struct work_struct dig_port_work;
 160
 161         struct work_struct poll_init_work;
 162         bool poll_enabled;
 163
 164         unsigned int hpd_storm_threshold;
 165         /* Whether or not to count short HPD IRQs in HPD storms */
 166         u8 hpd_short_storm_enabled;
 167
 168         /*
 169          * if we get a HPD irq from DP and a HPD irq from non-DP
 170          * the non-DP HPD could block the workqueue on a mode config
 171          * mutex getting, that userspace may have taken. However
 172          * userspace is waiting on the DP workqueue to run which is
 173          * blocked behind the non-DP one.
 174          */
 175         struct workqueue_struct *dp_wq;
 176 };
 177
 178 #define I915_GEM_GPU_DOMAINS \
 179         (I915_GEM_DOMAIN_RENDER | \
 180          I915_GEM_DOMAIN_SAMPLER | \
 181          I915_GEM_DOMAIN_COMMAND | \
 182          I915_GEM_DOMAIN_INSTRUCTION | \
 183          I915_GEM_DOMAIN_VERTEX)
 184
 185 struct drm_i915_private;
 186 struct i915_mm_struct;
 187 struct i915_mmu_object;
 188
 189 struct drm_i915_file_private {
 190         struct drm_i915_private *dev_priv;
 191
 192         union {
 193                 struct drm_file *file;
 194                 struct rcu_head rcu;
 195         };
 196
 197         struct {
 198                 spinlock_t lock;
 199                 struct list_head request_list;
 200         } mm;
 201
 202         struct idr context_idr;
 203         struct mutex context_idr_lock; /* guards context_idr */
 204
 205         struct idr vm_idr;
 206         struct mutex vm_idr_lock; /* guards vm_idr */
 207
 208         unsigned int bsd_engine;
 209
 210 /*
 211  * Every context ban increments per client ban score. Also
 212  * hangs in short succession increments ban score. If ban threshold
 213  * is reached, client is considered banned and submitting more work
 214  * will fail. This is a stop gap measure to limit the badly behaving
 215  * clients access to gpu. Note that unbannable contexts never increment
 216  * the client ban score.
 217  */
 218 #define I915_CLIENT_SCORE_HANG_FAST     1
 219 #define   I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
 220 #define I915_CLIENT_SCORE_CONTEXT_BAN   3
 221 #define I915_CLIENT_SCORE_BANNED        9
 222         /** ban_score: Accumulated score of all ctx bans and fast hangs. */
 223         atomic_t ban_score;
 224         unsigned long hang_timestamp;
 225 };
 226
 227 /* Interface history:
 228  *
 229  * 1.1: Original.
 230  * 1.2: Add Power Management
 231  * 1.3: Add vblank support
 232  * 1.4: Fix cmdbuffer path, add heap destroy
 233  * 1.5: Add vblank pipe configuration
 234  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 235  *      - Support vertical blank on secondary display pipe
 236  */
 237 #define DRIVER_MAJOR            1
 238 #define DRIVER_MINOR            6
 239 #define DRIVER_PATCHLEVEL       0
 240
 241 struct intel_overlay;
 242 struct intel_overlay_error_state;
 243
 244 struct sdvo_device_mapping {
 245         u8 initialized;
 246         u8 dvo_port;
 247         u8 slave_addr;
 248         u8 dvo_wiring;
 249         u8 i2c_pin;
 250         u8 ddc_pin;
 251 };
 252
 253 struct intel_connector;
 254 struct intel_encoder;
 255 struct intel_atomic_state;
 256 struct intel_crtc_state;
 257 struct intel_initial_plane_config;
 258 struct intel_crtc;
 259 struct intel_limit;
 260 struct dpll;
 261 struct intel_cdclk_state;
 262
 263 struct drm_i915_display_funcs {
 264         void (*get_cdclk)(struct drm_i915_private *dev_priv,
 265                           struct intel_cdclk_state *cdclk_state);
 266         void (*set_cdclk)(struct drm_i915_private *dev_priv,
 267                           const struct intel_cdclk_state *cdclk_state,
 268                           enum pipe pipe);
 269         int (*get_fifo_size)(struct drm_i915_private *dev_priv,
 270                              enum i9xx_plane_id i9xx_plane);
 271         int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state);
 272         int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state);
 273         void (*initial_watermarks)(struct intel_atomic_state *state,
 274                                    struct intel_crtc_state *crtc_state);
 275         void (*atomic_update_watermarks)(struct intel_atomic_state *state,
 276                                          struct intel_crtc_state *crtc_state);
 277         void (*optimize_watermarks)(struct intel_atomic_state *state,
 278                                     struct intel_crtc_state *crtc_state);
 279         int (*compute_global_watermarks)(struct intel_atomic_state *state);
 280         void (*update_wm)(struct intel_crtc *crtc);
 281         int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
 282         u8 (*calc_voltage_level)(int cdclk);
 283         /* Returns the active state of the crtc, and if the crtc is active,
 284          * fills out the pipe-config with the hw state. */
 285         bool (*get_pipe_config)(struct intel_crtc *,
 286                                 struct intel_crtc_state *);
 287         void (*get_initial_plane_config)(struct intel_crtc *,
 288                                          struct intel_initial_plane_config *);
 289         int (*crtc_compute_clock)(struct intel_crtc *crtc,
 290                                   struct intel_crtc_state *crtc_state);
 291         void (*crtc_enable)(struct intel_crtc_state *pipe_config,
 292                             struct intel_atomic_state *old_state);
 293         void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
 294                              struct intel_atomic_state *old_state);
 295         void (*commit_modeset_enables)(struct intel_atomic_state *state);
 296         void (*commit_modeset_disables)(struct intel_atomic_state *state);
 297         void (*audio_codec_enable)(struct intel_encoder *encoder,
 298                                    const struct intel_crtc_state *crtc_state,
 299                                    const struct drm_connector_state *conn_state);
 300         void (*audio_codec_disable)(struct intel_encoder *encoder,
 301                                     const struct intel_crtc_state *old_crtc_state,
 302                                     const struct drm_connector_state *old_conn_state);
 303         void (*fdi_link_train)(struct intel_crtc *crtc,
 304                                const struct intel_crtc_state *crtc_state);
 305         void (*init_clock_gating)(struct drm_i915_private *dev_priv);
 306         void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
 307         /* clock updates for mode set */
 308         /* cursor updates */
 309         /* render clock increase/decrease */
 310         /* display clock increase/decrease */
 311         /* pll clock increase/decrease */
 312
 313         int (*color_check)(struct intel_crtc_state *crtc_state);
 314         /*
 315          * Program double buffered color management registers during
 316          * vblank evasion. The registers should then latch during the
 317          * next vblank start, alongside any other double buffered registers
 318          * involved with the same commit.
 319          */
 320         void (*color_commit)(const struct intel_crtc_state *crtc_state);
 321         /*
 322          * Load LUTs (and other single buffered color management
 323          * registers). Will (hopefully) be called during the vblank
 324          * following the latching of any double buffered registers
 325          * involved with the same commit.
 326          */
 327         void (*load_luts)(const struct intel_crtc_state *crtc_state);
 328         void (*read_luts)(struct intel_crtc_state *crtc_state);
 329 };
 330
 331 struct intel_csr {
 332         struct work_struct work;
 333         const char *fw_path;
 334         u32 required_version;
 335         u32 max_fw_size; /* bytes */
 336         u32 *dmc_payload;
 337         u32 dmc_fw_size; /* dwords */
 338         u32 version;
 339         u32 mmio_count;
 340         i915_reg_t mmioaddr[20];
 341         u32 mmiodata[20];
 342         u32 dc_state;
 343         u32 target_dc_state;
 344         u32 allowed_dc_mask;
 345         intel_wakeref_t wakeref;
 346 };
 347
 348 enum i915_cache_level {
 349         I915_CACHE_NONE = 0,
 350         I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
 351         I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
 352                               caches, eg sampler/render caches, and the
 353                               large Last-Level-Cache. LLC is coherent with
 354                               the CPU, but L3 is only visible to the GPU. */
 355         I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
 356 };
 357
 358 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
 359
 360 struct intel_fbc {
 361         /* This is always the inner lock when overlapping with struct_mutex and
 362          * it's the outer lock when overlapping with stolen_lock. */
 363         struct mutex lock;
 364         unsigned threshold;
 365         unsigned int possible_framebuffer_bits;
 366         unsigned int busy_bits;
 367         unsigned int visible_pipes_mask;
 368         struct intel_crtc *crtc;
 369
 370         struct drm_mm_node compressed_fb;
 371         struct drm_mm_node *compressed_llb;
 372
 373         bool false_color;
 374
 375         bool enabled;
 376         bool active;
 377         bool flip_pending;
 378
 379         bool underrun_detected;
 380         struct work_struct underrun_work;
 381
 382         /*
 383          * Due to the atomic rules we can't access some structures without the
 384          * appropriate locking, so we cache information here in order to avoid
 385          * these problems.
 386          */
 387         struct intel_fbc_state_cache {
 388                 struct i915_vma *vma;
 389                 unsigned long flags;
 390
 391                 struct {
 392                         unsigned int mode_flags;
 393                         u32 hsw_bdw_pixel_rate;
 394                 } crtc;
 395
 396                 struct {
 397                         unsigned int rotation;
 398                         int src_w;
 399                         int src_h;
 400                         bool visible;
 401                         /*
 402                          * Display surface base address adjustement for
 403                          * pageflips. Note that on gen4+ this only adjusts up
 404                          * to a tile, offsets within a tile are handled in
 405                          * the hw itself (with the TILEOFF register).
 406                          */
 407                         int adjusted_x;
 408                         int adjusted_y;
 409
 410                         int y;
 411
 412                         u16 pixel_blend_mode;
 413                 } plane;
 414
 415                 struct {
 416                         const struct drm_format_info *format;
 417                         unsigned int stride;
 418                 } fb;
 419         } state_cache;
 420
 421         /*
 422          * This structure contains everything that's relevant to program the
 423          * hardware registers. When we want to figure out if we need to disable
 424          * and re-enable FBC for a new configuration we just check if there's
 425          * something different in the struct. The genx_fbc_activate functions
 426          * are supposed to read from it in order to program the registers.
 427          */
 428         struct intel_fbc_reg_params {
 429                 struct i915_vma *vma;
 430                 unsigned long flags;
 431
 432                 struct {
 433                         enum pipe pipe;
 434                         enum i9xx_plane_id i9xx_plane;
 435                         unsigned int fence_y_offset;
 436                 } crtc;
 437
 438                 struct {
 439                         const struct drm_format_info *format;
 440                         unsigned int stride;
 441                 } fb;
 442
 443                 int cfb_size;
 444                 unsigned int gen9_wa_cfb_stride;
 445         } params;
 446
 447         const char *no_fbc_reason;
 448 };
 449
 450 /*
 451  * HIGH_RR is the highest eDP panel refresh rate read from EDID
 452  * LOW_RR is the lowest eDP panel refresh rate found from EDID
 453  * parsing for same resolution.
 454  */
 455 enum drrs_refresh_rate_type {
 456         DRRS_HIGH_RR,
 457         DRRS_LOW_RR,
 458         DRRS_MAX_RR, /* RR count */
 459 };
 460
 461 enum drrs_support_type {
 462         DRRS_NOT_SUPPORTED = 0,
 463         STATIC_DRRS_SUPPORT = 1,
 464         SEAMLESS_DRRS_SUPPORT = 2
 465 };
 466
 467 struct intel_dp;
 468 struct i915_drrs {
 469         struct mutex mutex;
 470         struct delayed_work work;
 471         struct intel_dp *dp;
 472         unsigned busy_frontbuffer_bits;
 473         enum drrs_refresh_rate_type refresh_rate_type;
 474         enum drrs_support_type type;
 475 };
 476
 477 struct i915_psr {
 478         struct mutex lock;
 479
 480 #define I915_PSR_DEBUG_MODE_MASK        0x0f
 481 #define I915_PSR_DEBUG_DEFAULT          0x00
 482 #define I915_PSR_DEBUG_DISABLE          0x01
 483 #define I915_PSR_DEBUG_ENABLE           0x02
 484 #define I915_PSR_DEBUG_FORCE_PSR1       0x03
 485 #define I915_PSR_DEBUG_IRQ              0x10
 486
 487         u32 debug;
 488         bool sink_support;
 489         bool enabled;
 490         struct intel_dp *dp;
 491         enum pipe pipe;
 492         enum transcoder transcoder;
 493         bool active;
 494         struct work_struct work;
 495         unsigned busy_frontbuffer_bits;
 496         bool sink_psr2_support;
 497         bool link_standby;
 498         bool colorimetry_support;
 499         bool psr2_enabled;
 500         u8 sink_sync_latency;
 501         ktime_t last_entry_attempt;
 502         ktime_t last_exit;
 503         bool sink_not_reliable;
 504         bool irq_aux_error;
 505         u16 su_x_granularity;
 506         bool dc3co_enabled;
 507         u32 dc3co_exit_delay;
 508         struct delayed_work idle_work;
 509 };
 510
 511 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
 512 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
 513 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
 514 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
 515 #define QUIRK_INCREASE_T12_DELAY (1<<6)
 516 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
 517
 518 struct intel_fbdev;
 519 struct intel_fbc_work;
 520
 521 struct intel_gmbus {
 522         struct i2c_adapter adapter;
 523 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
 524         u32 force_bit;
 525         u32 reg0;
 526         i915_reg_t gpio_reg;
 527         struct i2c_algo_bit_data bit_algo;
 528         struct drm_i915_private *dev_priv;
 529 };
 530
 531 struct i915_suspend_saved_registers {
 532         u32 saveDSPARB;
 533         u32 saveFBC_CONTROL;
 534         u32 saveCACHE_MODE_0;
 535         u32 saveMI_ARB_STATE;
 536         u32 saveSWF0[16];
 537         u32 saveSWF1[16];
 538         u32 saveSWF3[3];
 539         u64 saveFENCE[I915_MAX_NUM_FENCES];
 540         u32 savePCH_PORT_HOTPLUG;
 541         u16 saveGCDGMBUS;
 542 };
 543
 544 struct vlv_s0ix_state;
 545
 546 struct intel_rps_ei {
 547         ktime_t ktime;
 548         u32 render_c0;
 549         u32 media_c0;
 550 };
 551
 552 struct intel_rps {
 553         struct mutex lock; /* protects enabling and the worker */
 554
 555         /*
 556          * work, interrupts_enabled and pm_iir are protected by
 557          * dev_priv->irq_lock
 558          */
 559         struct work_struct work;
 560         bool interrupts_enabled;
 561         u32 pm_iir;
 562
 563         /* PM interrupt bits that should never be masked */
 564         u32 pm_intrmsk_mbz;
 565
 566         /* Frequencies are stored in potentially platform dependent multiples.
 567          * In other words, *_freq needs to be multiplied by X to be interesting.
 568          * Soft limits are those which are used for the dynamic reclocking done
 569          * by the driver (raise frequencies under heavy loads, and lower for
 570          * lighter loads). Hard limits are those imposed by the hardware.
 571          *
 572          * A distinction is made for overclocking, which is never enabled by
 573          * default, and is considered to be above the hard limit if it's
 574          * possible at all.
 575          */
 576         u8 cur_freq;            /* Current frequency (cached, may not == HW) */
 577         u8 min_freq_softlimit;  /* Minimum frequency permitted by the driver */
 578         u8 max_freq_softlimit;  /* Max frequency permitted by the driver */
 579         u8 max_freq;            /* Maximum frequency, RP0 if not overclocking */
 580         u8 min_freq;            /* AKA RPn. Minimum frequency */
 581         u8 boost_freq;          /* Frequency to request when wait boosting */
 582         u8 idle_freq;           /* Frequency to request when we are idle */
 583         u8 efficient_freq;      /* AKA RPe. Pre-determined balanced frequency */
 584         u8 rp1_freq;            /* "less than" RP0 power/freqency */
 585         u8 rp0_freq;            /* Non-overclocked max frequency. */
 586         u16 gpll_ref_freq;      /* vlv/chv GPLL reference frequency */
 587
 588         int last_adj;
 589
 590         struct {
 591                 struct mutex mutex;
 592
 593                 enum { LOW_POWER, BETWEEN, HIGH_POWER } mode;
 594                 unsigned int interactive;
 595
 596                 u8 up_threshold; /* Current %busy required to uplock */
 597                 u8 down_threshold; /* Current %busy required to downclock */
 598         } power;
 599
 600         bool enabled;
 601         atomic_t num_waiters;
 602         atomic_t boosts;
 603
 604         /* manual wa residency calculations */
 605         struct intel_rps_ei ei;
 606 };
 607
 608 struct intel_gen6_power_mgmt {
 609         struct intel_rps rps;
 610 };
 611
 612 /* defined intel_pm.c */
 613 extern spinlock_t mchdev_lock;
 614
 615 struct intel_ilk_power_mgmt {
 616         u8 cur_delay;
 617         u8 min_delay;
 618         u8 max_delay;
 619         u8 fmax;
 620         u8 fstart;
 621
 622         u64 last_count1;
 623         unsigned long last_time1;
 624         unsigned long chipset_power;
 625         u64 last_count2;
 626         u64 last_time2;
 627         unsigned long gfx_power;
 628         u8 corr;
 629
 630         int c_m;
 631         int r_t;
 632 };
 633
 634 #define MAX_L3_SLICES 2
 635 struct intel_l3_parity {
 636         u32 *remap_info[MAX_L3_SLICES];
 637         struct work_struct error_work;
 638         int which_slice;
 639 };
 640
 641 struct i915_gem_mm {
 642         /** Memory allocator for GTT stolen memory */
 643         struct drm_mm stolen;
 644         /** Protects the usage of the GTT stolen memory allocator. This is
 645          * always the inner lock when overlapping with struct_mutex. */
 646         struct mutex stolen_lock;
 647
 648         /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
 649         spinlock_t obj_lock;
 650
 651         /**
 652          * List of objects which are purgeable.
 653          */
 654         struct list_head purge_list;
 655
 656         /**
 657          * List of objects which have allocated pages and are shrinkable.
 658          */
 659         struct list_head shrink_list;
 660
 661         /**
 662          * List of objects which are pending destruction.
 663          */
 664         struct llist_head free_list;
 665         struct work_struct free_work;
 666         /**
 667          * Count of objects pending destructions. Used to skip needlessly
 668          * waiting on an RCU barrier if no objects are waiting to be freed.
 669          */
 670         atomic_t free_count;
 671
 672         /**
 673          * Small stash of WC pages
 674          */
 675         struct pagestash wc_stash;
 676
 677         /**
 678          * tmpfs instance used for shmem backed objects
 679          */
 680         struct vfsmount *gemfs;
 681
 682         struct intel_memory_region *regions[INTEL_REGION_UNKNOWN];
 683
 684         struct notifier_block oom_notifier;
 685         struct notifier_block vmap_notifier;
 686         struct shrinker shrinker;
 687
 688         /**
 689          * Workqueue to fault in userptr pages, flushed by the execbuf
 690          * when required but otherwise left to userspace to try again
 691          * on EAGAIN.
 692          */
 693         struct workqueue_struct *userptr_wq;
 694
 695         /* shrinker accounting, also useful for userland debugging */
 696         u64 shrink_memory;
 697         u32 shrink_count;
 698 };
 699
 700 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
 701
 702 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
 703 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
 704
 705 #define I915_ENGINE_DEAD_TIMEOUT  (4 * HZ)  /* Seqno, head and subunits dead */
 706 #define I915_SEQNO_DEAD_TIMEOUT   (12 * HZ) /* Seqno dead with active head */
 707
 708 #define I915_ENGINE_WEDGED_TIMEOUT  (60 * HZ)  /* Reset but no recovery? */
 709
 710 struct ddi_vbt_port_info {
 711         /* Non-NULL if port present. */
 712         const struct child_device_config *child;
 713
 714         int max_tmds_clock;
 715
 716         /*
 717          * This is an index in the HDMI/DVI DDI buffer translation table.
 718          * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
 719          * populate this field.
 720          */
 721 #define HDMI_LEVEL_SHIFT_UNKNOWN        0xff
 722         u8 hdmi_level_shift;
 723
 724         u8 supports_dvi:1;
 725         u8 supports_hdmi:1;
 726         u8 supports_dp:1;
 727         u8 supports_edp:1;
 728         u8 supports_typec_usb:1;
 729         u8 supports_tbt:1;
 730
 731         u8 alternate_aux_channel;
 732         u8 alternate_ddc_pin;
 733
 734         u8 dp_boost_level;
 735         u8 hdmi_boost_level;
 736         int dp_max_link_rate;           /* 0 for not limited by VBT */
 737 };
 738
 739 enum psr_lines_to_wait {
 740         PSR_0_LINES_TO_WAIT = 0,
 741         PSR_1_LINE_TO_WAIT,
 742         PSR_4_LINES_TO_WAIT,
 743         PSR_8_LINES_TO_WAIT
 744 };
 745
 746 struct intel_vbt_data {
 747         struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
 748         struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
 749
 750         /* Feature bits */
 751         unsigned int int_tv_support:1;
 752         unsigned int lvds_dither:1;
 753         unsigned int int_crt_support:1;
 754         unsigned int lvds_use_ssc:1;
 755         unsigned int int_lvds_support:1;
 756         unsigned int display_clock_mode:1;
 757         unsigned int fdi_rx_polarity_inverted:1;
 758         unsigned int panel_type:4;
 759         int lvds_ssc_freq;
 760         unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
 761         enum drm_panel_orientation orientation;
 762
 763         enum drrs_support_type drrs_type;
 764
 765         struct {
 766                 int rate;
 767                 int lanes;
 768                 int preemphasis;
 769                 int vswing;
 770                 bool low_vswing;
 771                 bool initialized;
 772                 int bpp;
 773                 struct edp_power_seq pps;
 774         } edp;
 775
 776         struct {
 777                 bool enable;
 778                 bool full_link;
 779                 bool require_aux_wakeup;
 780                 int idle_frames;
 781                 enum psr_lines_to_wait lines_to_wait;
 782                 int tp1_wakeup_time_us;
 783                 int tp2_tp3_wakeup_time_us;
 784                 int psr2_tp2_tp3_wakeup_time_us;
 785         } psr;
 786
 787         struct {
 788                 u16 pwm_freq_hz;
 789                 bool present;
 790                 bool active_low_pwm;
 791                 u8 min_brightness;      /* min_brightness/255 of max */
 792                 u8 controller;          /* brightness controller number */
 793                 enum intel_backlight_type type;
 794         } backlight;
 795
 796         /* MIPI DSI */
 797         struct {
 798                 u16 panel_id;
 799                 struct mipi_config *config;
 800                 struct mipi_pps_data *pps;
 801                 u16 bl_ports;
 802                 u16 cabc_ports;
 803                 u8 seq_version;
 804                 u32 size;
 805                 u8 *data;
 806                 const u8 *sequence[MIPI_SEQ_MAX];
 807                 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
 808                 enum drm_panel_orientation orientation;
 809         } dsi;
 810
 811         int crt_ddc_pin;
 812
 813         int child_dev_num;
 814         struct child_device_config *child_dev;
 815
 816         struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
 817         struct sdvo_device_mapping sdvo_mappings[2];
 818 };
 819
 820 enum intel_ddb_partitioning {
 821         INTEL_DDB_PART_1_2,
 822         INTEL_DDB_PART_5_6, /* IVB+ */
 823 };
 824
 825 struct intel_wm_level {
 826         bool enable;
 827         u32 pri_val;
 828         u32 spr_val;
 829         u32 cur_val;
 830         u32 fbc_val;
 831 };
 832
 833 struct ilk_wm_values {
 834         u32 wm_pipe[3];
 835         u32 wm_lp[3];
 836         u32 wm_lp_spr[3];
 837         u32 wm_linetime[3];
 838         bool enable_fbc_wm;
 839         enum intel_ddb_partitioning partitioning;
 840 };
 841
 842 struct g4x_pipe_wm {
 843         u16 plane[I915_MAX_PLANES];
 844         u16 fbc;
 845 };
 846
 847 struct g4x_sr_wm {
 848         u16 plane;
 849         u16 cursor;
 850         u16 fbc;
 851 };
 852
 853 struct vlv_wm_ddl_values {
 854         u8 plane[I915_MAX_PLANES];
 855 };
 856
 857 struct vlv_wm_values {
 858         struct g4x_pipe_wm pipe[3];
 859         struct g4x_sr_wm sr;
 860         struct vlv_wm_ddl_values ddl[3];
 861         u8 level;
 862         bool cxsr;
 863 };
 864
 865 struct g4x_wm_values {
 866         struct g4x_pipe_wm pipe[2];
 867         struct g4x_sr_wm sr;
 868         struct g4x_sr_wm hpll;
 869         bool cxsr;
 870         bool hpll_en;
 871         bool fbc_en;
 872 };
 873
 874 struct skl_ddb_entry {
 875         u16 start, end; /* in number of blocks, 'end' is exclusive */
 876 };
 877
 878 static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)
 879 {
 880         return entry->end - entry->start;
 881 }
 882
 883 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
 884                                        const struct skl_ddb_entry *e2)
 885 {
 886         if (e1->start == e2->start && e1->end == e2->end)
 887                 return true;
 888
 889         return false;
 890 }
 891
 892 struct skl_ddb_allocation {
 893         u8 enabled_slices; /* GEN11 has configurable 2 slices */
 894 };
 895
 896 struct skl_ddb_values {
 897         unsigned dirty_pipes;
 898         struct skl_ddb_allocation ddb;
 899 };
 900
 901 struct skl_wm_level {
 902         u16 min_ddb_alloc;
 903         u16 plane_res_b;
 904         u8 plane_res_l;
 905         bool plane_en;
 906         bool ignore_lines;
 907 };
 908
 909 /* Stores plane specific WM parameters */
 910 struct skl_wm_params {
 911         bool x_tiled, y_tiled;
 912         bool rc_surface;
 913         bool is_planar;
 914         u32 width;
 915         u8 cpp;
 916         u32 plane_pixel_rate;
 917         u32 y_min_scanlines;
 918         u32 plane_bytes_per_line;
 919         uint_fixed_16_16_t plane_blocks_per_line;
 920         uint_fixed_16_16_t y_tile_minimum;
 921         u32 linetime_us;
 922         u32 dbuf_block_size;
 923 };
 924
 925 enum intel_pipe_crc_source {
 926         INTEL_PIPE_CRC_SOURCE_NONE,
 927         INTEL_PIPE_CRC_SOURCE_PLANE1,
 928         INTEL_PIPE_CRC_SOURCE_PLANE2,
 929         INTEL_PIPE_CRC_SOURCE_PLANE3,
 930         INTEL_PIPE_CRC_SOURCE_PLANE4,
 931         INTEL_PIPE_CRC_SOURCE_PLANE5,
 932         INTEL_PIPE_CRC_SOURCE_PLANE6,
 933         INTEL_PIPE_CRC_SOURCE_PLANE7,
 934         INTEL_PIPE_CRC_SOURCE_PIPE,
 935         /* TV/DP on pre-gen5/vlv can't use the pipe source. */
 936         INTEL_PIPE_CRC_SOURCE_TV,
 937         INTEL_PIPE_CRC_SOURCE_DP_B,
 938         INTEL_PIPE_CRC_SOURCE_DP_C,
 939         INTEL_PIPE_CRC_SOURCE_DP_D,
 940         INTEL_PIPE_CRC_SOURCE_AUTO,
 941         INTEL_PIPE_CRC_SOURCE_MAX,
 942 };
 943
 944 #define INTEL_PIPE_CRC_ENTRIES_NR       128
 945 struct intel_pipe_crc {
 946         spinlock_t lock;
 947         int skipped;
 948         enum intel_pipe_crc_source source;
 949 };
 950
 951 struct i915_frontbuffer_tracking {
 952         spinlock_t lock;
 953
 954         /*
 955          * Tracking bits for delayed frontbuffer flushing du to gpu activity or
 956          * scheduled flips.
 957          */
 958         unsigned busy_bits;
 959         unsigned flip_bits;
 960 };
 961
 962 struct i915_virtual_gpu {
 963         struct mutex lock; /* serialises sending of g2v_notify command pkts */
 964         bool active;
 965         u32 caps;
 966 };
 967
 968 /* used in computing the new watermarks state */
 969 struct intel_wm_config {
 970         unsigned int num_pipes_active;
 971         bool sprites_enabled;
 972         bool sprites_scaled;
 973 };
 974
 975 struct intel_cdclk_state {
 976         unsigned int cdclk, vco, ref, bypass;
 977         u8 voltage_level;
 978 };
 979
 980 struct drm_i915_private {
 981         struct drm_device drm;
 982
 983         const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
 984         struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
 985         struct intel_driver_caps caps;
 986
 987         /**
 988          * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
 989          * end of stolen which we can optionally use to create GEM objects
 990          * backed by stolen memory. Note that stolen_usable_size tells us
 991          * exactly how much of this we are actually allowed to use, given that
 992          * some portion of it is in fact reserved for use by hardware functions.
 993          */
 994         struct resource dsm;
 995         /**
 996          * Reseved portion of Data Stolen Memory
 997          */
 998         struct resource dsm_reserved;
 999
1000         /*
1001          * Stolen memory is segmented in hardware with different portions
1002          * offlimits to certain functions.
1003          *
1004          * The drm_mm is initialised to the total accessible range, as found
1005          * from the PCI config. On Broadwell+, this is further restricted to
1006          * avoid the first page! The upper end of stolen memory is reserved for
1007          * hardware functions and similarly removed from the accessible range.
1008          */
1009         resource_size_t stolen_usable_size;     /* Total size minus reserved ranges */
1010
1011         struct intel_uncore uncore;
1012         struct intel_uncore_mmio_debug mmio_debug;
1013
1014         struct i915_virtual_gpu vgpu;
1015
1016         struct intel_gvt *gvt;
1017
1018         struct intel_wopcm wopcm;
1019
1020         struct intel_csr csr;
1021
1022         struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1023
1024         /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1025          * controller on different i2c buses. */
1026         struct mutex gmbus_mutex;
1027
1028         /**
1029          * Base address of where the gmbus and gpio blocks are located (either
1030          * on PCH or on SoC for platforms without PCH).
1031          */
1032         u32 gpio_mmio_base;
1033
1034         u32 hsw_psr_mmio_adjust;
1035
1036         /* MMIO base address for MIPI regs */
1037         u32 mipi_mmio_base;
1038
1039         u32 pps_mmio_base;
1040
1041         wait_queue_head_t gmbus_wait_queue;
1042
1043         struct pci_dev *bridge_dev;
1044
1045         /* Context used internally to idle the GPU and setup initial state */
1046         struct i915_gem_context *kernel_context;
1047
1048         struct intel_engine_cs *engine[I915_NUM_ENGINES];
1049         struct rb_root uabi_engines;
1050
1051         struct resource mch_res;
1052
1053         /* protects the irq masks */
1054         spinlock_t irq_lock;
1055
1056         bool display_irqs_enabled;
1057
1058         /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1059         struct pm_qos_request pm_qos;
1060
1061         /* Sideband mailbox protection */
1062         struct mutex sb_lock;
1063         struct pm_qos_request sb_qos;
1064
1065         /** Cached value of IMR to avoid reads in updating the bitfield */
1066         union {
1067                 u32 irq_mask;
1068                 u32 de_irq_mask[I915_MAX_PIPES];
1069         };
1070         u32 pm_rps_events;
1071         u32 pipestat_irq_mask[I915_MAX_PIPES];
1072
1073         struct i915_hotplug hotplug;
1074         struct intel_fbc fbc;
1075         struct i915_drrs drrs;
1076         struct intel_opregion opregion;
1077         struct intel_vbt_data vbt;
1078
1079         bool preserve_bios_swizzle;
1080
1081         /* overlay */
1082         struct intel_overlay *overlay;
1083
1084         /* backlight registers and fields in struct intel_panel */
1085         struct mutex backlight_lock;
1086
1087         /* protects panel power sequencer state */
1088         struct mutex pps_mutex;
1089
1090         unsigned int fsb_freq, mem_freq, is_ddr3;
1091         unsigned int skl_preferred_vco_freq;
1092         unsigned int max_cdclk_freq;
1093
1094         unsigned int max_dotclk_freq;
1095         unsigned int rawclk_freq;
1096         unsigned int hpll_freq;
1097         unsigned int fdi_pll_freq;
1098         unsigned int czclk_freq;
1099
1100         /*
1101          * For reading holding any crtc lock is sufficient,
1102          * for writing must hold all of them.
1103          */
1104         struct {
1105                 /*
1106                  * The current logical cdclk state.
1107                  * See intel_atomic_state.cdclk.logical
1108                  */
1109                 struct intel_cdclk_state logical;
1110                 /*
1111                  * The current actual cdclk state.
1112                  * See intel_atomic_state.cdclk.actual
1113                  */
1114                 struct intel_cdclk_state actual;
1115                 /* The current hardware cdclk state */
1116                 struct intel_cdclk_state hw;
1117
1118                 /* cdclk, divider, and ratio table from bspec */
1119                 const struct intel_cdclk_vals *table;
1120
1121                 int force_min_cdclk;
1122         } cdclk;
1123
1124         /**
1125          * wq - Driver workqueue for GEM.
1126          *
1127          * NOTE: Work items scheduled here are not allowed to grab any modeset
1128          * locks, for otherwise the flushing done in the pageflip code will
1129          * result in deadlocks.
1130          */
1131         struct workqueue_struct *wq;
1132
1133         /* ordered wq for modesets */
1134         struct workqueue_struct *modeset_wq;
1135         /* unbound hipri wq for page flips/plane updates */
1136         struct workqueue_struct *flip_wq;
1137
1138         /* Display functions */
1139         struct drm_i915_display_funcs display;
1140
1141         /* PCH chipset type */
1142         enum intel_pch pch_type;
1143         unsigned short pch_id;
1144
1145         unsigned long quirks;
1146
1147         struct drm_atomic_state *modeset_restore_state;
1148         struct drm_modeset_acquire_ctx reset_ctx;
1149
1150         struct i915_ggtt ggtt; /* VM representing the global address space */
1151
1152         struct i915_gem_mm mm;
1153         DECLARE_HASHTABLE(mm_structs, 7);
1154         struct mutex mm_lock;
1155
1156         /* Kernel Modesetting */
1157
1158         struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1159         struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1160
1161 #ifdef CONFIG_DEBUG_FS
1162         struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1163 #endif
1164
1165         /* dpll and cdclk state is protected by connection_mutex */
1166         int num_shared_dpll;
1167         struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1168         const struct intel_dpll_mgr *dpll_mgr;
1169
1170         /*
1171          * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1172          * Must be global rather than per dpll, because on some platforms
1173          * plls share registers.
1174          */
1175         struct mutex dpll_lock;
1176
1177         /*
1178          * For reading active_pipes, min_cdclk, min_voltage_level holding
1179          * any crtc lock is sufficient, for writing must hold all of them.
1180          */
1181         u8 active_pipes;
1182         /* minimum acceptable cdclk for each pipe */
1183         int min_cdclk[I915_MAX_PIPES];
1184         /* minimum acceptable voltage level for each pipe */
1185         u8 min_voltage_level[I915_MAX_PIPES];
1186
1187         int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1188
1189         struct i915_wa_list gt_wa_list;
1190
1191         struct i915_frontbuffer_tracking fb_tracking;
1192
1193         struct intel_atomic_helper {
1194                 struct llist_head free_list;
1195                 struct work_struct free_work;
1196         } atomic_helper;
1197
1198         u16 orig_clock;
1199
1200         bool mchbar_need_disable;
1201
1202         struct intel_l3_parity l3_parity;
1203
1204         /*
1205          * edram size in MB.
1206          * Cannot be determined by PCIID. You must always read a register.
1207          */
1208         u32 edram_size_mb;
1209
1210         /* gen6+ GT PM state */
1211         struct intel_gen6_power_mgmt gt_pm;
1212
1213         /* ilk-only ips/rps state. Everything in here is protected by the global
1214          * mchdev_lock in intel_pm.c */
1215         struct intel_ilk_power_mgmt ips;
1216
1217         struct i915_power_domains power_domains;
1218
1219         struct i915_psr psr;
1220
1221         struct i915_gpu_error gpu_error;
1222
1223         struct drm_i915_gem_object *vlv_pctx;
1224
1225         /* list of fbdev register on this device */
1226         struct intel_fbdev *fbdev;
1227         struct work_struct fbdev_suspend_work;
1228
1229         struct drm_property *broadcast_rgb_property;
1230         struct drm_property *force_audio_property;
1231
1232         /* hda/i915 audio component */
1233         struct i915_audio_component *audio_component;
1234         bool audio_component_registered;
1235         /**
1236          * av_mutex - mutex for audio/video sync
1237          *
1238          */
1239         struct mutex av_mutex;
1240         int audio_power_refcount;
1241         u32 audio_freq_cntrl;
1242
1243         u32 fdi_rx_config;
1244
1245         /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1246         u32 chv_phy_control;
1247         /*
1248          * Shadows for CHV DPLL_MD regs to keep the state
1249          * checker somewhat working in the presence hardware
1250          * crappiness (can't read out DPLL_MD for pipes B & C).
1251          */
1252         u32 chv_dpll_md[I915_MAX_PIPES];
1253         u32 bxt_phy_grc;
1254
1255         u32 suspend_count;
1256         bool power_domains_suspended;
1257         struct i915_suspend_saved_registers regfile;
1258         struct vlv_s0ix_state *vlv_s0ix_state;
1259
1260         enum {
1261                 I915_SAGV_UNKNOWN = 0,
1262                 I915_SAGV_DISABLED,
1263                 I915_SAGV_ENABLED,
1264                 I915_SAGV_NOT_CONTROLLED
1265         } sagv_status;
1266
1267         u32 sagv_block_time_us;
1268
1269         struct {
1270                 /*
1271                  * Raw watermark latency values:
1272                  * in 0.1us units for WM0,
1273                  * in 0.5us units for WM1+.
1274                  */
1275                 /* primary */
1276                 u16 pri_latency[5];
1277                 /* sprite */
1278                 u16 spr_latency[5];
1279                 /* cursor */
1280                 u16 cur_latency[5];
1281                 /*
1282                  * Raw watermark memory latency values
1283                  * for SKL for all 8 levels
1284                  * in 1us units.
1285                  */
1286                 u16 skl_latency[8];
1287
1288                 /* current hardware state */
1289                 union {
1290                         struct ilk_wm_values hw;
1291                         struct skl_ddb_values skl_hw;
1292                         struct vlv_wm_values vlv;
1293                         struct g4x_wm_values g4x;
1294                 };
1295
1296                 u8 max_level;
1297
1298                 /*
1299                  * Should be held around atomic WM register writing; also
1300                  * protects * intel_crtc->wm.active and
1301                  * crtc_state->wm.need_postvbl_update.
1302                  */
1303                 struct mutex wm_mutex;
1304
1305                 /*
1306                  * Set during HW readout of watermarks/DDB.  Some platforms
1307                  * need to know when we're still using BIOS-provided values
1308                  * (which we don't fully trust).
1309                  */
1310                 bool distrust_bios_wm;
1311         } wm;
1312
1313         struct dram_info {
1314                 bool valid;
1315                 bool is_16gb_dimm;
1316                 u8 num_channels;
1317                 u8 ranks;
1318                 u32 bandwidth_kbps;
1319                 bool symmetric_memory;
1320                 enum intel_dram_type {
1321                         INTEL_DRAM_UNKNOWN,
1322                         INTEL_DRAM_DDR3,
1323                         INTEL_DRAM_DDR4,
1324                         INTEL_DRAM_LPDDR3,
1325                         INTEL_DRAM_LPDDR4
1326                 } type;
1327         } dram_info;
1328
1329         struct intel_bw_info {
1330                 unsigned int deratedbw[3]; /* for each QGV point */
1331                 u8 num_qgv_points;
1332                 u8 num_planes;
1333         } max_bw[6];
1334
1335         struct drm_private_obj bw_obj;
1336
1337         struct intel_runtime_pm runtime_pm;
1338
1339         struct i915_perf perf;
1340
1341         /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1342         struct intel_gt gt;
1343
1344         struct {
1345                 struct notifier_block pm_notifier;
1346
1347                 struct i915_gem_contexts {
1348                         spinlock_t lock; /* locks list */
1349                         struct list_head list;
1350
1351                         struct llist_head free_list;
1352                         struct work_struct free_work;
1353                 } contexts;
1354         } gem;
1355
1356         u8 pch_ssc_use;
1357
1358         /* For i915gm/i945gm vblank irq workaround */
1359         u8 vblank_enabled;
1360
1361         /* perform PHY state sanity checks? */
1362         bool chv_phy_assert[2];
1363
1364         bool ipc_enabled;
1365
1366         /* Used to save the pipe-to-encoder mapping for audio */
1367         struct intel_encoder *av_enc_map[I915_MAX_PIPES];
1368
1369         /* necessary resource sharing with HDMI LPE audio driver. */
1370         struct {
1371                 struct platform_device *platdev;
1372                 int     irq;
1373         } lpe_audio;
1374
1375         struct i915_pmu pmu;
1376
1377         struct i915_hdcp_comp_master *hdcp_master;
1378         bool hdcp_comp_added;
1379
1380         /* Mutex to protect the above hdcp component related values. */
1381         struct mutex hdcp_comp_mutex;
1382
1383         /*
1384          * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1385          * will be rejected. Instead look for a better place.
1386          */
1387 };
1388
1389 struct dram_dimm_info {
1390         u8 size, width, ranks;
1391 };
1392
1393 struct dram_channel_info {
1394         struct dram_dimm_info dimm_l, dimm_s;
1395         u8 ranks;
1396         bool is_16gb_dimm;
1397 };
1398
1399 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1400 {
1401         return container_of(dev, struct drm_i915_private, drm);
1402 }
1403
1404 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
1405 {
1406         return dev_get_drvdata(kdev);
1407 }
1408
1409 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
1410 {
1411         return pci_get_drvdata(pdev);
1412 }
1413
1414 /* Simple iterator over all initialised engines */
1415 #define for_each_engine(engine__, dev_priv__, id__) \
1416         for ((id__) = 0; \
1417              (id__) < I915_NUM_ENGINES; \
1418              (id__)++) \
1419                 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
1420
1421 /* Iterator over subset of engines selected by mask */
1422 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
1423         for ((tmp__) = (mask__) & INTEL_INFO((gt__)->i915)->engine_mask; \
1424              (tmp__) ? \
1425              ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \
1426              0;)
1427
1428 #define rb_to_uabi_engine(rb) \
1429         rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
1430
1431 #define for_each_uabi_engine(engine__, i915__) \
1432         for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
1433              (engine__); \
1434              (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
1435
1436 #define I915_GTT_OFFSET_NONE ((u32)-1)
1437
1438 /*
1439  * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1440  * considered to be the frontbuffer for the given plane interface-wise. This
1441  * doesn't mean that the hw necessarily already scans it out, but that any
1442  * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1443  *
1444  * We have one bit per pipe and per scanout plane type.
1445  */
1446 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
1447 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
1448         BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
1449         BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
1450         BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
1451 })
1452 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1453         BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1454 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1455         GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
1456                 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1457
1458 #define INTEL_INFO(dev_priv)    (&(dev_priv)->__info)
1459 #define RUNTIME_INFO(dev_priv)  (&(dev_priv)->__runtime)
1460 #define DRIVER_CAPS(dev_priv)   (&(dev_priv)->caps)
1461
1462 #define INTEL_GEN(dev_priv)     (INTEL_INFO(dev_priv)->gen)
1463 #define INTEL_DEVID(dev_priv)   (RUNTIME_INFO(dev_priv)->device_id)
1464
1465 #define REVID_FOREVER           0xff
1466 #define INTEL_REVID(dev_priv)   ((dev_priv)->drm.pdev->revision)
1467
1468 #define INTEL_GEN_MASK(s, e) ( \
1469         BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
1470         BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
1471         GENMASK((e) - 1, (s) - 1))
1472
1473 /* Returns true if Gen is in inclusive range [Start, End] */
1474 #define IS_GEN_RANGE(dev_priv, s, e) \
1475         (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e))))
1476
1477 #define IS_GEN(dev_priv, n) \
1478         (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \
1479          INTEL_INFO(dev_priv)->gen == (n))
1480
1481 #define HAS_DSB(dev_priv)       (INTEL_INFO(dev_priv)->display.has_dsb)
1482
1483 /*
1484  * Return true if revision is in range [since,until] inclusive.
1485  *
1486  * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
1487  */
1488 #define IS_REVID(p, since, until) \
1489         (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
1490
1491 static __always_inline unsigned int
1492 __platform_mask_index(const struct intel_runtime_info *info,
1493                       enum intel_platform p)
1494 {
1495         const unsigned int pbits =
1496                 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
1497
1498         /* Expand the platform_mask array if this fails. */
1499         BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
1500                      pbits * ARRAY_SIZE(info->platform_mask));
1501
1502         return p / pbits;
1503 }
1504
1505 static __always_inline unsigned int
1506 __platform_mask_bit(const struct intel_runtime_info *info,
1507                     enum intel_platform p)
1508 {
1509         const unsigned int pbits =
1510                 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
1511
1512         return p % pbits + INTEL_SUBPLATFORM_BITS;
1513 }
1514
1515 static inline u32
1516 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
1517 {
1518         const unsigned int pi = __platform_mask_index(info, p);
1519
1520         return info->platform_mask[pi] & INTEL_SUBPLATFORM_BITS;
1521 }
1522
1523 static __always_inline bool
1524 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
1525 {
1526         const struct intel_runtime_info *info = RUNTIME_INFO(i915);
1527         const unsigned int pi = __platform_mask_index(info, p);
1528         const unsigned int pb = __platform_mask_bit(info, p);
1529
1530         BUILD_BUG_ON(!__builtin_constant_p(p));
1531
1532         return info->platform_mask[pi] & BIT(pb);
1533 }
1534
1535 static __always_inline bool
1536 IS_SUBPLATFORM(const struct drm_i915_private *i915,
1537                enum intel_platform p, unsigned int s)
1538 {
1539         const struct intel_runtime_info *info = RUNTIME_INFO(i915);
1540         const unsigned int pi = __platform_mask_index(info, p);
1541         const unsigned int pb = __platform_mask_bit(info, p);
1542         const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
1543         const u32 mask = info->platform_mask[pi];
1544
1545         BUILD_BUG_ON(!__builtin_constant_p(p));
1546         BUILD_BUG_ON(!__builtin_constant_p(s));
1547         BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
1548
1549         /* Shift and test on the MSB position so sign flag can be used. */
1550         return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
1551 }
1552
1553 #define IS_MOBILE(dev_priv)     (INTEL_INFO(dev_priv)->is_mobile)
1554 #define IS_DGFX(dev_priv)   (INTEL_INFO(dev_priv)->is_dgfx)
1555
1556 #define IS_I830(dev_priv)       IS_PLATFORM(dev_priv, INTEL_I830)
1557 #define IS_I845G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I845G)
1558 #define IS_I85X(dev_priv)       IS_PLATFORM(dev_priv, INTEL_I85X)
1559 #define IS_I865G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I865G)
1560 #define IS_I915G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I915G)
1561 #define IS_I915GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I915GM)
1562 #define IS_I945G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I945G)
1563 #define IS_I945GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I945GM)
1564 #define IS_I965G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I965G)
1565 #define IS_I965GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I965GM)
1566 #define IS_G45(dev_priv)        IS_PLATFORM(dev_priv, INTEL_G45)
1567 #define IS_GM45(dev_priv)       IS_PLATFORM(dev_priv, INTEL_GM45)
1568 #define IS_G4X(dev_priv)        (IS_G45(dev_priv) || IS_GM45(dev_priv))
1569 #define IS_PINEVIEW(dev_priv)   IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
1570 #define IS_G33(dev_priv)        IS_PLATFORM(dev_priv, INTEL_G33)
1571 #define IS_IRONLAKE(dev_priv)   IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
1572 #define IS_IRONLAKE_M(dev_priv) \
1573         (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
1574 #define IS_IVYBRIDGE(dev_priv)  IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
1575 #define IS_IVB_GT1(dev_priv)    (IS_IVYBRIDGE(dev_priv) && \
1576                                  INTEL_INFO(dev_priv)->gt == 1)
1577 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
1578 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
1579 #define IS_HASWELL(dev_priv)    IS_PLATFORM(dev_priv, INTEL_HASWELL)
1580 #define IS_BROADWELL(dev_priv)  IS_PLATFORM(dev_priv, INTEL_BROADWELL)
1581 #define IS_SKYLAKE(dev_priv)    IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
1582 #define IS_BROXTON(dev_priv)    IS_PLATFORM(dev_priv, INTEL_BROXTON)
1583 #define IS_KABYLAKE(dev_priv)   IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
1584 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
1585 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
1586 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
1587 #define IS_ICELAKE(dev_priv)    IS_PLATFORM(dev_priv, INTEL_ICELAKE)
1588 #define IS_ELKHARTLAKE(dev_priv)        IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
1589 #define IS_TIGERLAKE(dev_priv)  IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
1590 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
1591                                     (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
1592 #define IS_BDW_ULT(dev_priv) \
1593         IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
1594 #define IS_BDW_ULX(dev_priv) \
1595         IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
1596 #define IS_BDW_GT3(dev_priv)    (IS_BROADWELL(dev_priv) && \
1597                                  INTEL_INFO(dev_priv)->gt == 3)
1598 #define IS_HSW_ULT(dev_priv) \
1599         IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
1600 #define IS_HSW_GT3(dev_priv)    (IS_HASWELL(dev_priv) && \
1601                                  INTEL_INFO(dev_priv)->gt == 3)
1602 #define IS_HSW_GT1(dev_priv)    (IS_HASWELL(dev_priv) && \
1603                                  INTEL_INFO(dev_priv)->gt == 1)
1604 /* ULX machines are also considered ULT. */
1605 #define IS_HSW_ULX(dev_priv) \
1606         IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
1607 #define IS_SKL_ULT(dev_priv) \
1608         IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
1609 #define IS_SKL_ULX(dev_priv) \
1610         IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
1611 #define IS_KBL_ULT(dev_priv) \
1612         IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
1613 #define IS_KBL_ULX(dev_priv) \
1614         IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
1615 #define IS_SKL_GT2(dev_priv)    (IS_SKYLAKE(dev_priv) && \
1616                                  INTEL_INFO(dev_priv)->gt == 2)
1617 #define IS_SKL_GT3(dev_priv)    (IS_SKYLAKE(dev_priv) && \
1618                                  INTEL_INFO(dev_priv)->gt == 3)
1619 #define IS_SKL_GT4(dev_priv)    (IS_SKYLAKE(dev_priv) && \
1620                                  INTEL_INFO(dev_priv)->gt == 4)
1621 #define IS_KBL_GT2(dev_priv)    (IS_KABYLAKE(dev_priv) && \
1622                                  INTEL_INFO(dev_priv)->gt == 2)
1623 #define IS_KBL_GT3(dev_priv)    (IS_KABYLAKE(dev_priv) && \
1624                                  INTEL_INFO(dev_priv)->gt == 3)
1625 #define IS_CFL_ULT(dev_priv) \
1626         IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
1627 #define IS_CFL_ULX(dev_priv) \
1628         IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
1629 #define IS_CFL_GT2(dev_priv)    (IS_COFFEELAKE(dev_priv) && \
1630                                  INTEL_INFO(dev_priv)->gt == 2)
1631 #define IS_CFL_GT3(dev_priv)    (IS_COFFEELAKE(dev_priv) && \
1632                                  INTEL_INFO(dev_priv)->gt == 3)
1633 #define IS_CNL_WITH_PORT_F(dev_priv) \
1634         IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
1635 #define IS_ICL_WITH_PORT_F(dev_priv) \
1636         IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
1637
1638 #define SKL_REVID_A0            0x0
1639 #define SKL_REVID_B0            0x1
1640 #define SKL_REVID_C0            0x2
1641 #define SKL_REVID_D0            0x3
1642 #define SKL_REVID_E0            0x4
1643 #define SKL_REVID_F0            0x5
1644 #define SKL_REVID_G0            0x6
1645 #define SKL_REVID_H0            0x7
1646
1647 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
1648
1649 #define BXT_REVID_A0            0x0
1650 #define BXT_REVID_A1            0x1
1651 #define BXT_REVID_B0            0x3
1652 #define BXT_REVID_B_LAST        0x8
1653 #define BXT_REVID_C0            0x9
1654
1655 #define IS_BXT_REVID(dev_priv, since, until) \
1656         (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
1657
1658 #define KBL_REVID_A0            0x0
1659 #define KBL_REVID_B0            0x1
1660 #define KBL_REVID_C0            0x2
1661 #define KBL_REVID_D0            0x3
1662 #define KBL_REVID_E0            0x4
1663
1664 #define IS_KBL_REVID(dev_priv, since, until) \
1665         (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
1666
1667 #define GLK_REVID_A0            0x0
1668 #define GLK_REVID_A1            0x1
1669
1670 #define IS_GLK_REVID(dev_priv, since, until) \
1671         (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
1672
1673 #define CNL_REVID_A0            0x0
1674 #define CNL_REVID_B0            0x1
1675 #define CNL_REVID_C0            0x2
1676
1677 #define IS_CNL_REVID(p, since, until) \
1678         (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
1679
1680 #define ICL_REVID_A0            0x0
1681 #define ICL_REVID_A2            0x1
1682 #define ICL_REVID_B0            0x3
1683 #define ICL_REVID_B2            0x4
1684 #define ICL_REVID_C0            0x5
1685
1686 #define IS_ICL_REVID(p, since, until) \
1687         (IS_ICELAKE(p) && IS_REVID(p, since, until))
1688
1689 #define TGL_REVID_A0            0x0
1690
1691 #define IS_TGL_REVID(p, since, until) \
1692         (IS_TIGERLAKE(p) && IS_REVID(p, since, until))
1693
1694 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
1695 #define IS_GEN9_LP(dev_priv)    (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
1696 #define IS_GEN9_BC(dev_priv)    (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
1697
1698 #define HAS_ENGINE(dev_priv, id) (INTEL_INFO(dev_priv)->engine_mask & BIT(id))
1699
1700 #define ENGINE_INSTANCES_MASK(dev_priv, first, count) ({                \
1701         unsigned int first__ = (first);                                 \
1702         unsigned int count__ = (count);                                 \
1703         (INTEL_INFO(dev_priv)->engine_mask &                            \
1704          GENMASK(first__ + count__ - 1, first__)) >> first__;           \
1705 })
1706 #define VDBOX_MASK(dev_priv) \
1707         ENGINE_INSTANCES_MASK(dev_priv, VCS0, I915_MAX_VCS)
1708 #define VEBOX_MASK(dev_priv) \
1709         ENGINE_INSTANCES_MASK(dev_priv, VECS0, I915_MAX_VECS)
1710
1711 #define HAS_LLC(dev_priv)       (INTEL_INFO(dev_priv)->has_llc)
1712 #define HAS_SNOOP(dev_priv)     (INTEL_INFO(dev_priv)->has_snoop)
1713 #define HAS_EDRAM(dev_priv)     ((dev_priv)->edram_size_mb)
1714 #define HAS_WT(dev_priv)        ((IS_HASWELL(dev_priv) || \
1715                                  IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
1716
1717 #define HWS_NEEDS_PHYSICAL(dev_priv)    (INTEL_INFO(dev_priv)->hws_needs_physical)
1718
1719 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
1720                 (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
1721 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
1722                 (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
1723 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
1724                 (INTEL_INFO(dev_priv)->has_logical_ring_preemption)
1725
1726 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
1727
1728 #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)
1729 #define HAS_PPGTT(dev_priv) \
1730         (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
1731 #define HAS_FULL_PPGTT(dev_priv) \
1732         (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
1733
1734 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
1735         GEM_BUG_ON((sizes) == 0); \
1736         ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \
1737 })
1738
1739 #define HAS_OVERLAY(dev_priv)            (INTEL_INFO(dev_priv)->display.has_overlay)
1740 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
1741                 (INTEL_INFO(dev_priv)->display.overlay_needs_physical)
1742
1743 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1744 #define HAS_BROKEN_CS_TLB(dev_priv)     (IS_I830(dev_priv) || IS_I845G(dev_priv))
1745
1746 /* WaRsDisableCoarsePowerGating:skl,cnl */
1747 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
1748         (IS_CANNONLAKE(dev_priv) || \
1749          IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
1750
1751 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
1752 #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
1753                                         IS_GEMINILAKE(dev_priv) || \
1754                                         IS_KABYLAKE(dev_priv))
1755
1756 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1757  * rows, which changed the alignment requirements and fence programming.
1758  */
1759 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \
1760                                          !(IS_I915G(dev_priv) || \
1761                                          IS_I915GM(dev_priv)))
1762 #define SUPPORTS_TV(dev_priv)           (INTEL_INFO(dev_priv)->display.supports_tv)
1763 #define I915_HAS_HOTPLUG(dev_priv)      (INTEL_INFO(dev_priv)->display.has_hotplug)
1764
1765 #define HAS_FW_BLC(dev_priv)    (INTEL_GEN(dev_priv) > 2)
1766 #define HAS_FBC(dev_priv)       (INTEL_INFO(dev_priv)->display.has_fbc)
1767 #define HAS_CUR_FBC(dev_priv)   (!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7)
1768
1769 #define HAS_IPS(dev_priv)       (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
1770
1771 #define HAS_DP_MST(dev_priv)    (INTEL_INFO(dev_priv)->display.has_dp_mst)
1772
1773 #define HAS_DDI(dev_priv)                (INTEL_INFO(dev_priv)->display.has_ddi)
1774 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg)
1775 #define HAS_PSR(dev_priv)                (INTEL_INFO(dev_priv)->display.has_psr)
1776 #define HAS_TRANSCODER_EDP(dev_priv)     (INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_EDP] != 0)
1777
1778 #define HAS_RC6(dev_priv)                (INTEL_INFO(dev_priv)->has_rc6)
1779 #define HAS_RC6p(dev_priv)               (INTEL_INFO(dev_priv)->has_rc6p)
1780 #define HAS_RC6pp(dev_priv)              (false) /* HW was never validated */
1781
1782 #define HAS_RPS(dev_priv)       (INTEL_INFO(dev_priv)->has_rps)
1783
1784 #define HAS_CSR(dev_priv)       (INTEL_INFO(dev_priv)->display.has_csr)
1785
1786 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
1787 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
1788
1789 #define HAS_IPC(dev_priv)                (INTEL_INFO(dev_priv)->display.has_ipc)
1790
1791 #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
1792
1793 #define HAS_GT_UC(dev_priv)     (INTEL_INFO(dev_priv)->has_gt_uc)
1794
1795 /* Having GuC is not the same as using GuC */
1796 #define USES_GUC(dev_priv)              intel_uc_uses_guc(&(dev_priv)->gt.uc)
1797 #define USES_GUC_SUBMISSION(dev_priv)   intel_uc_uses_guc_submission(&(dev_priv)->gt.uc)
1798
1799 #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
1800
1801 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv)     (INTEL_INFO(dev_priv)->has_global_mocs)
1802
1803
1804 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
1805
1806 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
1807
1808 /* DPF == dynamic parity feature */
1809 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
1810 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
1811                                  2 : HAS_L3_DPF(dev_priv))
1812
1813 #define GT_FREQUENCY_MULTIPLIER 50
1814 #define GEN9_FREQ_SCALER 3
1815
1816 #define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask))
1817
1818 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0)
1819
1820 /* Only valid when HAS_DISPLAY() is true */
1821 #define INTEL_DISPLAY_ENABLED(dev_priv) (WARN_ON(!HAS_DISPLAY(dev_priv)), !i915_modparams.disable_display)
1822
1823 static inline bool intel_vtd_active(void)
1824 {
1825 #ifdef CONFIG_INTEL_IOMMU
1826         if (intel_iommu_gfx_mapped)
1827                 return true;
1828 #endif
1829         return false;
1830 }
1831
1832 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
1833 {
1834         return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
1835 }
1836
1837 static inline bool
1838 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
1839 {
1840         return IS_BROXTON(dev_priv) && intel_vtd_active();
1841 }
1842
1843 /* i915_drv.c */
1844 #ifdef CONFIG_COMPAT
1845 long i915_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg);
1846 #else
1847 #define i915_compat_ioctl NULL
1848 #endif
1849 extern const struct dev_pm_ops i915_pm_ops;
1850
1851 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
1852 void i915_driver_remove(struct drm_i915_private *i915);
1853
1854 int i915_resume_switcheroo(struct drm_i915_private *i915);
1855 int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state);
1856
1857 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
1858
1859 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
1860 {
1861         return dev_priv->gvt;
1862 }
1863
1864 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
1865 {
1866         return dev_priv->vgpu.active;
1867 }
1868
1869 int i915_getparam_ioctl(struct drm_device *dev, void *data,
1870                         struct drm_file *file_priv);
1871
1872 /* i915_gem.c */
1873 int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
1874 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
1875 void i915_gem_sanitize(struct drm_i915_private *i915);
1876 void i915_gem_init_early(struct drm_i915_private *dev_priv);
1877 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
1878 int i915_gem_freeze(struct drm_i915_private *dev_priv);
1879 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
1880
1881 struct intel_memory_region *i915_gem_shmem_setup(struct drm_i915_private *i915);
1882
1883 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
1884 {
1885         /*
1886          * A single pass should suffice to release all the freed objects (along
1887          * most call paths) , but be a little more paranoid in that freeing
1888          * the objects does take a little amount of time, during which the rcu
1889          * callbacks could have added new objects into the freed list, and
1890          * armed the work again.
1891          */
1892         while (atomic_read(&i915->mm.free_count)) {
1893                 flush_work(&i915->mm.free_work);
1894                 rcu_barrier();
1895         }
1896 }
1897
1898 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
1899 {
1900         /*
1901          * Similar to objects above (see i915_gem_drain_freed-objects), in
1902          * general we have workers that are armed by RCU and then rearm
1903          * themselves in their callbacks. To be paranoid, we need to
1904          * drain the workqueue a second time after waiting for the RCU
1905          * grace period so that we catch work queued via RCU from the first
1906          * pass. As neither drain_workqueue() nor flush_workqueue() report
1907          * a result, we make an assumption that we only don't require more
1908          * than 3 passes to catch all _recursive_ RCU delayed work.
1909          *
1910          */
1911         int pass = 3;
1912         do {
1913                 flush_workqueue(i915->wq);
1914                 rcu_barrier();
1915                 i915_gem_drain_freed_objects(i915);
1916         } while (--pass);
1917         drain_workqueue(i915->wq);
1918 }
1919
1920 struct i915_vma * __must_check
1921 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
1922                          const struct i915_ggtt_view *view,
1923                          u64 size,
1924                          u64 alignment,
1925                          u64 flags);
1926
1927 int i915_gem_object_unbind(struct drm_i915_gem_object *obj,
1928                            unsigned long flags);
1929 #define I915_GEM_OBJECT_UNBIND_ACTIVE BIT(0)
1930
1931 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
1932
1933 static inline int __must_check
1934 i915_mutex_lock_interruptible(struct drm_device *dev)
1935 {
1936         return mutex_lock_interruptible(&dev->struct_mutex);
1937 }
1938
1939 int i915_gem_dumb_create(struct drm_file *file_priv,
1940                          struct drm_device *dev,
1941                          struct drm_mode_create_dumb *args);
1942 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1943                       u32 handle, u64 *offset);
1944 int i915_gem_mmap_gtt_version(void);
1945
1946 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
1947
1948 static inline u32 i915_reset_count(struct i915_gpu_error *error)
1949 {
1950         return atomic_read(&error->reset_count);
1951 }
1952
1953 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
1954                                           struct intel_engine_cs *engine)
1955 {
1956         return atomic_read(&error->reset_engine_count[engine->uabi_class]);
1957 }
1958
1959 void i915_gem_init_mmio(struct drm_i915_private *i915);
1960 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
1961 void i915_gem_driver_register(struct drm_i915_private *i915);
1962 void i915_gem_driver_unregister(struct drm_i915_private *i915);
1963 void i915_gem_driver_remove(struct drm_i915_private *dev_priv);
1964 void i915_gem_driver_release(struct drm_i915_private *dev_priv);
1965 void i915_gem_suspend(struct drm_i915_private *dev_priv);
1966 void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
1967 void i915_gem_resume(struct drm_i915_private *dev_priv);
1968 vm_fault_t i915_gem_fault(struct vm_fault *vmf);
1969
1970 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
1971 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1972
1973 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1974                                     enum i915_cache_level cache_level);
1975
1976 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1977                                 struct dma_buf *dma_buf);
1978
1979 struct dma_buf *i915_gem_prime_export(struct drm_gem_object *gem_obj, int flags);
1980
1981 static inline struct i915_gem_context *
1982 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
1983 {
1984         return idr_find(&file_priv->context_idr, id);
1985 }
1986
1987 static inline struct i915_gem_context *
1988 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
1989 {
1990         struct i915_gem_context *ctx;
1991
1992         rcu_read_lock();
1993         ctx = __i915_gem_context_lookup_rcu(file_priv, id);
1994         if (ctx && !kref_get_unless_zero(&ctx->ref))
1995                 ctx = NULL;
1996         rcu_read_unlock();
1997
1998         return ctx;
1999 }
2000
2001 /* i915_gem_evict.c */
2002 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
2003                                           u64 min_size, u64 alignment,
2004                                           unsigned long color,
2005                                           u64 start, u64 end,
2006                                           unsigned flags);
2007 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
2008                                          struct drm_mm_node *node,
2009                                          unsigned int flags);
2010 int i915_gem_evict_vm(struct i915_address_space *vm);
2011
2012 void i915_gem_cleanup_memory_regions(struct drm_i915_private *i915);
2013 int i915_gem_init_memory_regions(struct drm_i915_private *i915);
2014
2015 /* i915_gem_internal.c */
2016 struct drm_i915_gem_object *
2017 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
2018                                 phys_addr_t size);
2019
2020 /* i915_gem_tiling.c */
2021 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
2022 {
2023         struct drm_i915_private *i915 = to_i915(obj->base.dev);
2024
2025         return i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2026                 i915_gem_object_is_tiled(obj);
2027 }
2028
2029 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
2030                         unsigned int tiling, unsigned int stride);
2031 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
2032                              unsigned int tiling, unsigned int stride);
2033
2034 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
2035
2036 /* i915_cmd_parser.c */
2037 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
2038 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
2039 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
2040 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
2041                             struct drm_i915_gem_object *batch_obj,
2042                             struct drm_i915_gem_object *shadow_batch_obj,
2043                             u32 batch_start_offset,
2044                             u32 batch_len,
2045                             bool is_master);
2046
2047 /* intel_device_info.c */
2048 static inline struct intel_device_info *
2049 mkwrite_device_info(struct drm_i915_private *dev_priv)
2050 {
2051         return (struct intel_device_info *)INTEL_INFO(dev_priv);
2052 }
2053
2054 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
2055                         struct drm_file *file);
2056
2057 #define __I915_REG_OP(op__, dev_priv__, ...) \
2058         intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
2059
2060 #define I915_READ(reg__)         __I915_REG_OP(read, dev_priv, (reg__))
2061 #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
2062
2063 #define POSTING_READ(reg__)     __I915_REG_OP(posting_read, dev_priv, (reg__))
2064
2065 /* These are untraced mmio-accessors that are only valid to be used inside
2066  * critical sections, such as inside IRQ handlers, where forcewake is explicitly
2067  * controlled.
2068  *
2069  * Think twice, and think again, before using these.
2070  *
2071  * As an example, these accessors can possibly be used between:
2072  *
2073  * spin_lock_irq(&dev_priv->uncore.lock);
2074  * intel_uncore_forcewake_get__locked();
2075  *
2076  * and
2077  *
2078  * intel_uncore_forcewake_put__locked();
2079  * spin_unlock_irq(&dev_priv->uncore.lock);
2080  *
2081  *
2082  * Note: some registers may not need forcewake held, so
2083  * intel_uncore_forcewake_{get,put} can be omitted, see
2084  * intel_uncore_forcewake_for_reg().
2085  *
2086  * Certain architectures will die if the same cacheline is concurrently accessed
2087  * by different clients (e.g. on Ivybridge). Access to registers should
2088  * therefore generally be serialised, by either the dev_priv->uncore.lock or
2089  * a more localised lock guarding all access to that bank of registers.
2090  */
2091 #define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__))
2092 #define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__))
2093
2094 /* register wait wrappers for display regs */
2095 #define intel_de_wait_for_register(dev_priv_, reg_, mask_, value_, timeout_) \
2096         intel_wait_for_register(&(dev_priv_)->uncore, \
2097                                 (reg_), (mask_), (value_), (timeout_))
2098
2099 #define intel_de_wait_for_set(dev_priv_, reg_, mask_, timeout_) ({      \
2100         u32 mask__ = (mask_);                                           \
2101         intel_de_wait_for_register((dev_priv_), (reg_),                 \
2102                                    mask__, mask__, (timeout_)); \
2103 })
2104
2105 #define intel_de_wait_for_clear(dev_priv_, reg_, mask_, timeout_) \
2106         intel_de_wait_for_register((dev_priv_), (reg_), (mask_), 0, (timeout_))
2107
2108 /* i915_mm.c */
2109 int remap_io_mapping(struct vm_area_struct *vma,
2110                      unsigned long addr, unsigned long pfn, unsigned long size,
2111                      struct io_mapping *iomap);
2112
2113 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
2114 {
2115         if (INTEL_GEN(i915) >= 10)
2116                 return CNL_HWS_CSB_WRITE_INDEX;
2117         else
2118                 return I915_HWS_CSB_WRITE_INDEX;
2119 }
2120
2121 static inline enum i915_map_type
2122 i915_coherent_map_type(struct drm_i915_private *i915)
2123 {
2124         return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
2125 }
2126
2127 #endif