drivers/gpu/drm/i915/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 #include <uapi/drm/i915_drm.h>
  34 #include <uapi/drm/drm_fourcc.h>
  35
  36 #include <asm/hypervisor.h>
  37
  38 #include <linux/io-mapping.h>
  39 #include <linux/i2c.h>
  40 #include <linux/i2c-algo-bit.h>
  41 #include <linux/backlight.h>
  42 #include <linux/hash.h>
  43 #include <linux/intel-iommu.h>
  44 #include <linux/kref.h>
  45 #include <linux/mm_types.h>
  46 #include <linux/perf_event.h>
  47 #include <linux/pm_qos.h>
  48 #include <linux/dma-resv.h>
  49 #include <linux/shmem_fs.h>
  50 #include <linux/stackdepot.h>
  51 #include <linux/xarray.h>
  52
  53 #include <drm/intel-gtt.h>
  54 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
  55 #include <drm/drm_gem.h>
  56 #include <drm/drm_auth.h>
  57 #include <drm/drm_cache.h>
  58 #include <drm/drm_util.h>
  59 #include <drm/drm_dsc.h>
  60 #include <drm/drm_atomic.h>
  61 #include <drm/drm_connector.h>
  62 #include <drm/i915_mei_hdcp_interface.h>
  63
  64 #include "i915_params.h"
  65 #include "i915_reg.h"
  66 #include "i915_utils.h"
  67
  68 #include "display/intel_bios.h"
  69 #include "display/intel_display.h"
  70 #include "display/intel_display_power.h"
  71 #include "display/intel_dpll_mgr.h"
  72 #include "display/intel_dsb.h"
  73 #include "display/intel_frontbuffer.h"
  74 #include "display/intel_global_state.h"
  75 #include "display/intel_gmbus.h"
  76 #include "display/intel_opregion.h"
  77
  78 #include "gem/i915_gem_context_types.h"
  79 #include "gem/i915_gem_shrinker.h"
  80 #include "gem/i915_gem_stolen.h"
  81
  82 #include "gt/intel_engine.h"
  83 #include "gt/intel_gt_types.h"
  84 #include "gt/intel_region_lmem.h"
  85 #include "gt/intel_workarounds.h"
  86 #include "gt/uc/intel_uc.h"
  87
  88 #include "intel_device_info.h"
  89 #include "intel_memory_region.h"
  90 #include "intel_pch.h"
  91 #include "intel_runtime_pm.h"
  92 #include "intel_step.h"
  93 #include "intel_uncore.h"
  94 #include "intel_wakeref.h"
  95 #include "intel_wopcm.h"
  96
  97 #include "i915_gem.h"
  98 #include "i915_gem_gtt.h"
  99 #include "i915_gpu_error.h"
 100 #include "i915_perf_types.h"
 101 #include "i915_request.h"
 102 #include "i915_scheduler.h"
 103 #include "gt/intel_timeline.h"
 104 #include "i915_vma.h"
 105 #include "i915_irq.h"
 106
 107
 108 /* General customization:
 109  */
 110
 111 #define DRIVER_NAME             "i915"
 112 #define DRIVER_DESC             "Intel Graphics"
 113 #define DRIVER_DATE             "20201103"
 114 #define DRIVER_TIMESTAMP        1604406085
 115
 116 struct drm_i915_gem_object;
 117
 118 enum hpd_pin {
 119         HPD_NONE = 0,
 120         HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
 121         HPD_CRT,
 122         HPD_SDVO_B,
 123         HPD_SDVO_C,
 124         HPD_PORT_A,
 125         HPD_PORT_B,
 126         HPD_PORT_C,
 127         HPD_PORT_D,
 128         HPD_PORT_E,
 129         HPD_PORT_TC1,
 130         HPD_PORT_TC2,
 131         HPD_PORT_TC3,
 132         HPD_PORT_TC4,
 133         HPD_PORT_TC5,
 134         HPD_PORT_TC6,
 135
 136         HPD_NUM_PINS
 137 };
 138
 139 #define for_each_hpd_pin(__pin) \
 140         for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
 141
 142 /* Threshold == 5 for long IRQs, 50 for short */
 143 #define HPD_STORM_DEFAULT_THRESHOLD 50
 144
 145 struct i915_hotplug {
 146         struct delayed_work hotplug_work;
 147
 148         const u32 *hpd, *pch_hpd;
 149
 150         struct {
 151                 unsigned long last_jiffies;
 152                 int count;
 153                 enum {
 154                         HPD_ENABLED = 0,
 155                         HPD_DISABLED = 1,
 156                         HPD_MARK_DISABLED = 2
 157                 } state;
 158         } stats[HPD_NUM_PINS];
 159         u32 event_bits;
 160         u32 retry_bits;
 161         struct delayed_work reenable_work;
 162
 163         u32 long_port_mask;
 164         u32 short_port_mask;
 165         struct work_struct dig_port_work;
 166
 167         struct work_struct poll_init_work;
 168         bool poll_enabled;
 169
 170         unsigned int hpd_storm_threshold;
 171         /* Whether or not to count short HPD IRQs in HPD storms */
 172         u8 hpd_short_storm_enabled;
 173
 174         /*
 175          * if we get a HPD irq from DP and a HPD irq from non-DP
 176          * the non-DP HPD could block the workqueue on a mode config
 177          * mutex getting, that userspace may have taken. However
 178          * userspace is waiting on the DP workqueue to run which is
 179          * blocked behind the non-DP one.
 180          */
 181         struct workqueue_struct *dp_wq;
 182 };
 183
 184 #define I915_GEM_GPU_DOMAINS \
 185         (I915_GEM_DOMAIN_RENDER | \
 186          I915_GEM_DOMAIN_SAMPLER | \
 187          I915_GEM_DOMAIN_COMMAND | \
 188          I915_GEM_DOMAIN_INSTRUCTION | \
 189          I915_GEM_DOMAIN_VERTEX)
 190
 191 struct drm_i915_private;
 192 struct i915_mm_struct;
 193 struct i915_mmu_object;
 194
 195 struct drm_i915_file_private {
 196         struct drm_i915_private *dev_priv;
 197
 198         union {
 199                 struct drm_file *file;
 200                 struct rcu_head rcu;
 201         };
 202
 203         struct xarray context_xa;
 204         struct xarray vm_xa;
 205
 206         unsigned int bsd_engine;
 207
 208 /*
 209  * Every context ban increments per client ban score. Also
 210  * hangs in short succession increments ban score. If ban threshold
 211  * is reached, client is considered banned and submitting more work
 212  * will fail. This is a stop gap measure to limit the badly behaving
 213  * clients access to gpu. Note that unbannable contexts never increment
 214  * the client ban score.
 215  */
 216 #define I915_CLIENT_SCORE_HANG_FAST     1
 217 #define   I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
 218 #define I915_CLIENT_SCORE_CONTEXT_BAN   3
 219 #define I915_CLIENT_SCORE_BANNED        9
 220         /** ban_score: Accumulated score of all ctx bans and fast hangs. */
 221         atomic_t ban_score;
 222         unsigned long hang_timestamp;
 223 };
 224
 225 /* Interface history:
 226  *
 227  * 1.1: Original.
 228  * 1.2: Add Power Management
 229  * 1.3: Add vblank support
 230  * 1.4: Fix cmdbuffer path, add heap destroy
 231  * 1.5: Add vblank pipe configuration
 232  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 233  *      - Support vertical blank on secondary display pipe
 234  */
 235 #define DRIVER_MAJOR            1
 236 #define DRIVER_MINOR            6
 237 #define DRIVER_PATCHLEVEL       0
 238
 239 struct intel_overlay;
 240 struct intel_overlay_error_state;
 241
 242 struct sdvo_device_mapping {
 243         u8 initialized;
 244         u8 dvo_port;
 245         u8 slave_addr;
 246         u8 dvo_wiring;
 247         u8 i2c_pin;
 248         u8 ddc_pin;
 249 };
 250
 251 struct intel_connector;
 252 struct intel_encoder;
 253 struct intel_atomic_state;
 254 struct intel_cdclk_config;
 255 struct intel_cdclk_state;
 256 struct intel_cdclk_vals;
 257 struct intel_initial_plane_config;
 258 struct intel_crtc;
 259 struct intel_limit;
 260 struct dpll;
 261
 262 struct drm_i915_display_funcs {
 263         void (*get_cdclk)(struct drm_i915_private *dev_priv,
 264                           struct intel_cdclk_config *cdclk_config);
 265         void (*set_cdclk)(struct drm_i915_private *dev_priv,
 266                           const struct intel_cdclk_config *cdclk_config,
 267                           enum pipe pipe);
 268         int (*bw_calc_min_cdclk)(struct intel_atomic_state *state);
 269         int (*get_fifo_size)(struct drm_i915_private *dev_priv,
 270                              enum i9xx_plane_id i9xx_plane);
 271         int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state);
 272         int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state);
 273         void (*initial_watermarks)(struct intel_atomic_state *state,
 274                                    struct intel_crtc *crtc);
 275         void (*atomic_update_watermarks)(struct intel_atomic_state *state,
 276                                          struct intel_crtc *crtc);
 277         void (*optimize_watermarks)(struct intel_atomic_state *state,
 278                                     struct intel_crtc *crtc);
 279         int (*compute_global_watermarks)(struct intel_atomic_state *state);
 280         void (*update_wm)(struct intel_crtc *crtc);
 281         int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
 282         u8 (*calc_voltage_level)(int cdclk);
 283         /* Returns the active state of the crtc, and if the crtc is active,
 284          * fills out the pipe-config with the hw state. */
 285         bool (*get_pipe_config)(struct intel_crtc *,
 286                                 struct intel_crtc_state *);
 287         void (*get_initial_plane_config)(struct intel_crtc *,
 288                                          struct intel_initial_plane_config *);
 289         int (*crtc_compute_clock)(struct intel_crtc *crtc,
 290                                   struct intel_crtc_state *crtc_state);
 291         void (*crtc_enable)(struct intel_atomic_state *state,
 292                             struct intel_crtc *crtc);
 293         void (*crtc_disable)(struct intel_atomic_state *state,
 294                              struct intel_crtc *crtc);
 295         void (*commit_modeset_enables)(struct intel_atomic_state *state);
 296         void (*commit_modeset_disables)(struct intel_atomic_state *state);
 297         void (*audio_codec_enable)(struct intel_encoder *encoder,
 298                                    const struct intel_crtc_state *crtc_state,
 299                                    const struct drm_connector_state *conn_state);
 300         void (*audio_codec_disable)(struct intel_encoder *encoder,
 301                                     const struct intel_crtc_state *old_crtc_state,
 302                                     const struct drm_connector_state *old_conn_state);
 303         void (*fdi_link_train)(struct intel_crtc *crtc,
 304                                const struct intel_crtc_state *crtc_state);
 305         void (*init_clock_gating)(struct drm_i915_private *dev_priv);
 306         void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
 307         /* clock updates for mode set */
 308         /* cursor updates */
 309         /* render clock increase/decrease */
 310         /* display clock increase/decrease */
 311         /* pll clock increase/decrease */
 312
 313         int (*color_check)(struct intel_crtc_state *crtc_state);
 314         /*
 315          * Program double buffered color management registers during
 316          * vblank evasion. The registers should then latch during the
 317          * next vblank start, alongside any other double buffered registers
 318          * involved with the same commit.
 319          */
 320         void (*color_commit)(const struct intel_crtc_state *crtc_state);
 321         /*
 322          * Load LUTs (and other single buffered color management
 323          * registers). Will (hopefully) be called during the vblank
 324          * following the latching of any double buffered registers
 325          * involved with the same commit.
 326          */
 327         void (*load_luts)(const struct intel_crtc_state *crtc_state);
 328         void (*read_luts)(struct intel_crtc_state *crtc_state);
 329 };
 330
 331 struct intel_csr {
 332         struct work_struct work;
 333         const char *fw_path;
 334         u32 required_version;
 335         u32 max_fw_size; /* bytes */
 336         u32 *dmc_payload;
 337         u32 dmc_fw_size; /* dwords */
 338         u32 version;
 339         u32 mmio_count;
 340         i915_reg_t mmioaddr[20];
 341         u32 mmiodata[20];
 342         u32 dc_state;
 343         u32 target_dc_state;
 344         u32 allowed_dc_mask;
 345         intel_wakeref_t wakeref;
 346 };
 347
 348 enum i915_cache_level {
 349         I915_CACHE_NONE = 0,
 350         I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
 351         I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
 352                               caches, eg sampler/render caches, and the
 353                               large Last-Level-Cache. LLC is coherent with
 354                               the CPU, but L3 is only visible to the GPU. */
 355         I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
 356 };
 357
 358 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
 359
 360 struct intel_fbc {
 361         /* This is always the inner lock when overlapping with struct_mutex and
 362          * it's the outer lock when overlapping with stolen_lock. */
 363         struct mutex lock;
 364         unsigned threshold;
 365         unsigned int possible_framebuffer_bits;
 366         unsigned int busy_bits;
 367         struct intel_crtc *crtc;
 368
 369         struct drm_mm_node compressed_fb;
 370         struct drm_mm_node *compressed_llb;
 371
 372         bool false_color;
 373
 374         bool active;
 375         bool activated;
 376         bool flip_pending;
 377
 378         bool underrun_detected;
 379         struct work_struct underrun_work;
 380
 381         /*
 382          * Due to the atomic rules we can't access some structures without the
 383          * appropriate locking, so we cache information here in order to avoid
 384          * these problems.
 385          */
 386         struct intel_fbc_state_cache {
 387                 struct {
 388                         unsigned int mode_flags;
 389                         u32 hsw_bdw_pixel_rate;
 390                 } crtc;
 391
 392                 struct {
 393                         unsigned int rotation;
 394                         int src_w;
 395                         int src_h;
 396                         bool visible;
 397                         /*
 398                          * Display surface base address adjustement for
 399                          * pageflips. Note that on gen4+ this only adjusts up
 400                          * to a tile, offsets within a tile are handled in
 401                          * the hw itself (with the TILEOFF register).
 402                          */
 403                         int adjusted_x;
 404                         int adjusted_y;
 405
 406                         u16 pixel_blend_mode;
 407                 } plane;
 408
 409                 struct {
 410                         const struct drm_format_info *format;
 411                         unsigned int stride;
 412                         u64 modifier;
 413                 } fb;
 414
 415                 unsigned int fence_y_offset;
 416                 u16 gen9_wa_cfb_stride;
 417                 u16 interval;
 418                 s8 fence_id;
 419                 bool psr2_active;
 420         } state_cache;
 421
 422         /*
 423          * This structure contains everything that's relevant to program the
 424          * hardware registers. When we want to figure out if we need to disable
 425          * and re-enable FBC for a new configuration we just check if there's
 426          * something different in the struct. The genx_fbc_activate functions
 427          * are supposed to read from it in order to program the registers.
 428          */
 429         struct intel_fbc_reg_params {
 430                 struct {
 431                         enum pipe pipe;
 432                         enum i9xx_plane_id i9xx_plane;
 433                 } crtc;
 434
 435                 struct {
 436                         const struct drm_format_info *format;
 437                         unsigned int stride;
 438                         u64 modifier;
 439                 } fb;
 440
 441                 int cfb_size;
 442                 unsigned int fence_y_offset;
 443                 u16 gen9_wa_cfb_stride;
 444                 u16 interval;
 445                 s8 fence_id;
 446                 bool plane_visible;
 447         } params;
 448
 449         const char *no_fbc_reason;
 450 };
 451
 452 /*
 453  * HIGH_RR is the highest eDP panel refresh rate read from EDID
 454  * LOW_RR is the lowest eDP panel refresh rate found from EDID
 455  * parsing for same resolution.
 456  */
 457 enum drrs_refresh_rate_type {
 458         DRRS_HIGH_RR,
 459         DRRS_LOW_RR,
 460         DRRS_MAX_RR, /* RR count */
 461 };
 462
 463 enum drrs_support_type {
 464         DRRS_NOT_SUPPORTED = 0,
 465         STATIC_DRRS_SUPPORT = 1,
 466         SEAMLESS_DRRS_SUPPORT = 2
 467 };
 468
 469 struct intel_dp;
 470 struct i915_drrs {
 471         struct mutex mutex;
 472         struct delayed_work work;
 473         struct intel_dp *dp;
 474         unsigned busy_frontbuffer_bits;
 475         enum drrs_refresh_rate_type refresh_rate_type;
 476         enum drrs_support_type type;
 477 };
 478
 479 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
 480 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
 481 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
 482 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
 483 #define QUIRK_INCREASE_T12_DELAY (1<<6)
 484 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
 485
 486 struct intel_fbdev;
 487 struct intel_fbc_work;
 488
 489 struct intel_gmbus {
 490         struct i2c_adapter adapter;
 491 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
 492         u32 force_bit;
 493         u32 reg0;
 494         i915_reg_t gpio_reg;
 495         struct i2c_algo_bit_data bit_algo;
 496         struct drm_i915_private *dev_priv;
 497 };
 498
 499 struct i915_suspend_saved_registers {
 500         u32 saveDSPARB;
 501         u32 saveSWF0[16];
 502         u32 saveSWF1[16];
 503         u32 saveSWF3[3];
 504         u16 saveGCDGMBUS;
 505 };
 506
 507 struct vlv_s0ix_state;
 508
 509 #define MAX_L3_SLICES 2
 510 struct intel_l3_parity {
 511         u32 *remap_info[MAX_L3_SLICES];
 512         struct work_struct error_work;
 513         int which_slice;
 514 };
 515
 516 struct i915_gem_mm {
 517         /** Memory allocator for GTT stolen memory */
 518         struct drm_mm stolen;
 519         /** Protects the usage of the GTT stolen memory allocator. This is
 520          * always the inner lock when overlapping with struct_mutex. */
 521         struct mutex stolen_lock;
 522
 523         /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
 524         spinlock_t obj_lock;
 525
 526         /**
 527          * List of objects which are purgeable.
 528          */
 529         struct list_head purge_list;
 530
 531         /**
 532          * List of objects which have allocated pages and are shrinkable.
 533          */
 534         struct list_head shrink_list;
 535
 536         /**
 537          * List of objects which are pending destruction.
 538          */
 539         struct llist_head free_list;
 540         struct work_struct free_work;
 541         /**
 542          * Count of objects pending destructions. Used to skip needlessly
 543          * waiting on an RCU barrier if no objects are waiting to be freed.
 544          */
 545         atomic_t free_count;
 546
 547         /**
 548          * tmpfs instance used for shmem backed objects
 549          */
 550         struct vfsmount *gemfs;
 551
 552         struct intel_memory_region *regions[INTEL_REGION_UNKNOWN];
 553
 554         struct notifier_block oom_notifier;
 555         struct notifier_block vmap_notifier;
 556         struct shrinker shrinker;
 557
 558 #ifdef CONFIG_MMU_NOTIFIER
 559         /**
 560          * notifier_lock for mmu notifiers, memory may not be allocated
 561          * while holding this lock.
 562          */
 563         spinlock_t notifier_lock;
 564 #endif
 565
 566         /* shrinker accounting, also useful for userland debugging */
 567         u64 shrink_memory;
 568         u32 shrink_count;
 569 };
 570
 571 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
 572
 573 unsigned long i915_fence_context_timeout(const struct drm_i915_private *i915,
 574                                          u64 context);
 575
 576 static inline unsigned long
 577 i915_fence_timeout(const struct drm_i915_private *i915)
 578 {
 579         return i915_fence_context_timeout(i915, U64_MAX);
 580 }
 581
 582 /* Amount of SAGV/QGV points, BSpec precisely defines this */
 583 #define I915_NUM_QGV_POINTS 8
 584
 585 struct ddi_vbt_port_info {
 586         /* Non-NULL if port present. */
 587         struct intel_bios_encoder_data *devdata;
 588
 589         int max_tmds_clock;
 590
 591         /* This is an index in the HDMI/DVI DDI buffer translation table. */
 592         u8 hdmi_level_shift;
 593         u8 hdmi_level_shift_set:1;
 594
 595         u8 alternate_aux_channel;
 596         u8 alternate_ddc_pin;
 597
 598         int dp_max_link_rate;           /* 0 for not limited by VBT */
 599 };
 600
 601 enum psr_lines_to_wait {
 602         PSR_0_LINES_TO_WAIT = 0,
 603         PSR_1_LINE_TO_WAIT,
 604         PSR_4_LINES_TO_WAIT,
 605         PSR_8_LINES_TO_WAIT
 606 };
 607
 608 struct intel_vbt_data {
 609         /* bdb version */
 610         u16 version;
 611
 612         struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
 613         struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
 614
 615         /* Feature bits */
 616         unsigned int int_tv_support:1;
 617         unsigned int lvds_dither:1;
 618         unsigned int int_crt_support:1;
 619         unsigned int lvds_use_ssc:1;
 620         unsigned int int_lvds_support:1;
 621         unsigned int display_clock_mode:1;
 622         unsigned int fdi_rx_polarity_inverted:1;
 623         unsigned int panel_type:4;
 624         int lvds_ssc_freq;
 625         unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
 626         enum drm_panel_orientation orientation;
 627
 628         enum drrs_support_type drrs_type;
 629
 630         struct {
 631                 int rate;
 632                 int lanes;
 633                 int preemphasis;
 634                 int vswing;
 635                 bool low_vswing;
 636                 bool initialized;
 637                 int bpp;
 638                 struct edp_power_seq pps;
 639                 bool hobl;
 640         } edp;
 641
 642         struct {
 643                 bool enable;
 644                 bool full_link;
 645                 bool require_aux_wakeup;
 646                 int idle_frames;
 647                 enum psr_lines_to_wait lines_to_wait;
 648                 int tp1_wakeup_time_us;
 649                 int tp2_tp3_wakeup_time_us;
 650                 int psr2_tp2_tp3_wakeup_time_us;
 651         } psr;
 652
 653         struct {
 654                 u16 pwm_freq_hz;
 655                 bool present;
 656                 bool active_low_pwm;
 657                 u8 min_brightness;      /* min_brightness/255 of max */
 658                 u8 controller;          /* brightness controller number */
 659                 enum intel_backlight_type type;
 660         } backlight;
 661
 662         /* MIPI DSI */
 663         struct {
 664                 u16 panel_id;
 665                 struct mipi_config *config;
 666                 struct mipi_pps_data *pps;
 667                 u16 bl_ports;
 668                 u16 cabc_ports;
 669                 u8 seq_version;
 670                 u32 size;
 671                 u8 *data;
 672                 const u8 *sequence[MIPI_SEQ_MAX];
 673                 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
 674                 enum drm_panel_orientation orientation;
 675         } dsi;
 676
 677         int crt_ddc_pin;
 678
 679         struct list_head display_devices;
 680
 681         struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
 682         struct sdvo_device_mapping sdvo_mappings[2];
 683 };
 684
 685 enum intel_ddb_partitioning {
 686         INTEL_DDB_PART_1_2,
 687         INTEL_DDB_PART_5_6, /* IVB+ */
 688 };
 689
 690 struct ilk_wm_values {
 691         u32 wm_pipe[3];
 692         u32 wm_lp[3];
 693         u32 wm_lp_spr[3];
 694         bool enable_fbc_wm;
 695         enum intel_ddb_partitioning partitioning;
 696 };
 697
 698 struct g4x_pipe_wm {
 699         u16 plane[I915_MAX_PLANES];
 700         u16 fbc;
 701 };
 702
 703 struct g4x_sr_wm {
 704         u16 plane;
 705         u16 cursor;
 706         u16 fbc;
 707 };
 708
 709 struct vlv_wm_ddl_values {
 710         u8 plane[I915_MAX_PLANES];
 711 };
 712
 713 struct vlv_wm_values {
 714         struct g4x_pipe_wm pipe[3];
 715         struct g4x_sr_wm sr;
 716         struct vlv_wm_ddl_values ddl[3];
 717         u8 level;
 718         bool cxsr;
 719 };
 720
 721 struct g4x_wm_values {
 722         struct g4x_pipe_wm pipe[2];
 723         struct g4x_sr_wm sr;
 724         struct g4x_sr_wm hpll;
 725         bool cxsr;
 726         bool hpll_en;
 727         bool fbc_en;
 728 };
 729
 730 struct skl_ddb_entry {
 731         u16 start, end; /* in number of blocks, 'end' is exclusive */
 732 };
 733
 734 static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)
 735 {
 736         return entry->end - entry->start;
 737 }
 738
 739 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
 740                                        const struct skl_ddb_entry *e2)
 741 {
 742         if (e1->start == e2->start && e1->end == e2->end)
 743                 return true;
 744
 745         return false;
 746 }
 747
 748 struct i915_frontbuffer_tracking {
 749         spinlock_t lock;
 750
 751         /*
 752          * Tracking bits for delayed frontbuffer flushing du to gpu activity or
 753          * scheduled flips.
 754          */
 755         unsigned busy_bits;
 756         unsigned flip_bits;
 757 };
 758
 759 struct i915_virtual_gpu {
 760         struct mutex lock; /* serialises sending of g2v_notify command pkts */
 761         bool active;
 762         u32 caps;
 763 };
 764
 765 struct intel_cdclk_config {
 766         unsigned int cdclk, vco, ref, bypass;
 767         u8 voltage_level;
 768 };
 769
 770 struct i915_selftest_stash {
 771         atomic_t counter;
 772 };
 773
 774 struct drm_i915_private {
 775         struct drm_device drm;
 776
 777         /* FIXME: Device release actions should all be moved to drmm_ */
 778         bool do_release;
 779
 780         /* i915 device parameters */
 781         struct i915_params params;
 782
 783         const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
 784         struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
 785         struct intel_driver_caps caps;
 786
 787         /**
 788          * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
 789          * end of stolen which we can optionally use to create GEM objects
 790          * backed by stolen memory. Note that stolen_usable_size tells us
 791          * exactly how much of this we are actually allowed to use, given that
 792          * some portion of it is in fact reserved for use by hardware functions.
 793          */
 794         struct resource dsm;
 795         /**
 796          * Reseved portion of Data Stolen Memory
 797          */
 798         struct resource dsm_reserved;
 799
 800         /*
 801          * Stolen memory is segmented in hardware with different portions
 802          * offlimits to certain functions.
 803          *
 804          * The drm_mm is initialised to the total accessible range, as found
 805          * from the PCI config. On Broadwell+, this is further restricted to
 806          * avoid the first page! The upper end of stolen memory is reserved for
 807          * hardware functions and similarly removed from the accessible range.
 808          */
 809         resource_size_t stolen_usable_size;     /* Total size minus reserved ranges */
 810
 811         struct intel_uncore uncore;
 812         struct intel_uncore_mmio_debug mmio_debug;
 813
 814         struct i915_virtual_gpu vgpu;
 815
 816         struct intel_gvt *gvt;
 817
 818         struct intel_wopcm wopcm;
 819
 820         struct intel_csr csr;
 821
 822         struct intel_gmbus gmbus[GMBUS_NUM_PINS];
 823
 824         /** gmbus_mutex protects against concurrent usage of the single hw gmbus
 825          * controller on different i2c buses. */
 826         struct mutex gmbus_mutex;
 827
 828         /**
 829          * Base address of where the gmbus and gpio blocks are located (either
 830          * on PCH or on SoC for platforms without PCH).
 831          */
 832         u32 gpio_mmio_base;
 833
 834         u32 hsw_psr_mmio_adjust;
 835
 836         /* MMIO base address for MIPI regs */
 837         u32 mipi_mmio_base;
 838
 839         u32 pps_mmio_base;
 840
 841         wait_queue_head_t gmbus_wait_queue;
 842
 843         struct pci_dev *bridge_dev;
 844
 845         struct rb_root uabi_engines;
 846
 847         struct resource mch_res;
 848
 849         /* protects the irq masks */
 850         spinlock_t irq_lock;
 851
 852         bool display_irqs_enabled;
 853
 854         /* Sideband mailbox protection */
 855         struct mutex sb_lock;
 856         struct pm_qos_request sb_qos;
 857
 858         /** Cached value of IMR to avoid reads in updating the bitfield */
 859         union {
 860                 u32 irq_mask;
 861                 u32 de_irq_mask[I915_MAX_PIPES];
 862         };
 863         u32 pipestat_irq_mask[I915_MAX_PIPES];
 864
 865         struct i915_hotplug hotplug;
 866         struct intel_fbc fbc;
 867         struct i915_drrs drrs;
 868         struct intel_opregion opregion;
 869         struct intel_vbt_data vbt;
 870
 871         bool preserve_bios_swizzle;
 872
 873         /* overlay */
 874         struct intel_overlay *overlay;
 875
 876         /* backlight registers and fields in struct intel_panel */
 877         struct mutex backlight_lock;
 878
 879         /* protects panel power sequencer state */
 880         struct mutex pps_mutex;
 881
 882         unsigned int fsb_freq, mem_freq, is_ddr3;
 883         unsigned int skl_preferred_vco_freq;
 884         unsigned int max_cdclk_freq;
 885
 886         unsigned int max_dotclk_freq;
 887         unsigned int hpll_freq;
 888         unsigned int fdi_pll_freq;
 889         unsigned int czclk_freq;
 890
 891         struct {
 892                 /* The current hardware cdclk configuration */
 893                 struct intel_cdclk_config hw;
 894
 895                 /* cdclk, divider, and ratio table from bspec */
 896                 const struct intel_cdclk_vals *table;
 897
 898                 struct intel_global_obj obj;
 899         } cdclk;
 900
 901         struct {
 902                 /* The current hardware dbuf configuration */
 903                 u8 enabled_slices;
 904
 905                 struct intel_global_obj obj;
 906         } dbuf;
 907
 908         /**
 909          * wq - Driver workqueue for GEM.
 910          *
 911          * NOTE: Work items scheduled here are not allowed to grab any modeset
 912          * locks, for otherwise the flushing done in the pageflip code will
 913          * result in deadlocks.
 914          */
 915         struct workqueue_struct *wq;
 916
 917         /* ordered wq for modesets */
 918         struct workqueue_struct *modeset_wq;
 919         /* unbound hipri wq for page flips/plane updates */
 920         struct workqueue_struct *flip_wq;
 921
 922         /* Display functions */
 923         struct drm_i915_display_funcs display;
 924
 925         /* PCH chipset type */
 926         enum intel_pch pch_type;
 927         unsigned short pch_id;
 928
 929         unsigned long quirks;
 930
 931         struct drm_atomic_state *modeset_restore_state;
 932         struct drm_modeset_acquire_ctx reset_ctx;
 933
 934         struct i915_ggtt ggtt; /* VM representing the global address space */
 935
 936         struct i915_gem_mm mm;
 937
 938         /* Kernel Modesetting */
 939
 940         struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
 941         struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
 942
 943         /**
 944          * dpll and cdclk state is protected by connection_mutex
 945          * dpll.lock serializes intel_{prepare,enable,disable}_shared_dpll.
 946          * Must be global rather than per dpll, because on some platforms plls
 947          * share registers.
 948          */
 949         struct {
 950                 struct mutex lock;
 951
 952                 int num_shared_dpll;
 953                 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
 954                 const struct intel_dpll_mgr *mgr;
 955
 956                 struct {
 957                         int nssc;
 958                         int ssc;
 959                 } ref_clks;
 960         } dpll;
 961
 962         struct list_head global_obj_list;
 963
 964         /*
 965          * For reading active_pipes holding any crtc lock is
 966          * sufficient, for writing must hold all of them.
 967          */
 968         u8 active_pipes;
 969
 970         struct i915_wa_list gt_wa_list;
 971
 972         struct i915_frontbuffer_tracking fb_tracking;
 973
 974         struct intel_atomic_helper {
 975                 struct llist_head free_list;
 976                 struct work_struct free_work;
 977         } atomic_helper;
 978
 979         bool mchbar_need_disable;
 980
 981         struct intel_l3_parity l3_parity;
 982
 983         /*
 984          * HTI (aka HDPORT) state read during initial hw readout.  Most
 985          * platforms don't have HTI, so this will just stay 0.  Those that do
 986          * will use this later to figure out which PLLs and PHYs are unavailable
 987          * for driver usage.
 988          */
 989         u32 hti_state;
 990
 991         /*
 992          * edram size in MB.
 993          * Cannot be determined by PCIID. You must always read a register.
 994          */
 995         u32 edram_size_mb;
 996
 997         struct i915_power_domains power_domains;
 998
 999         struct i915_gpu_error gpu_error;
1000
1001         struct drm_i915_gem_object *vlv_pctx;
1002
1003         /* list of fbdev register on this device */
1004         struct intel_fbdev *fbdev;
1005         struct work_struct fbdev_suspend_work;
1006
1007         struct drm_property *broadcast_rgb_property;
1008         struct drm_property *force_audio_property;
1009
1010         /* hda/i915 audio component */
1011         struct i915_audio_component *audio_component;
1012         bool audio_component_registered;
1013         /**
1014          * av_mutex - mutex for audio/video sync
1015          *
1016          */
1017         struct mutex av_mutex;
1018         int audio_power_refcount;
1019         u32 audio_freq_cntrl;
1020
1021         u32 fdi_rx_config;
1022
1023         /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1024         u32 chv_phy_control;
1025         /*
1026          * Shadows for CHV DPLL_MD regs to keep the state
1027          * checker somewhat working in the presence hardware
1028          * crappiness (can't read out DPLL_MD for pipes B & C).
1029          */
1030         u32 chv_dpll_md[I915_MAX_PIPES];
1031         u32 bxt_phy_grc;
1032
1033         u32 suspend_count;
1034         bool power_domains_suspended;
1035         struct i915_suspend_saved_registers regfile;
1036         struct vlv_s0ix_state *vlv_s0ix_state;
1037
1038         enum {
1039                 I915_SAGV_UNKNOWN = 0,
1040                 I915_SAGV_DISABLED,
1041                 I915_SAGV_ENABLED,
1042                 I915_SAGV_NOT_CONTROLLED
1043         } sagv_status;
1044
1045         u32 sagv_block_time_us;
1046
1047         struct {
1048                 /*
1049                  * Raw watermark latency values:
1050                  * in 0.1us units for WM0,
1051                  * in 0.5us units for WM1+.
1052                  */
1053                 /* primary */
1054                 u16 pri_latency[5];
1055                 /* sprite */
1056                 u16 spr_latency[5];
1057                 /* cursor */
1058                 u16 cur_latency[5];
1059                 /*
1060                  * Raw watermark memory latency values
1061                  * for SKL for all 8 levels
1062                  * in 1us units.
1063                  */
1064                 u16 skl_latency[8];
1065
1066                 /* current hardware state */
1067                 union {
1068                         struct ilk_wm_values hw;
1069                         struct vlv_wm_values vlv;
1070                         struct g4x_wm_values g4x;
1071                 };
1072
1073                 u8 max_level;
1074
1075                 /*
1076                  * Should be held around atomic WM register writing; also
1077                  * protects * intel_crtc->wm.active and
1078                  * crtc_state->wm.need_postvbl_update.
1079                  */
1080                 struct mutex wm_mutex;
1081         } wm;
1082
1083         struct dram_info {
1084                 bool wm_lv_0_adjust_needed;
1085                 u8 num_channels;
1086                 bool symmetric_memory;
1087                 enum intel_dram_type {
1088                         INTEL_DRAM_UNKNOWN,
1089                         INTEL_DRAM_DDR3,
1090                         INTEL_DRAM_DDR4,
1091                         INTEL_DRAM_LPDDR3,
1092                         INTEL_DRAM_LPDDR4,
1093                         INTEL_DRAM_DDR5,
1094                         INTEL_DRAM_LPDDR5,
1095                 } type;
1096                 u8 num_qgv_points;
1097         } dram_info;
1098
1099         struct intel_bw_info {
1100                 /* for each QGV point */
1101                 unsigned int deratedbw[I915_NUM_QGV_POINTS];
1102                 u8 num_qgv_points;
1103                 u8 num_planes;
1104         } max_bw[6];
1105
1106         struct intel_global_obj bw_obj;
1107
1108         struct intel_runtime_pm runtime_pm;
1109
1110         struct i915_perf perf;
1111
1112         /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1113         struct intel_gt gt;
1114
1115         struct {
1116                 struct i915_gem_contexts {
1117                         spinlock_t lock; /* locks list */
1118                         struct list_head list;
1119                 } contexts;
1120
1121                 /*
1122                  * We replace the local file with a global mappings as the
1123                  * backing storage for the mmap is on the device and not
1124                  * on the struct file, and we do not want to prolong the
1125                  * lifetime of the local fd. To minimise the number of
1126                  * anonymous inodes we create, we use a global singleton to
1127                  * share the global mapping.
1128                  */
1129                 struct file *mmap_singleton;
1130         } gem;
1131
1132         u8 framestart_delay;
1133
1134         u8 pch_ssc_use;
1135
1136         /* For i915gm/i945gm vblank irq workaround */
1137         u8 vblank_enabled;
1138
1139         /* perform PHY state sanity checks? */
1140         bool chv_phy_assert[2];
1141
1142         bool ipc_enabled;
1143
1144         /* Used to save the pipe-to-encoder mapping for audio */
1145         struct intel_encoder *av_enc_map[I915_MAX_PIPES];
1146
1147         /* necessary resource sharing with HDMI LPE audio driver. */
1148         struct {
1149                 struct platform_device *platdev;
1150                 int     irq;
1151         } lpe_audio;
1152
1153         struct i915_pmu pmu;
1154
1155         struct i915_hdcp_comp_master *hdcp_master;
1156         bool hdcp_comp_added;
1157
1158         /* Mutex to protect the above hdcp component related values. */
1159         struct mutex hdcp_comp_mutex;
1160
1161         I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
1162
1163         /*
1164          * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1165          * will be rejected. Instead look for a better place.
1166          */
1167 };
1168
1169 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1170 {
1171         return container_of(dev, struct drm_i915_private, drm);
1172 }
1173
1174 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
1175 {
1176         return dev_get_drvdata(kdev);
1177 }
1178
1179 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
1180 {
1181         return pci_get_drvdata(pdev);
1182 }
1183
1184 /* Simple iterator over all initialised engines */
1185 #define for_each_engine(engine__, dev_priv__, id__) \
1186         for ((id__) = 0; \
1187              (id__) < I915_NUM_ENGINES; \
1188              (id__)++) \
1189                 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
1190
1191 /* Iterator over subset of engines selected by mask */
1192 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
1193         for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \
1194              (tmp__) ? \
1195              ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \
1196              0;)
1197
1198 #define rb_to_uabi_engine(rb) \
1199         rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
1200
1201 #define for_each_uabi_engine(engine__, i915__) \
1202         for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
1203              (engine__); \
1204              (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
1205
1206 #define for_each_uabi_class_engine(engine__, class__, i915__) \
1207         for ((engine__) = intel_engine_lookup_user((i915__), (class__), 0); \
1208              (engine__) && (engine__)->uabi_class == (class__); \
1209              (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
1210
1211 #define I915_GTT_OFFSET_NONE ((u32)-1)
1212
1213 /*
1214  * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1215  * considered to be the frontbuffer for the given plane interface-wise. This
1216  * doesn't mean that the hw necessarily already scans it out, but that any
1217  * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1218  *
1219  * We have one bit per pipe and per scanout plane type.
1220  */
1221 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
1222 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
1223         BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
1224         BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
1225         BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
1226 })
1227 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1228         BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1229 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1230         GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
1231                 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1232
1233 #define INTEL_INFO(dev_priv)    (&(dev_priv)->__info)
1234 #define RUNTIME_INFO(dev_priv)  (&(dev_priv)->__runtime)
1235 #define DRIVER_CAPS(dev_priv)   (&(dev_priv)->caps)
1236
1237 #define INTEL_DEVID(dev_priv)   (RUNTIME_INFO(dev_priv)->device_id)
1238
1239 /*
1240  * Deprecated: this will be replaced by individual IP checks:
1241  * GRAPHICS_VER(), MEDIA_VER() and DISPLAY_VER()
1242  */
1243 #define INTEL_GEN(dev_priv)             GRAPHICS_VER(dev_priv)
1244 /*
1245  * Deprecated: use IS_GRAPHICS_VER(), IS_MEDIA_VER() and IS_DISPLAY_VER() as
1246  * appropriate.
1247  */
1248 #define IS_GEN_RANGE(dev_priv, s, e)    IS_GRAPHICS_VER(dev_priv, (s), (e))
1249 /*
1250  * Deprecated: use GRAPHICS_VER(), MEDIA_VER() and DISPLAY_VER() as appropriate.
1251  */
1252 #define IS_GEN(dev_priv, n)             (GRAPHICS_VER(dev_priv) == (n))
1253
1254 #define GRAPHICS_VER(i915)              (INTEL_INFO(i915)->graphics_ver)
1255 #define IS_GRAPHICS_VER(i915, from, until) \
1256         (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
1257
1258 #define MEDIA_VER(i915)                 (INTEL_INFO(i915)->media_ver)
1259 #define IS_MEDIA_VER(i915, from, until) \
1260         (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))
1261
1262 #define DISPLAY_VER(i915)       (INTEL_INFO(i915)->display.ver)
1263 #define IS_DISPLAY_VER(i915, from, until) \
1264         (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
1265
1266 #define REVID_FOREVER           0xff
1267 #define INTEL_REVID(dev_priv)   (to_pci_dev((dev_priv)->drm.dev)->revision)
1268
1269 #define HAS_DSB(dev_priv)       (INTEL_INFO(dev_priv)->display.has_dsb)
1270
1271 /*
1272  * Return true if revision is in range [since,until] inclusive.
1273  *
1274  * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
1275  */
1276 #define IS_REVID(p, since, until) \
1277         (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
1278
1279 #define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step)
1280 #define INTEL_GT_STEP(__i915) (RUNTIME_INFO(__i915)->step.gt_step)
1281
1282 #define IS_DISPLAY_STEP(__i915, since, until) \
1283         (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \
1284          INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) <= (until))
1285
1286 #define IS_GT_STEP(__i915, since, until) \
1287         (drm_WARN_ON(&(__i915)->drm, INTEL_GT_STEP(__i915) == STEP_NONE), \
1288          INTEL_GT_STEP(__i915) >= (since) && INTEL_GT_STEP(__i915) <= (until))
1289
1290 static __always_inline unsigned int
1291 __platform_mask_index(const struct intel_runtime_info *info,
1292                       enum intel_platform p)
1293 {
1294         const unsigned int pbits =
1295                 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
1296
1297         /* Expand the platform_mask array if this fails. */
1298         BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
1299                      pbits * ARRAY_SIZE(info->platform_mask));
1300
1301         return p / pbits;
1302 }
1303
1304 static __always_inline unsigned int
1305 __platform_mask_bit(const struct intel_runtime_info *info,
1306                     enum intel_platform p)
1307 {
1308         const unsigned int pbits =
1309                 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
1310
1311         return p % pbits + INTEL_SUBPLATFORM_BITS;
1312 }
1313
1314 static inline u32
1315 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
1316 {
1317         const unsigned int pi = __platform_mask_index(info, p);
1318
1319         return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK;
1320 }
1321
1322 static __always_inline bool
1323 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
1324 {
1325         const struct intel_runtime_info *info = RUNTIME_INFO(i915);
1326         const unsigned int pi = __platform_mask_index(info, p);
1327         const unsigned int pb = __platform_mask_bit(info, p);
1328
1329         BUILD_BUG_ON(!__builtin_constant_p(p));
1330
1331         return info->platform_mask[pi] & BIT(pb);
1332 }
1333
1334 static __always_inline bool
1335 IS_SUBPLATFORM(const struct drm_i915_private *i915,
1336                enum intel_platform p, unsigned int s)
1337 {
1338         const struct intel_runtime_info *info = RUNTIME_INFO(i915);
1339         const unsigned int pi = __platform_mask_index(info, p);
1340         const unsigned int pb = __platform_mask_bit(info, p);
1341         const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
1342         const u32 mask = info->platform_mask[pi];
1343
1344         BUILD_BUG_ON(!__builtin_constant_p(p));
1345         BUILD_BUG_ON(!__builtin_constant_p(s));
1346         BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
1347
1348         /* Shift and test on the MSB position so sign flag can be used. */
1349         return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
1350 }
1351
1352 #define IS_MOBILE(dev_priv)     (INTEL_INFO(dev_priv)->is_mobile)
1353 #define IS_DGFX(dev_priv)   (INTEL_INFO(dev_priv)->is_dgfx)
1354
1355 #define IS_I830(dev_priv)       IS_PLATFORM(dev_priv, INTEL_I830)
1356 #define IS_I845G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I845G)
1357 #define IS_I85X(dev_priv)       IS_PLATFORM(dev_priv, INTEL_I85X)
1358 #define IS_I865G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I865G)
1359 #define IS_I915G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I915G)
1360 #define IS_I915GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I915GM)
1361 #define IS_I945G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I945G)
1362 #define IS_I945GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I945GM)
1363 #define IS_I965G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I965G)
1364 #define IS_I965GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I965GM)
1365 #define IS_G45(dev_priv)        IS_PLATFORM(dev_priv, INTEL_G45)
1366 #define IS_GM45(dev_priv)       IS_PLATFORM(dev_priv, INTEL_GM45)
1367 #define IS_G4X(dev_priv)        (IS_G45(dev_priv) || IS_GM45(dev_priv))
1368 #define IS_PINEVIEW(dev_priv)   IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
1369 #define IS_G33(dev_priv)        IS_PLATFORM(dev_priv, INTEL_G33)
1370 #define IS_IRONLAKE(dev_priv)   IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
1371 #define IS_IRONLAKE_M(dev_priv) \
1372         (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
1373 #define IS_SANDYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SANDYBRIDGE)
1374 #define IS_IVYBRIDGE(dev_priv)  IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
1375 #define IS_IVB_GT1(dev_priv)    (IS_IVYBRIDGE(dev_priv) && \
1376                                  INTEL_INFO(dev_priv)->gt == 1)
1377 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
1378 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
1379 #define IS_HASWELL(dev_priv)    IS_PLATFORM(dev_priv, INTEL_HASWELL)
1380 #define IS_BROADWELL(dev_priv)  IS_PLATFORM(dev_priv, INTEL_BROADWELL)
1381 #define IS_SKYLAKE(dev_priv)    IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
1382 #define IS_BROXTON(dev_priv)    IS_PLATFORM(dev_priv, INTEL_BROXTON)
1383 #define IS_KABYLAKE(dev_priv)   IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
1384 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
1385 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
1386 #define IS_COMETLAKE(dev_priv)  IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
1387 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
1388 #define IS_ICELAKE(dev_priv)    IS_PLATFORM(dev_priv, INTEL_ICELAKE)
1389 #define IS_JSL_EHL(dev_priv)    (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \
1390                                 IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
1391 #define IS_TIGERLAKE(dev_priv)  IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
1392 #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
1393 #define IS_DG1(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG1)
1394 #define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
1395 #define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P)
1396 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
1397                                     (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
1398 #define IS_BDW_ULT(dev_priv) \
1399         IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
1400 #define IS_BDW_ULX(dev_priv) \
1401         IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
1402 #define IS_BDW_GT3(dev_priv)    (IS_BROADWELL(dev_priv) && \
1403                                  INTEL_INFO(dev_priv)->gt == 3)
1404 #define IS_HSW_ULT(dev_priv) \
1405         IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
1406 #define IS_HSW_GT3(dev_priv)    (IS_HASWELL(dev_priv) && \
1407                                  INTEL_INFO(dev_priv)->gt == 3)
1408 #define IS_HSW_GT1(dev_priv)    (IS_HASWELL(dev_priv) && \
1409                                  INTEL_INFO(dev_priv)->gt == 1)
1410 /* ULX machines are also considered ULT. */
1411 #define IS_HSW_ULX(dev_priv) \
1412         IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
1413 #define IS_SKL_ULT(dev_priv) \
1414         IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
1415 #define IS_SKL_ULX(dev_priv) \
1416         IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
1417 #define IS_KBL_ULT(dev_priv) \
1418         IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
1419 #define IS_KBL_ULX(dev_priv) \
1420         IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
1421 #define IS_SKL_GT2(dev_priv)    (IS_SKYLAKE(dev_priv) && \
1422                                  INTEL_INFO(dev_priv)->gt == 2)
1423 #define IS_SKL_GT3(dev_priv)    (IS_SKYLAKE(dev_priv) && \
1424                                  INTEL_INFO(dev_priv)->gt == 3)
1425 #define IS_SKL_GT4(dev_priv)    (IS_SKYLAKE(dev_priv) && \
1426                                  INTEL_INFO(dev_priv)->gt == 4)
1427 #define IS_KBL_GT2(dev_priv)    (IS_KABYLAKE(dev_priv) && \
1428                                  INTEL_INFO(dev_priv)->gt == 2)
1429 #define IS_KBL_GT3(dev_priv)    (IS_KABYLAKE(dev_priv) && \
1430                                  INTEL_INFO(dev_priv)->gt == 3)
1431 #define IS_CFL_ULT(dev_priv) \
1432         IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
1433 #define IS_CFL_ULX(dev_priv) \
1434         IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
1435 #define IS_CFL_GT2(dev_priv)    (IS_COFFEELAKE(dev_priv) && \
1436                                  INTEL_INFO(dev_priv)->gt == 2)
1437 #define IS_CFL_GT3(dev_priv)    (IS_COFFEELAKE(dev_priv) && \
1438                                  INTEL_INFO(dev_priv)->gt == 3)
1439
1440 #define IS_CML_ULT(dev_priv) \
1441         IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
1442 #define IS_CML_ULX(dev_priv) \
1443         IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
1444 #define IS_CML_GT2(dev_priv)    (IS_COMETLAKE(dev_priv) && \
1445                                  INTEL_INFO(dev_priv)->gt == 2)
1446
1447 #define IS_CNL_WITH_PORT_F(dev_priv) \
1448         IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
1449 #define IS_ICL_WITH_PORT_F(dev_priv) \
1450         IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
1451
1452 #define IS_TGL_U(dev_priv) \
1453         IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULT)
1454
1455 #define IS_TGL_Y(dev_priv) \
1456         IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULX)
1457
1458 #define SKL_REVID_A0            0x0
1459 #define SKL_REVID_B0            0x1
1460 #define SKL_REVID_C0            0x2
1461 #define SKL_REVID_D0            0x3
1462 #define SKL_REVID_E0            0x4
1463 #define SKL_REVID_F0            0x5
1464 #define SKL_REVID_G0            0x6
1465 #define SKL_REVID_H0            0x7
1466
1467 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
1468
1469 #define BXT_REVID_A0            0x0
1470 #define BXT_REVID_A1            0x1
1471 #define BXT_REVID_B0            0x3
1472 #define BXT_REVID_B_LAST        0x8
1473 #define BXT_REVID_C0            0x9
1474
1475 #define IS_BXT_REVID(dev_priv, since, until) \
1476         (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
1477
1478 #define IS_KBL_GT_STEP(dev_priv, since, until) \
1479         (IS_KABYLAKE(dev_priv) && IS_GT_STEP(dev_priv, since, until))
1480 #define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \
1481         (IS_KABYLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, since, until))
1482
1483 #define GLK_REVID_A0            0x0
1484 #define GLK_REVID_A1            0x1
1485 #define GLK_REVID_A2            0x2
1486 #define GLK_REVID_B0            0x3
1487
1488 #define IS_GLK_REVID(dev_priv, since, until) \
1489         (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
1490
1491 #define CNL_REVID_A0            0x0
1492 #define CNL_REVID_B0            0x1
1493 #define CNL_REVID_C0            0x2
1494
1495 #define IS_CNL_REVID(p, since, until) \
1496         (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
1497
1498 #define ICL_REVID_A0            0x0
1499 #define ICL_REVID_A2            0x1
1500 #define ICL_REVID_B0            0x3
1501 #define ICL_REVID_B2            0x4
1502 #define ICL_REVID_C0            0x5
1503
1504 #define IS_ICL_REVID(p, since, until) \
1505         (IS_ICELAKE(p) && IS_REVID(p, since, until))
1506
1507 #define EHL_REVID_A0            0x0
1508 #define EHL_REVID_B0            0x1
1509
1510 #define IS_JSL_EHL_REVID(p, since, until) \
1511         (IS_JSL_EHL(p) && IS_REVID(p, since, until))
1512
1513 #define IS_TGL_DISPLAY_STEP(__i915, since, until) \
1514         (IS_TIGERLAKE(__i915) && \
1515          IS_DISPLAY_STEP(__i915, since, until))
1516
1517 #define IS_TGL_UY_GT_STEP(__i915, since, until) \
1518         ((IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \
1519          IS_GT_STEP(__i915, since, until))
1520
1521 #define IS_TGL_GT_STEP(__i915, since, until) \
1522         (IS_TIGERLAKE(__i915) && !(IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \
1523          IS_GT_STEP(__i915, since, until))
1524
1525 #define RKL_REVID_A0            0x0
1526 #define RKL_REVID_B0            0x1
1527 #define RKL_REVID_C0            0x4
1528
1529 #define IS_RKL_REVID(p, since, until) \
1530         (IS_ROCKETLAKE(p) && IS_REVID(p, since, until))
1531
1532 #define DG1_REVID_A0            0x0
1533 #define DG1_REVID_B0            0x1
1534
1535 #define IS_DG1_REVID(p, since, until) \
1536         (IS_DG1(p) && IS_REVID(p, since, until))
1537
1538 #define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
1539         (IS_ALDERLAKE_S(__i915) && \
1540          IS_DISPLAY_STEP(__i915, since, until))
1541
1542 #define IS_ADLS_GT_STEP(__i915, since, until) \
1543         (IS_ALDERLAKE_S(__i915) && \
1544          IS_GT_STEP(__i915, since, until))
1545
1546 #define IS_ADLP_DISPLAY_STEP(__i915, since, until) \
1547         (IS_ALDERLAKE_P(__i915) && \
1548          IS_DISPLAY_STEP(__i915, since, until))
1549
1550 #define IS_ADLP_GT_STEP(__i915, since, until) \
1551         (IS_ALDERLAKE_P(__i915) && \
1552          IS_GT_STEP(__i915, since, until))
1553
1554 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
1555 #define IS_GEN9_LP(dev_priv)    (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
1556 #define IS_GEN9_BC(dev_priv)    (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
1557
1558 #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
1559 #define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
1560
1561 #define ENGINE_INSTANCES_MASK(gt, first, count) ({              \
1562         unsigned int first__ = (first);                                 \
1563         unsigned int count__ = (count);                                 \
1564         ((gt)->info.engine_mask &                                               \
1565          GENMASK(first__ + count__ - 1, first__)) >> first__;           \
1566 })
1567 #define VDBOX_MASK(gt) \
1568         ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
1569 #define VEBOX_MASK(gt) \
1570         ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
1571
1572 /*
1573  * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
1574  * All later gens can run the final buffer from the ppgtt
1575  */
1576 #define CMDPARSER_USES_GGTT(dev_priv) IS_GEN(dev_priv, 7)
1577
1578 #define HAS_LLC(dev_priv)       (INTEL_INFO(dev_priv)->has_llc)
1579 #define HAS_SNOOP(dev_priv)     (INTEL_INFO(dev_priv)->has_snoop)
1580 #define HAS_EDRAM(dev_priv)     ((dev_priv)->edram_size_mb)
1581 #define HAS_SECURE_BATCHES(dev_priv) (INTEL_GEN(dev_priv) < 6)
1582 #define HAS_WT(dev_priv)        HAS_EDRAM(dev_priv)
1583
1584 #define HWS_NEEDS_PHYSICAL(dev_priv)    (INTEL_INFO(dev_priv)->hws_needs_physical)
1585
1586 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
1587                 (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
1588 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
1589                 (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
1590
1591 #define HAS_MASTER_UNIT_IRQ(dev_priv) (INTEL_INFO(dev_priv)->has_master_unit_irq)
1592
1593 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
1594
1595 #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)
1596 #define HAS_PPGTT(dev_priv) \
1597         (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
1598 #define HAS_FULL_PPGTT(dev_priv) \
1599         (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
1600
1601 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
1602         GEM_BUG_ON((sizes) == 0); \
1603         ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \
1604 })
1605
1606 #define HAS_OVERLAY(dev_priv)            (INTEL_INFO(dev_priv)->display.has_overlay)
1607 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
1608                 (INTEL_INFO(dev_priv)->display.overlay_needs_physical)
1609
1610 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1611 #define HAS_BROKEN_CS_TLB(dev_priv)     (IS_I830(dev_priv) || IS_I845G(dev_priv))
1612
1613 #define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv)   \
1614         (IS_BROADWELL(dev_priv) || IS_GEN(dev_priv, 9))
1615
1616 /* WaRsDisableCoarsePowerGating:skl,cnl */
1617 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv)                    \
1618         (IS_CANNONLAKE(dev_priv) ||                                     \
1619          IS_SKL_GT3(dev_priv) ||                                        \
1620          IS_SKL_GT4(dev_priv))
1621
1622 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
1623 #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
1624                                         IS_GEMINILAKE(dev_priv) || \
1625                                         IS_KABYLAKE(dev_priv))
1626
1627 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1628  * rows, which changed the alignment requirements and fence programming.
1629  */
1630 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \
1631                                          !(IS_I915G(dev_priv) || \
1632                                          IS_I915GM(dev_priv)))
1633 #define SUPPORTS_TV(dev_priv)           (INTEL_INFO(dev_priv)->display.supports_tv)
1634 #define I915_HAS_HOTPLUG(dev_priv)      (INTEL_INFO(dev_priv)->display.has_hotplug)
1635
1636 #define HAS_FW_BLC(dev_priv)    (INTEL_GEN(dev_priv) > 2)
1637 #define HAS_FBC(dev_priv)       (INTEL_INFO(dev_priv)->display.has_fbc)
1638 #define HAS_CUR_FBC(dev_priv)   (!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7)
1639
1640 #define HAS_IPS(dev_priv)       (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
1641
1642 #define HAS_DP_MST(dev_priv)    (INTEL_INFO(dev_priv)->display.has_dp_mst)
1643
1644 #define HAS_DDI(dev_priv)                (INTEL_INFO(dev_priv)->display.has_ddi)
1645 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
1646 #define HAS_PSR(dev_priv)                (INTEL_INFO(dev_priv)->display.has_psr)
1647 #define HAS_PSR_HW_TRACKING(dev_priv) \
1648         (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
1649 #define HAS_PSR2_SEL_FETCH(dev_priv)     (INTEL_GEN(dev_priv) >= 12)
1650 #define HAS_TRANSCODER(dev_priv, trans)  ((INTEL_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0)
1651
1652 #define HAS_RC6(dev_priv)                (INTEL_INFO(dev_priv)->has_rc6)
1653 #define HAS_RC6p(dev_priv)               (INTEL_INFO(dev_priv)->has_rc6p)
1654 #define HAS_RC6pp(dev_priv)              (false) /* HW was never validated */
1655
1656 #define HAS_RPS(dev_priv)       (INTEL_INFO(dev_priv)->has_rps)
1657
1658 #define HAS_CSR(dev_priv)       (INTEL_INFO(dev_priv)->display.has_csr)
1659
1660 #define HAS_MSO(i915)           (INTEL_GEN(i915) >= 12)
1661
1662 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
1663 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
1664
1665 #define HAS_IPC(dev_priv)                (INTEL_INFO(dev_priv)->display.has_ipc)
1666
1667 #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
1668 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
1669
1670 #define HAS_GT_UC(dev_priv)     (INTEL_INFO(dev_priv)->has_gt_uc)
1671
1672 #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
1673
1674 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv)     (INTEL_INFO(dev_priv)->has_global_mocs)
1675
1676
1677 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
1678
1679 #define HAS_LSPCON(dev_priv) (IS_GEN_RANGE(dev_priv, 9, 10))
1680
1681 /* DPF == dynamic parity feature */
1682 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
1683 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
1684                                  2 : HAS_L3_DPF(dev_priv))
1685
1686 #define GT_FREQUENCY_MULTIPLIER 50
1687 #define GEN9_FREQ_SCALER 3
1688
1689 #define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask))
1690
1691 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0)
1692
1693 #define HAS_VRR(i915)   (INTEL_GEN(i915) >= 12)
1694
1695 /* Only valid when HAS_DISPLAY() is true */
1696 #define INTEL_DISPLAY_ENABLED(dev_priv) \
1697         (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !(dev_priv)->params.disable_display)
1698
1699 static inline bool run_as_guest(void)
1700 {
1701         return !hypervisor_is_type(X86_HYPER_NATIVE);
1702 }
1703
1704 #define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \
1705                                               IS_ALDERLAKE_S(dev_priv))
1706
1707 static inline bool intel_vtd_active(void)
1708 {
1709 #ifdef CONFIG_INTEL_IOMMU
1710         if (intel_iommu_gfx_mapped)
1711                 return true;
1712 #endif
1713
1714         /* Running as a guest, we assume the host is enforcing VT'd */
1715         return run_as_guest();
1716 }
1717
1718 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
1719 {
1720         return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
1721 }
1722
1723 static inline bool
1724 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
1725 {
1726         return IS_BROXTON(dev_priv) && intel_vtd_active();
1727 }
1728
1729 /* i915_drv.c */
1730 extern const struct dev_pm_ops i915_pm_ops;
1731
1732 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
1733 void i915_driver_remove(struct drm_i915_private *i915);
1734 void i915_driver_shutdown(struct drm_i915_private *i915);
1735
1736 int i915_resume_switcheroo(struct drm_i915_private *i915);
1737 int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state);
1738
1739 int i915_getparam_ioctl(struct drm_device *dev, void *data,
1740                         struct drm_file *file_priv);
1741
1742 /* i915_gem.c */
1743 int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
1744 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
1745 void i915_gem_init_early(struct drm_i915_private *dev_priv);
1746 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
1747
1748 struct intel_memory_region *i915_gem_shmem_setup(struct drm_i915_private *i915);
1749
1750 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
1751 {
1752         /*
1753          * A single pass should suffice to release all the freed objects (along
1754          * most call paths) , but be a little more paranoid in that freeing
1755          * the objects does take a little amount of time, during which the rcu
1756          * callbacks could have added new objects into the freed list, and
1757          * armed the work again.
1758          */
1759         while (atomic_read(&i915->mm.free_count)) {
1760                 flush_work(&i915->mm.free_work);
1761                 rcu_barrier();
1762         }
1763 }
1764
1765 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
1766 {
1767         /*
1768          * Similar to objects above (see i915_gem_drain_freed-objects), in
1769          * general we have workers that are armed by RCU and then rearm
1770          * themselves in their callbacks. To be paranoid, we need to
1771          * drain the workqueue a second time after waiting for the RCU
1772          * grace period so that we catch work queued via RCU from the first
1773          * pass. As neither drain_workqueue() nor flush_workqueue() report
1774          * a result, we make an assumption that we only don't require more
1775          * than 3 passes to catch all _recursive_ RCU delayed work.
1776          *
1777          */
1778         int pass = 3;
1779         do {
1780                 flush_workqueue(i915->wq);
1781                 rcu_barrier();
1782                 i915_gem_drain_freed_objects(i915);
1783         } while (--pass);
1784         drain_workqueue(i915->wq);
1785 }
1786
1787 struct i915_vma * __must_check
1788 i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object *obj,
1789                             struct i915_gem_ww_ctx *ww,
1790                             const struct i915_ggtt_view *view,
1791                             u64 size, u64 alignment, u64 flags);
1792
1793 static inline struct i915_vma * __must_check
1794 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
1795                          const struct i915_ggtt_view *view,
1796                          u64 size, u64 alignment, u64 flags)
1797 {
1798         return i915_gem_object_ggtt_pin_ww(obj, NULL, view, size, alignment, flags);
1799 }
1800
1801 int i915_gem_object_unbind(struct drm_i915_gem_object *obj,
1802                            unsigned long flags);
1803 #define I915_GEM_OBJECT_UNBIND_ACTIVE BIT(0)
1804 #define I915_GEM_OBJECT_UNBIND_BARRIER BIT(1)
1805 #define I915_GEM_OBJECT_UNBIND_TEST BIT(2)
1806
1807 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
1808
1809 int i915_gem_dumb_create(struct drm_file *file_priv,
1810                          struct drm_device *dev,
1811                          struct drm_mode_create_dumb *args);
1812
1813 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
1814
1815 static inline u32 i915_reset_count(struct i915_gpu_error *error)
1816 {
1817         return atomic_read(&error->reset_count);
1818 }
1819
1820 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
1821                                           const struct intel_engine_cs *engine)
1822 {
1823         return atomic_read(&error->reset_engine_count[engine->uabi_class]);
1824 }
1825
1826 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
1827 void i915_gem_driver_register(struct drm_i915_private *i915);
1828 void i915_gem_driver_unregister(struct drm_i915_private *i915);
1829 void i915_gem_driver_remove(struct drm_i915_private *dev_priv);
1830 void i915_gem_driver_release(struct drm_i915_private *dev_priv);
1831 void i915_gem_suspend(struct drm_i915_private *dev_priv);
1832 void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
1833 void i915_gem_resume(struct drm_i915_private *dev_priv);
1834
1835 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
1836
1837 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1838                                     enum i915_cache_level cache_level);
1839
1840 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1841                                 struct dma_buf *dma_buf);
1842
1843 struct dma_buf *i915_gem_prime_export(struct drm_gem_object *gem_obj, int flags);
1844
1845 static inline struct i915_gem_context *
1846 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
1847 {
1848         return xa_load(&file_priv->context_xa, id);
1849 }
1850
1851 static inline struct i915_gem_context *
1852 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
1853 {
1854         struct i915_gem_context *ctx;
1855
1856         rcu_read_lock();
1857         ctx = __i915_gem_context_lookup_rcu(file_priv, id);
1858         if (ctx && !kref_get_unless_zero(&ctx->ref))
1859                 ctx = NULL;
1860         rcu_read_unlock();
1861
1862         return ctx;
1863 }
1864
1865 /* i915_gem_evict.c */
1866 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
1867                                           u64 min_size, u64 alignment,
1868                                           unsigned long color,
1869                                           u64 start, u64 end,
1870                                           unsigned flags);
1871 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
1872                                          struct drm_mm_node *node,
1873                                          unsigned int flags);
1874 int i915_gem_evict_vm(struct i915_address_space *vm);
1875
1876 /* i915_gem_internal.c */
1877 struct drm_i915_gem_object *
1878 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
1879                                 phys_addr_t size);
1880
1881 /* i915_gem_tiling.c */
1882 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
1883 {
1884         struct drm_i915_private *i915 = to_i915(obj->base.dev);
1885
1886         return i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
1887                 i915_gem_object_is_tiled(obj);
1888 }
1889
1890 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
1891                         unsigned int tiling, unsigned int stride);
1892 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
1893                              unsigned int tiling, unsigned int stride);
1894
1895 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
1896
1897 /* i915_cmd_parser.c */
1898 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
1899 int intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
1900 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
1901 unsigned long *intel_engine_cmd_parser_alloc_jump_whitelist(u32 batch_length,
1902                                                             bool trampoline);
1903
1904 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
1905                             struct i915_vma *batch,
1906                             unsigned long batch_offset,
1907                             unsigned long batch_length,
1908                             struct i915_vma *shadow,
1909                             unsigned long *jump_whitelist,
1910                             void *shadow_map,
1911                             const void *batch_map);
1912 #define I915_CMD_PARSER_TRAMPOLINE_SIZE 8
1913
1914 /* intel_device_info.c */
1915 static inline struct intel_device_info *
1916 mkwrite_device_info(struct drm_i915_private *dev_priv)
1917 {
1918         return (struct intel_device_info *)INTEL_INFO(dev_priv);
1919 }
1920
1921 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
1922                         struct drm_file *file);
1923
1924 /* i915_mm.c */
1925 int remap_io_sg(struct vm_area_struct *vma,
1926                 unsigned long addr, unsigned long size,
1927                 struct scatterlist *sgl, resource_size_t iobase);
1928
1929 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
1930 {
1931         if (INTEL_GEN(i915) >= 10)
1932                 return CNL_HWS_CSB_WRITE_INDEX;
1933         else
1934                 return I915_HWS_CSB_WRITE_INDEX;
1935 }
1936
1937 static inline enum i915_map_type
1938 i915_coherent_map_type(struct drm_i915_private *i915)
1939 {
1940         return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
1941 }
1942
1943 #endif