drivers/gpu/drm/i915/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 #include <uapi/drm/i915_drm.h>
  34 #include <uapi/drm/drm_fourcc.h>
  35
  36 #include <asm/hypervisor.h>
  37
  38 #include <linux/io-mapping.h>
  39 #include <linux/i2c.h>
  40 #include <linux/i2c-algo-bit.h>
  41 #include <linux/backlight.h>
  42 #include <linux/hash.h>
  43 #include <linux/intel-iommu.h>
  44 #include <linux/kref.h>
  45 #include <linux/mm_types.h>
  46 #include <linux/perf_event.h>
  47 #include <linux/pm_qos.h>
  48 #include <linux/dma-resv.h>
  49 #include <linux/shmem_fs.h>
  50 #include <linux/stackdepot.h>
  51 #include <linux/xarray.h>
  52
  53 #include <drm/intel-gtt.h>
  54 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
  55 #include <drm/drm_gem.h>
  56 #include <drm/drm_auth.h>
  57 #include <drm/drm_cache.h>
  58 #include <drm/drm_util.h>
  59 #include <drm/drm_dsc.h>
  60 #include <drm/drm_atomic.h>
  61 #include <drm/drm_connector.h>
  62 #include <drm/i915_mei_hdcp_interface.h>
  63
  64 #include "i915_params.h"
  65 #include "i915_reg.h"
  66 #include "i915_utils.h"
  67
  68 #include "display/intel_bios.h"
  69 #include "display/intel_display.h"
  70 #include "display/intel_display_power.h"
  71 #include "display/intel_dmc.h"
  72 #include "display/intel_dpll_mgr.h"
  73 #include "display/intel_dsb.h"
  74 #include "display/intel_frontbuffer.h"
  75 #include "display/intel_global_state.h"
  76 #include "display/intel_gmbus.h"
  77 #include "display/intel_opregion.h"
  78
  79 #include "gem/i915_gem_context_types.h"
  80 #include "gem/i915_gem_shrinker.h"
  81 #include "gem/i915_gem_stolen.h"
  82
  83 #include "gt/intel_engine.h"
  84 #include "gt/intel_gt_types.h"
  85 #include "gt/intel_region_lmem.h"
  86 #include "gt/intel_workarounds.h"
  87 #include "gt/uc/intel_uc.h"
  88
  89 #include "intel_device_info.h"
  90 #include "intel_memory_region.h"
  91 #include "intel_pch.h"
  92 #include "intel_runtime_pm.h"
  93 #include "intel_step.h"
  94 #include "intel_uncore.h"
  95 #include "intel_wakeref.h"
  96 #include "intel_wopcm.h"
  97
  98 #include "i915_gem.h"
  99 #include "i915_gem_gtt.h"
 100 #include "i915_gpu_error.h"
 101 #include "i915_perf_types.h"
 102 #include "i915_request.h"
 103 #include "i915_scheduler.h"
 104 #include "gt/intel_timeline.h"
 105 #include "i915_vma.h"
 106 #include "i915_irq.h"
 107
 108
 109 /* General customization:
 110  */
 111
 112 #define DRIVER_NAME             "i915"
 113 #define DRIVER_DESC             "Intel Graphics"
 114 #define DRIVER_DATE             "20201103"
 115 #define DRIVER_TIMESTAMP        1604406085
 116
 117 struct drm_i915_gem_object;
 118
 119 enum hpd_pin {
 120         HPD_NONE = 0,
 121         HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
 122         HPD_CRT,
 123         HPD_SDVO_B,
 124         HPD_SDVO_C,
 125         HPD_PORT_A,
 126         HPD_PORT_B,
 127         HPD_PORT_C,
 128         HPD_PORT_D,
 129         HPD_PORT_E,
 130         HPD_PORT_TC1,
 131         HPD_PORT_TC2,
 132         HPD_PORT_TC3,
 133         HPD_PORT_TC4,
 134         HPD_PORT_TC5,
 135         HPD_PORT_TC6,
 136
 137         HPD_NUM_PINS
 138 };
 139
 140 #define for_each_hpd_pin(__pin) \
 141         for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
 142
 143 /* Threshold == 5 for long IRQs, 50 for short */
 144 #define HPD_STORM_DEFAULT_THRESHOLD 50
 145
 146 struct i915_hotplug {
 147         struct delayed_work hotplug_work;
 148
 149         const u32 *hpd, *pch_hpd;
 150
 151         struct {
 152                 unsigned long last_jiffies;
 153                 int count;
 154                 enum {
 155                         HPD_ENABLED = 0,
 156                         HPD_DISABLED = 1,
 157                         HPD_MARK_DISABLED = 2
 158                 } state;
 159         } stats[HPD_NUM_PINS];
 160         u32 event_bits;
 161         u32 retry_bits;
 162         struct delayed_work reenable_work;
 163
 164         u32 long_port_mask;
 165         u32 short_port_mask;
 166         struct work_struct dig_port_work;
 167
 168         struct work_struct poll_init_work;
 169         bool poll_enabled;
 170
 171         unsigned int hpd_storm_threshold;
 172         /* Whether or not to count short HPD IRQs in HPD storms */
 173         u8 hpd_short_storm_enabled;
 174
 175         /*
 176          * if we get a HPD irq from DP and a HPD irq from non-DP
 177          * the non-DP HPD could block the workqueue on a mode config
 178          * mutex getting, that userspace may have taken. However
 179          * userspace is waiting on the DP workqueue to run which is
 180          * blocked behind the non-DP one.
 181          */
 182         struct workqueue_struct *dp_wq;
 183 };
 184
 185 #define I915_GEM_GPU_DOMAINS \
 186         (I915_GEM_DOMAIN_RENDER | \
 187          I915_GEM_DOMAIN_SAMPLER | \
 188          I915_GEM_DOMAIN_COMMAND | \
 189          I915_GEM_DOMAIN_INSTRUCTION | \
 190          I915_GEM_DOMAIN_VERTEX)
 191
 192 struct drm_i915_private;
 193 struct i915_mm_struct;
 194 struct i915_mmu_object;
 195
 196 struct drm_i915_file_private {
 197         struct drm_i915_private *dev_priv;
 198
 199         union {
 200                 struct drm_file *file;
 201                 struct rcu_head rcu;
 202         };
 203
 204         struct xarray context_xa;
 205         struct xarray vm_xa;
 206
 207         unsigned int bsd_engine;
 208
 209 /*
 210  * Every context ban increments per client ban score. Also
 211  * hangs in short succession increments ban score. If ban threshold
 212  * is reached, client is considered banned and submitting more work
 213  * will fail. This is a stop gap measure to limit the badly behaving
 214  * clients access to gpu. Note that unbannable contexts never increment
 215  * the client ban score.
 216  */
 217 #define I915_CLIENT_SCORE_HANG_FAST     1
 218 #define   I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
 219 #define I915_CLIENT_SCORE_CONTEXT_BAN   3
 220 #define I915_CLIENT_SCORE_BANNED        9
 221         /** ban_score: Accumulated score of all ctx bans and fast hangs. */
 222         atomic_t ban_score;
 223         unsigned long hang_timestamp;
 224 };
 225
 226 /* Interface history:
 227  *
 228  * 1.1: Original.
 229  * 1.2: Add Power Management
 230  * 1.3: Add vblank support
 231  * 1.4: Fix cmdbuffer path, add heap destroy
 232  * 1.5: Add vblank pipe configuration
 233  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 234  *      - Support vertical blank on secondary display pipe
 235  */
 236 #define DRIVER_MAJOR            1
 237 #define DRIVER_MINOR            6
 238 #define DRIVER_PATCHLEVEL       0
 239
 240 struct intel_overlay;
 241 struct intel_overlay_error_state;
 242
 243 struct sdvo_device_mapping {
 244         u8 initialized;
 245         u8 dvo_port;
 246         u8 slave_addr;
 247         u8 dvo_wiring;
 248         u8 i2c_pin;
 249         u8 ddc_pin;
 250 };
 251
 252 struct intel_connector;
 253 struct intel_encoder;
 254 struct intel_atomic_state;
 255 struct intel_cdclk_config;
 256 struct intel_cdclk_state;
 257 struct intel_cdclk_vals;
 258 struct intel_initial_plane_config;
 259 struct intel_crtc;
 260 struct intel_limit;
 261 struct dpll;
 262
 263 struct drm_i915_display_funcs {
 264         void (*get_cdclk)(struct drm_i915_private *dev_priv,
 265                           struct intel_cdclk_config *cdclk_config);
 266         void (*set_cdclk)(struct drm_i915_private *dev_priv,
 267                           const struct intel_cdclk_config *cdclk_config,
 268                           enum pipe pipe);
 269         int (*bw_calc_min_cdclk)(struct intel_atomic_state *state);
 270         int (*get_fifo_size)(struct drm_i915_private *dev_priv,
 271                              enum i9xx_plane_id i9xx_plane);
 272         int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state);
 273         int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state);
 274         void (*initial_watermarks)(struct intel_atomic_state *state,
 275                                    struct intel_crtc *crtc);
 276         void (*atomic_update_watermarks)(struct intel_atomic_state *state,
 277                                          struct intel_crtc *crtc);
 278         void (*optimize_watermarks)(struct intel_atomic_state *state,
 279                                     struct intel_crtc *crtc);
 280         int (*compute_global_watermarks)(struct intel_atomic_state *state);
 281         void (*update_wm)(struct intel_crtc *crtc);
 282         int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
 283         u8 (*calc_voltage_level)(int cdclk);
 284         /* Returns the active state of the crtc, and if the crtc is active,
 285          * fills out the pipe-config with the hw state. */
 286         bool (*get_pipe_config)(struct intel_crtc *,
 287                                 struct intel_crtc_state *);
 288         void (*get_initial_plane_config)(struct intel_crtc *,
 289                                          struct intel_initial_plane_config *);
 290         int (*crtc_compute_clock)(struct intel_crtc *crtc,
 291                                   struct intel_crtc_state *crtc_state);
 292         void (*crtc_enable)(struct intel_atomic_state *state,
 293                             struct intel_crtc *crtc);
 294         void (*crtc_disable)(struct intel_atomic_state *state,
 295                              struct intel_crtc *crtc);
 296         void (*commit_modeset_enables)(struct intel_atomic_state *state);
 297         void (*commit_modeset_disables)(struct intel_atomic_state *state);
 298         void (*audio_codec_enable)(struct intel_encoder *encoder,
 299                                    const struct intel_crtc_state *crtc_state,
 300                                    const struct drm_connector_state *conn_state);
 301         void (*audio_codec_disable)(struct intel_encoder *encoder,
 302                                     const struct intel_crtc_state *old_crtc_state,
 303                                     const struct drm_connector_state *old_conn_state);
 304         void (*fdi_link_train)(struct intel_crtc *crtc,
 305                                const struct intel_crtc_state *crtc_state);
 306         void (*init_clock_gating)(struct drm_i915_private *dev_priv);
 307         void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
 308         /* clock updates for mode set */
 309         /* cursor updates */
 310         /* render clock increase/decrease */
 311         /* display clock increase/decrease */
 312         /* pll clock increase/decrease */
 313
 314         int (*color_check)(struct intel_crtc_state *crtc_state);
 315         /*
 316          * Program double buffered color management registers during
 317          * vblank evasion. The registers should then latch during the
 318          * next vblank start, alongside any other double buffered registers
 319          * involved with the same commit.
 320          */
 321         void (*color_commit)(const struct intel_crtc_state *crtc_state);
 322         /*
 323          * Load LUTs (and other single buffered color management
 324          * registers). Will (hopefully) be called during the vblank
 325          * following the latching of any double buffered registers
 326          * involved with the same commit.
 327          */
 328         void (*load_luts)(const struct intel_crtc_state *crtc_state);
 329         void (*read_luts)(struct intel_crtc_state *crtc_state);
 330 };
 331
 332 enum i915_cache_level {
 333         I915_CACHE_NONE = 0,
 334         I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
 335         I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
 336                               caches, eg sampler/render caches, and the
 337                               large Last-Level-Cache. LLC is coherent with
 338                               the CPU, but L3 is only visible to the GPU. */
 339         I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
 340 };
 341
 342 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
 343
 344 struct intel_fbc {
 345         /* This is always the inner lock when overlapping with struct_mutex and
 346          * it's the outer lock when overlapping with stolen_lock. */
 347         struct mutex lock;
 348         unsigned threshold;
 349         unsigned int possible_framebuffer_bits;
 350         unsigned int busy_bits;
 351         struct intel_crtc *crtc;
 352
 353         struct drm_mm_node compressed_fb;
 354         struct drm_mm_node *compressed_llb;
 355
 356         bool false_color;
 357
 358         bool active;
 359         bool activated;
 360         bool flip_pending;
 361
 362         bool underrun_detected;
 363         struct work_struct underrun_work;
 364
 365         /*
 366          * Due to the atomic rules we can't access some structures without the
 367          * appropriate locking, so we cache information here in order to avoid
 368          * these problems.
 369          */
 370         struct intel_fbc_state_cache {
 371                 struct {
 372                         unsigned int mode_flags;
 373                         u32 hsw_bdw_pixel_rate;
 374                 } crtc;
 375
 376                 struct {
 377                         unsigned int rotation;
 378                         int src_w;
 379                         int src_h;
 380                         bool visible;
 381                         /*
 382                          * Display surface base address adjustement for
 383                          * pageflips. Note that on gen4+ this only adjusts up
 384                          * to a tile, offsets within a tile are handled in
 385                          * the hw itself (with the TILEOFF register).
 386                          */
 387                         int adjusted_x;
 388                         int adjusted_y;
 389
 390                         u16 pixel_blend_mode;
 391                 } plane;
 392
 393                 struct {
 394                         const struct drm_format_info *format;
 395                         unsigned int stride;
 396                         u64 modifier;
 397                 } fb;
 398
 399                 unsigned int fence_y_offset;
 400                 u16 gen9_wa_cfb_stride;
 401                 u16 interval;
 402                 s8 fence_id;
 403                 bool psr2_active;
 404         } state_cache;
 405
 406         /*
 407          * This structure contains everything that's relevant to program the
 408          * hardware registers. When we want to figure out if we need to disable
 409          * and re-enable FBC for a new configuration we just check if there's
 410          * something different in the struct. The genx_fbc_activate functions
 411          * are supposed to read from it in order to program the registers.
 412          */
 413         struct intel_fbc_reg_params {
 414                 struct {
 415                         enum pipe pipe;
 416                         enum i9xx_plane_id i9xx_plane;
 417                 } crtc;
 418
 419                 struct {
 420                         const struct drm_format_info *format;
 421                         unsigned int stride;
 422                         u64 modifier;
 423                 } fb;
 424
 425                 int cfb_size;
 426                 unsigned int fence_y_offset;
 427                 u16 gen9_wa_cfb_stride;
 428                 u16 interval;
 429                 s8 fence_id;
 430                 bool plane_visible;
 431         } params;
 432
 433         const char *no_fbc_reason;
 434 };
 435
 436 /*
 437  * HIGH_RR is the highest eDP panel refresh rate read from EDID
 438  * LOW_RR is the lowest eDP panel refresh rate found from EDID
 439  * parsing for same resolution.
 440  */
 441 enum drrs_refresh_rate_type {
 442         DRRS_HIGH_RR,
 443         DRRS_LOW_RR,
 444         DRRS_MAX_RR, /* RR count */
 445 };
 446
 447 enum drrs_support_type {
 448         DRRS_NOT_SUPPORTED = 0,
 449         STATIC_DRRS_SUPPORT = 1,
 450         SEAMLESS_DRRS_SUPPORT = 2
 451 };
 452
 453 struct intel_dp;
 454 struct i915_drrs {
 455         struct mutex mutex;
 456         struct delayed_work work;
 457         struct intel_dp *dp;
 458         unsigned busy_frontbuffer_bits;
 459         enum drrs_refresh_rate_type refresh_rate_type;
 460         enum drrs_support_type type;
 461 };
 462
 463 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
 464 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
 465 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
 466 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
 467 #define QUIRK_INCREASE_T12_DELAY (1<<6)
 468 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
 469
 470 struct intel_fbdev;
 471 struct intel_fbc_work;
 472
 473 struct intel_gmbus {
 474         struct i2c_adapter adapter;
 475 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
 476         u32 force_bit;
 477         u32 reg0;
 478         i915_reg_t gpio_reg;
 479         struct i2c_algo_bit_data bit_algo;
 480         struct drm_i915_private *dev_priv;
 481 };
 482
 483 struct i915_suspend_saved_registers {
 484         u32 saveDSPARB;
 485         u32 saveSWF0[16];
 486         u32 saveSWF1[16];
 487         u32 saveSWF3[3];
 488         u16 saveGCDGMBUS;
 489 };
 490
 491 struct vlv_s0ix_state;
 492
 493 #define MAX_L3_SLICES 2
 494 struct intel_l3_parity {
 495         u32 *remap_info[MAX_L3_SLICES];
 496         struct work_struct error_work;
 497         int which_slice;
 498 };
 499
 500 struct i915_gem_mm {
 501         /** Memory allocator for GTT stolen memory */
 502         struct drm_mm stolen;
 503         /** Protects the usage of the GTT stolen memory allocator. This is
 504          * always the inner lock when overlapping with struct_mutex. */
 505         struct mutex stolen_lock;
 506
 507         /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
 508         spinlock_t obj_lock;
 509
 510         /**
 511          * List of objects which are purgeable.
 512          */
 513         struct list_head purge_list;
 514
 515         /**
 516          * List of objects which have allocated pages and are shrinkable.
 517          */
 518         struct list_head shrink_list;
 519
 520         /**
 521          * List of objects which are pending destruction.
 522          */
 523         struct llist_head free_list;
 524         struct work_struct free_work;
 525         /**
 526          * Count of objects pending destructions. Used to skip needlessly
 527          * waiting on an RCU barrier if no objects are waiting to be freed.
 528          */
 529         atomic_t free_count;
 530
 531         /**
 532          * tmpfs instance used for shmem backed objects
 533          */
 534         struct vfsmount *gemfs;
 535
 536         struct intel_memory_region *regions[INTEL_REGION_UNKNOWN];
 537
 538         struct notifier_block oom_notifier;
 539         struct notifier_block vmap_notifier;
 540         struct shrinker shrinker;
 541
 542 #ifdef CONFIG_MMU_NOTIFIER
 543         /**
 544          * notifier_lock for mmu notifiers, memory may not be allocated
 545          * while holding this lock.
 546          */
 547         spinlock_t notifier_lock;
 548 #endif
 549
 550         /* shrinker accounting, also useful for userland debugging */
 551         u64 shrink_memory;
 552         u32 shrink_count;
 553 };
 554
 555 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
 556
 557 unsigned long i915_fence_context_timeout(const struct drm_i915_private *i915,
 558                                          u64 context);
 559
 560 static inline unsigned long
 561 i915_fence_timeout(const struct drm_i915_private *i915)
 562 {
 563         return i915_fence_context_timeout(i915, U64_MAX);
 564 }
 565
 566 /* Amount of SAGV/QGV points, BSpec precisely defines this */
 567 #define I915_NUM_QGV_POINTS 8
 568
 569 #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
 570
 571 struct ddi_vbt_port_info {
 572         /* Non-NULL if port present. */
 573         struct intel_bios_encoder_data *devdata;
 574
 575         int max_tmds_clock;
 576
 577         /* This is an index in the HDMI/DVI DDI buffer translation table. */
 578         u8 hdmi_level_shift;
 579         u8 hdmi_level_shift_set:1;
 580
 581         u8 alternate_aux_channel;
 582         u8 alternate_ddc_pin;
 583
 584         int dp_max_link_rate;           /* 0 for not limited by VBT */
 585 };
 586
 587 enum psr_lines_to_wait {
 588         PSR_0_LINES_TO_WAIT = 0,
 589         PSR_1_LINE_TO_WAIT,
 590         PSR_4_LINES_TO_WAIT,
 591         PSR_8_LINES_TO_WAIT
 592 };
 593
 594 struct intel_vbt_data {
 595         /* bdb version */
 596         u16 version;
 597
 598         struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
 599         struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
 600
 601         /* Feature bits */
 602         unsigned int int_tv_support:1;
 603         unsigned int lvds_dither:1;
 604         unsigned int int_crt_support:1;
 605         unsigned int lvds_use_ssc:1;
 606         unsigned int int_lvds_support:1;
 607         unsigned int display_clock_mode:1;
 608         unsigned int fdi_rx_polarity_inverted:1;
 609         unsigned int panel_type:4;
 610         int lvds_ssc_freq;
 611         unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
 612         enum drm_panel_orientation orientation;
 613
 614         enum drrs_support_type drrs_type;
 615
 616         struct {
 617                 int rate;
 618                 int lanes;
 619                 int preemphasis;
 620                 int vswing;
 621                 bool low_vswing;
 622                 bool initialized;
 623                 int bpp;
 624                 struct edp_power_seq pps;
 625                 bool hobl;
 626         } edp;
 627
 628         struct {
 629                 bool enable;
 630                 bool full_link;
 631                 bool require_aux_wakeup;
 632                 int idle_frames;
 633                 enum psr_lines_to_wait lines_to_wait;
 634                 int tp1_wakeup_time_us;
 635                 int tp2_tp3_wakeup_time_us;
 636                 int psr2_tp2_tp3_wakeup_time_us;
 637         } psr;
 638
 639         struct {
 640                 u16 pwm_freq_hz;
 641                 bool present;
 642                 bool active_low_pwm;
 643                 u8 min_brightness;      /* min_brightness/255 of max */
 644                 u8 controller;          /* brightness controller number */
 645                 enum intel_backlight_type type;
 646         } backlight;
 647
 648         /* MIPI DSI */
 649         struct {
 650                 u16 panel_id;
 651                 struct mipi_config *config;
 652                 struct mipi_pps_data *pps;
 653                 u16 bl_ports;
 654                 u16 cabc_ports;
 655                 u8 seq_version;
 656                 u32 size;
 657                 u8 *data;
 658                 const u8 *sequence[MIPI_SEQ_MAX];
 659                 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
 660                 enum drm_panel_orientation orientation;
 661         } dsi;
 662
 663         int crt_ddc_pin;
 664
 665         struct list_head display_devices;
 666
 667         struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
 668         struct sdvo_device_mapping sdvo_mappings[2];
 669 };
 670
 671 enum intel_ddb_partitioning {
 672         INTEL_DDB_PART_1_2,
 673         INTEL_DDB_PART_5_6, /* IVB+ */
 674 };
 675
 676 struct ilk_wm_values {
 677         u32 wm_pipe[3];
 678         u32 wm_lp[3];
 679         u32 wm_lp_spr[3];
 680         bool enable_fbc_wm;
 681         enum intel_ddb_partitioning partitioning;
 682 };
 683
 684 struct g4x_pipe_wm {
 685         u16 plane[I915_MAX_PLANES];
 686         u16 fbc;
 687 };
 688
 689 struct g4x_sr_wm {
 690         u16 plane;
 691         u16 cursor;
 692         u16 fbc;
 693 };
 694
 695 struct vlv_wm_ddl_values {
 696         u8 plane[I915_MAX_PLANES];
 697 };
 698
 699 struct vlv_wm_values {
 700         struct g4x_pipe_wm pipe[3];
 701         struct g4x_sr_wm sr;
 702         struct vlv_wm_ddl_values ddl[3];
 703         u8 level;
 704         bool cxsr;
 705 };
 706
 707 struct g4x_wm_values {
 708         struct g4x_pipe_wm pipe[2];
 709         struct g4x_sr_wm sr;
 710         struct g4x_sr_wm hpll;
 711         bool cxsr;
 712         bool hpll_en;
 713         bool fbc_en;
 714 };
 715
 716 struct skl_ddb_entry {
 717         u16 start, end; /* in number of blocks, 'end' is exclusive */
 718 };
 719
 720 static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)
 721 {
 722         return entry->end - entry->start;
 723 }
 724
 725 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
 726                                        const struct skl_ddb_entry *e2)
 727 {
 728         if (e1->start == e2->start && e1->end == e2->end)
 729                 return true;
 730
 731         return false;
 732 }
 733
 734 struct i915_frontbuffer_tracking {
 735         spinlock_t lock;
 736
 737         /*
 738          * Tracking bits for delayed frontbuffer flushing du to gpu activity or
 739          * scheduled flips.
 740          */
 741         unsigned busy_bits;
 742         unsigned flip_bits;
 743 };
 744
 745 struct i915_virtual_gpu {
 746         struct mutex lock; /* serialises sending of g2v_notify command pkts */
 747         bool active;
 748         u32 caps;
 749 };
 750
 751 struct intel_cdclk_config {
 752         unsigned int cdclk, vco, ref, bypass;
 753         u8 voltage_level;
 754 };
 755
 756 struct i915_selftest_stash {
 757         atomic_t counter;
 758 };
 759
 760 struct drm_i915_private {
 761         struct drm_device drm;
 762
 763         /* FIXME: Device release actions should all be moved to drmm_ */
 764         bool do_release;
 765
 766         /* i915 device parameters */
 767         struct i915_params params;
 768
 769         const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
 770         struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
 771         struct intel_driver_caps caps;
 772
 773         /**
 774          * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
 775          * end of stolen which we can optionally use to create GEM objects
 776          * backed by stolen memory. Note that stolen_usable_size tells us
 777          * exactly how much of this we are actually allowed to use, given that
 778          * some portion of it is in fact reserved for use by hardware functions.
 779          */
 780         struct resource dsm;
 781         /**
 782          * Reseved portion of Data Stolen Memory
 783          */
 784         struct resource dsm_reserved;
 785
 786         /*
 787          * Stolen memory is segmented in hardware with different portions
 788          * offlimits to certain functions.
 789          *
 790          * The drm_mm is initialised to the total accessible range, as found
 791          * from the PCI config. On Broadwell+, this is further restricted to
 792          * avoid the first page! The upper end of stolen memory is reserved for
 793          * hardware functions and similarly removed from the accessible range.
 794          */
 795         resource_size_t stolen_usable_size;     /* Total size minus reserved ranges */
 796
 797         struct intel_uncore uncore;
 798         struct intel_uncore_mmio_debug mmio_debug;
 799
 800         struct i915_virtual_gpu vgpu;
 801
 802         struct intel_gvt *gvt;
 803
 804         struct intel_wopcm wopcm;
 805
 806         struct intel_dmc dmc;
 807
 808         struct intel_gmbus gmbus[GMBUS_NUM_PINS];
 809
 810         /** gmbus_mutex protects against concurrent usage of the single hw gmbus
 811          * controller on different i2c buses. */
 812         struct mutex gmbus_mutex;
 813
 814         /**
 815          * Base address of where the gmbus and gpio blocks are located (either
 816          * on PCH or on SoC for platforms without PCH).
 817          */
 818         u32 gpio_mmio_base;
 819
 820         u32 hsw_psr_mmio_adjust;
 821
 822         /* MMIO base address for MIPI regs */
 823         u32 mipi_mmio_base;
 824
 825         u32 pps_mmio_base;
 826
 827         wait_queue_head_t gmbus_wait_queue;
 828
 829         struct pci_dev *bridge_dev;
 830
 831         struct rb_root uabi_engines;
 832
 833         struct resource mch_res;
 834
 835         /* protects the irq masks */
 836         spinlock_t irq_lock;
 837
 838         bool display_irqs_enabled;
 839
 840         /* Sideband mailbox protection */
 841         struct mutex sb_lock;
 842         struct pm_qos_request sb_qos;
 843
 844         /** Cached value of IMR to avoid reads in updating the bitfield */
 845         union {
 846                 u32 irq_mask;
 847                 u32 de_irq_mask[I915_MAX_PIPES];
 848         };
 849         u32 pipestat_irq_mask[I915_MAX_PIPES];
 850
 851         struct i915_hotplug hotplug;
 852         struct intel_fbc fbc;
 853         struct i915_drrs drrs;
 854         struct intel_opregion opregion;
 855         struct intel_vbt_data vbt;
 856
 857         bool preserve_bios_swizzle;
 858
 859         /* overlay */
 860         struct intel_overlay *overlay;
 861
 862         /* backlight registers and fields in struct intel_panel */
 863         struct mutex backlight_lock;
 864
 865         /* protects panel power sequencer state */
 866         struct mutex pps_mutex;
 867
 868         unsigned int fsb_freq, mem_freq, is_ddr3;
 869         unsigned int skl_preferred_vco_freq;
 870         unsigned int max_cdclk_freq;
 871
 872         unsigned int max_dotclk_freq;
 873         unsigned int hpll_freq;
 874         unsigned int fdi_pll_freq;
 875         unsigned int czclk_freq;
 876
 877         struct {
 878                 /* The current hardware cdclk configuration */
 879                 struct intel_cdclk_config hw;
 880
 881                 /* cdclk, divider, and ratio table from bspec */
 882                 const struct intel_cdclk_vals *table;
 883
 884                 struct intel_global_obj obj;
 885         } cdclk;
 886
 887         struct {
 888                 /* The current hardware dbuf configuration */
 889                 u8 enabled_slices;
 890
 891                 struct intel_global_obj obj;
 892         } dbuf;
 893
 894         /**
 895          * wq - Driver workqueue for GEM.
 896          *
 897          * NOTE: Work items scheduled here are not allowed to grab any modeset
 898          * locks, for otherwise the flushing done in the pageflip code will
 899          * result in deadlocks.
 900          */
 901         struct workqueue_struct *wq;
 902
 903         /* ordered wq for modesets */
 904         struct workqueue_struct *modeset_wq;
 905         /* unbound hipri wq for page flips/plane updates */
 906         struct workqueue_struct *flip_wq;
 907
 908         /* Display functions */
 909         struct drm_i915_display_funcs display;
 910
 911         /* PCH chipset type */
 912         enum intel_pch pch_type;
 913         unsigned short pch_id;
 914
 915         unsigned long quirks;
 916
 917         struct drm_atomic_state *modeset_restore_state;
 918         struct drm_modeset_acquire_ctx reset_ctx;
 919
 920         struct i915_ggtt ggtt; /* VM representing the global address space */
 921
 922         struct i915_gem_mm mm;
 923
 924         /* Kernel Modesetting */
 925
 926         struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
 927         struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
 928
 929         /**
 930          * dpll and cdclk state is protected by connection_mutex
 931          * dpll.lock serializes intel_{prepare,enable,disable}_shared_dpll.
 932          * Must be global rather than per dpll, because on some platforms plls
 933          * share registers.
 934          */
 935         struct {
 936                 struct mutex lock;
 937
 938                 int num_shared_dpll;
 939                 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
 940                 const struct intel_dpll_mgr *mgr;
 941
 942                 struct {
 943                         int nssc;
 944                         int ssc;
 945                 } ref_clks;
 946         } dpll;
 947
 948         struct list_head global_obj_list;
 949
 950         /*
 951          * For reading active_pipes holding any crtc lock is
 952          * sufficient, for writing must hold all of them.
 953          */
 954         u8 active_pipes;
 955
 956         struct i915_wa_list gt_wa_list;
 957
 958         struct i915_frontbuffer_tracking fb_tracking;
 959
 960         struct intel_atomic_helper {
 961                 struct llist_head free_list;
 962                 struct work_struct free_work;
 963         } atomic_helper;
 964
 965         bool mchbar_need_disable;
 966
 967         struct intel_l3_parity l3_parity;
 968
 969         /*
 970          * HTI (aka HDPORT) state read during initial hw readout.  Most
 971          * platforms don't have HTI, so this will just stay 0.  Those that do
 972          * will use this later to figure out which PLLs and PHYs are unavailable
 973          * for driver usage.
 974          */
 975         u32 hti_state;
 976
 977         /*
 978          * edram size in MB.
 979          * Cannot be determined by PCIID. You must always read a register.
 980          */
 981         u32 edram_size_mb;
 982
 983         struct i915_power_domains power_domains;
 984
 985         struct i915_gpu_error gpu_error;
 986
 987         struct drm_i915_gem_object *vlv_pctx;
 988
 989         /* list of fbdev register on this device */
 990         struct intel_fbdev *fbdev;
 991         struct work_struct fbdev_suspend_work;
 992
 993         struct drm_property *broadcast_rgb_property;
 994         struct drm_property *force_audio_property;
 995
 996         /* hda/i915 audio component */
 997         struct i915_audio_component *audio_component;
 998         bool audio_component_registered;
 999         /**
1000          * av_mutex - mutex for audio/video sync
1001          *
1002          */
1003         struct mutex av_mutex;
1004         int audio_power_refcount;
1005         u32 audio_freq_cntrl;
1006
1007         u32 fdi_rx_config;
1008
1009         /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1010         u32 chv_phy_control;
1011         /*
1012          * Shadows for CHV DPLL_MD regs to keep the state
1013          * checker somewhat working in the presence hardware
1014          * crappiness (can't read out DPLL_MD for pipes B & C).
1015          */
1016         u32 chv_dpll_md[I915_MAX_PIPES];
1017         u32 bxt_phy_grc;
1018
1019         u32 suspend_count;
1020         bool power_domains_suspended;
1021         struct i915_suspend_saved_registers regfile;
1022         struct vlv_s0ix_state *vlv_s0ix_state;
1023
1024         enum {
1025                 I915_SAGV_UNKNOWN = 0,
1026                 I915_SAGV_DISABLED,
1027                 I915_SAGV_ENABLED,
1028                 I915_SAGV_NOT_CONTROLLED
1029         } sagv_status;
1030
1031         u32 sagv_block_time_us;
1032
1033         struct {
1034                 /*
1035                  * Raw watermark latency values:
1036                  * in 0.1us units for WM0,
1037                  * in 0.5us units for WM1+.
1038                  */
1039                 /* primary */
1040                 u16 pri_latency[5];
1041                 /* sprite */
1042                 u16 spr_latency[5];
1043                 /* cursor */
1044                 u16 cur_latency[5];
1045                 /*
1046                  * Raw watermark memory latency values
1047                  * for SKL for all 8 levels
1048                  * in 1us units.
1049                  */
1050                 u16 skl_latency[8];
1051
1052                 /* current hardware state */
1053                 union {
1054                         struct ilk_wm_values hw;
1055                         struct vlv_wm_values vlv;
1056                         struct g4x_wm_values g4x;
1057                 };
1058
1059                 u8 max_level;
1060
1061                 /*
1062                  * Should be held around atomic WM register writing; also
1063                  * protects * intel_crtc->wm.active and
1064                  * crtc_state->wm.need_postvbl_update.
1065                  */
1066                 struct mutex wm_mutex;
1067         } wm;
1068
1069         struct dram_info {
1070                 bool wm_lv_0_adjust_needed;
1071                 u8 num_channels;
1072                 bool symmetric_memory;
1073                 enum intel_dram_type {
1074                         INTEL_DRAM_UNKNOWN,
1075                         INTEL_DRAM_DDR3,
1076                         INTEL_DRAM_DDR4,
1077                         INTEL_DRAM_LPDDR3,
1078                         INTEL_DRAM_LPDDR4,
1079                         INTEL_DRAM_DDR5,
1080                         INTEL_DRAM_LPDDR5,
1081                 } type;
1082                 u8 num_qgv_points;
1083         } dram_info;
1084
1085         struct intel_bw_info {
1086                 /* for each QGV point */
1087                 unsigned int deratedbw[I915_NUM_QGV_POINTS];
1088                 u8 num_qgv_points;
1089                 u8 num_planes;
1090         } max_bw[6];
1091
1092         struct intel_global_obj bw_obj;
1093
1094         struct intel_runtime_pm runtime_pm;
1095
1096         struct i915_perf perf;
1097
1098         /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1099         struct intel_gt gt;
1100
1101         struct {
1102                 struct i915_gem_contexts {
1103                         spinlock_t lock; /* locks list */
1104                         struct list_head list;
1105                 } contexts;
1106
1107                 /*
1108                  * We replace the local file with a global mappings as the
1109                  * backing storage for the mmap is on the device and not
1110                  * on the struct file, and we do not want to prolong the
1111                  * lifetime of the local fd. To minimise the number of
1112                  * anonymous inodes we create, we use a global singleton to
1113                  * share the global mapping.
1114                  */
1115                 struct file *mmap_singleton;
1116         } gem;
1117
1118         u8 framestart_delay;
1119
1120         /* Window2 specifies time required to program DSB (Window2) in number of scan lines */
1121         u8 window2_delay;
1122
1123         u8 pch_ssc_use;
1124
1125         /* For i915gm/i945gm vblank irq workaround */
1126         u8 vblank_enabled;
1127
1128         /* perform PHY state sanity checks? */
1129         bool chv_phy_assert[2];
1130
1131         bool ipc_enabled;
1132
1133         /* Used to save the pipe-to-encoder mapping for audio */
1134         struct intel_encoder *av_enc_map[I915_MAX_PIPES];
1135
1136         /* necessary resource sharing with HDMI LPE audio driver. */
1137         struct {
1138                 struct platform_device *platdev;
1139                 int     irq;
1140         } lpe_audio;
1141
1142         struct i915_pmu pmu;
1143
1144         struct i915_hdcp_comp_master *hdcp_master;
1145         bool hdcp_comp_added;
1146
1147         /* Mutex to protect the above hdcp component related values. */
1148         struct mutex hdcp_comp_mutex;
1149
1150         I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
1151
1152         /*
1153          * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1154          * will be rejected. Instead look for a better place.
1155          */
1156 };
1157
1158 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1159 {
1160         return container_of(dev, struct drm_i915_private, drm);
1161 }
1162
1163 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
1164 {
1165         return dev_get_drvdata(kdev);
1166 }
1167
1168 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
1169 {
1170         return pci_get_drvdata(pdev);
1171 }
1172
1173 /* Simple iterator over all initialised engines */
1174 #define for_each_engine(engine__, dev_priv__, id__) \
1175         for ((id__) = 0; \
1176              (id__) < I915_NUM_ENGINES; \
1177              (id__)++) \
1178                 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
1179
1180 /* Iterator over subset of engines selected by mask */
1181 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
1182         for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \
1183              (tmp__) ? \
1184              ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \
1185              0;)
1186
1187 #define rb_to_uabi_engine(rb) \
1188         rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
1189
1190 #define for_each_uabi_engine(engine__, i915__) \
1191         for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
1192              (engine__); \
1193              (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
1194
1195 #define for_each_uabi_class_engine(engine__, class__, i915__) \
1196         for ((engine__) = intel_engine_lookup_user((i915__), (class__), 0); \
1197              (engine__) && (engine__)->uabi_class == (class__); \
1198              (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
1199
1200 #define I915_GTT_OFFSET_NONE ((u32)-1)
1201
1202 /*
1203  * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1204  * considered to be the frontbuffer for the given plane interface-wise. This
1205  * doesn't mean that the hw necessarily already scans it out, but that any
1206  * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1207  *
1208  * We have one bit per pipe and per scanout plane type.
1209  */
1210 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
1211 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
1212         BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
1213         BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
1214         BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
1215 })
1216 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1217         BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1218 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1219         GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
1220                 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1221
1222 #define INTEL_INFO(dev_priv)    (&(dev_priv)->__info)
1223 #define RUNTIME_INFO(dev_priv)  (&(dev_priv)->__runtime)
1224 #define DRIVER_CAPS(dev_priv)   (&(dev_priv)->caps)
1225
1226 #define INTEL_DEVID(dev_priv)   (RUNTIME_INFO(dev_priv)->device_id)
1227
1228 /*
1229  * Deprecated: this will be replaced by individual IP checks:
1230  * GRAPHICS_VER(), MEDIA_VER() and DISPLAY_VER()
1231  */
1232 #define INTEL_GEN(dev_priv)             GRAPHICS_VER(dev_priv)
1233 /*
1234  * Deprecated: use IS_GRAPHICS_VER(), IS_MEDIA_VER() and IS_DISPLAY_VER() as
1235  * appropriate.
1236  */
1237 #define IS_GEN_RANGE(dev_priv, s, e)    IS_GRAPHICS_VER(dev_priv, (s), (e))
1238 /*
1239  * Deprecated: use GRAPHICS_VER(), MEDIA_VER() and DISPLAY_VER() as appropriate.
1240  */
1241 #define IS_GEN(dev_priv, n)             (GRAPHICS_VER(dev_priv) == (n))
1242
1243 #define GRAPHICS_VER(i915)              (INTEL_INFO(i915)->graphics_ver)
1244 #define IS_GRAPHICS_VER(i915, from, until) \
1245         (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
1246
1247 #define MEDIA_VER(i915)                 (INTEL_INFO(i915)->media_ver)
1248 #define IS_MEDIA_VER(i915, from, until) \
1249         (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))
1250
1251 #define DISPLAY_VER(i915)       (INTEL_INFO(i915)->display.ver)
1252 #define IS_DISPLAY_VER(i915, from, until) \
1253         (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
1254
1255 #define REVID_FOREVER           0xff
1256 #define INTEL_REVID(dev_priv)   (to_pci_dev((dev_priv)->drm.dev)->revision)
1257
1258 #define HAS_DSB(dev_priv)       (INTEL_INFO(dev_priv)->display.has_dsb)
1259
1260 /*
1261  * Return true if revision is in range [since,until] inclusive.
1262  *
1263  * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
1264  */
1265 #define IS_REVID(p, since, until) \
1266         (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
1267
1268 #define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step)
1269 #define INTEL_GT_STEP(__i915) (RUNTIME_INFO(__i915)->step.gt_step)
1270
1271 #define IS_DISPLAY_STEP(__i915, since, until) \
1272         (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \
1273          INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) <= (until))
1274
1275 #define IS_GT_STEP(__i915, since, until) \
1276         (drm_WARN_ON(&(__i915)->drm, INTEL_GT_STEP(__i915) == STEP_NONE), \
1277          INTEL_GT_STEP(__i915) >= (since) && INTEL_GT_STEP(__i915) <= (until))
1278
1279 static __always_inline unsigned int
1280 __platform_mask_index(const struct intel_runtime_info *info,
1281                       enum intel_platform p)
1282 {
1283         const unsigned int pbits =
1284                 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
1285
1286         /* Expand the platform_mask array if this fails. */
1287         BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
1288                      pbits * ARRAY_SIZE(info->platform_mask));
1289
1290         return p / pbits;
1291 }
1292
1293 static __always_inline unsigned int
1294 __platform_mask_bit(const struct intel_runtime_info *info,
1295                     enum intel_platform p)
1296 {
1297         const unsigned int pbits =
1298                 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
1299
1300         return p % pbits + INTEL_SUBPLATFORM_BITS;
1301 }
1302
1303 static inline u32
1304 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
1305 {
1306         const unsigned int pi = __platform_mask_index(info, p);
1307
1308         return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK;
1309 }
1310
1311 static __always_inline bool
1312 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
1313 {
1314         const struct intel_runtime_info *info = RUNTIME_INFO(i915);
1315         const unsigned int pi = __platform_mask_index(info, p);
1316         const unsigned int pb = __platform_mask_bit(info, p);
1317
1318         BUILD_BUG_ON(!__builtin_constant_p(p));
1319
1320         return info->platform_mask[pi] & BIT(pb);
1321 }
1322
1323 static __always_inline bool
1324 IS_SUBPLATFORM(const struct drm_i915_private *i915,
1325                enum intel_platform p, unsigned int s)
1326 {
1327         const struct intel_runtime_info *info = RUNTIME_INFO(i915);
1328         const unsigned int pi = __platform_mask_index(info, p);
1329         const unsigned int pb = __platform_mask_bit(info, p);
1330         const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
1331         const u32 mask = info->platform_mask[pi];
1332
1333         BUILD_BUG_ON(!__builtin_constant_p(p));
1334         BUILD_BUG_ON(!__builtin_constant_p(s));
1335         BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
1336
1337         /* Shift and test on the MSB position so sign flag can be used. */
1338         return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
1339 }
1340
1341 #define IS_MOBILE(dev_priv)     (INTEL_INFO(dev_priv)->is_mobile)
1342 #define IS_DGFX(dev_priv)   (INTEL_INFO(dev_priv)->is_dgfx)
1343
1344 #define IS_I830(dev_priv)       IS_PLATFORM(dev_priv, INTEL_I830)
1345 #define IS_I845G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I845G)
1346 #define IS_I85X(dev_priv)       IS_PLATFORM(dev_priv, INTEL_I85X)
1347 #define IS_I865G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I865G)
1348 #define IS_I915G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I915G)
1349 #define IS_I915GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I915GM)
1350 #define IS_I945G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I945G)
1351 #define IS_I945GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I945GM)
1352 #define IS_I965G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I965G)
1353 #define IS_I965GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I965GM)
1354 #define IS_G45(dev_priv)        IS_PLATFORM(dev_priv, INTEL_G45)
1355 #define IS_GM45(dev_priv)       IS_PLATFORM(dev_priv, INTEL_GM45)
1356 #define IS_G4X(dev_priv)        (IS_G45(dev_priv) || IS_GM45(dev_priv))
1357 #define IS_PINEVIEW(dev_priv)   IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
1358 #define IS_G33(dev_priv)        IS_PLATFORM(dev_priv, INTEL_G33)
1359 #define IS_IRONLAKE(dev_priv)   IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
1360 #define IS_IRONLAKE_M(dev_priv) \
1361         (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
1362 #define IS_SANDYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SANDYBRIDGE)
1363 #define IS_IVYBRIDGE(dev_priv)  IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
1364 #define IS_IVB_GT1(dev_priv)    (IS_IVYBRIDGE(dev_priv) && \
1365                                  INTEL_INFO(dev_priv)->gt == 1)
1366 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
1367 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
1368 #define IS_HASWELL(dev_priv)    IS_PLATFORM(dev_priv, INTEL_HASWELL)
1369 #define IS_BROADWELL(dev_priv)  IS_PLATFORM(dev_priv, INTEL_BROADWELL)
1370 #define IS_SKYLAKE(dev_priv)    IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
1371 #define IS_BROXTON(dev_priv)    IS_PLATFORM(dev_priv, INTEL_BROXTON)
1372 #define IS_KABYLAKE(dev_priv)   IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
1373 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
1374 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
1375 #define IS_COMETLAKE(dev_priv)  IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
1376 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
1377 #define IS_ICELAKE(dev_priv)    IS_PLATFORM(dev_priv, INTEL_ICELAKE)
1378 #define IS_JSL_EHL(dev_priv)    (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \
1379                                 IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
1380 #define IS_TIGERLAKE(dev_priv)  IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
1381 #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
1382 #define IS_DG1(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG1)
1383 #define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
1384 #define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P)
1385 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
1386                                     (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
1387 #define IS_BDW_ULT(dev_priv) \
1388         IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
1389 #define IS_BDW_ULX(dev_priv) \
1390         IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
1391 #define IS_BDW_GT3(dev_priv)    (IS_BROADWELL(dev_priv) && \
1392                                  INTEL_INFO(dev_priv)->gt == 3)
1393 #define IS_HSW_ULT(dev_priv) \
1394         IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
1395 #define IS_HSW_GT3(dev_priv)    (IS_HASWELL(dev_priv) && \
1396                                  INTEL_INFO(dev_priv)->gt == 3)
1397 #define IS_HSW_GT1(dev_priv)    (IS_HASWELL(dev_priv) && \
1398                                  INTEL_INFO(dev_priv)->gt == 1)
1399 /* ULX machines are also considered ULT. */
1400 #define IS_HSW_ULX(dev_priv) \
1401         IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
1402 #define IS_SKL_ULT(dev_priv) \
1403         IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
1404 #define IS_SKL_ULX(dev_priv) \
1405         IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
1406 #define IS_KBL_ULT(dev_priv) \
1407         IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
1408 #define IS_KBL_ULX(dev_priv) \
1409         IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
1410 #define IS_SKL_GT2(dev_priv)    (IS_SKYLAKE(dev_priv) && \
1411                                  INTEL_INFO(dev_priv)->gt == 2)
1412 #define IS_SKL_GT3(dev_priv)    (IS_SKYLAKE(dev_priv) && \
1413                                  INTEL_INFO(dev_priv)->gt == 3)
1414 #define IS_SKL_GT4(dev_priv)    (IS_SKYLAKE(dev_priv) && \
1415                                  INTEL_INFO(dev_priv)->gt == 4)
1416 #define IS_KBL_GT2(dev_priv)    (IS_KABYLAKE(dev_priv) && \
1417                                  INTEL_INFO(dev_priv)->gt == 2)
1418 #define IS_KBL_GT3(dev_priv)    (IS_KABYLAKE(dev_priv) && \
1419                                  INTEL_INFO(dev_priv)->gt == 3)
1420 #define IS_CFL_ULT(dev_priv) \
1421         IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
1422 #define IS_CFL_ULX(dev_priv) \
1423         IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
1424 #define IS_CFL_GT2(dev_priv)    (IS_COFFEELAKE(dev_priv) && \
1425                                  INTEL_INFO(dev_priv)->gt == 2)
1426 #define IS_CFL_GT3(dev_priv)    (IS_COFFEELAKE(dev_priv) && \
1427                                  INTEL_INFO(dev_priv)->gt == 3)
1428
1429 #define IS_CML_ULT(dev_priv) \
1430         IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
1431 #define IS_CML_ULX(dev_priv) \
1432         IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
1433 #define IS_CML_GT2(dev_priv)    (IS_COMETLAKE(dev_priv) && \
1434                                  INTEL_INFO(dev_priv)->gt == 2)
1435
1436 #define IS_CNL_WITH_PORT_F(dev_priv) \
1437         IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
1438 #define IS_ICL_WITH_PORT_F(dev_priv) \
1439         IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
1440
1441 #define IS_TGL_U(dev_priv) \
1442         IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULT)
1443
1444 #define IS_TGL_Y(dev_priv) \
1445         IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULX)
1446
1447 #define SKL_REVID_A0            0x0
1448 #define SKL_REVID_B0            0x1
1449 #define SKL_REVID_C0            0x2
1450 #define SKL_REVID_D0            0x3
1451 #define SKL_REVID_E0            0x4
1452 #define SKL_REVID_F0            0x5
1453 #define SKL_REVID_G0            0x6
1454 #define SKL_REVID_H0            0x7
1455
1456 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
1457
1458 #define BXT_REVID_A0            0x0
1459 #define BXT_REVID_A1            0x1
1460 #define BXT_REVID_B0            0x3
1461 #define BXT_REVID_B_LAST        0x8
1462 #define BXT_REVID_C0            0x9
1463
1464 #define IS_BXT_REVID(dev_priv, since, until) \
1465         (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
1466
1467 #define IS_KBL_GT_STEP(dev_priv, since, until) \
1468         (IS_KABYLAKE(dev_priv) && IS_GT_STEP(dev_priv, since, until))
1469 #define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \
1470         (IS_KABYLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, since, until))
1471
1472 #define GLK_REVID_A0            0x0
1473 #define GLK_REVID_A1            0x1
1474 #define GLK_REVID_A2            0x2
1475 #define GLK_REVID_B0            0x3
1476
1477 #define IS_GLK_REVID(dev_priv, since, until) \
1478         (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
1479
1480 #define CNL_REVID_A0            0x0
1481 #define CNL_REVID_B0            0x1
1482 #define CNL_REVID_C0            0x2
1483
1484 #define IS_CNL_REVID(p, since, until) \
1485         (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
1486
1487 #define ICL_REVID_A0            0x0
1488 #define ICL_REVID_A2            0x1
1489 #define ICL_REVID_B0            0x3
1490 #define ICL_REVID_B2            0x4
1491 #define ICL_REVID_C0            0x5
1492
1493 #define IS_ICL_REVID(p, since, until) \
1494         (IS_ICELAKE(p) && IS_REVID(p, since, until))
1495
1496 #define EHL_REVID_A0            0x0
1497 #define EHL_REVID_B0            0x1
1498
1499 #define IS_JSL_EHL_REVID(p, since, until) \
1500         (IS_JSL_EHL(p) && IS_REVID(p, since, until))
1501
1502 #define IS_TGL_DISPLAY_STEP(__i915, since, until) \
1503         (IS_TIGERLAKE(__i915) && \
1504          IS_DISPLAY_STEP(__i915, since, until))
1505
1506 #define IS_TGL_UY_GT_STEP(__i915, since, until) \
1507         ((IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \
1508          IS_GT_STEP(__i915, since, until))
1509
1510 #define IS_TGL_GT_STEP(__i915, since, until) \
1511         (IS_TIGERLAKE(__i915) && !(IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \
1512          IS_GT_STEP(__i915, since, until))
1513
1514 #define RKL_REVID_A0            0x0
1515 #define RKL_REVID_B0            0x1
1516 #define RKL_REVID_C0            0x4
1517
1518 #define IS_RKL_REVID(p, since, until) \
1519         (IS_ROCKETLAKE(p) && IS_REVID(p, since, until))
1520
1521 #define DG1_REVID_A0            0x0
1522 #define DG1_REVID_B0            0x1
1523
1524 #define IS_DG1_REVID(p, since, until) \
1525         (IS_DG1(p) && IS_REVID(p, since, until))
1526
1527 #define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
1528         (IS_ALDERLAKE_S(__i915) && \
1529          IS_DISPLAY_STEP(__i915, since, until))
1530
1531 #define IS_ADLS_GT_STEP(__i915, since, until) \
1532         (IS_ALDERLAKE_S(__i915) && \
1533          IS_GT_STEP(__i915, since, until))
1534
1535 #define IS_ADLP_DISPLAY_STEP(__i915, since, until) \
1536         (IS_ALDERLAKE_P(__i915) && \
1537          IS_DISPLAY_STEP(__i915, since, until))
1538
1539 #define IS_ADLP_GT_STEP(__i915, since, until) \
1540         (IS_ALDERLAKE_P(__i915) && \
1541          IS_GT_STEP(__i915, since, until))
1542
1543 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
1544 #define IS_GEN9_LP(dev_priv)    (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
1545 #define IS_GEN9_BC(dev_priv)    (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
1546
1547 #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
1548 #define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
1549
1550 #define ENGINE_INSTANCES_MASK(gt, first, count) ({              \
1551         unsigned int first__ = (first);                                 \
1552         unsigned int count__ = (count);                                 \
1553         ((gt)->info.engine_mask &                                               \
1554          GENMASK(first__ + count__ - 1, first__)) >> first__;           \
1555 })
1556 #define VDBOX_MASK(gt) \
1557         ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
1558 #define VEBOX_MASK(gt) \
1559         ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
1560
1561 /*
1562  * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
1563  * All later gens can run the final buffer from the ppgtt
1564  */
1565 #define CMDPARSER_USES_GGTT(dev_priv) IS_GEN(dev_priv, 7)
1566
1567 #define HAS_LLC(dev_priv)       (INTEL_INFO(dev_priv)->has_llc)
1568 #define HAS_SNOOP(dev_priv)     (INTEL_INFO(dev_priv)->has_snoop)
1569 #define HAS_EDRAM(dev_priv)     ((dev_priv)->edram_size_mb)
1570 #define HAS_SECURE_BATCHES(dev_priv) (INTEL_GEN(dev_priv) < 6)
1571 #define HAS_WT(dev_priv)        HAS_EDRAM(dev_priv)
1572
1573 #define HWS_NEEDS_PHYSICAL(dev_priv)    (INTEL_INFO(dev_priv)->hws_needs_physical)
1574
1575 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
1576                 (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
1577 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
1578                 (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
1579
1580 #define HAS_MASTER_UNIT_IRQ(dev_priv) (INTEL_INFO(dev_priv)->has_master_unit_irq)
1581
1582 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
1583
1584 #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)
1585 #define HAS_PPGTT(dev_priv) \
1586         (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
1587 #define HAS_FULL_PPGTT(dev_priv) \
1588         (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
1589
1590 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
1591         GEM_BUG_ON((sizes) == 0); \
1592         ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \
1593 })
1594
1595 #define HAS_OVERLAY(dev_priv)            (INTEL_INFO(dev_priv)->display.has_overlay)
1596 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
1597                 (INTEL_INFO(dev_priv)->display.overlay_needs_physical)
1598
1599 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1600 #define HAS_BROKEN_CS_TLB(dev_priv)     (IS_I830(dev_priv) || IS_I845G(dev_priv))
1601
1602 #define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv)   \
1603         (IS_BROADWELL(dev_priv) || IS_GEN(dev_priv, 9))
1604
1605 /* WaRsDisableCoarsePowerGating:skl,cnl */
1606 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv)                    \
1607         (IS_CANNONLAKE(dev_priv) ||                                     \
1608          IS_SKL_GT3(dev_priv) ||                                        \
1609          IS_SKL_GT4(dev_priv))
1610
1611 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
1612 #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
1613                                         IS_GEMINILAKE(dev_priv) || \
1614                                         IS_KABYLAKE(dev_priv))
1615
1616 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1617  * rows, which changed the alignment requirements and fence programming.
1618  */
1619 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \
1620                                          !(IS_I915G(dev_priv) || \
1621                                          IS_I915GM(dev_priv)))
1622 #define SUPPORTS_TV(dev_priv)           (INTEL_INFO(dev_priv)->display.supports_tv)
1623 #define I915_HAS_HOTPLUG(dev_priv)      (INTEL_INFO(dev_priv)->display.has_hotplug)
1624
1625 #define HAS_FW_BLC(dev_priv)    (INTEL_GEN(dev_priv) > 2)
1626 #define HAS_FBC(dev_priv)       (INTEL_INFO(dev_priv)->display.has_fbc)
1627 #define HAS_CUR_FBC(dev_priv)   (!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7)
1628
1629 #define HAS_IPS(dev_priv)       (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
1630
1631 #define HAS_DP_MST(dev_priv)    (INTEL_INFO(dev_priv)->display.has_dp_mst)
1632
1633 #define HAS_DDI(dev_priv)                (INTEL_INFO(dev_priv)->display.has_ddi)
1634 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
1635 #define HAS_PSR(dev_priv)                (INTEL_INFO(dev_priv)->display.has_psr)
1636 #define HAS_PSR_HW_TRACKING(dev_priv) \
1637         (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
1638 #define HAS_PSR2_SEL_FETCH(dev_priv)     (INTEL_GEN(dev_priv) >= 12)
1639 #define HAS_TRANSCODER(dev_priv, trans)  ((INTEL_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0)
1640
1641 #define HAS_RC6(dev_priv)                (INTEL_INFO(dev_priv)->has_rc6)
1642 #define HAS_RC6p(dev_priv)               (INTEL_INFO(dev_priv)->has_rc6p)
1643 #define HAS_RC6pp(dev_priv)              (false) /* HW was never validated */
1644
1645 #define HAS_RPS(dev_priv)       (INTEL_INFO(dev_priv)->has_rps)
1646
1647 #define HAS_DMC(dev_priv)       (INTEL_INFO(dev_priv)->display.has_dmc)
1648
1649 #define HAS_MSO(i915)           (INTEL_GEN(i915) >= 12)
1650
1651 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
1652 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
1653
1654 #define HAS_IPC(dev_priv)                (INTEL_INFO(dev_priv)->display.has_ipc)
1655
1656 #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
1657 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
1658
1659 #define HAS_GT_UC(dev_priv)     (INTEL_INFO(dev_priv)->has_gt_uc)
1660
1661 #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
1662
1663 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv)     (INTEL_INFO(dev_priv)->has_global_mocs)
1664
1665
1666 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
1667
1668 #define HAS_LSPCON(dev_priv) (IS_GEN_RANGE(dev_priv, 9, 10))
1669
1670 /* DPF == dynamic parity feature */
1671 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
1672 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
1673                                  2 : HAS_L3_DPF(dev_priv))
1674
1675 #define GT_FREQUENCY_MULTIPLIER 50
1676 #define GEN9_FREQ_SCALER 3
1677
1678 #define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask))
1679
1680 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0)
1681
1682 #define HAS_VRR(i915)   (INTEL_GEN(i915) >= 12)
1683
1684 /* Only valid when HAS_DISPLAY() is true */
1685 #define INTEL_DISPLAY_ENABLED(dev_priv) \
1686         (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !(dev_priv)->params.disable_display)
1687
1688 static inline bool run_as_guest(void)
1689 {
1690         return !hypervisor_is_type(X86_HYPER_NATIVE);
1691 }
1692
1693 #define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \
1694                                               IS_ALDERLAKE_S(dev_priv))
1695
1696 static inline bool intel_vtd_active(void)
1697 {
1698 #ifdef CONFIG_INTEL_IOMMU
1699         if (intel_iommu_gfx_mapped)
1700                 return true;
1701 #endif
1702
1703         /* Running as a guest, we assume the host is enforcing VT'd */
1704         return run_as_guest();
1705 }
1706
1707 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
1708 {
1709         return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
1710 }
1711
1712 static inline bool
1713 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
1714 {
1715         return IS_BROXTON(dev_priv) && intel_vtd_active();
1716 }
1717
1718 /* i915_drv.c */
1719 extern const struct dev_pm_ops i915_pm_ops;
1720
1721 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
1722 void i915_driver_remove(struct drm_i915_private *i915);
1723 void i915_driver_shutdown(struct drm_i915_private *i915);
1724
1725 int i915_resume_switcheroo(struct drm_i915_private *i915);
1726 int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state);
1727
1728 int i915_getparam_ioctl(struct drm_device *dev, void *data,
1729                         struct drm_file *file_priv);
1730
1731 /* i915_gem.c */
1732 int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
1733 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
1734 void i915_gem_init_early(struct drm_i915_private *dev_priv);
1735 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
1736
1737 struct intel_memory_region *i915_gem_shmem_setup(struct drm_i915_private *i915);
1738
1739 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
1740 {
1741         /*
1742          * A single pass should suffice to release all the freed objects (along
1743          * most call paths) , but be a little more paranoid in that freeing
1744          * the objects does take a little amount of time, during which the rcu
1745          * callbacks could have added new objects into the freed list, and
1746          * armed the work again.
1747          */
1748         while (atomic_read(&i915->mm.free_count)) {
1749                 flush_work(&i915->mm.free_work);
1750                 rcu_barrier();
1751         }
1752 }
1753
1754 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
1755 {
1756         /*
1757          * Similar to objects above (see i915_gem_drain_freed-objects), in
1758          * general we have workers that are armed by RCU and then rearm
1759          * themselves in their callbacks. To be paranoid, we need to
1760          * drain the workqueue a second time after waiting for the RCU
1761          * grace period so that we catch work queued via RCU from the first
1762          * pass. As neither drain_workqueue() nor flush_workqueue() report
1763          * a result, we make an assumption that we only don't require more
1764          * than 3 passes to catch all _recursive_ RCU delayed work.
1765          *
1766          */
1767         int pass = 3;
1768         do {
1769                 flush_workqueue(i915->wq);
1770                 rcu_barrier();
1771                 i915_gem_drain_freed_objects(i915);
1772         } while (--pass);
1773         drain_workqueue(i915->wq);
1774 }
1775
1776 struct i915_vma * __must_check
1777 i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object *obj,
1778                             struct i915_gem_ww_ctx *ww,
1779                             const struct i915_ggtt_view *view,
1780                             u64 size, u64 alignment, u64 flags);
1781
1782 static inline struct i915_vma * __must_check
1783 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
1784                          const struct i915_ggtt_view *view,
1785                          u64 size, u64 alignment, u64 flags)
1786 {
1787         return i915_gem_object_ggtt_pin_ww(obj, NULL, view, size, alignment, flags);
1788 }
1789
1790 int i915_gem_object_unbind(struct drm_i915_gem_object *obj,
1791                            unsigned long flags);
1792 #define I915_GEM_OBJECT_UNBIND_ACTIVE BIT(0)
1793 #define I915_GEM_OBJECT_UNBIND_BARRIER BIT(1)
1794 #define I915_GEM_OBJECT_UNBIND_TEST BIT(2)
1795
1796 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
1797
1798 int i915_gem_dumb_create(struct drm_file *file_priv,
1799                          struct drm_device *dev,
1800                          struct drm_mode_create_dumb *args);
1801
1802 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
1803
1804 static inline u32 i915_reset_count(struct i915_gpu_error *error)
1805 {
1806         return atomic_read(&error->reset_count);
1807 }
1808
1809 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
1810                                           const struct intel_engine_cs *engine)
1811 {
1812         return atomic_read(&error->reset_engine_count[engine->uabi_class]);
1813 }
1814
1815 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
1816 void i915_gem_driver_register(struct drm_i915_private *i915);
1817 void i915_gem_driver_unregister(struct drm_i915_private *i915);
1818 void i915_gem_driver_remove(struct drm_i915_private *dev_priv);
1819 void i915_gem_driver_release(struct drm_i915_private *dev_priv);
1820 void i915_gem_suspend(struct drm_i915_private *dev_priv);
1821 void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
1822 void i915_gem_resume(struct drm_i915_private *dev_priv);
1823
1824 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
1825
1826 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1827                                     enum i915_cache_level cache_level);
1828
1829 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1830                                 struct dma_buf *dma_buf);
1831
1832 struct dma_buf *i915_gem_prime_export(struct drm_gem_object *gem_obj, int flags);
1833
1834 static inline struct i915_gem_context *
1835 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
1836 {
1837         return xa_load(&file_priv->context_xa, id);
1838 }
1839
1840 static inline struct i915_gem_context *
1841 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
1842 {
1843         struct i915_gem_context *ctx;
1844
1845         rcu_read_lock();
1846         ctx = __i915_gem_context_lookup_rcu(file_priv, id);
1847         if (ctx && !kref_get_unless_zero(&ctx->ref))
1848                 ctx = NULL;
1849         rcu_read_unlock();
1850
1851         return ctx;
1852 }
1853
1854 /* i915_gem_evict.c */
1855 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
1856                                           u64 min_size, u64 alignment,
1857                                           unsigned long color,
1858                                           u64 start, u64 end,
1859                                           unsigned flags);
1860 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
1861                                          struct drm_mm_node *node,
1862                                          unsigned int flags);
1863 int i915_gem_evict_vm(struct i915_address_space *vm);
1864
1865 /* i915_gem_internal.c */
1866 struct drm_i915_gem_object *
1867 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
1868                                 phys_addr_t size);
1869
1870 /* i915_gem_tiling.c */
1871 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
1872 {
1873         struct drm_i915_private *i915 = to_i915(obj->base.dev);
1874
1875         return i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
1876                 i915_gem_object_is_tiled(obj);
1877 }
1878
1879 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
1880                         unsigned int tiling, unsigned int stride);
1881 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
1882                              unsigned int tiling, unsigned int stride);
1883
1884 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
1885
1886 /* i915_cmd_parser.c */
1887 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
1888 int intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
1889 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
1890 unsigned long *intel_engine_cmd_parser_alloc_jump_whitelist(u32 batch_length,
1891                                                             bool trampoline);
1892
1893 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
1894                             struct i915_vma *batch,
1895                             unsigned long batch_offset,
1896                             unsigned long batch_length,
1897                             struct i915_vma *shadow,
1898                             unsigned long *jump_whitelist,
1899                             void *shadow_map,
1900                             const void *batch_map);
1901 #define I915_CMD_PARSER_TRAMPOLINE_SIZE 8
1902
1903 /* intel_device_info.c */
1904 static inline struct intel_device_info *
1905 mkwrite_device_info(struct drm_i915_private *dev_priv)
1906 {
1907         return (struct intel_device_info *)INTEL_INFO(dev_priv);
1908 }
1909
1910 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
1911                         struct drm_file *file);
1912
1913 /* i915_mm.c */
1914 int remap_io_sg(struct vm_area_struct *vma,
1915                 unsigned long addr, unsigned long size,
1916                 struct scatterlist *sgl, resource_size_t iobase);
1917
1918 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
1919 {
1920         if (INTEL_GEN(i915) >= 10)
1921                 return CNL_HWS_CSB_WRITE_INDEX;
1922         else
1923                 return I915_HWS_CSB_WRITE_INDEX;
1924 }
1925
1926 static inline enum i915_map_type
1927 i915_coherent_map_type(struct drm_i915_private *i915)
1928 {
1929         return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
1930 }
1931
1932 #endif