1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include <linux/io-mapping.h>
39 #include <linux/i2c.h>
40 #include <linux/i2c-algo-bit.h>
41 #include <drm/intel-gtt.h>
42 #include <linux/backlight.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/kref.h>
45 #include <linux/pm_qos.h>
47 /* General customization:
50 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
52 #define DRIVER_NAME "i915"
53 #define DRIVER_DESC "Intel Graphics"
54 #define DRIVER_DATE "20080730"
63 #define pipe_name(p) ((p) + 'A')
71 #define transcoder_name(t) ((t) + 'A')
78 #define plane_name(p) ((p) + 'A')
80 #define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A')
90 #define port_name(p) ((p) + 'A')
92 enum intel_display_power_domain {
96 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
97 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
98 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
99 POWER_DOMAIN_TRANSCODER_A,
100 POWER_DOMAIN_TRANSCODER_B,
101 POWER_DOMAIN_TRANSCODER_C,
102 POWER_DOMAIN_TRANSCODER_EDP,
109 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
111 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
112 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
113 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
114 #define POWER_DOMAIN_TRANSCODER(tran) \
115 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
116 (tran) + POWER_DOMAIN_TRANSCODER_A)
118 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \
119 BIT(POWER_DOMAIN_PIPE_A) | \
120 BIT(POWER_DOMAIN_TRANSCODER_EDP))
121 #define BDW_ALWAYS_ON_POWER_DOMAINS ( \
122 BIT(POWER_DOMAIN_PIPE_A) | \
123 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
124 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
128 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
129 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
139 #define I915_GEM_GPU_DOMAINS \
140 (I915_GEM_DOMAIN_RENDER | \
141 I915_GEM_DOMAIN_SAMPLER | \
142 I915_GEM_DOMAIN_COMMAND | \
143 I915_GEM_DOMAIN_INSTRUCTION | \
144 I915_GEM_DOMAIN_VERTEX)
146 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
148 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
149 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
150 if ((intel_encoder)->base.crtc == (__crtc))
152 struct drm_i915_private;
155 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
156 /* real shared dpll ids must be >= 0 */
160 #define I915_NUM_PLLS 2
162 struct intel_dpll_hw_state {
169 struct intel_shared_dpll {
170 int refcount; /* count of number of CRTCs sharing this PLL */
171 int active; /* count of number of active CRTCs (i.e. DPMS on) */
172 bool on; /* is the PLL actually active? Disabled during modeset */
174 /* should match the index in the dev_priv->shared_dplls array */
175 enum intel_dpll_id id;
176 struct intel_dpll_hw_state hw_state;
177 void (*mode_set)(struct drm_i915_private *dev_priv,
178 struct intel_shared_dpll *pll);
179 void (*enable)(struct drm_i915_private *dev_priv,
180 struct intel_shared_dpll *pll);
181 void (*disable)(struct drm_i915_private *dev_priv,
182 struct intel_shared_dpll *pll);
183 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
184 struct intel_shared_dpll *pll,
185 struct intel_dpll_hw_state *hw_state);
188 /* Used by dp and fdi links */
189 struct intel_link_m_n {
197 void intel_link_compute_m_n(int bpp, int nlanes,
198 int pixel_clock, int link_clock,
199 struct intel_link_m_n *m_n);
201 struct intel_ddi_plls {
207 /* Interface history:
210 * 1.2: Add Power Management
211 * 1.3: Add vblank support
212 * 1.4: Fix cmdbuffer path, add heap destroy
213 * 1.5: Add vblank pipe configuration
214 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
215 * - Support vertical blank on secondary display pipe
217 #define DRIVER_MAJOR 1
218 #define DRIVER_MINOR 6
219 #define DRIVER_PATCHLEVEL 0
221 #define WATCH_LISTS 0
224 #define I915_GEM_PHYS_CURSOR_0 1
225 #define I915_GEM_PHYS_CURSOR_1 2
226 #define I915_GEM_PHYS_OVERLAY_REGS 3
227 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
229 struct drm_i915_gem_phys_object {
231 struct page **page_list;
232 drm_dma_handle_t *handle;
233 struct drm_i915_gem_object *cur_obj;
236 struct opregion_header;
237 struct opregion_acpi;
238 struct opregion_swsci;
239 struct opregion_asle;
241 struct intel_opregion {
242 struct opregion_header __iomem *header;
243 struct opregion_acpi __iomem *acpi;
244 struct opregion_swsci __iomem *swsci;
245 u32 swsci_gbda_sub_functions;
246 u32 swsci_sbcb_sub_functions;
247 struct opregion_asle __iomem *asle;
249 u32 __iomem *lid_state;
250 struct work_struct asle_work;
252 #define OPREGION_SIZE (8*1024)
254 struct intel_overlay;
255 struct intel_overlay_error_state;
257 struct drm_i915_master_private {
258 drm_local_map_t *sarea;
259 struct _drm_i915_sarea *sarea_priv;
261 #define I915_FENCE_REG_NONE -1
262 #define I915_MAX_NUM_FENCES 32
263 /* 32 fences + sign bit for FENCE_REG_NONE */
264 #define I915_MAX_NUM_FENCE_BITS 6
266 struct drm_i915_fence_reg {
267 struct list_head lru_list;
268 struct drm_i915_gem_object *obj;
272 struct sdvo_device_mapping {
281 struct intel_display_error_state;
283 struct drm_i915_error_state {
291 bool waiting[I915_NUM_RINGS];
292 u32 pipestat[I915_MAX_PIPES];
293 u32 tail[I915_NUM_RINGS];
294 u32 head[I915_NUM_RINGS];
295 u32 ctl[I915_NUM_RINGS];
296 u32 ipeir[I915_NUM_RINGS];
297 u32 ipehr[I915_NUM_RINGS];
298 u32 instdone[I915_NUM_RINGS];
299 u32 acthd[I915_NUM_RINGS];
300 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
301 u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1];
302 u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */
303 /* our own tracking of ring head and tail */
304 u32 cpu_ring_head[I915_NUM_RINGS];
305 u32 cpu_ring_tail[I915_NUM_RINGS];
306 u32 error; /* gen6+ */
307 u32 err_int; /* gen7 */
308 u32 bbstate[I915_NUM_RINGS];
309 u32 instpm[I915_NUM_RINGS];
310 u32 instps[I915_NUM_RINGS];
311 u32 extra_instdone[I915_NUM_INSTDONE_REG];
312 u32 seqno[I915_NUM_RINGS];
314 u32 fault_reg[I915_NUM_RINGS];
316 u32 faddr[I915_NUM_RINGS];
317 u64 fence[I915_MAX_NUM_FENCES];
319 struct drm_i915_error_ring {
320 struct drm_i915_error_object {
324 } *ringbuffer, *batchbuffer, *ctx;
325 struct drm_i915_error_request {
331 } ring[I915_NUM_RINGS];
332 struct drm_i915_error_buffer {
339 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
346 } **active_bo, **pinned_bo;
347 u32 *active_bo_count, *pinned_bo_count;
348 struct intel_overlay_error_state *overlay;
349 struct intel_display_error_state *display;
350 int hangcheck_score[I915_NUM_RINGS];
351 enum intel_ring_hangcheck_action hangcheck_action[I915_NUM_RINGS];
354 struct intel_connector;
355 struct intel_crtc_config;
360 struct drm_i915_display_funcs {
361 bool (*fbc_enabled)(struct drm_device *dev);
362 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
363 void (*disable_fbc)(struct drm_device *dev);
364 int (*get_display_clock_speed)(struct drm_device *dev);
365 int (*get_fifo_size)(struct drm_device *dev, int plane);
367 * find_dpll() - Find the best values for the PLL
368 * @limit: limits for the PLL
369 * @crtc: current CRTC
370 * @target: target frequency in kHz
371 * @refclk: reference clock frequency in kHz
372 * @match_clock: if provided, @best_clock P divider must
373 * match the P divider from @match_clock
374 * used for LVDS downclocking
375 * @best_clock: best PLL values found
377 * Returns true on success, false on failure.
379 bool (*find_dpll)(const struct intel_limit *limit,
380 struct drm_crtc *crtc,
381 int target, int refclk,
382 struct dpll *match_clock,
383 struct dpll *best_clock);
384 void (*update_wm)(struct drm_crtc *crtc);
385 void (*update_sprite_wm)(struct drm_plane *plane,
386 struct drm_crtc *crtc,
387 uint32_t sprite_width, int pixel_size,
388 bool enable, bool scaled);
389 void (*modeset_global_resources)(struct drm_device *dev);
390 /* Returns the active state of the crtc, and if the crtc is active,
391 * fills out the pipe-config with the hw state. */
392 bool (*get_pipe_config)(struct intel_crtc *,
393 struct intel_crtc_config *);
394 int (*crtc_mode_set)(struct drm_crtc *crtc,
396 struct drm_framebuffer *old_fb);
397 void (*crtc_enable)(struct drm_crtc *crtc);
398 void (*crtc_disable)(struct drm_crtc *crtc);
399 void (*off)(struct drm_crtc *crtc);
400 void (*write_eld)(struct drm_connector *connector,
401 struct drm_crtc *crtc,
402 struct drm_display_mode *mode);
403 void (*fdi_link_train)(struct drm_crtc *crtc);
404 void (*init_clock_gating)(struct drm_device *dev);
405 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
406 struct drm_framebuffer *fb,
407 struct drm_i915_gem_object *obj,
409 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
411 void (*hpd_irq_setup)(struct drm_device *dev);
412 /* clock updates for mode set */
414 /* render clock increase/decrease */
415 /* display clock increase/decrease */
416 /* pll clock increase/decrease */
418 int (*setup_backlight)(struct intel_connector *connector);
419 uint32_t (*get_backlight)(struct intel_connector *connector);
420 void (*set_backlight)(struct intel_connector *connector,
422 void (*disable_backlight)(struct intel_connector *connector);
423 void (*enable_backlight)(struct intel_connector *connector);
426 struct intel_uncore_funcs {
427 void (*force_wake_get)(struct drm_i915_private *dev_priv);
428 void (*force_wake_put)(struct drm_i915_private *dev_priv);
430 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
431 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
432 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
433 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
435 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
436 uint8_t val, bool trace);
437 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
438 uint16_t val, bool trace);
439 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
440 uint32_t val, bool trace);
441 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
442 uint64_t val, bool trace);
445 struct intel_uncore {
446 spinlock_t lock; /** lock is also taken in irq contexts. */
448 struct intel_uncore_funcs funcs;
451 unsigned forcewake_count;
453 struct delayed_work force_wake_work;
456 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
457 func(is_mobile) sep \
460 func(is_i945gm) sep \
462 func(need_gfx_hws) sep \
464 func(is_pineview) sep \
465 func(is_broadwater) sep \
466 func(is_crestline) sep \
467 func(is_ivybridge) sep \
468 func(is_valleyview) sep \
469 func(is_haswell) sep \
470 func(is_preliminary) sep \
472 func(has_pipe_cxsr) sep \
473 func(has_hotplug) sep \
474 func(cursor_needs_physical) sep \
475 func(has_overlay) sep \
476 func(overlay_needs_physical) sep \
477 func(supports_tv) sep \
482 #define DEFINE_FLAG(name) u8 name:1
483 #define SEP_SEMICOLON ;
485 struct intel_device_info {
486 u32 display_mmio_offset;
489 u8 ring_mask; /* Rings supported by the HW */
490 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
496 enum i915_cache_level {
498 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
499 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
500 caches, eg sampler/render caches, and the
501 large Last-Level-Cache. LLC is coherent with
502 the CPU, but L3 is only visible to the GPU. */
503 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
506 typedef uint32_t gen6_gtt_pte_t;
508 struct i915_address_space {
510 struct drm_device *dev;
511 struct list_head global_link;
512 unsigned long start; /* Start offset always 0 for dri2 */
513 size_t total; /* size addr space maps (ex. 2GB for ggtt) */
521 * List of objects currently involved in rendering.
523 * Includes buffers having the contents of their GPU caches
524 * flushed, not necessarily primitives. last_rendering_seqno
525 * represents when the rendering involved will be completed.
527 * A reference is held on the buffer while on this list.
529 struct list_head active_list;
532 * LRU list of objects which are not in the ringbuffer and
533 * are ready to unbind, but are still in the GTT.
535 * last_rendering_seqno is 0 while an object is in this list.
537 * A reference is not held on the buffer while on this list,
538 * as merely being GTT-bound shouldn't prevent its being
539 * freed, and we'll pull it off the list in the free path.
541 struct list_head inactive_list;
543 /* FIXME: Need a more generic return type */
544 gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr,
545 enum i915_cache_level level,
546 bool valid); /* Create a valid PTE */
547 void (*clear_range)(struct i915_address_space *vm,
548 unsigned int first_entry,
549 unsigned int num_entries,
551 void (*insert_entries)(struct i915_address_space *vm,
553 unsigned int first_entry,
554 enum i915_cache_level cache_level);
555 void (*cleanup)(struct i915_address_space *vm);
558 /* The Graphics Translation Table is the way in which GEN hardware translates a
559 * Graphics Virtual Address into a Physical Address. In addition to the normal
560 * collateral associated with any va->pa translations GEN hardware also has a
561 * portion of the GTT which can be mapped by the CPU and remain both coherent
562 * and correct (in cases like swizzling). That region is referred to as GMADR in
566 struct i915_address_space base;
567 size_t stolen_size; /* Total size of stolen memory */
569 unsigned long mappable_end; /* End offset that we can CPU map */
570 struct io_mapping *mappable; /* Mapping to our CPU mappable region */
571 phys_addr_t mappable_base; /* PA of our GMADR */
573 /** "Graphics Stolen Memory" holds the global PTEs */
581 int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total,
582 size_t *stolen, phys_addr_t *mappable_base,
583 unsigned long *mappable_end);
585 #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT)
587 struct i915_hw_ppgtt {
588 struct i915_address_space base;
589 unsigned num_pd_entries;
591 struct page **pt_pages;
592 struct page *gen8_pt_pages;
594 struct page *pd_pages;
599 dma_addr_t pd_dma_addr[4];
602 dma_addr_t *pt_dma_addr;
603 dma_addr_t *gen8_pt_dma_addr[4];
605 int (*enable)(struct drm_device *dev);
609 * A VMA represents a GEM BO that is bound into an address space. Therefore, a
610 * VMA's presence cannot be guaranteed before binding, or after unbinding the
611 * object into/from the address space.
613 * To make things as simple as possible (ie. no refcounting), a VMA's lifetime
614 * will always be <= an objects lifetime. So object refcounting should cover us.
617 struct drm_mm_node node;
618 struct drm_i915_gem_object *obj;
619 struct i915_address_space *vm;
621 /** This object's place on the active/inactive lists */
622 struct list_head mm_list;
624 struct list_head vma_link; /* Link in the object's VMA list */
626 /** This vma's place in the batchbuffer or on the eviction list */
627 struct list_head exec_list;
630 * Used for performing relocations during execbuffer insertion.
632 struct hlist_node exec_node;
633 unsigned long exec_handle;
634 struct drm_i915_gem_exec_object2 *exec_entry;
638 struct i915_ctx_hang_stats {
639 /* This context had batch pending when hang was declared */
640 unsigned batch_pending;
642 /* This context had batch active when hang was declared */
643 unsigned batch_active;
645 /* Time when this context was last blamed for a GPU reset */
646 unsigned long guilty_ts;
648 /* This context is banned to submit more work */
652 /* This must match up with the value previously used for execbuf2.rsvd1. */
653 #define DEFAULT_CONTEXT_ID 0
654 struct i915_hw_context {
659 struct drm_i915_file_private *file_priv;
660 struct intel_ring_buffer *ring;
661 struct drm_i915_gem_object *obj;
662 struct i915_ctx_hang_stats hang_stats;
664 struct list_head link;
673 struct drm_mm_node *compressed_fb;
674 struct drm_mm_node *compressed_llb;
676 struct intel_fbc_work {
677 struct delayed_work work;
678 struct drm_crtc *crtc;
679 struct drm_framebuffer *fb;
684 FBC_OK, /* FBC is enabled */
685 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
686 FBC_NO_OUTPUT, /* no outputs enabled to compress */
687 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
688 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
689 FBC_MODE_TOO_LARGE, /* mode too large for compression */
690 FBC_BAD_PLANE, /* fbc not supported on plane */
691 FBC_NOT_TILED, /* buffer not tiled */
692 FBC_MULTIPLE_PIPES, /* more than one pipe active */
694 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
704 PCH_NONE = 0, /* No PCH present */
705 PCH_IBX, /* Ibexpeak PCH */
706 PCH_CPT, /* Cougarpoint PCH */
707 PCH_LPT, /* Lynxpoint PCH */
711 enum intel_sbi_destination {
716 #define QUIRK_PIPEA_FORCE (1<<0)
717 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
718 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
721 struct intel_fbc_work;
724 struct i2c_adapter adapter;
728 struct i2c_algo_bit_data bit_algo;
729 struct drm_i915_private *dev_priv;
732 struct i915_suspend_saved_registers {
753 u32 saveTRANS_HTOTAL_A;
754 u32 saveTRANS_HBLANK_A;
755 u32 saveTRANS_HSYNC_A;
756 u32 saveTRANS_VTOTAL_A;
757 u32 saveTRANS_VBLANK_A;
758 u32 saveTRANS_VSYNC_A;
766 u32 savePFIT_PGM_RATIOS;
767 u32 saveBLC_HIST_CTL;
769 u32 saveBLC_PWM_CTL2;
770 u32 saveBLC_HIST_CTL_B;
771 u32 saveBLC_CPU_PWM_CTL;
772 u32 saveBLC_CPU_PWM_CTL2;
785 u32 saveTRANS_HTOTAL_B;
786 u32 saveTRANS_HBLANK_B;
787 u32 saveTRANS_HSYNC_B;
788 u32 saveTRANS_VTOTAL_B;
789 u32 saveTRANS_VBLANK_B;
790 u32 saveTRANS_VSYNC_B;
804 u32 savePP_ON_DELAYS;
805 u32 savePP_OFF_DELAYS;
813 u32 savePFIT_CONTROL;
814 u32 save_palette_a[256];
815 u32 save_palette_b[256];
816 u32 saveDPFC_CB_BASE;
817 u32 saveFBC_CFB_BASE;
820 u32 saveFBC_CONTROL2;
830 u32 saveCACHE_MODE_0;
831 u32 saveMI_ARB_STATE;
842 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
853 u32 savePIPEA_GMCH_DATA_M;
854 u32 savePIPEB_GMCH_DATA_M;
855 u32 savePIPEA_GMCH_DATA_N;
856 u32 savePIPEB_GMCH_DATA_N;
857 u32 savePIPEA_DP_LINK_M;
858 u32 savePIPEB_DP_LINK_M;
859 u32 savePIPEA_DP_LINK_N;
860 u32 savePIPEB_DP_LINK_N;
871 u32 savePCH_DREF_CONTROL;
872 u32 saveDISP_ARB_CTL;
873 u32 savePIPEA_DATA_M1;
874 u32 savePIPEA_DATA_N1;
875 u32 savePIPEA_LINK_M1;
876 u32 savePIPEA_LINK_N1;
877 u32 savePIPEB_DATA_M1;
878 u32 savePIPEB_DATA_N1;
879 u32 savePIPEB_LINK_M1;
880 u32 savePIPEB_LINK_N1;
881 u32 saveMCHBAR_RENDER_STANDBY;
882 u32 savePCH_PORT_HOTPLUG;
885 struct intel_gen6_power_mgmt {
886 /* work and pm_iir are protected by dev_priv->irq_lock */
887 struct work_struct work;
890 /* The below variables an all the rps hw state are protected by
891 * dev->struct mutext. */
901 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
904 struct delayed_work delayed_resume_work;
907 * Protects RPS/RC6 register access and PCU communication.
908 * Must be taken after struct_mutex if nested.
910 struct mutex hw_lock;
913 /* defined intel_pm.c */
914 extern spinlock_t mchdev_lock;
916 struct intel_ilk_power_mgmt {
924 unsigned long last_time1;
925 unsigned long chipset_power;
927 struct timespec last_time2;
928 unsigned long gfx_power;
934 struct drm_i915_gem_object *pwrctx;
935 struct drm_i915_gem_object *renderctx;
938 /* Power well structure for haswell */
939 struct i915_power_well {
940 /* power well enable/disable usage count */
944 #define I915_MAX_POWER_WELLS 1
946 struct i915_power_domains {
948 * Power wells needed for initialization at driver init and suspend
949 * time are on. They are kept on until after the first modeset.
954 struct i915_power_well power_wells[I915_MAX_POWER_WELLS];
957 struct i915_dri1_state {
958 unsigned allow_batchbuffer : 1;
959 u32 __iomem *gfx_hws_cpu_addr;
970 struct i915_ums_state {
972 * Flag if the X Server, and thus DRM, is not currently in
973 * control of the device.
975 * This is set between LeaveVT and EnterVT. It needs to be
976 * replaced with a semaphore. It also needs to be
977 * transitioned away from for kernel modesetting.
982 #define MAX_L3_SLICES 2
983 struct intel_l3_parity {
984 u32 *remap_info[MAX_L3_SLICES];
985 struct work_struct error_work;
990 /** Memory allocator for GTT stolen memory */
991 struct drm_mm stolen;
992 /** List of all objects in gtt_space. Used to restore gtt
993 * mappings on resume */
994 struct list_head bound_list;
996 * List of objects which are not bound to the GTT (thus
997 * are idle and not used by the GPU) but still have
998 * (presumably uncached) pages still attached.
1000 struct list_head unbound_list;
1002 /** Usable portion of the GTT for GEM */
1003 unsigned long stolen_base; /* limited to low memory (32-bit) */
1005 /** PPGTT used for aliasing the PPGTT with the GTT */
1006 struct i915_hw_ppgtt *aliasing_ppgtt;
1008 struct shrinker inactive_shrinker;
1009 bool shrinker_no_lock_stealing;
1011 /** LRU list of objects with fence regs on them. */
1012 struct list_head fence_list;
1015 * We leave the user IRQ off as much as possible,
1016 * but this means that requests will finish and never
1017 * be retired once the system goes idle. Set a timer to
1018 * fire periodically while the ring is running. When it
1019 * fires, go retire requests.
1021 struct delayed_work retire_work;
1024 * When we detect an idle GPU, we want to turn on
1025 * powersaving features. So once we see that there
1026 * are no more requests outstanding and no more
1027 * arrive within a small period of time, we fire
1028 * off the idle_work.
1030 struct delayed_work idle_work;
1033 * Are we in a non-interruptible section of code like
1038 /** Bit 6 swizzling required for X tiling */
1039 uint32_t bit_6_swizzle_x;
1040 /** Bit 6 swizzling required for Y tiling */
1041 uint32_t bit_6_swizzle_y;
1043 /* storage for physical objects */
1044 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
1046 /* accounting, useful for userland debugging */
1047 spinlock_t object_stat_lock;
1048 size_t object_memory;
1052 struct drm_i915_error_state_buf {
1061 struct i915_error_state_file_priv {
1062 struct drm_device *dev;
1063 struct drm_i915_error_state *error;
1066 struct i915_gpu_error {
1067 /* For hangcheck timer */
1068 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1069 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1070 /* Hang gpu twice in this window and your context gets banned */
1071 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1073 struct timer_list hangcheck_timer;
1075 /* For reset and error_state handling. */
1077 /* Protected by the above dev->gpu_error.lock. */
1078 struct drm_i915_error_state *first_error;
1079 struct work_struct work;
1082 unsigned long missed_irq_rings;
1085 * State variable and reset counter controlling the reset flow
1087 * Upper bits are for the reset counter. This counter is used by the
1088 * wait_seqno code to race-free noticed that a reset event happened and
1089 * that it needs to restart the entire ioctl (since most likely the
1090 * seqno it waited for won't ever signal anytime soon).
1092 * This is important for lock-free wait paths, where no contended lock
1093 * naturally enforces the correct ordering between the bail-out of the
1094 * waiter and the gpu reset work code.
1096 * Lowest bit controls the reset state machine: Set means a reset is in
1097 * progress. This state will (presuming we don't have any bugs) decay
1098 * into either unset (successful reset) or the special WEDGED value (hw
1099 * terminally sour). All waiters on the reset_queue will be woken when
1102 atomic_t reset_counter;
1105 * Special values/flags for reset_counter
1107 * Note that the code relies on
1108 * I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG
1111 #define I915_RESET_IN_PROGRESS_FLAG 1
1112 #define I915_WEDGED 0xffffffff
1115 * Waitqueue to signal when the reset has completed. Used by clients
1116 * that wait for dev_priv->mm.wedged to settle.
1118 wait_queue_head_t reset_queue;
1120 /* For gpu hang simulation. */
1121 unsigned int stop_rings;
1123 /* For missed irq/seqno simulation. */
1124 unsigned int test_irq_rings;
1127 enum modeset_restore {
1128 MODESET_ON_LID_OPEN,
1133 struct ddi_vbt_port_info {
1134 uint8_t hdmi_level_shift;
1136 uint8_t supports_dvi:1;
1137 uint8_t supports_hdmi:1;
1138 uint8_t supports_dp:1;
1141 struct intel_vbt_data {
1142 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1143 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1146 unsigned int int_tv_support:1;
1147 unsigned int lvds_dither:1;
1148 unsigned int lvds_vbt:1;
1149 unsigned int int_crt_support:1;
1150 unsigned int lvds_use_ssc:1;
1151 unsigned int display_clock_mode:1;
1152 unsigned int fdi_rx_polarity_inverted:1;
1154 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1159 int edp_preemphasis;
1161 bool edp_initialized;
1164 struct edp_power_seq edp_pps;
1174 union child_device_config *child_dev;
1176 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1179 enum intel_ddb_partitioning {
1181 INTEL_DDB_PART_5_6, /* IVB+ */
1184 struct intel_wm_level {
1192 struct hsw_wm_values {
1193 uint32_t wm_pipe[3];
1195 uint32_t wm_lp_spr[3];
1196 uint32_t wm_linetime[3];
1198 enum intel_ddb_partitioning partitioning;
1202 * This struct tracks the state needed for the Package C8+ feature.
1204 * Package states C8 and deeper are really deep PC states that can only be
1205 * reached when all the devices on the system allow it, so even if the graphics
1206 * device allows PC8+, it doesn't mean the system will actually get to these
1209 * Our driver only allows PC8+ when all the outputs are disabled, the power well
1210 * is disabled and the GPU is idle. When these conditions are met, we manually
1211 * do the other conditions: disable the interrupts, clocks and switch LCPLL
1214 * When we really reach PC8 or deeper states (not just when we allow it) we lose
1215 * the state of some registers, so when we come back from PC8+ we need to
1216 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
1217 * need to take care of the registers kept by RC6.
1219 * The interrupt disabling is part of the requirements. We can only leave the
1220 * PCH HPD interrupts enabled. If we're in PC8+ and we get another interrupt we
1221 * can lock the machine.
1223 * Ideally every piece of our code that needs PC8+ disabled would call
1224 * hsw_disable_package_c8, which would increment disable_count and prevent the
1225 * system from reaching PC8+. But we don't have a symmetric way to do this for
1226 * everything, so we have the requirements_met and gpu_idle variables. When we
1227 * switch requirements_met or gpu_idle to true we decrease disable_count, and
1228 * increase it in the opposite case. The requirements_met variable is true when
1229 * all the CRTCs, encoders and the power well are disabled. The gpu_idle
1230 * variable is true when the GPU is idle.
1232 * In addition to everything, we only actually enable PC8+ if disable_count
1233 * stays at zero for at least some seconds. This is implemented with the
1234 * enable_work variable. We do this so we don't enable/disable PC8 dozens of
1235 * consecutive times when all screens are disabled and some background app
1236 * queries the state of our connectors, or we have some application constantly
1237 * waking up to use the GPU. Only after the enable_work function actually
1238 * enables PC8+ the "enable" variable will become true, which means that it can
1239 * be false even if disable_count is 0.
1241 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1242 * goes back to false exactly before we reenable the IRQs. We use this variable
1243 * to check if someone is trying to enable/disable IRQs while they're supposed
1244 * to be disabled. This shouldn't happen and we'll print some error messages in
1245 * case it happens, but if it actually happens we'll also update the variables
1246 * inside struct regsave so when we restore the IRQs they will contain the
1247 * latest expected values.
1249 * For more, read "Display Sequences for Package C8" on our documentation.
1251 struct i915_package_c8 {
1252 bool requirements_met;
1255 /* Only true after the delayed work task actually enables it. */
1259 struct delayed_work enable_work;
1266 uint32_t gen6_pmimr;
1270 enum intel_pipe_crc_source {
1271 INTEL_PIPE_CRC_SOURCE_NONE,
1272 INTEL_PIPE_CRC_SOURCE_PLANE1,
1273 INTEL_PIPE_CRC_SOURCE_PLANE2,
1274 INTEL_PIPE_CRC_SOURCE_PF,
1275 INTEL_PIPE_CRC_SOURCE_PIPE,
1276 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1277 INTEL_PIPE_CRC_SOURCE_TV,
1278 INTEL_PIPE_CRC_SOURCE_DP_B,
1279 INTEL_PIPE_CRC_SOURCE_DP_C,
1280 INTEL_PIPE_CRC_SOURCE_DP_D,
1281 INTEL_PIPE_CRC_SOURCE_AUTO,
1282 INTEL_PIPE_CRC_SOURCE_MAX,
1285 struct intel_pipe_crc_entry {
1290 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1291 struct intel_pipe_crc {
1293 bool opened; /* exclusive access to the result file */
1294 struct intel_pipe_crc_entry *entries;
1295 enum intel_pipe_crc_source source;
1297 wait_queue_head_t wq;
1300 typedef struct drm_i915_private {
1301 struct drm_device *dev;
1302 struct kmem_cache *slab;
1304 const struct intel_device_info *info;
1306 int relative_constants_mode;
1310 struct intel_uncore uncore;
1312 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
1315 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1316 * controller on different i2c buses. */
1317 struct mutex gmbus_mutex;
1320 * Base address of the gmbus and gpio block.
1322 uint32_t gpio_mmio_base;
1324 wait_queue_head_t gmbus_wait_queue;
1326 struct pci_dev *bridge_dev;
1327 struct intel_ring_buffer ring[I915_NUM_RINGS];
1328 uint32_t last_seqno, next_seqno;
1330 drm_dma_handle_t *status_page_dmah;
1331 struct resource mch_res;
1333 atomic_t irq_received;
1335 /* protects the irq masks */
1336 spinlock_t irq_lock;
1338 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1339 struct pm_qos_request pm_qos;
1341 /* DPIO indirect register protection */
1342 struct mutex dpio_lock;
1344 /** Cached value of IMR to avoid reads in updating the bitfield */
1347 u32 de_irq_mask[I915_MAX_PIPES];
1352 struct work_struct hotplug_work;
1353 bool enable_hotplug_processing;
1355 unsigned long hpd_last_jiffies;
1360 HPD_MARK_DISABLED = 2
1362 } hpd_stats[HPD_NUM_PINS];
1364 struct timer_list hotplug_reenable_timer;
1368 struct i915_fbc fbc;
1369 struct intel_opregion opregion;
1370 struct intel_vbt_data vbt;
1373 struct intel_overlay *overlay;
1374 unsigned int sprite_scaling_enabled;
1376 /* backlight registers and fields in struct intel_panel */
1377 spinlock_t backlight_lock;
1380 bool no_aux_handshake;
1382 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1383 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1384 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1386 unsigned int fsb_freq, mem_freq, is_ddr3;
1389 * wq - Driver workqueue for GEM.
1391 * NOTE: Work items scheduled here are not allowed to grab any modeset
1392 * locks, for otherwise the flushing done in the pageflip code will
1393 * result in deadlocks.
1395 struct workqueue_struct *wq;
1397 /* Display functions */
1398 struct drm_i915_display_funcs display;
1400 /* PCH chipset type */
1401 enum intel_pch pch_type;
1402 unsigned short pch_id;
1404 unsigned long quirks;
1406 enum modeset_restore modeset_restore;
1407 struct mutex modeset_restore_lock;
1409 struct list_head vm_list; /* Global list of all address spaces */
1410 struct i915_gtt gtt; /* VMA representing the global address space */
1412 struct i915_gem_mm mm;
1414 /* Kernel Modesetting */
1416 struct sdvo_device_mapping sdvo_mappings[2];
1418 struct drm_crtc *plane_to_crtc_mapping[3];
1419 struct drm_crtc *pipe_to_crtc_mapping[3];
1420 wait_queue_head_t pending_flip_queue;
1422 #ifdef CONFIG_DEBUG_FS
1423 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1426 int num_shared_dpll;
1427 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1428 struct intel_ddi_plls ddi_plls;
1430 /* Reclocking support */
1431 bool render_reclock_avail;
1432 bool lvds_downclock_avail;
1433 /* indicates the reduced downclock for LVDS*/
1437 bool mchbar_need_disable;
1439 struct intel_l3_parity l3_parity;
1441 /* Cannot be determined by PCIID. You must always read a register. */
1444 /* gen6+ rps state */
1445 struct intel_gen6_power_mgmt rps;
1447 /* ilk-only ips/rps state. Everything in here is protected by the global
1448 * mchdev_lock in intel_pm.c */
1449 struct intel_ilk_power_mgmt ips;
1451 struct i915_power_domains power_domains;
1453 struct i915_psr psr;
1455 struct i915_gpu_error gpu_error;
1457 struct drm_i915_gem_object *vlv_pctx;
1459 #ifdef CONFIG_DRM_I915_FBDEV
1460 /* list of fbdev register on this device */
1461 struct intel_fbdev *fbdev;
1465 * The console may be contended at resume, but we don't
1466 * want it to block on it.
1468 struct work_struct console_resume_work;
1470 struct drm_property *broadcast_rgb_property;
1471 struct drm_property *force_audio_property;
1473 bool hw_contexts_disabled;
1474 uint32_t hw_context_size;
1475 struct list_head context_list;
1479 struct i915_suspend_saved_registers regfile;
1483 * Raw watermark latency values:
1484 * in 0.1us units for WM0,
1485 * in 0.5us units for WM1+.
1488 uint16_t pri_latency[5];
1490 uint16_t spr_latency[5];
1492 uint16_t cur_latency[5];
1494 /* current hardware state */
1495 struct hsw_wm_values hw;
1498 struct i915_package_c8 pc8;
1500 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1502 struct i915_dri1_state dri1;
1503 /* Old ums support infrastructure, same warning applies. */
1504 struct i915_ums_state ums;
1505 } drm_i915_private_t;
1507 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1509 return dev->dev_private;
1512 /* Iterate over initialised rings */
1513 #define for_each_ring(ring__, dev_priv__, i__) \
1514 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1515 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1517 enum hdmi_force_audio {
1518 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1519 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1520 HDMI_AUDIO_AUTO, /* trust EDID */
1521 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1524 #define I915_GTT_OFFSET_NONE ((u32)-1)
1526 struct drm_i915_gem_object_ops {
1527 /* Interface between the GEM object and its backing storage.
1528 * get_pages() is called once prior to the use of the associated set
1529 * of pages before to binding them into the GTT, and put_pages() is
1530 * called after we no longer need them. As we expect there to be
1531 * associated cost with migrating pages between the backing storage
1532 * and making them available for the GPU (e.g. clflush), we may hold
1533 * onto the pages after they are no longer referenced by the GPU
1534 * in case they may be used again shortly (for example migrating the
1535 * pages to a different memory domain within the GTT). put_pages()
1536 * will therefore most likely be called when the object itself is
1537 * being released or under memory pressure (where we attempt to
1538 * reap pages for the shrinker).
1540 int (*get_pages)(struct drm_i915_gem_object *);
1541 void (*put_pages)(struct drm_i915_gem_object *);
1544 struct drm_i915_gem_object {
1545 struct drm_gem_object base;
1547 const struct drm_i915_gem_object_ops *ops;
1549 /** List of VMAs backed by this object */
1550 struct list_head vma_list;
1552 /** Stolen memory for this object, instead of being backed by shmem. */
1553 struct drm_mm_node *stolen;
1554 struct list_head global_list;
1556 struct list_head ring_list;
1557 /** Used in execbuf to temporarily hold a ref */
1558 struct list_head obj_exec_link;
1561 * This is set if the object is on the active lists (has pending
1562 * rendering and so a non-zero seqno), and is not set if it i s on
1563 * inactive (ready to be unbound) list.
1565 unsigned int active:1;
1568 * This is set if the object has been written to since last bound
1571 unsigned int dirty:1;
1574 * Fence register bits (if any) for this object. Will be set
1575 * as needed when mapped into the GTT.
1576 * Protected by dev->struct_mutex.
1578 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1581 * Advice: are the backing pages purgeable?
1583 unsigned int madv:2;
1586 * Current tiling mode for the object.
1588 unsigned int tiling_mode:2;
1590 * Whether the tiling parameters for the currently associated fence
1591 * register have changed. Note that for the purposes of tracking
1592 * tiling changes we also treat the unfenced register, the register
1593 * slot that the object occupies whilst it executes a fenced
1594 * command (such as BLT on gen2/3), as a "fence".
1596 unsigned int fence_dirty:1;
1598 /** How many users have pinned this object in GTT space. The following
1599 * users can each hold at most one reference: pwrite/pread, pin_ioctl
1600 * (via user_pin_count), execbuffer (objects are not allowed multiple
1601 * times for the same batchbuffer), and the framebuffer code. When
1602 * switching/pageflipping, the framebuffer code has at most two buffers
1605 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
1606 * bits with absolutely no headroom. So use 4 bits. */
1607 unsigned int pin_count:4;
1608 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
1611 * Is the object at the current location in the gtt mappable and
1612 * fenceable? Used to avoid costly recalculations.
1614 unsigned int map_and_fenceable:1;
1617 * Whether the current gtt mapping needs to be mappable (and isn't just
1618 * mappable by accident). Track pin and fault separate for a more
1619 * accurate mappable working set.
1621 unsigned int fault_mappable:1;
1622 unsigned int pin_mappable:1;
1623 unsigned int pin_display:1;
1626 * Is the GPU currently using a fence to access this buffer,
1628 unsigned int pending_fenced_gpu_access:1;
1629 unsigned int fenced_gpu_access:1;
1631 unsigned int cache_level:3;
1633 unsigned int has_aliasing_ppgtt_mapping:1;
1634 unsigned int has_global_gtt_mapping:1;
1635 unsigned int has_dma_mapping:1;
1637 struct sg_table *pages;
1638 int pages_pin_count;
1640 /* prime dma-buf support */
1641 void *dma_buf_vmapping;
1644 struct intel_ring_buffer *ring;
1646 /** Breadcrumb of last rendering to the buffer. */
1647 uint32_t last_read_seqno;
1648 uint32_t last_write_seqno;
1649 /** Breadcrumb of last fenced GPU access to the buffer. */
1650 uint32_t last_fenced_seqno;
1652 /** Current tiling stride for the object, if it's tiled. */
1655 /** References from framebuffers, locks out tiling changes. */
1656 unsigned long framebuffer_references;
1658 /** Record of address bit 17 of each page at last unbind. */
1659 unsigned long *bit_17;
1661 /** User space pin count and filp owning the pin */
1662 unsigned long user_pin_count;
1663 struct drm_file *pin_filp;
1665 /** for phy allocated objects */
1666 struct drm_i915_gem_phys_object *phys_obj;
1668 #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
1670 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1673 * Request queue structure.
1675 * The request queue allows us to note sequence numbers that have been emitted
1676 * and may be associated with active buffers to be retired.
1678 * By keeping this list, we can avoid having to do questionable
1679 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1680 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1682 struct drm_i915_gem_request {
1683 /** On Which ring this request was generated */
1684 struct intel_ring_buffer *ring;
1686 /** GEM sequence number associated with this request. */
1689 /** Position in the ringbuffer of the start of the request */
1692 /** Position in the ringbuffer of the end of the request */
1695 /** Context related to this request */
1696 struct i915_hw_context *ctx;
1698 /** Batch buffer related to this request if any */
1699 struct drm_i915_gem_object *batch_obj;
1701 /** Time at which this request was emitted, in jiffies. */
1702 unsigned long emitted_jiffies;
1704 /** global list entry for this request */
1705 struct list_head list;
1707 struct drm_i915_file_private *file_priv;
1708 /** file_priv list entry for this request */
1709 struct list_head client_list;
1712 struct drm_i915_file_private {
1713 struct drm_i915_private *dev_priv;
1717 struct list_head request_list;
1718 struct delayed_work idle_work;
1720 struct idr context_idr;
1722 struct i915_ctx_hang_stats hang_stats;
1723 atomic_t rps_wait_boost;
1726 #define INTEL_INFO(dev) (to_i915(dev)->info)
1728 #define IS_I830(dev) ((dev)->pdev->device == 0x3577)
1729 #define IS_845G(dev) ((dev)->pdev->device == 0x2562)
1730 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1731 #define IS_I865G(dev) ((dev)->pdev->device == 0x2572)
1732 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1733 #define IS_I915GM(dev) ((dev)->pdev->device == 0x2592)
1734 #define IS_I945G(dev) ((dev)->pdev->device == 0x2772)
1735 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1736 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1737 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1738 #define IS_GM45(dev) ((dev)->pdev->device == 0x2A42)
1739 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1740 #define IS_PINEVIEW_G(dev) ((dev)->pdev->device == 0xa001)
1741 #define IS_PINEVIEW_M(dev) ((dev)->pdev->device == 0xa011)
1742 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1743 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1744 #define IS_IRONLAKE_M(dev) ((dev)->pdev->device == 0x0046)
1745 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1746 #define IS_IVB_GT1(dev) ((dev)->pdev->device == 0x0156 || \
1747 (dev)->pdev->device == 0x0152 || \
1748 (dev)->pdev->device == 0x015a)
1749 #define IS_SNB_GT1(dev) ((dev)->pdev->device == 0x0102 || \
1750 (dev)->pdev->device == 0x0106 || \
1751 (dev)->pdev->device == 0x010A)
1752 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1753 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1754 #define IS_BROADWELL(dev) (INTEL_INFO(dev)->gen == 8)
1755 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1756 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
1757 ((dev)->pdev->device & 0xFF00) == 0x0C00)
1758 #define IS_ULT(dev) (IS_HASWELL(dev) && \
1759 ((dev)->pdev->device & 0xFF00) == 0x0A00)
1760 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
1761 ((dev)->pdev->device & 0x00F0) == 0x0020)
1762 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
1765 * The genX designation typically refers to the render engine, so render
1766 * capability related checks should use IS_GEN, while display and other checks
1767 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1770 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1771 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1772 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1773 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1774 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1775 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1776 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
1778 #define RENDER_RING (1<<RCS)
1779 #define BSD_RING (1<<VCS)
1780 #define BLT_RING (1<<BCS)
1781 #define VEBOX_RING (1<<VECS)
1782 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
1783 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
1784 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
1785 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1786 #define HAS_WT(dev) (IS_HASWELL(dev) && to_i915(dev)->ellc_size)
1787 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1789 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1790 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
1792 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1793 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1795 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1796 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
1798 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1799 * rows, which changed the alignment requirements and fence programming.
1801 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1803 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1804 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1805 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1806 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1807 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1809 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1810 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1811 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1813 #define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev))
1815 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
1816 #define HAS_POWER_WELL(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
1817 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
1818 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
1820 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
1821 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
1822 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
1823 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
1824 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
1825 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1827 #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type)
1828 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1829 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1830 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1831 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
1832 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1834 /* DPF == dynamic parity feature */
1835 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1836 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
1838 #define GT_FREQUENCY_MULTIPLIER 50
1840 #include "i915_trace.h"
1842 extern const struct drm_ioctl_desc i915_ioctls[];
1843 extern int i915_max_ioctl;
1844 extern unsigned int i915_fbpercrtc __always_unused;
1845 extern int i915_panel_ignore_lid __read_mostly;
1846 extern unsigned int i915_powersave __read_mostly;
1847 extern int i915_semaphores __read_mostly;
1848 extern unsigned int i915_lvds_downclock __read_mostly;
1849 extern int i915_lvds_channel_mode __read_mostly;
1850 extern int i915_panel_use_ssc __read_mostly;
1851 extern int i915_vbt_sdvo_panel_type __read_mostly;
1852 extern int i915_enable_rc6 __read_mostly;
1853 extern int i915_enable_fbc __read_mostly;
1854 extern bool i915_enable_hangcheck __read_mostly;
1855 extern int i915_enable_ppgtt __read_mostly;
1856 extern int i915_enable_psr __read_mostly;
1857 extern unsigned int i915_preliminary_hw_support __read_mostly;
1858 extern int i915_disable_power_well __read_mostly;
1859 extern int i915_enable_ips __read_mostly;
1860 extern bool i915_fastboot __read_mostly;
1861 extern int i915_enable_pc8 __read_mostly;
1862 extern int i915_pc8_timeout __read_mostly;
1863 extern bool i915_prefault_disable __read_mostly;
1865 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1866 extern int i915_resume(struct drm_device *dev);
1867 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1868 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1871 void i915_update_dri1_breadcrumb(struct drm_device *dev);
1872 extern void i915_kernel_lost_context(struct drm_device * dev);
1873 extern int i915_driver_load(struct drm_device *, unsigned long flags);
1874 extern int i915_driver_unload(struct drm_device *);
1875 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1876 extern void i915_driver_lastclose(struct drm_device * dev);
1877 extern void i915_driver_preclose(struct drm_device *dev,
1878 struct drm_file *file_priv);
1879 extern void i915_driver_postclose(struct drm_device *dev,
1880 struct drm_file *file_priv);
1881 extern int i915_driver_device_is_agp(struct drm_device * dev);
1882 #ifdef CONFIG_COMPAT
1883 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1886 extern int i915_emit_box(struct drm_device *dev,
1887 struct drm_clip_rect *box,
1889 extern int intel_gpu_reset(struct drm_device *dev);
1890 extern int i915_reset(struct drm_device *dev);
1891 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1892 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1893 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1894 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1896 extern void intel_console_resume(struct work_struct *work);
1899 void i915_queue_hangcheck(struct drm_device *dev);
1900 void i915_handle_error(struct drm_device *dev, bool wedged);
1902 extern void intel_irq_init(struct drm_device *dev);
1903 extern void intel_pm_init(struct drm_device *dev);
1904 extern void intel_hpd_init(struct drm_device *dev);
1905 extern void intel_pm_init(struct drm_device *dev);
1907 extern void intel_uncore_sanitize(struct drm_device *dev);
1908 extern void intel_uncore_early_sanitize(struct drm_device *dev);
1909 extern void intel_uncore_init(struct drm_device *dev);
1910 extern void intel_uncore_clear_errors(struct drm_device *dev);
1911 extern void intel_uncore_check_errors(struct drm_device *dev);
1912 extern void intel_uncore_fini(struct drm_device *dev);
1915 i915_enable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask);
1918 i915_disable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask);
1921 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1922 struct drm_file *file_priv);
1923 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1924 struct drm_file *file_priv);
1925 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1926 struct drm_file *file_priv);
1927 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1928 struct drm_file *file_priv);
1929 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1930 struct drm_file *file_priv);
1931 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1932 struct drm_file *file_priv);
1933 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1934 struct drm_file *file_priv);
1935 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1936 struct drm_file *file_priv);
1937 int i915_gem_execbuffer(struct drm_device *dev, void *data,
1938 struct drm_file *file_priv);
1939 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1940 struct drm_file *file_priv);
1941 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1942 struct drm_file *file_priv);
1943 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1944 struct drm_file *file_priv);
1945 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1946 struct drm_file *file_priv);
1947 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
1948 struct drm_file *file);
1949 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
1950 struct drm_file *file);
1951 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1952 struct drm_file *file_priv);
1953 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1954 struct drm_file *file_priv);
1955 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1956 struct drm_file *file_priv);
1957 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1958 struct drm_file *file_priv);
1959 int i915_gem_set_tiling(struct drm_device *dev, void *data,
1960 struct drm_file *file_priv);
1961 int i915_gem_get_tiling(struct drm_device *dev, void *data,
1962 struct drm_file *file_priv);
1963 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1964 struct drm_file *file_priv);
1965 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
1966 struct drm_file *file_priv);
1967 void i915_gem_load(struct drm_device *dev);
1968 void *i915_gem_object_alloc(struct drm_device *dev);
1969 void i915_gem_object_free(struct drm_i915_gem_object *obj);
1970 void i915_gem_object_init(struct drm_i915_gem_object *obj,
1971 const struct drm_i915_gem_object_ops *ops);
1972 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1974 void i915_gem_free_object(struct drm_gem_object *obj);
1975 void i915_gem_vma_destroy(struct i915_vma *vma);
1977 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1978 struct i915_address_space *vm,
1980 bool map_and_fenceable,
1982 void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1983 int __must_check i915_vma_unbind(struct i915_vma *vma);
1984 int __must_check i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj);
1985 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
1986 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1987 void i915_gem_lastclose(struct drm_device *dev);
1989 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
1990 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
1992 struct sg_page_iter sg_iter;
1994 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
1995 return sg_page_iter_page(&sg_iter);
1999 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2001 BUG_ON(obj->pages == NULL);
2002 obj->pages_pin_count++;
2004 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2006 BUG_ON(obj->pages_pin_count == 0);
2007 obj->pages_pin_count--;
2010 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2011 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2012 struct intel_ring_buffer *to);
2013 void i915_vma_move_to_active(struct i915_vma *vma,
2014 struct intel_ring_buffer *ring);
2015 int i915_gem_dumb_create(struct drm_file *file_priv,
2016 struct drm_device *dev,
2017 struct drm_mode_create_dumb *args);
2018 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2019 uint32_t handle, uint64_t *offset);
2021 * Returns true if seq1 is later than seq2.
2024 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2026 return (int32_t)(seq1 - seq2) >= 0;
2029 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2030 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2031 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
2032 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
2035 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
2037 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2038 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2039 dev_priv->fence_regs[obj->fence_reg].pin_count++;
2046 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
2048 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2049 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2050 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
2051 dev_priv->fence_regs[obj->fence_reg].pin_count--;
2055 bool i915_gem_retire_requests(struct drm_device *dev);
2056 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
2057 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2058 bool interruptible);
2059 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2061 return unlikely(atomic_read(&error->reset_counter)
2062 & I915_RESET_IN_PROGRESS_FLAG);
2065 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2067 return atomic_read(&error->reset_counter) == I915_WEDGED;
2070 void i915_gem_reset(struct drm_device *dev);
2071 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
2072 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
2073 int __must_check i915_gem_init(struct drm_device *dev);
2074 int __must_check i915_gem_init_hw(struct drm_device *dev);
2075 int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice);
2076 void i915_gem_init_swizzling(struct drm_device *dev);
2077 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
2078 int __must_check i915_gpu_idle(struct drm_device *dev);
2079 int __must_check i915_gem_suspend(struct drm_device *dev);
2080 int __i915_add_request(struct intel_ring_buffer *ring,
2081 struct drm_file *file,
2082 struct drm_i915_gem_object *batch_obj,
2084 #define i915_add_request(ring, seqno) \
2085 __i915_add_request(ring, NULL, NULL, seqno)
2086 int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
2088 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2090 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2093 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2095 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2097 struct intel_ring_buffer *pipelined);
2098 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj);
2099 int i915_gem_attach_phys_object(struct drm_device *dev,
2100 struct drm_i915_gem_object *obj,
2103 void i915_gem_detach_phys_object(struct drm_device *dev,
2104 struct drm_i915_gem_object *obj);
2105 void i915_gem_free_all_phys_object(struct drm_device *dev);
2106 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
2107 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
2110 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
2112 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2113 int tiling_mode, bool fenced);
2115 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2116 enum i915_cache_level cache_level);
2118 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2119 struct dma_buf *dma_buf);
2121 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2122 struct drm_gem_object *gem_obj, int flags);
2124 void i915_gem_restore_fences(struct drm_device *dev);
2126 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
2127 struct i915_address_space *vm);
2128 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
2129 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
2130 struct i915_address_space *vm);
2131 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
2132 struct i915_address_space *vm);
2133 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
2134 struct i915_address_space *vm);
2136 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2137 struct i915_address_space *vm);
2139 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj);
2141 /* Some GGTT VM helpers */
2142 #define obj_to_ggtt(obj) \
2143 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2144 static inline bool i915_is_ggtt(struct i915_address_space *vm)
2146 struct i915_address_space *ggtt =
2147 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
2151 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
2153 return i915_gem_obj_bound(obj, obj_to_ggtt(obj));
2156 static inline unsigned long
2157 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj)
2159 return i915_gem_obj_offset(obj, obj_to_ggtt(obj));
2162 static inline unsigned long
2163 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
2165 return i915_gem_obj_size(obj, obj_to_ggtt(obj));
2168 static inline int __must_check
2169 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
2171 bool map_and_fenceable,
2174 return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment,
2175 map_and_fenceable, nonblocking);
2178 /* i915_gem_context.c */
2179 void i915_gem_context_init(struct drm_device *dev);
2180 void i915_gem_context_fini(struct drm_device *dev);
2181 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
2182 int i915_switch_context(struct intel_ring_buffer *ring,
2183 struct drm_file *file, int to_id);
2184 void i915_gem_context_free(struct kref *ctx_ref);
2185 static inline void i915_gem_context_reference(struct i915_hw_context *ctx)
2187 kref_get(&ctx->ref);
2190 static inline void i915_gem_context_unreference(struct i915_hw_context *ctx)
2192 kref_put(&ctx->ref, i915_gem_context_free);
2195 struct i915_ctx_hang_stats * __must_check
2196 i915_gem_context_get_hang_stats(struct drm_device *dev,
2197 struct drm_file *file,
2199 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
2200 struct drm_file *file);
2201 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
2202 struct drm_file *file);
2204 /* i915_gem_gtt.c */
2205 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
2206 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
2207 struct drm_i915_gem_object *obj,
2208 enum i915_cache_level cache_level);
2209 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
2210 struct drm_i915_gem_object *obj);
2212 void i915_check_and_clear_faults(struct drm_device *dev);
2213 void i915_gem_suspend_gtt_mappings(struct drm_device *dev);
2214 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
2215 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
2216 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
2217 enum i915_cache_level cache_level);
2218 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
2219 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
2220 void i915_gem_init_global_gtt(struct drm_device *dev);
2221 void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
2222 unsigned long mappable_end, unsigned long end);
2223 int i915_gem_gtt_init(struct drm_device *dev);
2224 static inline void i915_gem_chipset_flush(struct drm_device *dev)
2226 if (INTEL_INFO(dev)->gen < 6)
2227 intel_gtt_chipset_flush();
2231 /* i915_gem_evict.c */
2232 int __must_check i915_gem_evict_something(struct drm_device *dev,
2233 struct i915_address_space *vm,
2236 unsigned cache_level,
2239 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
2240 int i915_gem_evict_everything(struct drm_device *dev);
2242 /* i915_gem_stolen.c */
2243 int i915_gem_init_stolen(struct drm_device *dev);
2244 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size);
2245 void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
2246 void i915_gem_cleanup_stolen(struct drm_device *dev);
2247 struct drm_i915_gem_object *
2248 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
2249 struct drm_i915_gem_object *
2250 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
2254 void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj);
2256 /* i915_gem_tiling.c */
2257 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
2259 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2261 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2262 obj->tiling_mode != I915_TILING_NONE;
2265 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
2266 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
2267 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
2269 /* i915_gem_debug.c */
2271 int i915_verify_lists(struct drm_device *dev);
2273 #define i915_verify_lists(dev) 0
2276 /* i915_debugfs.c */
2277 int i915_debugfs_init(struct drm_minor *minor);
2278 void i915_debugfs_cleanup(struct drm_minor *minor);
2279 #ifdef CONFIG_DEBUG_FS
2280 void intel_display_crc_init(struct drm_device *dev);
2282 static inline void intel_display_crc_init(struct drm_device *dev) {}
2285 /* i915_gpu_error.c */
2287 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
2288 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
2289 const struct i915_error_state_file_priv *error);
2290 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
2291 size_t count, loff_t pos);
2292 static inline void i915_error_state_buf_release(
2293 struct drm_i915_error_state_buf *eb)
2297 void i915_capture_error_state(struct drm_device *dev);
2298 void i915_error_state_get(struct drm_device *dev,
2299 struct i915_error_state_file_priv *error_priv);
2300 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
2301 void i915_destroy_error_state(struct drm_device *dev);
2303 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
2304 const char *i915_cache_level_str(int type);
2306 /* i915_suspend.c */
2307 extern int i915_save_state(struct drm_device *dev);
2308 extern int i915_restore_state(struct drm_device *dev);
2311 void i915_save_display_reg(struct drm_device *dev);
2312 void i915_restore_display_reg(struct drm_device *dev);
2315 void i915_setup_sysfs(struct drm_device *dev_priv);
2316 void i915_teardown_sysfs(struct drm_device *dev_priv);
2319 extern int intel_setup_gmbus(struct drm_device *dev);
2320 extern void intel_teardown_gmbus(struct drm_device *dev);
2321 static inline bool intel_gmbus_is_port_valid(unsigned port)
2323 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
2326 extern struct i2c_adapter *intel_gmbus_get_adapter(
2327 struct drm_i915_private *dev_priv, unsigned port);
2328 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
2329 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
2330 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
2332 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
2334 extern void intel_i2c_reset(struct drm_device *dev);
2336 /* intel_opregion.c */
2337 struct intel_encoder;
2338 extern int intel_opregion_setup(struct drm_device *dev);
2340 extern void intel_opregion_init(struct drm_device *dev);
2341 extern void intel_opregion_fini(struct drm_device *dev);
2342 extern void intel_opregion_asle_intr(struct drm_device *dev);
2343 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
2345 extern int intel_opregion_notify_adapter(struct drm_device *dev,
2348 static inline void intel_opregion_init(struct drm_device *dev) { return; }
2349 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
2350 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
2352 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
2357 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
2365 extern void intel_register_dsm_handler(void);
2366 extern void intel_unregister_dsm_handler(void);
2368 static inline void intel_register_dsm_handler(void) { return; }
2369 static inline void intel_unregister_dsm_handler(void) { return; }
2370 #endif /* CONFIG_ACPI */
2373 extern void intel_modeset_init_hw(struct drm_device *dev);
2374 extern void intel_modeset_suspend_hw(struct drm_device *dev);
2375 extern void intel_modeset_init(struct drm_device *dev);
2376 extern void intel_modeset_gem_init(struct drm_device *dev);
2377 extern void intel_modeset_cleanup(struct drm_device *dev);
2378 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
2379 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
2380 bool force_restore);
2381 extern void i915_redisable_vga(struct drm_device *dev);
2382 extern bool intel_fbc_enabled(struct drm_device *dev);
2383 extern void intel_disable_fbc(struct drm_device *dev);
2384 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
2385 extern void intel_init_pch_refclk(struct drm_device *dev);
2386 extern void gen6_set_rps(struct drm_device *dev, u8 val);
2387 extern void valleyview_set_rps(struct drm_device *dev, u8 val);
2388 extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv);
2389 extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv);
2390 extern void intel_detect_pch(struct drm_device *dev);
2391 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
2392 extern int intel_enable_rc6(const struct drm_device *dev);
2394 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
2395 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
2396 struct drm_file *file);
2399 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
2400 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
2401 struct intel_overlay_error_state *error);
2403 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
2404 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
2405 struct drm_device *dev,
2406 struct intel_display_error_state *error);
2408 /* On SNB platform, before reading ring registers forcewake bit
2409 * must be set to prevent GT core from power down and stale values being
2412 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
2413 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
2415 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
2416 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
2418 /* intel_sideband.c */
2419 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
2420 void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
2421 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
2422 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
2423 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2424 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
2425 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2426 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
2427 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2428 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
2429 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2430 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
2431 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
2432 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
2433 enum intel_sbi_destination destination);
2434 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
2435 enum intel_sbi_destination destination);
2437 int vlv_gpu_freq(int ddr_freq, int val);
2438 int vlv_freq_opcode(int ddr_freq, int val);
2440 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
2441 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
2443 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
2444 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
2445 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
2446 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
2448 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
2449 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
2450 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
2451 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
2453 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
2454 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
2456 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
2457 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
2459 /* "Broadcast RGB" property */
2460 #define INTEL_BROADCAST_RGB_AUTO 0
2461 #define INTEL_BROADCAST_RGB_FULL 1
2462 #define INTEL_BROADCAST_RGB_LIMITED 2
2464 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
2466 if (HAS_PCH_SPLIT(dev))
2467 return CPU_VGACNTRL;
2468 else if (IS_VALLEYVIEW(dev))
2469 return VLV_VGACNTRL;
2474 static inline void __user *to_user_ptr(u64 address)
2476 return (void __user *)(uintptr_t)address;
2479 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
2481 unsigned long j = msecs_to_jiffies(m);
2483 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2486 static inline unsigned long
2487 timespec_to_jiffies_timeout(const struct timespec *value)
2489 unsigned long j = timespec_to_jiffies(value);
2491 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);